LLVM
10.0.0svn
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#include "AArch64Disassembler.h"
#include "AArch64ExternalSymbolizer.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "TargetInfo/AArch64TargetInfo.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm-c/Disassembler.h"
#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include <algorithm>
#include <memory>
#include "AArch64GenDisassemblerTables.inc"
#include "AArch64GenInstrInfo.inc"
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "aarch64-disassembler" |
#define | Success MCDisassembler::Success |
#define | Fail MCDisassembler::Fail |
#define | SoftFail MCDisassembler::SoftFail |
Typedefs | |
using | DecodeStatus = MCDisassembler::DecodeStatus |
Functions | |
static DecodeStatus | DecodeFPR128RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeFPR128_loRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeFPR64RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeFPR32RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeFPR16RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeFPR8RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeGPR64commonRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeGPR64RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeGPR64spRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeGPR32RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeGPR32spRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeQQRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeQQQRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeQQQQRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeDDRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeDDDRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeDDDDRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeZPRRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeZPR_4bRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeZPR_3bRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeZPR2RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeZPR3RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeZPR4RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodePPRRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodePPR_3bRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeFixedPointScaleImm32 (MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeFixedPointScaleImm64 (MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodePCRelLabel19 (MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeMemExtend (MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeMRSSystemRegister (MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeMSRSystemRegister (MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeThreeAddrSRegInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeMoveImmInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeUnsignedLdStInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeSignedLdStInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeExclusiveLdStInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodePairLdStInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeAddSubERegInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeLogicalImmInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeModImmInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeModImmTiedInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeAdrInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeAddSubImmShift (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeUnconditionalBranch (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeSystemPStateInstruction (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeTestAndBranch (MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeFMOVLaneInstruction (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
static DecodeStatus | DecodeVecShiftR64Imm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftR64ImmNarrow (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftR32Imm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftR32ImmNarrow (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftR16Imm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftR16ImmNarrow (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftR8Imm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftL64Imm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftL32Imm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftL16Imm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftL8Imm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeWSeqPairsClassRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeXSeqPairsClassRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeSVELogicalImmInstruction (llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder) |
template<int Bits> | |
static DecodeStatus | DecodeSImm (llvm::MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) |
template<int ElementWidth> | |
static DecodeStatus | DecodeImm8OptLsl (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeSVEIncDecImm (MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) |
static bool | Check (DecodeStatus &Out, DecodeStatus In) |
static MCDisassembler * | createAArch64Disassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) |
static MCSymbolizer * | createAArch64ExternalSymbolizer (const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo) |
void | LLVMInitializeAArch64Disassembler () |
static DecodeStatus | DecodeVectorRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) |
static DecodeStatus | DecodeVecShiftRImm (MCInst &Inst, unsigned Imm, unsigned Add) |
static DecodeStatus | DecodeVecShiftLImm (MCInst &Inst, unsigned Imm, unsigned Add) |
static DecodeStatus | DecodeGPRSeqPairsClassRegisterClass (MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder) |
Variables | |
static const unsigned | FPR128DecoderTable [] |
static const unsigned | FPR64DecoderTable [] |
static const unsigned | FPR32DecoderTable [] |
static const unsigned | FPR16DecoderTable [] |
static const unsigned | FPR8DecoderTable [] |
static const unsigned | GPR64DecoderTable [] |
static const unsigned | GPR32DecoderTable [] |
static const unsigned | ZPRDecoderTable [] |
static const unsigned | ZZDecoderTable [] |
static const unsigned | ZZZDecoderTable [] |
static const unsigned | ZZZZDecoderTable [] |
static const unsigned | PPRDecoderTable [] |
static const unsigned | VectorDecoderTable [] |
static const unsigned | QQDecoderTable [] |
static const unsigned | QQQDecoderTable [] |
static const unsigned | QQQQDecoderTable [] |
static const unsigned | DDDecoderTable [] |
static const unsigned | DDDDecoderTable [] |
static const unsigned | DDDDDecoderTable [] |
#define DEBUG_TYPE "aarch64-disassembler" |
Definition at line 33 of file AArch64Disassembler.cpp.
#define Fail MCDisassembler::Fail |
Definition at line 242 of file AArch64Disassembler.cpp.
Referenced by adjustDuplex(), DecodeL4RSrcDstSrcDstInstruction(), DecodeMoveHRegInstruction(), llvm::GVNExpression::Expression::dump(), getDecoderTable(), getDPPOp(), logger(), mapBinOpcode(), llvm::sys::RetryAfterSignal(), SafeToMergeTerminators(), and sinkLastInstruction().
#define SoftFail MCDisassembler::SoftFail |
Definition at line 243 of file AArch64Disassembler.cpp.
Referenced by isVectorPredicable().
#define Success MCDisassembler::Success |
Definition at line 241 of file AArch64Disassembler.cpp.
Referenced by adjustDuplex(), llvm::CodeViewDebug::CodeViewDebug(), createOrdering(), DecodeMoveHRegInstruction(), llvm::AMDGPUAsmPrinter::EmitEndOfAsmFile(), llvm::InstructionSelector::executeMatchTable(), FindAllMemoryUses(), llvm::IRTranslator::getAnalysisUsage(), llvm::IRPosition::getAttrs(), getCompoundInsn(), llvm::ConstantRange::getEquivalentICmp(), getOffsetFromIndices(), GetRMWLibcall(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), llvm::Attributor::identifyDefaultAbstractAttributes(), llvm::DWARFVerifier::DieRangeInfo::intersects(), isCopyFeedingInvariantStore(), isLocalCopy(), isSubBorrowChain(), isVectorPredicable(), LLVMInitializeHexagonDisassembler(), logger(), LowerCMP_SWAP(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::AArch64CallLowering::lowerReturn(), makeCombineInst(), operator<<(), performMaskedAtomicOp(), llvm::SymbolRemappingReader::read(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::LiveDebugVariables::splitRegister(), llvm::DWARFContext::verify(), and llvm::raw_fd_ostream::~raw_fd_ostream().
Definition at line 36 of file AArch64Disassembler.cpp.
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Definition at line 223 of file AArch64Disassembler.cpp.
References llvm::MCDisassembler::Fail, llvm::tgtok::In, llvm_unreachable, llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.
Referenced by llvm::LoopAccessInfo::addRuntimeChecks(), expandBounds(), llvm::SCEVExpander::expandUnionPredicate(), llvm::FileCheckString::FileCheckString(), generatePoisonChecks(), generatePoisonChecksForBinOp(), llvm::LoopVersioning::getNonVersionedLoop(), isLoadConditional(), isSupportedGuardInstruction(), llvm::Intrinsic::matchIntrinsicSignature(), llvm::LoopVersioning::prepareNoAliasMetadata(), llvm::RuntimePointerChecking::printChecks(), and rewrite().
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Definition at line 245 of file AArch64Disassembler.cpp.
Referenced by LLVMInitializeAArch64Disassembler().
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Definition at line 273 of file AArch64Disassembler.cpp.
Referenced by LLVMInitializeAArch64Disassembler().
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Definition at line 1505 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeGPR32RegisterClass(), DecodeGPR32spRegisterClass(), DecodeGPR64RegisterClass(), DecodeGPR64spRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), and llvm::MCDisassembler::Success.
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Definition at line 1669 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeGPR32RegisterClass(), DecodeGPR32spRegisterClass(), DecodeGPR64RegisterClass(), DecodeGPR64spRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCDisassembler::Success, and llvm::MCDisassembler::tryAddingSymbolicOperand().
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Definition at line 1650 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeGPR64RegisterClass(), llvm::MCDisassembler::Fail, llvm::MCDisassembler::Success, and llvm::MCDisassembler::tryAddingSymbolicOperand().
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Definition at line 774 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 751 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 728 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 1288 of file AArch64Disassembler.cpp.
References DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), DecodeGPR64spRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), LLVM_FALLTHROUGH, llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.
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Definition at line 784 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 793 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 841 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeFPR128RegisterClass(), DecodeGPR64RegisterClass(), and llvm::MCDisassembler::Success.
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Definition at line 326 of file AArch64Disassembler.cpp.
References DecodeFPR128RegisterClass(), and llvm::MCDisassembler::Fail.
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Definition at line 315 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeFMOVLaneInstruction(), DecodeFPR128_loRegisterClass(), DecodePairLdStInstruction(), DecodeSignedLdStInstruction(), and DecodeUnsignedLdStInstruction().
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Definition at line 386 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeSignedLdStInstruction(), and DecodeUnsignedLdStInstruction().
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Definition at line 365 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodePairLdStInstruction(), DecodeSignedLdStInstruction(), and DecodeUnsignedLdStInstruction().
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Definition at line 344 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeModImmInstruction(), DecodePairLdStInstruction(), DecodeSignedLdStInstruction(), and DecodeUnsignedLdStInstruction().
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Definition at line 407 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeSignedLdStInstruction(), and DecodeUnsignedLdStInstruction().
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Definition at line 472 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeAddSubERegInstruction(), DecodeAddSubImmShift(), DecodeExclusiveLdStInstruction(), DecodeLogicalImmInstruction(), DecodeMoveImmInstruction(), DecodePairLdStInstruction(), DecodeSignedLdStInstruction(), DecodeTestAndBranch(), DecodeThreeAddrSRegInstruction(), and DecodeUnsignedLdStInstruction().
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Definition at line 483 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeAddSubERegInstruction(), DecodeAddSubImmShift(), and DecodeLogicalImmInstruction().
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Definition at line 428 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 439 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeAddSubERegInstruction(), DecodeAddSubImmShift(), DecodeAdrInstruction(), DecodeExclusiveLdStInstruction(), DecodeFMOVLaneInstruction(), DecodeLogicalImmInstruction(), DecodeMoveImmInstruction(), DecodePairLdStInstruction(), DecodeSignedLdStInstruction(), DecodeTestAndBranch(), DecodeThreeAddrSRegInstruction(), and DecodeUnsignedLdStInstruction().
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Definition at line 450 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeAddSubERegInstruction(), DecodeAddSubImmShift(), DecodeExclusiveLdStInstruction(), DecodeLogicalImmInstruction(), DecodePairLdStInstruction(), DecodeSignedLdStInstruction(), and DecodeUnsignedLdStInstruction().
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Definition at line 1776 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeWSeqPairsClassRegisterClass(), and DecodeXSeqPairsClassRegisterClass().
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Definition at line 1841 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 1562 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeGPR32RegisterClass(), DecodeGPR32spRegisterClass(), DecodeGPR64RegisterClass(), DecodeGPR64spRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), llvm::AArch64_AM::isValidDecodeLogicalImmediate(), and llvm::MCDisassembler::Success.
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Definition at line 816 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 1593 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeFPR64RegisterClass(), DecodeVectorRegisterClass(), llvm::MCInst::getOpcode(), and llvm::MCDisassembler::Success.
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Definition at line 1632 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeVectorRegisterClass(), and llvm::MCDisassembler::Success.
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Definition at line 996 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), and llvm::MCDisassembler::Success.
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Definition at line 823 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 833 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 1371 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeFPR128RegisterClass(), DecodeFPR32RegisterClass(), DecodeFPR64RegisterClass(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), DecodeGPR64spRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), LLVM_FALLTHROUGH, llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.
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Definition at line 800 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::Success, and llvm::MCDisassembler::tryAddingSymbolicOperand().
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Definition at line 619 of file AArch64Disassembler.cpp.
References DecodePPRRegisterClass(), and llvm::MCDisassembler::Fail.
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Definition at line 609 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodePPR_3bRegisterClass().
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Definition at line 707 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 684 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 661 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 1090 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeFPR128RegisterClass(), DecodeFPR16RegisterClass(), DecodeFPR32RegisterClass(), DecodeFPR64RegisterClass(), DecodeFPR8RegisterClass(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), DecodeGPR64spRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.
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Definition at line 1826 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::tgtok::Bits, llvm::MCOperand::createImm(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 1853 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
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Definition at line 1722 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), llvm::MCDisassembler::Fail, llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCDisassembler::getSubtargetInfo(), and llvm::MCDisassembler::Success.
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Definition at line 1752 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), llvm::MCDisassembler::Success, and llvm::MCDisassembler::tryAddingSymbolicOperand().
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Definition at line 934 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), LLVM_FALLTHROUGH, and llvm::MCDisassembler::Success.
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Definition at line 1705 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), llvm::MCDisassembler::Success, and llvm::MCDisassembler::tryAddingSymbolicOperand().
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Definition at line 1029 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), DecodeFPR128RegisterClass(), DecodeFPR16RegisterClass(), DecodeFPR32RegisterClass(), DecodeFPR64RegisterClass(), DecodeFPR8RegisterClass(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), DecodeGPR64spRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), llvm::MCDisassembler::Success, and llvm::MCDisassembler::tryAddingSymbolicOperand().
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Definition at line 924 of file AArch64Disassembler.cpp.
References DecodeVecShiftLImm().
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Definition at line 919 of file AArch64Disassembler.cpp.
References DecodeVecShiftLImm().
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Definition at line 914 of file AArch64Disassembler.cpp.
References DecodeVecShiftLImm().
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Definition at line 929 of file AArch64Disassembler.cpp.
References DecodeVecShiftLImm().
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Definition at line 870 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
Referenced by DecodeVecShiftL16Imm(), DecodeVecShiftL32Imm(), DecodeVecShiftL64Imm(), and DecodeVecShiftL8Imm().
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Definition at line 898 of file AArch64Disassembler.cpp.
References DecodeVecShiftRImm().
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Definition at line 903 of file AArch64Disassembler.cpp.
References DecodeVecShiftRImm().
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Definition at line 887 of file AArch64Disassembler.cpp.
References DecodeVecShiftRImm().
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Definition at line 892 of file AArch64Disassembler.cpp.
References DecodeVecShiftRImm().
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Definition at line 876 of file AArch64Disassembler.cpp.
References DecodeVecShiftRImm().
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Definition at line 881 of file AArch64Disassembler.cpp.
References DecodeVecShiftRImm().
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Definition at line 909 of file AArch64Disassembler.cpp.
References DecodeVecShiftRImm().
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Definition at line 864 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
Referenced by DecodeVecShiftR16Imm(), DecodeVecShiftR16ImmNarrow(), DecodeVecShiftR32Imm(), DecodeVecShiftR32ImmNarrow(), DecodeVecShiftR64Imm(), DecodeVecShiftR64ImmNarrow(), and DecodeVecShiftR8Imm().
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Definition at line 639 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeModImmInstruction(), and DecodeModImmTiedInstruction().
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Definition at line 1790 of file AArch64Disassembler.cpp.
References DecodeGPRSeqPairsClassRegisterClass().
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Definition at line 1799 of file AArch64Disassembler.cpp.
References DecodeGPRSeqPairsClassRegisterClass().
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Definition at line 544 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 568 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 592 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
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Definition at line 525 of file AArch64Disassembler.cpp.
References DecodeZPRRegisterClass(), and llvm::MCDisassembler::Fail.
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Definition at line 517 of file AArch64Disassembler.cpp.
References DecodeZPRRegisterClass(), and llvm::MCDisassembler::Fail.
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Definition at line 506 of file AArch64Disassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeSVELogicalImmInstruction(), DecodeZPR_3bRegisterClass(), and DecodeZPR_4bRegisterClass().
void LLVMInitializeAArch64Disassembler | ( | ) |
Definition at line 281 of file AArch64Disassembler.cpp.
References createAArch64Disassembler(), createAArch64ExternalSymbolizer(), llvm::getTheAArch64_32Target(), llvm::getTheAArch64beTarget(), llvm::getTheAArch64leTarget(), llvm::getTheARM64_32Target(), llvm::getTheARM64Target(), llvm::TargetRegistry::RegisterMCDisassembler(), and llvm::TargetRegistry::RegisterMCSymbolizer().
Definition at line 760 of file AArch64Disassembler.cpp.
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Definition at line 578 of file AArch64Disassembler.cpp.