LLVM 19.0.0git
AArch64Disassembler.cpp
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1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm-c/Disassembler.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <algorithm>
30#include <memory>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-disassembler"
35
36// Pull DecodeStatus and its enum values into the global namespace.
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39// Forward declare these because the autogenerated code will reference them.
40// Definitions are further down.
41static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
42 uint64_t Address,
43 const MCDisassembler *Decoder);
44static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
45 uint64_t Address,
46 const MCDisassembler *Decoder);
47static DecodeStatus
48DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
49 const MCDisassembler *Decoder);
50static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
51 uint64_t Address,
52 const MCDisassembler *Decoder);
53static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
54 uint64_t Address,
55 const MCDisassembler *Decoder);
56static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
57 uint64_t Address,
58 const MCDisassembler *Decoder);
59static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
60 uint64_t Address,
61 const MCDisassembler *Decoder);
62static DecodeStatus
63DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
64 const MCDisassembler *Decoder);
65static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
66 uint64_t Address,
67 const MCDisassembler *Decoder);
68static DecodeStatus
69DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
70 const MCDisassembler *Decoder);
71static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
72 uint64_t Address,
73 const MCDisassembler *Decoder);
74static DecodeStatus
75DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
76 uint64_t Address, const void *Decoder);
77static DecodeStatus
78DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
79 uint64_t Address,
80 const MCDisassembler *Decoder);
81static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
82 uint64_t Address,
83 const MCDisassembler *Decoder);
84static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
85 uint64_t Address,
86 const MCDisassembler *Decoder);
87static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
88 uint64_t Address,
89 const MCDisassembler *Decoder);
90static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
91 uint64_t Address,
92 const MCDisassembler *Decoder);
93static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
94 uint64_t Address,
95 const MCDisassembler *Decoder);
96static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
97 uint64_t Address,
98 const MCDisassembler *Decoder);
99static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
100 uint64_t Address,
101 const MCDisassembler *Decoder);
102static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
103 uint64_t Address,
104 const MCDisassembler *Decoder);
105static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
106 uint64_t Address,
107 const MCDisassembler *Decoder);
108static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
109 uint64_t Address,
110 const MCDisassembler *Decoder);
111static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
112 uint64_t Address,
113 const MCDisassembler *Decoder);
114static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
118 uint64_t Address,
119 const MCDisassembler *Decoder);
120static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder);
123static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
126static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
127 uint64_t Address,
128 const void *Decoder);
129static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
130 uint64_t Address,
131 const void *Decoder);
132static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
133 uint64_t Address,
134 const void *Decoder);
135template <unsigned NumBitsForTile>
136static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
137 uint64_t Address,
138 const MCDisassembler *Decoder);
139static DecodeStatus
140DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
141 uint64_t Address,
142 const MCDisassembler *Decoder);
143static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
144 uint64_t Address,
145 const MCDisassembler *Decoder);
146static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Addr,
148 const MCDisassembler *Decoder);
149static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address,
151 const MCDisassembler *Decoder);
152static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
153 uint64_t Address,
154 const MCDisassembler *Decoder);
155static DecodeStatus
156DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
157 const MCDisassembler *Decoder);
158static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address,
160 const void *Decoder);
161static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address,
163 const void *Decoder);
164
165static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
166 uint64_t Address,
167 const MCDisassembler *Decoder);
168static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
169 uint64_t Address,
170 const MCDisassembler *Decoder);
171static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
172 uint64_t Address,
173 const MCDisassembler *Decoder);
174static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
175 uint64_t Address,
176 const MCDisassembler *Decoder);
177static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
178 uint64_t Address,
179 const MCDisassembler *Decoder);
180static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
181 uint64_t Address,
182 const MCDisassembler *Decoder);
183static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
184 uint64_t Address,
185 const MCDisassembler *Decoder);
186static DecodeStatus
187DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
188 const MCDisassembler *Decoder);
189static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
190 uint64_t Address,
191 const MCDisassembler *Decoder);
192static DecodeStatus
193DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
194 const MCDisassembler *Decoder);
195static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
196 uint64_t Address,
197 const MCDisassembler *Decoder);
198static DecodeStatus
199DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
200 const MCDisassembler *Decoder);
201static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
202 uint64_t Address,
203 const MCDisassembler *Decoder);
204static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
205 uint64_t Address,
206 const MCDisassembler *Decoder);
207static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
208 uint64_t Address,
209 const MCDisassembler *Decoder);
210static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
211 uint64_t Address,
212 const MCDisassembler *Decoder);
213static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
214 uint64_t Address,
215 const MCDisassembler *Decoder);
216static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
217 uint64_t Address,
218 const MCDisassembler *Decoder);
219static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
220 uint64_t Address,
221 const MCDisassembler *Decoder);
222static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
223 uint64_t Address,
224 const MCDisassembler *Decoder);
225static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
226 uint64_t Address,
227 const MCDisassembler *Decoder);
228static DecodeStatus
229DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn,
230 uint64_t Address,
231 const MCDisassembler *Decoder);
232static DecodeStatus
233DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn,
234 uint64_t Address,
235 const MCDisassembler *Decoder);
236static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
237 uint64_t Address,
238 const MCDisassembler *Decoder);
239
240static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
241 uint64_t Address,
242 const MCDisassembler *Decoder);
243static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
244 uint64_t Addr,
245 const MCDisassembler *Decoder);
246static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
247 uint64_t Addr,
248 const MCDisassembler *Decoder);
249static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
250 uint64_t Addr,
251 const MCDisassembler *Decoder);
252static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
253 uint64_t Addr,
254 const MCDisassembler *Decoder);
255static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
256 uint64_t Addr,
257 const MCDisassembler *Decoder);
258static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
259 uint64_t Addr,
260 const MCDisassembler *Decoder);
261static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
262 uint64_t Addr,
263 const MCDisassembler *Decoder);
264static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
265 uint64_t Addr,
266 const MCDisassembler *Decoder);
267static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
268 uint64_t Addr,
269 const MCDisassembler *Decoder);
270static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
271 uint64_t Addr,
272 const MCDisassembler *Decoder);
273static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
274 uint64_t Addr,
275 const MCDisassembler *Decoder);
276static DecodeStatus
277DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
278 const MCDisassembler *Decoder);
279static DecodeStatus
280DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
281 const MCDisassembler *Decoder);
282static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
283 uint64_t Addr,
284 const MCDisassembler *Decoder);
285static DecodeStatus
286DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
287 const MCDisassembler *Decoder);
288template <int Bits>
289static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
290 const MCDisassembler *Decoder);
291template <int ElementWidth>
292static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
293 const MCDisassembler *Decoder);
294static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
295 uint64_t Addr,
296 const MCDisassembler *Decoder);
297static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
298 const MCDisassembler *Decoder);
299static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
300 uint64_t Addr,
301 const MCDisassembler *Decoder);
302static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
303 uint64_t Addr,
304 const MCDisassembler *Decoder);
305static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
306 uint64_t Address,
307 const MCDisassembler *Decoder);
308
309#include "AArch64GenDisassemblerTables.inc"
310#include "AArch64GenInstrInfo.inc"
311
312#define Success MCDisassembler::Success
313#define Fail MCDisassembler::Fail
314#define SoftFail MCDisassembler::SoftFail
315
316static MCDisassembler *createAArch64Disassembler(const Target &T,
317 const MCSubtargetInfo &STI,
318 MCContext &Ctx) {
319
320 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
321}
322
323DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
324 ArrayRef<uint8_t> Bytes,
325 uint64_t Address,
326 raw_ostream &CS) const {
327 CommentStream = &CS;
328
329 Size = 0;
330 // We want to read exactly 4 bytes of data.
331 if (Bytes.size() < 4)
332 return Fail;
333 Size = 4;
334
335 // Encoded as a small-endian 32-bit word in the stream.
336 uint32_t Insn =
337 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
338
339 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
340
341 for (const auto *Table : Tables) {
342 DecodeStatus Result =
343 decodeInstruction(Table, MI, Insn, Address, this, STI);
344
345 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
346
347 // For Scalable Matrix Extension (SME) instructions that have an implicit
348 // operand for the accumulator (ZA) or implicit immediate zero which isn't
349 // encoded, manually insert operand.
350 for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
351 if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
352 switch (Desc.operands()[i].RegClass) {
353 default:
354 break;
355 case AArch64::MPRRegClassID:
356 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
357 break;
358 case AArch64::MPR8RegClassID:
359 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
360 break;
361 case AArch64::ZTRRegClassID:
362 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
363 break;
364 }
365 } else if (Desc.operands()[i].OperandType ==
366 AArch64::OPERAND_IMPLICIT_IMM_0) {
367 MI.insert(MI.begin() + i, MCOperand::createImm(0));
368 }
369 }
370
371 if (MI.getOpcode() == AArch64::LDR_ZA ||
372 MI.getOpcode() == AArch64::STR_ZA) {
373 // Spill and fill instructions have a single immediate used for both
374 // the vector select offset and optional memory offset. Replicate
375 // the decoded immediate.
376 const MCOperand &Imm4Op = MI.getOperand(2);
377 assert(Imm4Op.isImm() && "Unexpected operand type!");
378 MI.addOperand(Imm4Op);
379 }
380
381 if (Result != MCDisassembler::Fail)
382 return Result;
383 }
384
385 return MCDisassembler::Fail;
386}
387
388uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
389 uint64_t Address) const {
390 // AArch64 instructions are always 4 bytes wide, so there's no point
391 // in skipping any smaller number of bytes if an instruction can't
392 // be decoded.
393 return 4;
394}
395
396static MCSymbolizer *
397createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
398 LLVMSymbolLookupCallback SymbolLookUp,
399 void *DisInfo, MCContext *Ctx,
400 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
401 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
402 SymbolLookUp, DisInfo);
403}
404
405extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
406 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
407 createAArch64Disassembler);
408 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
409 createAArch64Disassembler);
410 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
411 createAArch64ExternalSymbolizer);
412 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
413 createAArch64ExternalSymbolizer);
414 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
415 createAArch64Disassembler);
416 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
417 createAArch64ExternalSymbolizer);
418
419 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
420 createAArch64Disassembler);
421 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
422 createAArch64ExternalSymbolizer);
423 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
424 createAArch64Disassembler);
425 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
426 createAArch64ExternalSymbolizer);
427}
428
429static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
430 uint64_t Addr,
431 const MCDisassembler *Decoder) {
432 if (RegNo > 31)
433 return Fail;
434
435 unsigned Register =
436 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
437 Inst.addOperand(MCOperand::createReg(Register));
438 return Success;
439}
440
441static DecodeStatus
442DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
443 const MCDisassembler *Decoder) {
444 if (RegNo > 15)
445 return Fail;
446 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
447}
448
449static DecodeStatus
450DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
451 const MCDisassembler *Decoder) {
452 if (RegNo > 7)
453 return Fail;
454 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
455}
456
457static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
458 uint64_t Addr,
459 const MCDisassembler *Decoder) {
460 if (RegNo > 31)
461 return Fail;
462
463 unsigned Register =
464 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
465 Inst.addOperand(MCOperand::createReg(Register));
466 return Success;
467}
468
469static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
470 uint64_t Addr,
471 const MCDisassembler *Decoder) {
472 if (RegNo > 31)
473 return Fail;
474
475 unsigned Register =
476 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
477 Inst.addOperand(MCOperand::createReg(Register));
478 return Success;
479}
480
481static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
482 uint64_t Addr,
483 const MCDisassembler *Decoder) {
484 if (RegNo > 31)
485 return Fail;
486
487 unsigned Register =
488 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
489 Inst.addOperand(MCOperand::createReg(Register));
490 return Success;
491}
492
493static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
494 uint64_t Addr,
495 const MCDisassembler *Decoder) {
496 if (RegNo > 31)
497 return Fail;
498
499 unsigned Register =
500 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
501 Inst.addOperand(MCOperand::createReg(Register));
502 return Success;
503}
504
505static DecodeStatus
506DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
507 const MCDisassembler *Decoder) {
508 if (RegNo > 30)
509 return Fail;
510
511 unsigned Register =
512 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
513 RegNo);
514 Inst.addOperand(MCOperand::createReg(Register));
515 return Success;
516}
517
518static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
519 uint64_t Addr,
520 const MCDisassembler *Decoder) {
521 if (RegNo > 31)
522 return Fail;
523
524 unsigned Register =
525 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
526 Inst.addOperand(MCOperand::createReg(Register));
527 return Success;
528}
529
530static DecodeStatus
531DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
532 const MCDisassembler *Decoder) {
533 if (RegNo > 22)
534 return Fail;
535 if (RegNo & 1)
536 return Fail;
537
538 unsigned Register =
539 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
540 RegNo >> 1);
541 Inst.addOperand(MCOperand::createReg(Register));
542 return Success;
543}
544
545static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
546 uint64_t Addr,
547 const MCDisassembler *Decoder) {
548 if (RegNo > 31)
549 return Fail;
550 unsigned Register =
551 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
552 Inst.addOperand(MCOperand::createReg(Register));
553 return Success;
554}
555
556static DecodeStatus
557DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
558 uint64_t Addr, const void *Decoder) {
559 if (RegNo > 3)
560 return Fail;
561
562 unsigned Register =
563 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
564 .getRegister(RegNo);
565 Inst.addOperand(MCOperand::createReg(Register));
566 return Success;
567}
568
569static DecodeStatus
570DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
571 uint64_t Addr,
572 const MCDisassembler *Decoder) {
573 if (RegNo > 3)
574 return Fail;
575
576 unsigned Register =
577 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
578 .getRegister(RegNo);
579 Inst.addOperand(MCOperand::createReg(Register));
580 return Success;
581}
582
583static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
584 uint64_t Addr,
585 const MCDisassembler *Decoder) {
586 if (RegNo > 31)
587 return Fail;
588
589 unsigned Register =
590 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
591 Inst.addOperand(MCOperand::createReg(Register));
592 return Success;
593}
594
595static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
596 uint64_t Addr,
597 const MCDisassembler *Decoder) {
598 if (RegNo > 31)
599 return Fail;
600
601 unsigned Register =
602 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
603 Inst.addOperand(MCOperand::createReg(Register));
604 return Success;
605}
606
607static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
608 uint64_t Address,
609 const MCDisassembler *Decoder) {
610 if (RegNo > 31)
611 return Fail;
612
613 unsigned Register =
614 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
615 Inst.addOperand(MCOperand::createReg(Register));
616 return Success;
617}
618
619static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
620 uint64_t Address,
621 const MCDisassembler *Decoder) {
622 if (RegNo > 15)
623 return Fail;
624 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
625}
626
627static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
628 uint64_t Address,
629 const MCDisassembler *Decoder) {
630 if (RegNo > 7)
631 return Fail;
632 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
633}
634
635static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
636 uint64_t Address,
637 const MCDisassembler *Decoder) {
638 if (RegNo > 31)
639 return Fail;
640 unsigned Register =
641 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
642 Inst.addOperand(MCOperand::createReg(Register));
643 return Success;
644}
645
646static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
647 uint64_t Address,
648 const MCDisassembler *Decoder) {
649 if (RegNo > 31)
650 return Fail;
651 unsigned Register =
652 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
653 Inst.addOperand(MCOperand::createReg(Register));
654 return Success;
655}
656
657static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
658 uint64_t Address,
659 const MCDisassembler *Decoder) {
660 if (RegNo > 31)
661 return Fail;
662 unsigned Register =
663 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
664 Inst.addOperand(MCOperand::createReg(Register));
665 return Success;
666}
667
668static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
669 uint64_t Address,
670 const void *Decoder) {
671 if (RegNo * 2 > 30)
672 return Fail;
673 unsigned Register =
674 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
675 Inst.addOperand(MCOperand::createReg(Register));
676 return Success;
677}
678
679static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
680 uint64_t Address,
681 const void *Decoder) {
682 if (RegNo * 4 > 28)
683 return Fail;
684 unsigned Register =
685 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
686 Inst.addOperand(MCOperand::createReg(Register));
687 return Success;
688}
689
690static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
691 uint64_t Address,
692 const void *Decoder) {
693 if (RegNo > 15)
694 return Fail;
695 unsigned Register =
696 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
697 RegNo);
698 Inst.addOperand(MCOperand::createReg(Register));
699 return Success;
700}
701
702static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
703 uint64_t Address,
704 const void *Decoder) {
705 if (RegNo > 7)
706 return Fail;
707 unsigned Register =
708 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
709 RegNo);
710 Inst.addOperand(MCOperand::createReg(Register));
711 return Success;
712}
713
714static DecodeStatus
715DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
716 uint64_t Address,
717 const MCDisassembler *Decoder) {
718 if (RegMask > 0xFF)
719 return Fail;
720 Inst.addOperand(MCOperand::createImm(RegMask));
721 return Success;
722}
723
724static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
725 {AArch64::ZAB0},
726 {AArch64::ZAH0, AArch64::ZAH1},
727 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
728 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
729 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
730 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
731 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
732 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
733 AArch64::ZAQ14, AArch64::ZAQ15}};
734
735template <unsigned NumBitsForTile>
736static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
737 uint64_t Address,
738 const MCDisassembler *Decoder) {
739 unsigned LastReg = (1 << NumBitsForTile) - 1;
740 if (RegNo > LastReg)
741 return Fail;
742 Inst.addOperand(
743 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
744 return Success;
745}
746
747static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
748 uint64_t Addr,
749 const MCDisassembler *Decoder) {
750 if (RegNo > 15)
751 return Fail;
752
753 unsigned Register =
754 AArch64MCRegisterClasses[AArch64::PPRorPNRRegClassID].getRegister(RegNo);
755 Inst.addOperand(MCOperand::createReg(Register));
756 return Success;
757}
758
759static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
760 uint64_t Addr,
761 const MCDisassembler *Decoder) {
762 if (RegNo > 15)
763 return Fail;
764
765 unsigned Register =
766 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
767 Inst.addOperand(MCOperand::createReg(Register));
768 return Success;
769}
770
771static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
772 uint64_t Addr,
773 const MCDisassembler *Decoder) {
774 if (RegNo > 15)
775 return Fail;
776
777 unsigned Register =
778 AArch64MCRegisterClasses[AArch64::PNRRegClassID].getRegister(RegNo);
779 Inst.addOperand(MCOperand::createReg(Register));
780 return Success;
781}
782
783static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
784 uint64_t Addr,
785 const MCDisassembler *Decoder) {
786 if (RegNo > 7)
787 return Fail;
788
789 // Just reuse the PPR decode table
790 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
791}
792
793static DecodeStatus
794DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
795 const MCDisassembler *Decoder) {
796 if (RegNo > 7)
797 return Fail;
798
799 // Just reuse the PPR decode table
800 return DecodePNRRegisterClass(Inst, RegNo + 8, Addr, Decoder);
801}
802
803static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
804 uint64_t Address,
805 const void *Decoder) {
806 if (RegNo > 15)
807 return Fail;
808
809 unsigned Register =
810 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
811 Inst.addOperand(MCOperand::createReg(Register));
812 return Success;
813}
814
815static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
816 uint64_t Address,
817 const void *Decoder) {
818 if ((RegNo * 2) > 14)
819 return Fail;
820 unsigned Register =
821 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
822 Inst.addOperand(MCOperand::createReg(Register));
823 return Success;
824}
825
826static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
827 uint64_t Addr,
828 const MCDisassembler *Decoder) {
829 if (RegNo > 31)
830 return Fail;
831 unsigned Register =
832 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
833 Inst.addOperand(MCOperand::createReg(Register));
834 return Success;
835}
836
837static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
838 uint64_t Addr,
839 const MCDisassembler *Decoder) {
840 if (RegNo > 31)
841 return Fail;
842 unsigned Register =
843 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
844 Inst.addOperand(MCOperand::createReg(Register));
845 return Success;
846}
847
848static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
849 uint64_t Addr,
850 const MCDisassembler *Decoder) {
851 if (RegNo > 31)
852 return Fail;
853 unsigned Register =
854 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
855 Inst.addOperand(MCOperand::createReg(Register));
856 return Success;
857}
858
859static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
860 uint64_t Addr,
861 const MCDisassembler *Decoder) {
862 if (RegNo > 31)
863 return Fail;
864 unsigned Register =
865 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
866 Inst.addOperand(MCOperand::createReg(Register));
867 return Success;
868}
869
870static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
871 uint64_t Addr,
872 const MCDisassembler *Decoder) {
873 if (RegNo > 31)
874 return Fail;
875 unsigned Register =
876 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
877 Inst.addOperand(MCOperand::createReg(Register));
878 return Success;
879}
880
881static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
882 uint64_t Addr,
883 const MCDisassembler *Decoder) {
884 if (RegNo > 31)
885 return Fail;
886 unsigned Register =
887 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
888 Inst.addOperand(MCOperand::createReg(Register));
889 return Success;
890}
891
892static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
893 uint64_t Addr,
894 const MCDisassembler *Decoder) {
895 // scale{5} is asserted as 1 in tblgen.
896 Imm |= 0x20;
897 Inst.addOperand(MCOperand::createImm(64 - Imm));
898 return Success;
899}
900
901static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
902 uint64_t Addr,
903 const MCDisassembler *Decoder) {
904 Inst.addOperand(MCOperand::createImm(64 - Imm));
905 return Success;
906}
907
908static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
909 uint64_t Addr,
910 const MCDisassembler *Decoder) {
911 // Immediate is encoded as the top 16-bits of an unsigned 18-bit negative
912 // PC-relative offset.
913 uint64_t ImmVal = Imm;
914 if (ImmVal > (1 << 16))
915 return Fail;
916 ImmVal = -ImmVal;
917 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal << 2), Addr,
918 /*IsBranch=*/false, 0, 0, 4))
919 Inst.addOperand(MCOperand::createImm(ImmVal));
920 return Success;
921}
922
923static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
924 uint64_t Addr,
925 const MCDisassembler *Decoder) {
926 int64_t ImmVal = Imm;
927
928 // Sign-extend 19-bit immediate.
929 if (ImmVal & (1 << (19 - 1)))
930 ImmVal |= ~((1LL << 19) - 1);
931
932 if (!Decoder->tryAddingSymbolicOperand(
933 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
934 Inst.addOperand(MCOperand::createImm(ImmVal));
935 return Success;
936}
937
938static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
939 uint64_t Address,
940 const MCDisassembler *Decoder) {
941 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
942 Inst.addOperand(MCOperand::createImm(Imm & 1));
943 return Success;
944}
945
946static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
947 uint64_t Address,
948 const MCDisassembler *Decoder) {
949 Inst.addOperand(MCOperand::createImm(Imm));
950
951 // Every system register in the encoding space is valid with the syntax
952 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
953 return Success;
954}
955
956static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
957 uint64_t Address,
958 const MCDisassembler *Decoder) {
959 Inst.addOperand(MCOperand::createImm(Imm));
960
961 return Success;
962}
963
964static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
965 uint64_t Address,
966 const MCDisassembler *Decoder) {
967 // This decoder exists to add the dummy Lane operand to the MCInst, which must
968 // be 1 in assembly but has no other real manifestation.
969 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
970 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
971 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
972
973 if (IsToVec) {
974 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
975 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
976 } else {
977 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
978 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
979 }
980
981 // Add the lane
982 Inst.addOperand(MCOperand::createImm(1));
983
984 return Success;
985}
986
987static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
988 unsigned Add) {
989 Inst.addOperand(MCOperand::createImm(Add - Imm));
990 return Success;
991}
992
993static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
994 unsigned Add) {
995 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
996 return Success;
997}
998
999static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
1000 uint64_t Addr,
1001 const MCDisassembler *Decoder) {
1002 return DecodeVecShiftRImm(Inst, Imm, 64);
1003}
1004
1005static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
1006 uint64_t Addr,
1007 const MCDisassembler *Decoder) {
1008 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
1009}
1010
1011static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
1012 uint64_t Addr,
1013 const MCDisassembler *Decoder) {
1014 return DecodeVecShiftRImm(Inst, Imm, 32);
1015}
1016
1017static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
1018 uint64_t Addr,
1019 const MCDisassembler *Decoder) {
1020 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
1021}
1022
1023static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
1024 uint64_t Addr,
1025 const MCDisassembler *Decoder) {
1026 return DecodeVecShiftRImm(Inst, Imm, 16);
1027}
1028
1029static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
1030 uint64_t Addr,
1031 const MCDisassembler *Decoder) {
1032 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
1033}
1034
1035static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
1036 uint64_t Addr,
1037 const MCDisassembler *Decoder) {
1038 return DecodeVecShiftRImm(Inst, Imm, 8);
1039}
1040
1041static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
1042 uint64_t Addr,
1043 const MCDisassembler *Decoder) {
1044 return DecodeVecShiftLImm(Inst, Imm, 64);
1045}
1046
1047static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
1048 uint64_t Addr,
1049 const MCDisassembler *Decoder) {
1050 return DecodeVecShiftLImm(Inst, Imm, 32);
1051}
1052
1053static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
1054 uint64_t Addr,
1055 const MCDisassembler *Decoder) {
1056 return DecodeVecShiftLImm(Inst, Imm, 16);
1057}
1058
1059static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
1060 uint64_t Addr,
1061 const MCDisassembler *Decoder) {
1062 return DecodeVecShiftLImm(Inst, Imm, 8);
1063}
1064
1065static DecodeStatus
1066DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1067 const MCDisassembler *Decoder) {
1068 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1069 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1070 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1071 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1072 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1073 unsigned shift = (shiftHi << 6) | shiftLo;
1074 switch (Inst.getOpcode()) {
1075 default:
1076 return Fail;
1077 case AArch64::ADDWrs:
1078 case AArch64::ADDSWrs:
1079 case AArch64::SUBWrs:
1080 case AArch64::SUBSWrs:
1081 // if shift == '11' then ReservedValue()
1082 if (shiftHi == 0x3)
1083 return Fail;
1084 [[fallthrough]];
1085 case AArch64::ANDWrs:
1086 case AArch64::ANDSWrs:
1087 case AArch64::BICWrs:
1088 case AArch64::BICSWrs:
1089 case AArch64::ORRWrs:
1090 case AArch64::ORNWrs:
1091 case AArch64::EORWrs:
1092 case AArch64::EONWrs: {
1093 // if sf == '0' and imm6<5> == '1' then ReservedValue()
1094 if (shiftLo >> 5 == 1)
1095 return Fail;
1096 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1097 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1098 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1099 break;
1100 }
1101 case AArch64::ADDXrs:
1102 case AArch64::ADDSXrs:
1103 case AArch64::SUBXrs:
1104 case AArch64::SUBSXrs:
1105 // if shift == '11' then ReservedValue()
1106 if (shiftHi == 0x3)
1107 return Fail;
1108 [[fallthrough]];
1109 case AArch64::ANDXrs:
1110 case AArch64::ANDSXrs:
1111 case AArch64::BICXrs:
1112 case AArch64::BICSXrs:
1113 case AArch64::ORRXrs:
1114 case AArch64::ORNXrs:
1115 case AArch64::EORXrs:
1116 case AArch64::EONXrs:
1117 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1118 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1119 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1120 break;
1121 }
1122
1123 Inst.addOperand(MCOperand::createImm(shift));
1124 return Success;
1125}
1126
1127static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
1128 uint64_t Addr,
1129 const MCDisassembler *Decoder) {
1130 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1131 unsigned imm = fieldFromInstruction(insn, 5, 16);
1132 unsigned shift = fieldFromInstruction(insn, 21, 2);
1133 shift <<= 4;
1134 switch (Inst.getOpcode()) {
1135 default:
1136 return Fail;
1137 case AArch64::MOVZWi:
1138 case AArch64::MOVNWi:
1139 case AArch64::MOVKWi:
1140 if (shift & (1U << 5))
1141 return Fail;
1142 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1143 break;
1144 case AArch64::MOVZXi:
1145 case AArch64::MOVNXi:
1146 case AArch64::MOVKXi:
1147 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1148 break;
1149 }
1150
1151 if (Inst.getOpcode() == AArch64::MOVKWi ||
1152 Inst.getOpcode() == AArch64::MOVKXi)
1153 Inst.addOperand(Inst.getOperand(0));
1154
1155 Inst.addOperand(MCOperand::createImm(imm));
1156 Inst.addOperand(MCOperand::createImm(shift));
1157 return Success;
1158}
1159
1160static DecodeStatus
1161DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1162 const MCDisassembler *Decoder) {
1163 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1164 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1165 unsigned offset = fieldFromInstruction(insn, 10, 12);
1166
1167 switch (Inst.getOpcode()) {
1168 default:
1169 return Fail;
1170 case AArch64::PRFMui:
1171 // Rt is an immediate in prefetch.
1172 Inst.addOperand(MCOperand::createImm(Rt));
1173 break;
1174 case AArch64::STRBBui:
1175 case AArch64::LDRBBui:
1176 case AArch64::LDRSBWui:
1177 case AArch64::STRHHui:
1178 case AArch64::LDRHHui:
1179 case AArch64::LDRSHWui:
1180 case AArch64::STRWui:
1181 case AArch64::LDRWui:
1182 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1183 break;
1184 case AArch64::LDRSBXui:
1185 case AArch64::LDRSHXui:
1186 case AArch64::LDRSWui:
1187 case AArch64::STRXui:
1188 case AArch64::LDRXui:
1189 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1190 break;
1191 case AArch64::LDRQui:
1192 case AArch64::STRQui:
1193 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1194 break;
1195 case AArch64::LDRDui:
1196 case AArch64::STRDui:
1197 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1198 break;
1199 case AArch64::LDRSui:
1200 case AArch64::STRSui:
1201 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1202 break;
1203 case AArch64::LDRHui:
1204 case AArch64::STRHui:
1205 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1206 break;
1207 case AArch64::LDRBui:
1208 case AArch64::STRBui:
1209 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1210 break;
1211 }
1212
1213 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1214 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
1215 Inst.addOperand(MCOperand::createImm(offset));
1216 return Success;
1217}
1218
1219static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1220 uint64_t Addr,
1221 const MCDisassembler *Decoder) {
1222 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1223 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1224 int64_t offset = fieldFromInstruction(insn, 12, 9);
1225
1226 // offset is a 9-bit signed immediate, so sign extend it to
1227 // fill the unsigned.
1228 if (offset & (1 << (9 - 1)))
1229 offset |= ~((1LL << 9) - 1);
1230
1231 // First operand is always the writeback to the address register, if needed.
1232 switch (Inst.getOpcode()) {
1233 default:
1234 break;
1235 case AArch64::LDRSBWpre:
1236 case AArch64::LDRSHWpre:
1237 case AArch64::STRBBpre:
1238 case AArch64::LDRBBpre:
1239 case AArch64::STRHHpre:
1240 case AArch64::LDRHHpre:
1241 case AArch64::STRWpre:
1242 case AArch64::LDRWpre:
1243 case AArch64::LDRSBWpost:
1244 case AArch64::LDRSHWpost:
1245 case AArch64::STRBBpost:
1246 case AArch64::LDRBBpost:
1247 case AArch64::STRHHpost:
1248 case AArch64::LDRHHpost:
1249 case AArch64::STRWpost:
1250 case AArch64::LDRWpost:
1251 case AArch64::LDRSBXpre:
1252 case AArch64::LDRSHXpre:
1253 case AArch64::STRXpre:
1254 case AArch64::LDRSWpre:
1255 case AArch64::LDRXpre:
1256 case AArch64::LDRSBXpost:
1257 case AArch64::LDRSHXpost:
1258 case AArch64::STRXpost:
1259 case AArch64::LDRSWpost:
1260 case AArch64::LDRXpost:
1261 case AArch64::LDRQpre:
1262 case AArch64::STRQpre:
1263 case AArch64::LDRQpost:
1264 case AArch64::STRQpost:
1265 case AArch64::LDRDpre:
1266 case AArch64::STRDpre:
1267 case AArch64::LDRDpost:
1268 case AArch64::STRDpost:
1269 case AArch64::LDRSpre:
1270 case AArch64::STRSpre:
1271 case AArch64::LDRSpost:
1272 case AArch64::STRSpost:
1273 case AArch64::LDRHpre:
1274 case AArch64::STRHpre:
1275 case AArch64::LDRHpost:
1276 case AArch64::STRHpost:
1277 case AArch64::LDRBpre:
1278 case AArch64::STRBpre:
1279 case AArch64::LDRBpost:
1280 case AArch64::STRBpost:
1281 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1282 break;
1283 }
1284
1285 switch (Inst.getOpcode()) {
1286 default:
1287 return Fail;
1288 case AArch64::PRFUMi:
1289 // Rt is an immediate in prefetch.
1290 Inst.addOperand(MCOperand::createImm(Rt));
1291 break;
1292 case AArch64::STURBBi:
1293 case AArch64::LDURBBi:
1294 case AArch64::LDURSBWi:
1295 case AArch64::STURHHi:
1296 case AArch64::LDURHHi:
1297 case AArch64::LDURSHWi:
1298 case AArch64::STURWi:
1299 case AArch64::LDURWi:
1300 case AArch64::LDTRSBWi:
1301 case AArch64::LDTRSHWi:
1302 case AArch64::STTRWi:
1303 case AArch64::LDTRWi:
1304 case AArch64::STTRHi:
1305 case AArch64::LDTRHi:
1306 case AArch64::LDTRBi:
1307 case AArch64::STTRBi:
1308 case AArch64::LDRSBWpre:
1309 case AArch64::LDRSHWpre:
1310 case AArch64::STRBBpre:
1311 case AArch64::LDRBBpre:
1312 case AArch64::STRHHpre:
1313 case AArch64::LDRHHpre:
1314 case AArch64::STRWpre:
1315 case AArch64::LDRWpre:
1316 case AArch64::LDRSBWpost:
1317 case AArch64::LDRSHWpost:
1318 case AArch64::STRBBpost:
1319 case AArch64::LDRBBpost:
1320 case AArch64::STRHHpost:
1321 case AArch64::LDRHHpost:
1322 case AArch64::STRWpost:
1323 case AArch64::LDRWpost:
1324 case AArch64::STLURBi:
1325 case AArch64::STLURHi:
1326 case AArch64::STLURWi:
1327 case AArch64::LDAPURBi:
1328 case AArch64::LDAPURSBWi:
1329 case AArch64::LDAPURHi:
1330 case AArch64::LDAPURSHWi:
1331 case AArch64::LDAPURi:
1332 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1333 break;
1334 case AArch64::LDURSBXi:
1335 case AArch64::LDURSHXi:
1336 case AArch64::LDURSWi:
1337 case AArch64::STURXi:
1338 case AArch64::LDURXi:
1339 case AArch64::LDTRSBXi:
1340 case AArch64::LDTRSHXi:
1341 case AArch64::LDTRSWi:
1342 case AArch64::STTRXi:
1343 case AArch64::LDTRXi:
1344 case AArch64::LDRSBXpre:
1345 case AArch64::LDRSHXpre:
1346 case AArch64::STRXpre:
1347 case AArch64::LDRSWpre:
1348 case AArch64::LDRXpre:
1349 case AArch64::LDRSBXpost:
1350 case AArch64::LDRSHXpost:
1351 case AArch64::STRXpost:
1352 case AArch64::LDRSWpost:
1353 case AArch64::LDRXpost:
1354 case AArch64::LDAPURSWi:
1355 case AArch64::LDAPURSHXi:
1356 case AArch64::LDAPURSBXi:
1357 case AArch64::STLURXi:
1358 case AArch64::LDAPURXi:
1359 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1360 break;
1361 case AArch64::LDURQi:
1362 case AArch64::STURQi:
1363 case AArch64::LDRQpre:
1364 case AArch64::STRQpre:
1365 case AArch64::LDRQpost:
1366 case AArch64::STRQpost:
1367 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1368 break;
1369 case AArch64::LDURDi:
1370 case AArch64::STURDi:
1371 case AArch64::LDRDpre:
1372 case AArch64::STRDpre:
1373 case AArch64::LDRDpost:
1374 case AArch64::STRDpost:
1375 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1376 break;
1377 case AArch64::LDURSi:
1378 case AArch64::STURSi:
1379 case AArch64::LDRSpre:
1380 case AArch64::STRSpre:
1381 case AArch64::LDRSpost:
1382 case AArch64::STRSpost:
1383 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1384 break;
1385 case AArch64::LDURHi:
1386 case AArch64::STURHi:
1387 case AArch64::LDRHpre:
1388 case AArch64::STRHpre:
1389 case AArch64::LDRHpost:
1390 case AArch64::STRHpost:
1391 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1392 break;
1393 case AArch64::LDURBi:
1394 case AArch64::STURBi:
1395 case AArch64::LDRBpre:
1396 case AArch64::STRBpre:
1397 case AArch64::LDRBpost:
1398 case AArch64::STRBpost:
1399 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1400 break;
1401 }
1402
1403 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1404 Inst.addOperand(MCOperand::createImm(offset));
1405
1406 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1407 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1408 bool IsFP = fieldFromInstruction(insn, 26, 1);
1409
1410 // Cannot write back to a transfer register (but xzr != sp).
1411 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1412 return SoftFail;
1413
1414 return Success;
1415}
1416
1417static DecodeStatus
1418DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1419 const MCDisassembler *Decoder) {
1420 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1421 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1422 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1423 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1424
1425 unsigned Opcode = Inst.getOpcode();
1426 switch (Opcode) {
1427 default:
1428 return Fail;
1429 case AArch64::STLXRW:
1430 case AArch64::STLXRB:
1431 case AArch64::STLXRH:
1432 case AArch64::STXRW:
1433 case AArch64::STXRB:
1434 case AArch64::STXRH:
1435 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1436 [[fallthrough]];
1437 case AArch64::LDARW:
1438 case AArch64::LDARB:
1439 case AArch64::LDARH:
1440 case AArch64::LDAXRW:
1441 case AArch64::LDAXRB:
1442 case AArch64::LDAXRH:
1443 case AArch64::LDXRW:
1444 case AArch64::LDXRB:
1445 case AArch64::LDXRH:
1446 case AArch64::STLRW:
1447 case AArch64::STLRB:
1448 case AArch64::STLRH:
1449 case AArch64::STLLRW:
1450 case AArch64::STLLRB:
1451 case AArch64::STLLRH:
1452 case AArch64::LDLARW:
1453 case AArch64::LDLARB:
1454 case AArch64::LDLARH:
1455 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1456 break;
1457 case AArch64::STLXRX:
1458 case AArch64::STXRX:
1459 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1460 [[fallthrough]];
1461 case AArch64::LDARX:
1462 case AArch64::LDAXRX:
1463 case AArch64::LDXRX:
1464 case AArch64::STLRX:
1465 case AArch64::LDLARX:
1466 case AArch64::STLLRX:
1467 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1468 break;
1469 case AArch64::STLXPW:
1470 case AArch64::STXPW:
1471 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1472 [[fallthrough]];
1473 case AArch64::LDAXPW:
1474 case AArch64::LDXPW:
1475 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1476 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1477 break;
1478 case AArch64::STLXPX:
1479 case AArch64::STXPX:
1480 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1481 [[fallthrough]];
1482 case AArch64::LDAXPX:
1483 case AArch64::LDXPX:
1484 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1485 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1486 break;
1487 }
1488
1489 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1490
1491 // You shouldn't load to the same register twice in an instruction...
1492 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1493 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1494 Rt == Rt2)
1495 return SoftFail;
1496
1497 return Success;
1498}
1499
1500static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1501 uint64_t Addr,
1502 const MCDisassembler *Decoder) {
1503 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1504 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1505 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1506 int64_t offset = fieldFromInstruction(insn, 15, 7);
1507 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1508
1509 // offset is a 7-bit signed immediate, so sign extend it to
1510 // fill the unsigned.
1511 if (offset & (1 << (7 - 1)))
1512 offset |= ~((1LL << 7) - 1);
1513
1514 unsigned Opcode = Inst.getOpcode();
1515 bool NeedsDisjointWritebackTransfer = false;
1516
1517 // First operand is always writeback of base register.
1518 switch (Opcode) {
1519 default:
1520 break;
1521 case AArch64::LDPXpost:
1522 case AArch64::STPXpost:
1523 case AArch64::LDPSWpost:
1524 case AArch64::LDPXpre:
1525 case AArch64::STPXpre:
1526 case AArch64::LDPSWpre:
1527 case AArch64::LDPWpost:
1528 case AArch64::STPWpost:
1529 case AArch64::LDPWpre:
1530 case AArch64::STPWpre:
1531 case AArch64::LDPQpost:
1532 case AArch64::STPQpost:
1533 case AArch64::LDPQpre:
1534 case AArch64::STPQpre:
1535 case AArch64::LDPDpost:
1536 case AArch64::STPDpost:
1537 case AArch64::LDPDpre:
1538 case AArch64::STPDpre:
1539 case AArch64::LDPSpost:
1540 case AArch64::STPSpost:
1541 case AArch64::LDPSpre:
1542 case AArch64::STPSpre:
1543 case AArch64::STGPpre:
1544 case AArch64::STGPpost:
1545 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1546 break;
1547 }
1548
1549 switch (Opcode) {
1550 default:
1551 return Fail;
1552 case AArch64::LDPXpost:
1553 case AArch64::STPXpost:
1554 case AArch64::LDPSWpost:
1555 case AArch64::LDPXpre:
1556 case AArch64::STPXpre:
1557 case AArch64::LDPSWpre:
1558 case AArch64::STGPpre:
1559 case AArch64::STGPpost:
1560 NeedsDisjointWritebackTransfer = true;
1561 [[fallthrough]];
1562 case AArch64::LDNPXi:
1563 case AArch64::STNPXi:
1564 case AArch64::LDPXi:
1565 case AArch64::STPXi:
1566 case AArch64::LDPSWi:
1567 case AArch64::STGPi:
1568 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1569 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1570 break;
1571 case AArch64::LDPWpost:
1572 case AArch64::STPWpost:
1573 case AArch64::LDPWpre:
1574 case AArch64::STPWpre:
1575 NeedsDisjointWritebackTransfer = true;
1576 [[fallthrough]];
1577 case AArch64::LDNPWi:
1578 case AArch64::STNPWi:
1579 case AArch64::LDPWi:
1580 case AArch64::STPWi:
1581 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1582 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1583 break;
1584 case AArch64::LDNPQi:
1585 case AArch64::STNPQi:
1586 case AArch64::LDPQpost:
1587 case AArch64::STPQpost:
1588 case AArch64::LDPQi:
1589 case AArch64::STPQi:
1590 case AArch64::LDPQpre:
1591 case AArch64::STPQpre:
1592 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1593 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1594 break;
1595 case AArch64::LDNPDi:
1596 case AArch64::STNPDi:
1597 case AArch64::LDPDpost:
1598 case AArch64::STPDpost:
1599 case AArch64::LDPDi:
1600 case AArch64::STPDi:
1601 case AArch64::LDPDpre:
1602 case AArch64::STPDpre:
1603 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1604 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1605 break;
1606 case AArch64::LDNPSi:
1607 case AArch64::STNPSi:
1608 case AArch64::LDPSpost:
1609 case AArch64::STPSpost:
1610 case AArch64::LDPSi:
1611 case AArch64::STPSi:
1612 case AArch64::LDPSpre:
1613 case AArch64::STPSpre:
1614 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1615 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1616 break;
1617 }
1618
1619 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1620 Inst.addOperand(MCOperand::createImm(offset));
1621
1622 // You shouldn't load to the same register twice in an instruction...
1623 if (IsLoad && Rt == Rt2)
1624 return SoftFail;
1625
1626 // ... or do any operation that writes-back to a transfer register. But note
1627 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1628 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1629 return SoftFail;
1630
1631 return Success;
1632}
1633
1634static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1635 uint64_t Addr,
1636 const MCDisassembler *Decoder) {
1637 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1638 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1639 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1640 fieldFromInstruction(insn, 12, 9);
1641 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1642
1643 switch (Inst.getOpcode()) {
1644 default:
1645 return Fail;
1646 case AArch64::LDRAAwriteback:
1647 case AArch64::LDRABwriteback:
1648 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1649 Decoder);
1650 break;
1651 case AArch64::LDRAAindexed:
1652 case AArch64::LDRABindexed:
1653 break;
1654 }
1655
1656 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1657 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1658 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1659
1660 if (writeback && Rt == Rn && Rn != 31) {
1661 return SoftFail;
1662 }
1663
1664 return Success;
1665}
1666
1667static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1668 uint64_t Addr,
1669 const MCDisassembler *Decoder) {
1670 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1671 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1672 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1673 unsigned extend = fieldFromInstruction(insn, 10, 6);
1674
1675 unsigned shift = extend & 0x7;
1676 if (shift > 4)
1677 return Fail;
1678
1679 switch (Inst.getOpcode()) {
1680 default:
1681 return Fail;
1682 case AArch64::ADDWrx:
1683 case AArch64::SUBWrx:
1684 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1685 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1686 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1687 break;
1688 case AArch64::ADDSWrx:
1689 case AArch64::SUBSWrx:
1690 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1691 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1692 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1693 break;
1694 case AArch64::ADDXrx:
1695 case AArch64::SUBXrx:
1696 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1697 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1698 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1699 break;
1700 case AArch64::ADDSXrx:
1701 case AArch64::SUBSXrx:
1702 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1703 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1704 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1705 break;
1706 case AArch64::ADDXrx64:
1707 case AArch64::SUBXrx64:
1708 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1709 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1710 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1711 break;
1712 case AArch64::SUBSXrx64:
1713 case AArch64::ADDSXrx64:
1714 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1715 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1716 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1717 break;
1718 }
1719
1720 Inst.addOperand(MCOperand::createImm(extend));
1721 return Success;
1722}
1723
1724static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1725 uint64_t Addr,
1726 const MCDisassembler *Decoder) {
1727 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1728 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1729 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1730 unsigned imm;
1731
1732 if (Datasize) {
1733 if (Inst.getOpcode() == AArch64::ANDSXri)
1734 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1735 else
1736 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1737 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1738 imm = fieldFromInstruction(insn, 10, 13);
1739 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1740 return Fail;
1741 } else {
1742 if (Inst.getOpcode() == AArch64::ANDSWri)
1743 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1744 else
1745 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1746 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1747 imm = fieldFromInstruction(insn, 10, 12);
1748 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1749 return Fail;
1750 }
1751 Inst.addOperand(MCOperand::createImm(imm));
1752 return Success;
1753}
1754
1755static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1756 uint64_t Addr,
1757 const MCDisassembler *Decoder) {
1758 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1759 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1760 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1761 imm |= fieldFromInstruction(insn, 5, 5);
1762
1763 if (Inst.getOpcode() == AArch64::MOVID)
1764 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1765 else
1766 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1767
1768 Inst.addOperand(MCOperand::createImm(imm));
1769
1770 switch (Inst.getOpcode()) {
1771 default:
1772 break;
1773 case AArch64::MOVIv4i16:
1774 case AArch64::MOVIv8i16:
1775 case AArch64::MVNIv4i16:
1776 case AArch64::MVNIv8i16:
1777 case AArch64::MOVIv2i32:
1778 case AArch64::MOVIv4i32:
1779 case AArch64::MVNIv2i32:
1780 case AArch64::MVNIv4i32:
1781 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1782 break;
1783 case AArch64::MOVIv2s_msl:
1784 case AArch64::MOVIv4s_msl:
1785 case AArch64::MVNIv2s_msl:
1786 case AArch64::MVNIv4s_msl:
1787 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1788 break;
1789 }
1790
1791 return Success;
1792}
1793
1794static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1795 uint64_t Addr,
1796 const MCDisassembler *Decoder) {
1797 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1798 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1799 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1800 imm |= fieldFromInstruction(insn, 5, 5);
1801
1802 // Tied operands added twice.
1803 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1804 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1805
1806 Inst.addOperand(MCOperand::createImm(imm));
1807 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1808
1809 return Success;
1810}
1811
1812static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1813 uint64_t Addr,
1814 const MCDisassembler *Decoder) {
1815 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1816 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1817 imm |= fieldFromInstruction(insn, 29, 2);
1818
1819 // Sign-extend the 21-bit immediate.
1820 if (imm & (1 << (21 - 1)))
1821 imm |= ~((1LL << 21) - 1);
1822
1823 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1824 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1825 Inst.addOperand(MCOperand::createImm(imm));
1826
1827 return Success;
1828}
1829
1830static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1831 uint64_t Addr,
1832 const MCDisassembler *Decoder) {
1833 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1834 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1835 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1836 unsigned S = fieldFromInstruction(insn, 29, 1);
1837 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1838
1839 unsigned ShifterVal = (Imm >> 12) & 3;
1840 unsigned ImmVal = Imm & 0xFFF;
1841
1842 if (ShifterVal != 0 && ShifterVal != 1)
1843 return Fail;
1844
1845 if (Datasize) {
1846 if (Rd == 31 && !S)
1847 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1848 else
1849 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1850 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1851 } else {
1852 if (Rd == 31 && !S)
1853 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1854 else
1855 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1856 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1857 }
1858
1859 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1860 Inst.addOperand(MCOperand::createImm(ImmVal));
1861 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1862 return Success;
1863}
1864
1865static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1866 uint64_t Addr,
1867 const MCDisassembler *Decoder) {
1868 int64_t imm = fieldFromInstruction(insn, 0, 26);
1869
1870 // Sign-extend the 26-bit immediate.
1871 if (imm & (1 << (26 - 1)))
1872 imm |= ~((1LL << 26) - 1);
1873
1874 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1875 Inst.addOperand(MCOperand::createImm(imm));
1876
1877 return Success;
1878}
1879
1880static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1881 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1882 Op2 == 0b001 || // XAFlag
1883 Op2 == 0b010); // AXFlag
1884}
1885
1886static DecodeStatus
1887DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1888 const MCDisassembler *Decoder) {
1889 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1890 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1891 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1892 uint64_t pstate_field = (op1 << 3) | op2;
1893
1894 if (isInvalidPState(op1, op2))
1895 return Fail;
1896
1897 Inst.addOperand(MCOperand::createImm(pstate_field));
1898 Inst.addOperand(MCOperand::createImm(imm));
1899
1900 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1901 if (PState &&
1902 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1903 return Success;
1904 return Fail;
1905}
1906
1907static DecodeStatus
1908DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1909 const MCDisassembler *Decoder) {
1910 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1911 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1912 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1913 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1914 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1915
1916 if (isInvalidPState(op1, op2))
1917 return Fail;
1918
1919 Inst.addOperand(MCOperand::createImm(pstate_field));
1920 Inst.addOperand(MCOperand::createImm(imm));
1921
1922 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1923 if (PState &&
1924 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1925 return Success;
1926 return Fail;
1927}
1928
1929static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1930 uint64_t Addr,
1931 const MCDisassembler *Decoder) {
1932 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1933 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1934 bit |= fieldFromInstruction(insn, 19, 5);
1935 int64_t dst = fieldFromInstruction(insn, 5, 14);
1936
1937 // Sign-extend 14-bit immediate.
1938 if (dst & (1 << (14 - 1)))
1939 dst |= ~((1LL << 14) - 1);
1940
1941 if (fieldFromInstruction(insn, 31, 1) == 0)
1942 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1943 else
1944 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1945 Inst.addOperand(MCOperand::createImm(bit));
1946 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1947 Inst.addOperand(MCOperand::createImm(dst));
1948
1949 return Success;
1950}
1951
1952static DecodeStatus
1953DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1954 unsigned RegNo, uint64_t Addr,
1955 const MCDisassembler *Decoder) {
1956 // Register number must be even (see CASP instruction)
1957 if (RegNo & 0x1)
1958 return Fail;
1959
1960 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1961 Inst.addOperand(MCOperand::createReg(Reg));
1962 return Success;
1963}
1964
1965static DecodeStatus
1966DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1967 const MCDisassembler *Decoder) {
1968 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1969 AArch64::WSeqPairsClassRegClassID,
1970 RegNo, Addr, Decoder);
1971}
1972
1973static DecodeStatus
1974DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1975 const MCDisassembler *Decoder) {
1976 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1977 AArch64::XSeqPairsClassRegClassID,
1978 RegNo, Addr, Decoder);
1979}
1980
1981static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1982 uint64_t Addr,
1983 const MCDisassembler *Decoder) {
1984 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1985 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1986 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1987 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1988 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1989 if (Rt != 0b11111)
1990 return Fail;
1991
1992 Inst.addOperand(MCOperand::createImm(op1));
1993 Inst.addOperand(MCOperand::createImm(CRn));
1994 Inst.addOperand(MCOperand::createImm(CRm));
1995 Inst.addOperand(MCOperand::createImm(op2));
1996 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1997
1998 return Success;
1999}
2000
2001static DecodeStatus
2002DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
2003 const MCDisassembler *Decoder) {
2004 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
2005 unsigned imm = fieldFromInstruction(insn, 5, 13);
2006 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
2007 return Fail;
2008
2009 // The same (tied) operand is added twice to the instruction.
2010 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
2011 if (Inst.getOpcode() != AArch64::DUPM_ZI)
2012 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
2013 Inst.addOperand(MCOperand::createImm(imm));
2014 return Success;
2015}
2016
2017template <int Bits>
2018static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
2019 const MCDisassembler *Decoder) {
2020 if (Imm & ~((1LL << Bits) - 1))
2021 return Fail;
2022
2023 // Imm is a signed immediate, so sign extend it.
2024 if (Imm & (1 << (Bits - 1)))
2025 Imm |= ~((1LL << Bits) - 1);
2026
2027 Inst.addOperand(MCOperand::createImm(Imm));
2028 return Success;
2029}
2030
2031// Decode 8-bit signed/unsigned immediate for a given element width.
2032template <int ElementWidth>
2033static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
2034 const MCDisassembler *Decoder) {
2035 unsigned Val = (uint8_t)Imm;
2036 unsigned Shift = (Imm & 0x100) ? 8 : 0;
2037 if (ElementWidth == 8 && Shift)
2038 return Fail;
2039 Inst.addOperand(MCOperand::createImm(Val));
2040 Inst.addOperand(MCOperand::createImm(Shift));
2041 return Success;
2042}
2043
2044// Decode uimm4 ranged from 1-16.
2045static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
2046 uint64_t Addr,
2047 const MCDisassembler *Decoder) {
2048 Inst.addOperand(MCOperand::createImm(Imm + 1));
2049 return Success;
2050}
2051
2052static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
2053 const MCDisassembler *Decoder) {
2054 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2055 Inst.addOperand(MCOperand::createImm(Imm));
2056 return Success;
2057 }
2058 return Fail;
2059}
2060
2061static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
2062 uint64_t Addr,
2063 const MCDisassembler *Decoder) {
2064 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2065 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2066 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2067
2068 // None of the registers may alias: if they do, then the instruction is not
2069 // merely unpredictable but actually entirely unallocated.
2070 if (Rd == Rs || Rs == Rn || Rd == Rn)
2071 return MCDisassembler::Fail;
2072
2073 // All three register operands are written back, so they all appear
2074 // twice in the operand list, once as outputs and once as inputs.
2075 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2076 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2077 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2078 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2079 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2080 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder))
2081 return MCDisassembler::Fail;
2082
2083 return MCDisassembler::Success;
2084}
2085
2086static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
2087 uint64_t Addr,
2088 const MCDisassembler *Decoder) {
2089 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2090 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2091 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2092
2093 // None of the registers may alias: if they do, then the instruction is not
2094 // merely unpredictable but actually entirely unallocated.
2095 if (Rd == Rm || Rm == Rn || Rd == Rn)
2096 return MCDisassembler::Fail;
2097
2098 // Rd and Rn (not Rm) register operands are written back, so they appear
2099 // twice in the operand list, once as outputs and once as inputs.
2100 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2101 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2102 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2103 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2104 !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder))
2105 return MCDisassembler::Fail;
2106
2107 return MCDisassembler::Success;
2108}
2109
2110static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
2111 uint64_t Addr,
2112 const MCDisassembler *Decoder) {
2113 // PRFM with Rt = '11xxx' should be decoded as RPRFM.
2114 // Fail to decode and defer to fallback decoder table to decode RPRFM.
2115 unsigned Mask = 0x18;
2116 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2117 if ((Rt & Mask) == Mask)
2118 return Fail;
2119
2120 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2121 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2122 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2123 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2124
2125 Inst.addOperand(MCOperand::createImm(Rt));
2126 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
2127
2128 switch (Inst.getOpcode()) {
2129 default:
2130 return Fail;
2131 case AArch64::PRFMroW:
2132 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
2133 break;
2134 case AArch64::PRFMroX:
2135 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
2136 break;
2137 }
2138
2139 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
2140
2141 return Success;
2142}
DecodePPRRegisterClass
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:759
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1865
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1041
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1047
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:397
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2061
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1035
DecodeQQQQRegisterClass
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:848
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:901
DecodeGPR32spRegisterClass
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:595
DecodePNRRegisterClass
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:771
DecodeFPR8RegisterClass
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:493
DecodeZPR4RegisterClass
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:657
DecodeFPR128_loRegisterClass
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:442
DecodeQQRegisterClass
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:826
DecodeZPR3RegisterClass
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:646
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1667
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1755
DecodeDDDRegisterClass
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:870
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1724
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1127
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1908
DecodeDDRegisterClass
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:859
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:316
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:531
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1161
DecodePPR2RegisterClass
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:803
MatrixZATileDecoderTable
static const MCPhysReg MatrixZATileDecoderTable[5][16]
Definition: AArch64Disassembler.cpp:724
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1974
DecodeGPR64commonRegisterClass
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:506
DecodeMatrixIndexGPR32_12_15RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:570
DecodeQQQRegisterClass
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:837
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:668
DecodeZPRRegisterClass
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:607
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1634
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1053
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1500
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:481
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:314
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:736
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2018
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1017
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:815
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1887
DecodeDDDDRegisterClass
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:881
DecodeGPR64spRegisterClass
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:545
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1059
DecodePCRelLabel16
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:908
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2045
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:892
DecodeFPR128_0to7RegisterClass
static DecodeStatus DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:450
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1929
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2002
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:987
DecodePNR_p8to15RegisterClass
static DecodeStatus DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:794
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:405
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:999
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:993
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1029
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:583
DecodePPR_3bRegisterClass
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:783
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2052
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1966
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1005
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:679
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1830
Fail
#define Fail
Definition: AArch64Disassembler.cpp:313
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:956
DecodeZPR2StridedRegisterClass
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:690
Success
#define Success
Definition: AArch64Disassembler.cpp:312
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2086
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:923
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1066
DecodeZPR4StridedRegisterClass
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:702
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:938
DecodeZPR_3bRegisterClass
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:627
DecodeMatrixIndexGPR32_8_11RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:557
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1219
DecodePPRorPNRRegisterClass
static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:747
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1418
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1981
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:964
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:518
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition: AArch64Disassembler.cpp:1880
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:715
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1812
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2110
DecodeZPR_4bRegisterClass
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:619
DecodeZPR2RegisterClass
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:635
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1023
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1011
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:469
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2033
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:429
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1953
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:946
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:457
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1794
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:158
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:113
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:323
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: AArch64Disassembler.cpp:388
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:81
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:84
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:217
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:200
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:224
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:108
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:154
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint32_t
uint64_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:321
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:61
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1090
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:988
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