LLVM 19.0.0git
AArch64TargetMachine.cpp
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1//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
13#include "AArch64.h"
17#include "AArch64MacroFusion.h"
18#include "AArch64Subtarget.h"
23#include "llvm/ADT/STLExtras.h"
37#include "llvm/CodeGen/Passes.h"
40#include "llvm/IR/Attributes.h"
41#include "llvm/IR/Function.h"
43#include "llvm/MC/MCAsmInfo.h"
46#include "llvm/Pass.h"
55#include <memory>
56#include <optional>
57#include <string>
58
59using namespace llvm;
60
61static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
62 cl::desc("Enable the CCMP formation pass"),
63 cl::init(true), cl::Hidden);
64
65static cl::opt<bool>
66 EnableCondBrTuning("aarch64-enable-cond-br-tune",
67 cl::desc("Enable the conditional branch tuning pass"),
68 cl::init(true), cl::Hidden);
69
71 "aarch64-enable-copy-propagation",
72 cl::desc("Enable the copy propagation with AArch64 copy instr"),
73 cl::init(true), cl::Hidden);
74
75static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
76 cl::desc("Enable the machine combiner pass"),
77 cl::init(true), cl::Hidden);
78
79static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
80 cl::desc("Suppress STP for AArch64"),
81 cl::init(true), cl::Hidden);
82
84 "aarch64-enable-simd-scalar",
85 cl::desc("Enable use of AdvSIMD scalar integer instructions"),
86 cl::init(false), cl::Hidden);
87
88static cl::opt<bool>
89 EnablePromoteConstant("aarch64-enable-promote-const",
90 cl::desc("Enable the promote constant pass"),
91 cl::init(true), cl::Hidden);
92
94 "aarch64-enable-collect-loh",
95 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
96 cl::init(true), cl::Hidden);
97
98static cl::opt<bool>
99 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
100 cl::desc("Enable the pass that removes dead"
101 " definitons and replaces stores to"
102 " them with stores to the zero"
103 " register"),
104 cl::init(true));
105
107 "aarch64-enable-copyelim",
108 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
109 cl::Hidden);
110
111static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
112 cl::desc("Enable the load/store pair"
113 " optimization pass"),
114 cl::init(true), cl::Hidden);
115
117 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
118 cl::desc("Run SimplifyCFG after expanding atomic operations"
119 " to make use of cmpxchg flow-based information"),
120 cl::init(true));
121
122static cl::opt<bool>
123EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
124 cl::desc("Run early if-conversion"),
125 cl::init(true));
126
127static cl::opt<bool>
128 EnableCondOpt("aarch64-enable-condopt",
129 cl::desc("Enable the condition optimizer pass"),
130 cl::init(true), cl::Hidden);
131
132static cl::opt<bool>
133 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
134 cl::desc("Enable optimizations on complex GEPs"),
135 cl::init(false));
136
137static cl::opt<bool>
138 EnableSelectOpt("aarch64-select-opt", cl::Hidden,
139 cl::desc("Enable select to branch optimizations"),
140 cl::init(true));
141
142static cl::opt<bool>
143 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
144 cl::desc("Relax out of range conditional branches"));
145
147 "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
148 cl::desc("Use smallest entry possible for jump tables"));
149
150// FIXME: Unify control over GlobalMerge.
152 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
153 cl::desc("Enable the global merge pass"));
154
155static cl::opt<bool>
156 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
157 cl::desc("Enable the loop data prefetch pass"),
158 cl::init(true));
159
161 "aarch64-enable-global-isel-at-O", cl::Hidden,
162 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
163 cl::init(0));
164
165static cl::opt<bool>
166 EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
167 cl::desc("Enable SVE intrinsic opts"),
168 cl::init(true));
169
170static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
171 cl::init(true), cl::Hidden);
172
173static cl::opt<bool>
174 EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
175 cl::desc("Enable the AArch64 branch target pass"),
176 cl::init(true));
177
179 "aarch64-sve-vector-bits-max",
180 cl::desc("Assume SVE vector registers are at most this big, "
181 "with zero meaning no maximum size is assumed."),
182 cl::init(0), cl::Hidden);
183
185 "aarch64-sve-vector-bits-min",
186 cl::desc("Assume SVE vector registers are at least this big, "
187 "with zero meaning no minimum size is assumed."),
188 cl::init(0), cl::Hidden);
189
191
193 "aarch64-enable-gisel-ldst-prelegal",
194 cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),
195 cl::init(true), cl::Hidden);
196
198 "aarch64-enable-gisel-ldst-postlegal",
199 cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),
200 cl::init(false), cl::Hidden);
201
202static cl::opt<bool>
203 EnableSinkFold("aarch64-enable-sink-fold",
204 cl::desc("Enable sinking and folding of instruction copies"),
205 cl::init(true), cl::Hidden);
206
207static cl::opt<bool>
208 EnableMachinePipeliner("aarch64-enable-pipeliner",
209 cl::desc("Enable Machine Pipeliner for AArch64"),
210 cl::init(false), cl::Hidden);
211
213 // Register the target.
257}
258
259//===----------------------------------------------------------------------===//
260// AArch64 Lowering public interface.
261//===----------------------------------------------------------------------===//
262static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
263 if (TT.isOSBinFormatMachO())
264 return std::make_unique<AArch64_MachoTargetObjectFile>();
265 if (TT.isOSBinFormatCOFF())
266 return std::make_unique<AArch64_COFFTargetObjectFile>();
267
268 return std::make_unique<AArch64_ELFTargetObjectFile>();
269}
270
271// Helper function to build a DataLayout string
272static std::string computeDataLayout(const Triple &TT,
274 bool LittleEndian) {
275 if (TT.isOSBinFormatMachO()) {
276 if (TT.getArch() == Triple::aarch64_32)
277 return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
278 return "e-m:o-i64:64-i128:128-n32:64-S128";
279 }
280 if (TT.isOSBinFormatCOFF())
281 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
282 std::string Endian = LittleEndian ? "e" : "E";
283 std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
284 return Endian + "-m:e" + Ptr32 +
285 "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
286}
287
289 if (CPU.empty() && TT.isArm64e())
290 return "apple-a12";
291 return CPU;
292}
293
295 std::optional<Reloc::Model> RM) {
296 // AArch64 Darwin and Windows are always PIC.
297 if (TT.isOSDarwin() || TT.isOSWindows())
298 return Reloc::PIC_;
299 // On ELF platforms the default static relocation model has a smart enough
300 // linker to cope with referencing external symbols defined in a shared
301 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
302 if (!RM || *RM == Reloc::DynamicNoPIC)
303 return Reloc::Static;
304 return *RM;
305}
306
307static CodeModel::Model
309 std::optional<CodeModel::Model> CM, bool JIT) {
310 if (CM) {
311 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
312 *CM != CodeModel::Large) {
314 "Only small, tiny and large code models are allowed on AArch64");
315 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
316 report_fatal_error("tiny code model is only supported on ELF");
317 return *CM;
318 }
319 // The default MCJIT memory managers make no guarantees about where they can
320 // find an executable page; JITed code needs to be able to refer to globals
321 // no matter how far away they are.
322 // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
323 // since with large code model LLVM generating 4 MOV instructions, and
324 // Windows doesn't support relocating these long branch (4 MOVs).
325 if (JIT && !TT.isOSWindows())
326 return CodeModel::Large;
327 return CodeModel::Small;
328}
329
330/// Create an AArch64 architecture model.
331///
333 StringRef CPU, StringRef FS,
334 const TargetOptions &Options,
335 std::optional<Reloc::Model> RM,
336 std::optional<CodeModel::Model> CM,
337 CodeGenOptLevel OL, bool JIT,
338 bool LittleEndian)
340 computeDataLayout(TT, Options.MCOptions, LittleEndian),
341 TT, computeDefaultCPU(TT, CPU), FS, Options,
343 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
344 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
345 initAsmInfo();
346
347 if (TT.isOSBinFormatMachO()) {
348 this->Options.TrapUnreachable = true;
349 this->Options.NoTrapAfterNoreturn = true;
350 }
351
352 if (getMCAsmInfo()->usesWindowsCFI()) {
353 // Unwinding can get confused if the last instruction in an
354 // exception-handling region (function, funclet, try block, etc.)
355 // is a call.
356 //
357 // FIXME: We could elide the trap if the next instruction would be in
358 // the same region anyway.
359 this->Options.TrapUnreachable = true;
360 }
361
362 if (this->Options.TLSSize == 0) // default
363 this->Options.TLSSize = 24;
364 if ((getCodeModel() == CodeModel::Small ||
366 this->Options.TLSSize > 32)
367 // for the small (and kernel) code model, the maximum TLS size is 4GiB
368 this->Options.TLSSize = 32;
369 else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
370 // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
371 this->Options.TLSSize = 24;
372
373 // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
374 // MachO/CodeModel::Large, which GlobalISel does not support.
375 if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO &&
376 TT.getArch() != Triple::aarch64_32 &&
377 TT.getEnvironment() != Triple::GNUILP32 &&
378 !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
379 setGlobalISel(true);
381 }
382
383 // AArch64 supports the MachineOutliner.
384 setMachineOutliner(true);
385
386 // AArch64 supports default outlining behaviour.
388
389 // AArch64 supports the debug entry values.
391
392 // AArch64 supports fixing up the DWARF unwind information.
393 if (!getMCAsmInfo()->usesWindowsCFI())
394 setCFIFixup(true);
395}
396
398
399const AArch64Subtarget *
401 Attribute CPUAttr = F.getFnAttribute("target-cpu");
402 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
403 Attribute FSAttr = F.getFnAttribute("target-features");
404
405 StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;
406 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU;
407 StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;
408 bool HasMinSize = F.hasMinSize();
409
410 bool StreamingSVEMode = F.hasFnAttribute("aarch64_pstate_sm_enabled") ||
411 F.hasFnAttribute("aarch64_pstate_sm_body");
412 bool StreamingCompatibleSVEMode =
413 F.hasFnAttribute("aarch64_pstate_sm_compatible");
414
415 unsigned MinSVEVectorSize = 0;
416 unsigned MaxSVEVectorSize = 0;
417 if (F.hasFnAttribute(Attribute::VScaleRange)) {
418 ConstantRange CR = getVScaleRange(&F, 64);
419 MinSVEVectorSize = CR.getUnsignedMin().getZExtValue() * 128;
420 MaxSVEVectorSize = CR.getUnsignedMax().getZExtValue() * 128;
421 } else {
422 MinSVEVectorSize = SVEVectorBitsMinOpt;
423 MaxSVEVectorSize = SVEVectorBitsMaxOpt;
424 }
425
426 assert(MinSVEVectorSize % 128 == 0 &&
427 "SVE requires vector length in multiples of 128!");
428 assert(MaxSVEVectorSize % 128 == 0 &&
429 "SVE requires vector length in multiples of 128!");
430 assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
431 "Minimum SVE vector size should not be larger than its maximum!");
432
433 // Sanitize user input in case of no asserts
434 if (MaxSVEVectorSize != 0) {
435 MinSVEVectorSize = std::min(MinSVEVectorSize, MaxSVEVectorSize);
436 MaxSVEVectorSize = std::max(MinSVEVectorSize, MaxSVEVectorSize);
437 }
438
440 raw_svector_ostream(Key) << "SVEMin" << MinSVEVectorSize << "SVEMax"
441 << MaxSVEVectorSize
442 << "StreamingSVEMode=" << StreamingSVEMode
443 << "StreamingCompatibleSVEMode="
444 << StreamingCompatibleSVEMode << CPU << TuneCPU << FS
445 << "HasMinSize=" << HasMinSize;
446
447 auto &I = SubtargetMap[Key];
448 if (!I) {
449 // This needs to be done before we create a new subtarget since any
450 // creation will depend on the TM and the code generation flags on the
451 // function that reside in TargetOptions.
453 I = std::make_unique<AArch64Subtarget>(
454 TargetTriple, CPU, TuneCPU, FS, *this, isLittle, MinSVEVectorSize,
455 MaxSVEVectorSize, StreamingSVEMode, StreamingCompatibleSVEMode,
456 HasMinSize);
457 }
458
459 assert((!StreamingSVEMode || I->hasSME()) &&
460 "Expected SME to be available");
461
462 return I.get();
463}
464
465void AArch64leTargetMachine::anchor() { }
466
468 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
469 const TargetOptions &Options, std::optional<Reloc::Model> RM,
470 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
471 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
472
473void AArch64beTargetMachine::anchor() { }
474
476 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
477 const TargetOptions &Options, std::optional<Reloc::Model> RM,
478 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
479 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
480
481namespace {
482
483/// AArch64 Code Generator Pass Configuration Options.
484class AArch64PassConfig : public TargetPassConfig {
485public:
486 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
487 : TargetPassConfig(TM, PM) {
488 if (TM.getOptLevel() != CodeGenOptLevel::None)
489 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
490 setEnableSinkAndFold(EnableSinkFold);
491 }
492
493 AArch64TargetMachine &getAArch64TargetMachine() const {
494 return getTM<AArch64TargetMachine>();
495 }
496
498 createMachineScheduler(MachineSchedContext *C) const override {
499 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
501 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
502 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
503 if (ST.hasFusion())
504 DAG->addMutation(createAArch64MacroFusionDAGMutation());
505 return DAG;
506 }
507
509 createPostMachineScheduler(MachineSchedContext *C) const override {
510 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
511 ScheduleDAGMI *DAG =
512 new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
513 /* RemoveKillFlags=*/true);
514 if (ST.hasFusion()) {
515 // Run the Macro Fusion after RA again since literals are expanded from
516 // pseudos then (v. addPreSched2()).
517 DAG->addMutation(createAArch64MacroFusionDAGMutation());
518 return DAG;
519 }
520
521 return DAG;
522 }
523
524 void addIRPasses() override;
525 bool addPreISel() override;
526 void addCodeGenPrepare() override;
527 bool addInstSelector() override;
528 bool addIRTranslator() override;
529 void addPreLegalizeMachineIR() override;
530 bool addLegalizeMachineIR() override;
531 void addPreRegBankSelect() override;
532 bool addRegBankSelect() override;
533 bool addGlobalInstructionSelect() override;
534 void addMachineSSAOptimization() override;
535 bool addILPOpts() override;
536 void addPreRegAlloc() override;
537 void addPostRegAlloc() override;
538 void addPreSched2() override;
539 void addPreEmitPass() override;
540 void addPostBBSections() override;
541 void addPreEmitPass2() override;
542
543 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
544};
545
546} // end anonymous namespace
547
549 PassBuilder &PB, bool PopulateClassToPassNames) {
550
551#define GET_PASS_REGISTRY "AArch64PassRegistry.def"
553
555 [=](LoopPassManager &LPM, OptimizationLevel Level) {
557 });
558}
559
562 return TargetTransformInfo(AArch64TTIImpl(this, F));
563}
564
566 return new AArch64PassConfig(*this, PM);
567}
568
569std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
570 return getStandardCSEConfigForOpt(TM->getOptLevel());
571}
572
573void AArch64PassConfig::addIRPasses() {
574 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
575 // ourselves.
577
578 // Expand any SVE vector library calls that we can't code generate directly.
580 TM->getOptLevel() == CodeGenOptLevel::Aggressive)
582
583 // Cmpxchg instructions are often used with a subsequent comparison to
584 // determine whether it succeeded. We can exploit existing control-flow in
585 // ldrex/strex loops to simplify this, but it needs tidying up.
586 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
588 .forwardSwitchCondToPhi(true)
589 .convertSwitchRangeToICmp(true)
590 .convertSwitchToLookupTable(true)
591 .needCanonicalLoops(false)
592 .hoistCommonInsts(true)
593 .sinkCommonInsts(true)));
594
595 // Run LoopDataPrefetch
596 //
597 // Run this before LSR to remove the multiplies involved in computing the
598 // pointer values N iterations ahead.
599 if (TM->getOptLevel() != CodeGenOptLevel::None) {
604 }
605
606 if (EnableGEPOpt) {
607 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
608 // and lower a GEP with multiple indices to either arithmetic operations or
609 // multiple GEPs with single index.
611 // Call EarlyCSE pass to find and remove subexpressions in the lowered
612 // result.
613 addPass(createEarlyCSEPass());
614 // Do loop invariant code motion in case part of the lowered result is
615 // invariant.
616 addPass(createLICMPass());
617 }
618
620
621 if (getOptLevel() == CodeGenOptLevel::Aggressive && EnableSelectOpt)
622 addPass(createSelectOptimizePass());
623
626 /*IsOptNone=*/TM->getOptLevel() == CodeGenOptLevel::None));
627
628 // Match complex arithmetic patterns
629 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
631
632 // Match interleaved memory accesses to ldN/stN intrinsics.
633 if (TM->getOptLevel() != CodeGenOptLevel::None) {
636 }
637
638 // Expand any functions marked with SME attributes which require special
639 // changes for the calling convention or that require the lazy-saving
640 // mechanism specified in the SME ABI.
641 addPass(createSMEABIPass());
642
643 // Add Control Flow Guard checks.
644 if (TM->getTargetTriple().isOSWindows()) {
645 if (TM->getTargetTriple().isWindowsArm64EC())
647 else
648 addPass(createCFGuardCheckPass());
649 }
650
651 if (TM->Options.JMCInstrument)
652 addPass(createJMCInstrumenterPass());
653}
654
655// Pass Pipeline Configuration
656bool AArch64PassConfig::addPreISel() {
657 // Run promote constant before global merge, so that the promoted constants
658 // get a chance to be merged
659 if (TM->getOptLevel() != CodeGenOptLevel::None && EnablePromoteConstant)
661 // FIXME: On AArch64, this depends on the type.
662 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
663 // and the offset has to be a multiple of the related size in bytes.
664 if ((TM->getOptLevel() != CodeGenOptLevel::None &&
667 bool OnlyOptimizeForSize =
668 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
670
671 // Merging of extern globals is enabled by default on non-Mach-O as we
672 // expect it to be generally either beneficial or harmless. On Mach-O it
673 // is disabled as we emit the .subsections_via_symbols directive which
674 // means that merging extern globals is not safe.
675 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
676
677 // FIXME: extern global merging is only enabled when we optimise for size
678 // because there are some regressions with it also enabled for performance.
679 if (!OnlyOptimizeForSize)
680 MergeExternalByDefault = false;
681
682 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
683 MergeExternalByDefault));
684 }
685
686 return false;
687}
688
689void AArch64PassConfig::addCodeGenPrepare() {
690 if (getOptLevel() != CodeGenOptLevel::None)
693}
694
695bool AArch64PassConfig::addInstSelector() {
696 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
697
698 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
699 // references to _TLS_MODULE_BASE_ as possible.
700 if (TM->getTargetTriple().isOSBinFormatELF() &&
701 getOptLevel() != CodeGenOptLevel::None)
703
704 return false;
705}
706
707bool AArch64PassConfig::addIRTranslator() {
708 addPass(new IRTranslator(getOptLevel()));
709 return false;
710}
711
712void AArch64PassConfig::addPreLegalizeMachineIR() {
713 if (getOptLevel() == CodeGenOptLevel::None) {
715 addPass(new Localizer());
716 } else {
718 addPass(new Localizer());
720 addPass(new LoadStoreOpt());
721 }
722}
723
724bool AArch64PassConfig::addLegalizeMachineIR() {
725 addPass(new Legalizer());
726 return false;
727}
728
729void AArch64PassConfig::addPreRegBankSelect() {
730 bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
731 if (!IsOptNone) {
732 addPass(createAArch64PostLegalizerCombiner(IsOptNone));
734 addPass(new LoadStoreOpt());
735 }
737}
738
739bool AArch64PassConfig::addRegBankSelect() {
740 addPass(new RegBankSelect());
741 return false;
742}
743
744bool AArch64PassConfig::addGlobalInstructionSelect() {
745 addPass(new InstructionSelect(getOptLevel()));
746 if (getOptLevel() != CodeGenOptLevel::None)
748 return false;
749}
750
751void AArch64PassConfig::addMachineSSAOptimization() {
752 // Run default MachineSSAOptimization first.
754
755 if (TM->getOptLevel() != CodeGenOptLevel::None)
757}
758
759bool AArch64PassConfig::addILPOpts() {
760 if (EnableCondOpt)
762 if (EnableCCMP)
764 if (EnableMCR)
765 addPass(&MachineCombinerID);
767 addPass(createAArch64CondBrTuning());
769 addPass(&EarlyIfConverterID);
773 if (TM->getOptLevel() != CodeGenOptLevel::None)
775 return true;
776}
777
778void AArch64PassConfig::addPreRegAlloc() {
779 // Change dead register definitions to refer to the zero register.
780 if (TM->getOptLevel() != CodeGenOptLevel::None &&
783
784 // Use AdvSIMD scalar instructions whenever profitable.
785 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAdvSIMDScalar) {
787 // The AdvSIMD pass may produce copies that can be rewritten to
788 // be register coalescer friendly.
789 addPass(&PeepholeOptimizerID);
790 }
791 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableMachinePipeliner)
792 addPass(&MachinePipelinerID);
793}
794
795void AArch64PassConfig::addPostRegAlloc() {
796 // Remove redundant copy instructions.
797 if (TM->getOptLevel() != CodeGenOptLevel::None &&
800
801 if (TM->getOptLevel() != CodeGenOptLevel::None && usingDefaultRegAlloc())
802 // Improve performance for some FP/SIMD code for A57.
804}
805
806void AArch64PassConfig::addPreSched2() {
807 // Lower homogeneous frame instructions
810 // Expand some pseudo instructions to allow proper scheduling.
812 // Use load/store pair instructions when possible.
813 if (TM->getOptLevel() != CodeGenOptLevel::None) {
816 }
817 // Emit KCFI checks for indirect calls.
818 addPass(createKCFIPass());
819
820 // The AArch64SpeculationHardeningPass destroys dominator tree and natural
821 // loop info, which is needed for the FalkorHWPFFixPass and also later on.
822 // Therefore, run the AArch64SpeculationHardeningPass before the
823 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
824 // info.
826
827 if (TM->getOptLevel() != CodeGenOptLevel::None) {
829 addPass(createFalkorHWPFFixPass());
830 }
831}
832
833void AArch64PassConfig::addPreEmitPass() {
834 // Machine Block Placement might have created new opportunities when run
835 // at O3, where the Tail Duplication Threshold is set to 4 instructions.
836 // Run the load/store optimizer once more.
837 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive && EnableLoadStoreOpt)
839
840 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&
843
844 addPass(createAArch64A53Fix835769());
845
846 if (TM->getTargetTriple().isOSWindows()) {
847 // Identify valid longjmp targets for Windows Control Flow Guard.
848 addPass(createCFGuardLongjmpPass());
849 // Identify valid eh continuation targets for Windows EHCont Guard.
851 }
852
853 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCollectLOH &&
854 TM->getTargetTriple().isOSBinFormatMachO())
856}
857
858void AArch64PassConfig::addPostBBSections() {
864 // Relax conditional branch instructions if they're otherwise out of
865 // range of their destination.
866 if (BranchRelaxation)
867 addPass(&BranchRelaxationPassID);
868
869 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCompressJumpTables)
871}
872
873void AArch64PassConfig::addPreEmitPass2() {
874 // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
875 // instructions are lowered to bundles as well.
876 addPass(createUnpackMachineBundles(nullptr));
877}
878
880 BumpPtrAllocator &Allocator, const Function &F,
881 const TargetSubtargetInfo *STI) const {
882 return AArch64FunctionInfo::create<AArch64FunctionInfo>(
883 Allocator, F, static_cast<const AArch64Subtarget *>(STI));
884}
885
888 return new yaml::AArch64FunctionInfo();
889}
890
893 const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
894 return new yaml::AArch64FunctionInfo(*MFI);
895}
896
899 SMDiagnostic &Error, SMRange &SourceRange) const {
900 const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);
901 MachineFunction &MF = PFS.MF;
902 MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
903 return false;
904}
cl::opt< bool > EnableHomogeneousPrologEpilog("homogeneous-prolog-epilog", cl::Hidden, cl::desc("Emit homogeneous prologue and epilogue for the size " "optimization (default = off)"))
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AArch64 branch target pass"), cl::init(true))
static cl::opt< bool > EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true))
static cl::opt< bool > EnableAArch64CopyPropagation("aarch64-enable-copy-propagation", cl::desc("Enable the copy propagation with AArch64 copy instr"), cl::init(true), cl::Hidden)
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
static cl::opt< bool > EnableSelectOpt("aarch64-select-opt", cl::Hidden, cl::desc("Enable select to branch optimizations"), cl::init(true))
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
cl::opt< bool > EnableHomogeneousPrologEpilog
static cl::opt< bool > EnableGISelLoadStoreOptPostLegal("aarch64-enable-gisel-ldst-postlegal", cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"), cl::init(false), cl::Hidden)
static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU)
static cl::opt< unsigned > SVEVectorBitsMinOpt("aarch64-sve-vector-bits-min", cl::desc("Assume SVE vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableGISelLoadStoreOptPreLegal("aarch64-enable-gisel-ldst-prelegal", cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target()
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
static cl::opt< unsigned > SVEVectorBitsMaxOpt("aarch64-sve-vector-bits-max", cl::desc("Assume SVE vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
This file a TargetTransformInfo::Concept conforming object specific to the AArch64 target machine.
This file contains the simple types necessary to represent the attributes associated with functions a...
basic Basic Alias true
Contains definition of the base CFIFixup pass.
Provides analysis for continuously CSEing during GISel passes.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
endianness Endian
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const AArch64Subtarget * getSubtargetImpl() const =delete
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
void registerPassBuilderCallbacks(PassBuilder &PB, bool PopulateClassToPassNames) override
Allow the target to modify the pass pipeline.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1491
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:349
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:193
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
This class represents a range of values.
Definition: ConstantRange.h:47
APInt getUnsignedMin() const
Return the smallest unsigned value contained in the ConstantRange.
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:43
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:104
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:414
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:95
void setMachineOutliner(bool Enable)
void setCFIFixup(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
void setGlobalISelAbort(GlobalISelAbortMode Mode)
std::string TargetFS
Definition: TargetMachine.h:97
std::string TargetCPU
Definition: TargetMachine.h:96
std::unique_ptr< const MCSubtargetInfo > STI
void setGlobalISel(bool Enable)
CodeModel::Model getCodeModel() const
Returns the code model.
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned TLSSize
Bit size of immediate TLS offsets (0 == use the default).
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
@ aarch64_32
Definition: Triple.h:53
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:690
Interfaces for registering analysis passes, producing common pass manager configurations,...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ DynamicNoPIC
Definition: CodeGen.h:25
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createAArch64PreLegalizerCombiner()
void initializeLDTLSCleanupPass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
FunctionPass * createSMEABIPass()
Definition: SMEABIPass.cpp:53
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
FunctionPass * createAArch64PostSelectOptimize()
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &)
FunctionPass * createAArch64RedundantCopyEliminationPass()
FunctionPass * createAArch64StackTaggingPreRAPass()
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)
FunctionPass * createAArch64MIPeepholeOptPass()
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
void initializeAArch64GlobalsTaggingPass(PassRegistry &)
void initializeAArch64PromoteConstantPass(PassRegistry &)
FunctionPass * createFalkorMarkStridedAccessesPass()
Target & getTheAArch64beTarget()
FunctionPass * createAArch64PointerAuthPass()
FunctionPass * createFalkorHWPFFixPass()
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createAArch64O0PreLegalizerCombiner()
FunctionPass * createAArch64A57FPLoadBalancing()
FunctionPass * createAArch64CondBrTuning()
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition: CSEInfo.cpp:79
void initializeSMEABIPass(PassRegistry &)
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Pass * createLICMPass()
Definition: LICM.cpp:379
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Target & getTheAArch64leTarget()
FunctionPass * createAArch64DeadRegisterDefinitions()
FunctionPass * createAArch64PostLegalizerLowering()
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
FunctionPass * createAArch64IndirectThunks()
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
FunctionPass * createAArch64CompressJumpTablesPass()
Target & getTheAArch64_32Target()
FunctionPass * createAArch64ConditionalCompares()
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
void initializeAArch64DAGToDAGISelPass(PassRegistry &)
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
void initializeAArch64StackTaggingPass(PassRegistry &)
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:61
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
FunctionPass * createComplexDeinterleavingPass(const TargetMachine *TM)
This pass implements generation of target-specific intrinsics to support handling of complex number a...
ModulePass * createAArch64GlobalsTaggingPass()
ModulePass * createAArch64Arm64ECCallLoweringPass()
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
FunctionPass * createAArch64StorePairSuppressPass()
FunctionPass * createAArch64ConditionOptimizerPass()
ModulePass * createSVEIntrinsicOptsPass()
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
void initializeAArch64SLSHardeningPass(PassRegistry &)
FunctionPass * createAArch64CollectLOHPass()
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass.
void initializeAArch64StackTaggingPreRAPass(PassRegistry &)
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
Target & getTheARM64_32Target()
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)
void initializeAArch64StorePairSuppressPass(PassRegistry &)
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &)
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
void initializeAArch64LoopIdiomTransformLegacyPassPass(PassRegistry &)
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOptLevel OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG,...
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
void initializeAArch64MIPeepholeOptPass(PassRegistry &)
FunctionPass * createAArch64SLSHardeningPass()
FunctionPass * createAArch64BranchTargetsPass()
Target & getTheARM64Target()
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
void initializeFalkorHWPFFixPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeKCFIPass(PassRegistry &)
void initializeAArch64BranchTargetsPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:313
void initializeAArch64A53Fix835769Pass(PassRegistry &)
ModulePass * createAArch64LowerHomogeneousPrologEpilogPass()
void initializeAArch64LoadStoreOptPass(PassRegistry &)
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
void initializeAArch64PostSelectOptimizePass(PassRegistry &)
void initializeAArch64CollectLOHPass(PassRegistry &)
FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &)
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
void initializeAArch64ConditionalComparesPass(PassRegistry &)
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
ModulePass * createAArch64PromoteConstantPass()
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1932
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
FunctionPass * createAArch64AdvSIMDScalar()
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
void initializeSVEIntrinsicOptsPass(PassRegistry &)
void initializeAArch64PointerAuthPass(PassRegistry &)
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
FunctionPass * createAArch64A53Fix835769()
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.