62 cl::desc(
"Enable the CCMP formation pass"),
67 cl::desc(
"Enable the conditional branch tuning pass"),
71 "aarch64-enable-copy-propagation",
72 cl::desc(
"Enable the copy propagation with AArch64 copy instr"),
76 cl::desc(
"Enable the machine combiner pass"),
80 cl::desc(
"Suppress STP for AArch64"),
84 "aarch64-enable-simd-scalar",
85 cl::desc(
"Enable use of AdvSIMD scalar integer instructions"),
90 cl::desc(
"Enable the promote constant pass"),
94 "aarch64-enable-collect-loh",
95 cl::desc(
"Enable the pass that emits the linker optimization hints (LOH)"),
100 cl::desc(
"Enable the pass that removes dead"
101 " definitons and replaces stores to"
102 " them with stores to the zero"
107 "aarch64-enable-copyelim",
112 cl::desc(
"Enable the load/store pair"
113 " optimization pass"),
118 cl::desc(
"Run SimplifyCFG after expanding atomic operations"
119 " to make use of cmpxchg flow-based information"),
124 cl::desc(
"Run early if-conversion"),
129 cl::desc(
"Enable the condition optimizer pass"),
134 cl::desc(
"Enable optimizations on complex GEPs"),
139 cl::desc(
"Enable select to branch optimizations"),
144 cl::desc(
"Relax out of range conditional branches"));
148 cl::desc(
"Use smallest entry possible for jump tables"));
153 cl::desc(
"Enable the global merge pass"));
157 cl::desc(
"Enable the loop data prefetch pass"),
161 "aarch64-enable-global-isel-at-O",
cl::Hidden,
162 cl::desc(
"Enable GlobalISel at or below an opt level (-1 to disable)"),
167 cl::desc(
"Enable SVE intrinsic opts"),
175 cl::desc(
"Enable the AArch64 branch target pass"),
179 "aarch64-sve-vector-bits-max",
180 cl::desc(
"Assume SVE vector registers are at most this big, "
181 "with zero meaning no maximum size is assumed."),
185 "aarch64-sve-vector-bits-min",
186 cl::desc(
"Assume SVE vector registers are at least this big, "
187 "with zero meaning no minimum size is assumed."),
193 "aarch64-enable-gisel-ldst-prelegal",
194 cl::desc(
"Enable GlobalISel's pre-legalizer load/store optimization pass"),
198 "aarch64-enable-gisel-ldst-postlegal",
199 cl::desc(
"Enable GlobalISel's post-legalizer load/store optimization pass"),
204 cl::desc(
"Enable sinking and folding of instruction copies"),
209 cl::desc(
"Enable Machine Pipeliner for AArch64"),
263 if (TT.isOSBinFormatMachO())
264 return std::make_unique<AArch64_MachoTargetObjectFile>();
265 if (TT.isOSBinFormatCOFF())
266 return std::make_unique<AArch64_COFFTargetObjectFile>();
268 return std::make_unique<AArch64_ELFTargetObjectFile>();
275 if (TT.isOSBinFormatMachO()) {
277 return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
278 return "e-m:o-i64:64-i128:128-n32:64-S128";
280 if (TT.isOSBinFormatCOFF())
281 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
282 std::string
Endian = LittleEndian ?
"e" :
"E";
283 std::string Ptr32 = TT.getEnvironment() ==
Triple::GNUILP32 ?
"-p:32:32" :
"";
284 return Endian +
"-m:e" + Ptr32 +
285 "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
289 if (CPU.
empty() && TT.isArm64e())
295 std::optional<Reloc::Model> RM) {
297 if (TT.isOSDarwin() || TT.isOSWindows())
309 std::optional<CodeModel::Model> CM,
bool JIT) {
314 "Only small, tiny and large code models are allowed on AArch64");
325 if (JIT && !TT.isOSWindows())
335 std::optional<Reloc::Model> RM,
336 std::optional<CodeModel::Model> CM,
344 TLOF(
createTLOF(getTargetTriple())), isLittle(LittleEndian) {
347 if (TT.isOSBinFormatMachO()) {
362 if (this->Options.
TLSSize == 0)
401 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
402 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
403 Attribute FSAttr =
F.getFnAttribute(
"target-features");
408 bool HasMinSize =
F.hasMinSize();
410 bool StreamingSVEMode =
F.hasFnAttribute(
"aarch64_pstate_sm_enabled") ||
411 F.hasFnAttribute(
"aarch64_pstate_sm_body");
412 bool StreamingCompatibleSVEMode =
413 F.hasFnAttribute(
"aarch64_pstate_sm_compatible");
415 unsigned MinSVEVectorSize = 0;
416 unsigned MaxSVEVectorSize = 0;
417 if (
F.hasFnAttribute(Attribute::VScaleRange)) {
426 assert(MinSVEVectorSize % 128 == 0 &&
427 "SVE requires vector length in multiples of 128!");
428 assert(MaxSVEVectorSize % 128 == 0 &&
429 "SVE requires vector length in multiples of 128!");
430 assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
431 "Minimum SVE vector size should not be larger than its maximum!");
434 if (MaxSVEVectorSize != 0) {
435 MinSVEVectorSize = std::min(MinSVEVectorSize, MaxSVEVectorSize);
436 MaxSVEVectorSize = std::max(MinSVEVectorSize, MaxSVEVectorSize);
442 <<
"StreamingSVEMode=" << StreamingSVEMode
443 <<
"StreamingCompatibleSVEMode="
444 << StreamingCompatibleSVEMode << CPU << TuneCPU << FS
445 <<
"HasMinSize=" << HasMinSize;
453 I = std::make_unique<AArch64Subtarget>(
454 TargetTriple, CPU, TuneCPU, FS, *
this, isLittle, MinSVEVectorSize,
455 MaxSVEVectorSize, StreamingSVEMode, StreamingCompatibleSVEMode,
459 assert((!StreamingSVEMode ||
I->hasSME()) &&
460 "Expected SME to be available");
465void AArch64leTargetMachine::anchor() { }
473void AArch64beTargetMachine::anchor() { }
488 if (
TM.getOptLevel() != CodeGenOptLevel::None)
494 return getTM<AArch64TargetMachine>();
514 if (
ST.hasFusion()) {
524 void addIRPasses()
override;
525 bool addPreISel()
override;
526 void addCodeGenPrepare()
override;
527 bool addInstSelector()
override;
528 bool addIRTranslator()
override;
529 void addPreLegalizeMachineIR()
override;
530 bool addLegalizeMachineIR()
override;
531 void addPreRegBankSelect()
override;
532 bool addRegBankSelect()
override;
533 bool addGlobalInstructionSelect()
override;
534 void addMachineSSAOptimization()
override;
535 bool addILPOpts()
override;
536 void addPreRegAlloc()
override;
537 void addPostRegAlloc()
override;
538 void addPreSched2()
override;
539 void addPreEmitPass()
override;
540 void addPostBBSections()
override;
541 void addPreEmitPass2()
override;
543 std::unique_ptr<CSEConfigBase> getCSEConfig()
const override;
551#define GET_PASS_REGISTRY "AArch64PassRegistry.def"
566 return new AArch64PassConfig(*
this, PM);
569std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig()
const {
573void AArch64PassConfig::addIRPasses() {
588 .forwardSwitchCondToPhi(
true)
589 .convertSwitchRangeToICmp(
true)
590 .convertSwitchToLookupTable(
true)
591 .needCanonicalLoops(
false)
592 .hoistCommonInsts(
true)
593 .sinkCommonInsts(
true)));
644 if (
TM->getTargetTriple().isOSWindows()) {
645 if (
TM->getTargetTriple().isWindowsArm64EC())
651 if (
TM->Options.JMCInstrument)
656bool AArch64PassConfig::addPreISel() {
667 bool OnlyOptimizeForSize =
675 bool MergeExternalByDefault = !
TM->getTargetTriple().isOSBinFormatMachO();
679 if (!OnlyOptimizeForSize)
680 MergeExternalByDefault =
false;
683 MergeExternalByDefault));
689void AArch64PassConfig::addCodeGenPrepare() {
695bool AArch64PassConfig::addInstSelector() {
700 if (
TM->getTargetTriple().isOSBinFormatELF() &&
707bool AArch64PassConfig::addIRTranslator() {
712void AArch64PassConfig::addPreLegalizeMachineIR() {
724bool AArch64PassConfig::addLegalizeMachineIR() {
729void AArch64PassConfig::addPreRegBankSelect() {
739bool AArch64PassConfig::addRegBankSelect() {
744bool AArch64PassConfig::addGlobalInstructionSelect() {
751void AArch64PassConfig::addMachineSSAOptimization() {
759bool AArch64PassConfig::addILPOpts() {
778void AArch64PassConfig::addPreRegAlloc() {
795void AArch64PassConfig::addPostRegAlloc() {
806void AArch64PassConfig::addPreSched2() {
833void AArch64PassConfig::addPreEmitPass() {
846 if (
TM->getTargetTriple().isOSWindows()) {
854 TM->getTargetTriple().isOSBinFormatMachO())
858void AArch64PassConfig::addPostBBSections() {
866 if (BranchRelaxation)
873void AArch64PassConfig::addPreEmitPass2() {
882 return AArch64FunctionInfo::create<AArch64FunctionInfo>(
cl::opt< bool > EnableHomogeneousPrologEpilog("homogeneous-prolog-epilog", cl::Hidden, cl::desc("Emit homogeneous prologue and epilogue for the size " "optimization (default = off)"))
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AArch64 branch target pass"), cl::init(true))
static cl::opt< bool > EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true))
static cl::opt< bool > EnableAArch64CopyPropagation("aarch64-enable-copy-propagation", cl::desc("Enable the copy propagation with AArch64 copy instr"), cl::init(true), cl::Hidden)
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
static cl::opt< bool > EnableSelectOpt("aarch64-select-opt", cl::Hidden, cl::desc("Enable select to branch optimizations"), cl::init(true))
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
cl::opt< bool > EnableHomogeneousPrologEpilog
static cl::opt< bool > EnableGISelLoadStoreOptPostLegal("aarch64-enable-gisel-ldst-postlegal", cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"), cl::init(false), cl::Hidden)
static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU)
static cl::opt< unsigned > SVEVectorBitsMinOpt("aarch64-sve-vector-bits-min", cl::desc("Assume SVE vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableGISelLoadStoreOptPreLegal("aarch64-enable-gisel-ldst-prelegal", cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target()
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
static cl::opt< unsigned > SVEVectorBitsMaxOpt("aarch64-sve-vector-bits-max", cl::desc("Assume SVE vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
Contains definition of the base CFIFixup pass.
Provides analysis for continuously CSEing during GISel passes.
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static std::string computeDataLayout()
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target-Independent Code Generator Pass Configuration Options pass.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const AArch64Subtarget * getSubtargetImpl() const =delete
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
~AArch64TargetMachine() override
void registerPassBuilderCallbacks(PassBuilder &PB, bool PopulateClassToPassNames) override
Allow the target to modify the pass pipeline.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
uint64_t getZExtValue() const
Get zero extended value.
StringRef getValueAsString() const
Return the attribute's value as a string.
bool isValid() const
Return true if the attribute is any kind of attribute.
Allocate memory in an ever growing pool, as if by bump-pointer.
This class represents a range of values.
APInt getUnsignedMin() const
Return the smallest unsigned value contained in the ConstantRange.
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
Lightweight error class with error context and mandatory checking.
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This pass implements the localization mechanism described at the top of this file.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
This class provides access to building LLVM's passes.
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a range in source code.
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
void setMachineOutliner(bool Enable)
void setCFIFixup(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
void setGlobalISelAbort(GlobalISelAbortMode Mode)
std::unique_ptr< const MCSubtargetInfo > STI
void setGlobalISel(bool Enable)
CodeModel::Model getCodeModel() const
Returns the code model.
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned TLSSize
Bit size of immediate TLS offsets (0 == use the default).
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
TargetSubtargetInfo - Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
A raw_ostream that writes to an SmallVector or SmallString.
Interfaces for registering analysis passes, producing common pass manager configurations,...
@ C
The default llvm calling convention, compatible with C.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createAArch64PreLegalizerCombiner()
void initializeLDTLSCleanupPass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
FunctionPass * createSMEABIPass()
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
FunctionPass * createAArch64PostSelectOptimize()
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &)
FunctionPass * createAArch64RedundantCopyEliminationPass()
FunctionPass * createAArch64StackTaggingPreRAPass()
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)
FunctionPass * createAArch64MIPeepholeOptPass()
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
void initializeAArch64GlobalsTaggingPass(PassRegistry &)
void initializeAArch64PromoteConstantPass(PassRegistry &)
FunctionPass * createFalkorMarkStridedAccessesPass()
Target & getTheAArch64beTarget()
FunctionPass * createAArch64PointerAuthPass()
FunctionPass * createFalkorHWPFFixPass()
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createAArch64O0PreLegalizerCombiner()
FunctionPass * createAArch64A57FPLoadBalancing()
FunctionPass * createAArch64CondBrTuning()
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
void initializeSMEABIPass(PassRegistry &)
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Target & getTheAArch64leTarget()
FunctionPass * createAArch64DeadRegisterDefinitions()
FunctionPass * createAArch64PostLegalizerLowering()
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
FunctionPass * createAArch64IndirectThunks()
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
FunctionPass * createAArch64CompressJumpTablesPass()
Target & getTheAArch64_32Target()
FunctionPass * createAArch64ConditionalCompares()
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
void initializeAArch64DAGToDAGISelPass(PassRegistry &)
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
void initializeAArch64StackTaggingPass(PassRegistry &)
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
FunctionPass * createComplexDeinterleavingPass(const TargetMachine *TM)
This pass implements generation of target-specific intrinsics to support handling of complex number a...
ModulePass * createAArch64GlobalsTaggingPass()
ModulePass * createAArch64Arm64ECCallLoweringPass()
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
FunctionPass * createAArch64StorePairSuppressPass()
FunctionPass * createAArch64ConditionOptimizerPass()
ModulePass * createSVEIntrinsicOptsPass()
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
void initializeAArch64SLSHardeningPass(PassRegistry &)
FunctionPass * createAArch64CollectLOHPass()
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
CodeGenOptLevel
Code generation optimization level.
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass.
void initializeAArch64StackTaggingPreRAPass(PassRegistry &)
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
Target & getTheARM64_32Target()
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)
void initializeAArch64StorePairSuppressPass(PassRegistry &)
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &)
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
void initializeAArch64LoopIdiomTransformLegacyPassPass(PassRegistry &)
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOptLevel OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG,...
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
void initializeAArch64MIPeepholeOptPass(PassRegistry &)
FunctionPass * createAArch64SLSHardeningPass()
FunctionPass * createAArch64BranchTargetsPass()
Target & getTheARM64Target()
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
void initializeFalkorHWPFFixPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeKCFIPass(PassRegistry &)
void initializeAArch64BranchTargetsPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
void initializeAArch64A53Fix835769Pass(PassRegistry &)
ModulePass * createAArch64LowerHomogeneousPrologEpilogPass()
void initializeAArch64LoadStoreOptPass(PassRegistry &)
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
void initializeAArch64PostSelectOptimizePass(PassRegistry &)
void initializeAArch64CollectLOHPass(PassRegistry &)
FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &)
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
void initializeAArch64ConditionalComparesPass(PassRegistry &)
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
ModulePass * createAArch64PromoteConstantPass()
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
FunctionPass * createAArch64AdvSIMDScalar()
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
void initializeSVEIntrinsicOptsPass(PassRegistry &)
void initializeAArch64PointerAuthPass(PassRegistry &)
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
FunctionPass * createAArch64A53Fix835769()
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.