LLVM  10.0.0svn
AMDGPUArgumentUsageInfo.cpp
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1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPU.h"
11 #include "SIRegisterInfo.h"
14 
15 using namespace llvm;
16 
17 #define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
18 
20  "Argument Register Usage Information Storage", false, true)
21 
23  const TargetRegisterInfo *TRI) const {
24  if (!isSet()) {
25  OS << "<not set>\n";
26  return;
27  }
28 
29  if (isRegister())
30  OS << "Reg " << printReg(getRegister(), TRI);
31  else
32  OS << "Stack offset " << getStackOffset();
33 
34  if (isMasked()) {
35  OS << " & ";
37  }
38 
39  OS << '\n';
40 }
41 
43 
44 const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
45 
47  return false;
48 }
49 
51  ArgInfoMap.clear();
52  return false;
53 }
54 
56  for (const auto &FI : ArgInfoMap) {
57  OS << "Arguments for " << FI.first->getName() << '\n'
58  << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
59  << " DispatchPtr: " << FI.second.DispatchPtr
60  << " QueuePtr: " << FI.second.QueuePtr
61  << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
62  << " DispatchID: " << FI.second.DispatchID
63  << " FlatScratchInit: " << FI.second.FlatScratchInit
64  << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
65  << " WorkGroupIDX: " << FI.second.WorkGroupIDX
66  << " WorkGroupIDY: " << FI.second.WorkGroupIDY
67  << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
68  << " WorkGroupInfo: " << FI.second.WorkGroupInfo
69  << " PrivateSegmentWaveByteOffset: "
70  << FI.second.PrivateSegmentWaveByteOffset
71  << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
72  << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
73  << " WorkItemIDX " << FI.second.WorkItemIDX
74  << " WorkItemIDY " << FI.second.WorkItemIDY
75  << " WorkItemIDZ " << FI.second.WorkItemIDZ
76  << '\n';
77  }
78 }
79 
80 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
83  switch (Value) {
85  return std::make_pair(
86  PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
87  &AMDGPU::SGPR_128RegClass);
88  }
90  return std::make_pair(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
91  &AMDGPU::SGPR_64RegClass);
93  return std::make_pair(WorkGroupIDX ? &WorkGroupIDX : nullptr,
94  &AMDGPU::SGPR_32RegClass);
95 
97  return std::make_pair(WorkGroupIDY ? &WorkGroupIDY : nullptr,
98  &AMDGPU::SGPR_32RegClass);
100  return std::make_pair(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
101  &AMDGPU::SGPR_32RegClass);
103  return std::make_pair(
104  PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
105  &AMDGPU::SGPR_32RegClass);
107  return std::make_pair(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
108  &AMDGPU::SGPR_64RegClass);
110  return std::make_pair(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
111  &AMDGPU::SGPR_64RegClass);
113  return std::make_pair(DispatchID ? &DispatchID : nullptr,
114  &AMDGPU::SGPR_64RegClass);
116  return std::make_pair(FlatScratchInit ? &FlatScratchInit : nullptr,
117  &AMDGPU::SGPR_64RegClass);
119  return std::make_pair(DispatchPtr ? &DispatchPtr : nullptr,
120  &AMDGPU::SGPR_64RegClass);
122  return std::make_pair(QueuePtr ? &QueuePtr : nullptr,
123  &AMDGPU::SGPR_64RegClass);
125  return std::make_pair(WorkItemIDX ? &WorkItemIDX : nullptr,
126  &AMDGPU::VGPR_32RegClass);
128  return std::make_pair(WorkItemIDY ? &WorkItemIDY : nullptr,
129  &AMDGPU::VGPR_32RegClass);
131  return std::make_pair(WorkItemIDZ ? &WorkItemIDZ : nullptr,
132  &AMDGPU::VGPR_32RegClass);
133  }
134  llvm_unreachable("unexpected preloaded value type");
135 }
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Interface definition for SIRegisterInfo.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:66
unsigned const TargetRegisterInfo * TRI
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
std::pair< const ArgDescriptor *, const TargetRegisterClass * > getPreloadedValue(PreloadedValue Value) const
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
static StackOffset getStackOffset(const MachineFunction &MF, int ObjectOffset)
void write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style, Optional< size_t > Width=None)
#define DEBUG_TYPE
aarch64 promote const
LLVM Value Representation.
Definition: Value.h:74
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...