LLVM 19.0.0git
AMDGPUAsmBackend.cpp
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1//===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
15#include "llvm/MC/MCAssembler.h"
16#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25using namespace llvm::AMDGPU;
26
27namespace {
28
29class AMDGPUAsmBackend : public MCAsmBackend {
30public:
31 AMDGPUAsmBackend(const Target &T) : MCAsmBackend(llvm::endianness::little) {}
32
33 unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
34
35 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
37 uint64_t Value, bool IsResolved,
38 const MCSubtargetInfo *STI) const override;
41 const MCAsmLayout &Layout) const override;
42
43 void relaxInstruction(MCInst &Inst,
44 const MCSubtargetInfo &STI) const override;
45
46 bool mayNeedRelaxation(const MCInst &Inst,
47 const MCSubtargetInfo &STI) const override;
48
49 unsigned getMinimumNopSize() const override;
51 const MCSubtargetInfo *STI) const override;
52
53 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
54 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
55 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
56 const MCValue &Target,
57 const MCSubtargetInfo *STI) override;
58};
59
60} //End anonymous namespace
61
62void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,
63 const MCSubtargetInfo &STI) const {
64 MCInst Res;
65 unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode());
66 Res.setOpcode(RelaxedOpcode);
67 Res.addOperand(Inst.getOperand(0));
68 Inst = std::move(Res);
69}
70
71bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
74 const MCAsmLayout &Layout) const {
75 // if the branch target has an offset of x3f this needs to be relaxed to
76 // add a s_nop 0 immediately after branch to effectively increment offset
77 // for hardware workaround in gfx1010
78 return (((int64_t(Value)/4)-1) == 0x3f);
79}
80
81bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst,
82 const MCSubtargetInfo &STI) const {
83 if (!STI.hasFeature(AMDGPU::FeatureOffset3fBug))
84 return false;
85
87 return true;
88
89 return false;
90}
91
92static unsigned getFixupKindNumBytes(unsigned Kind) {
93 switch (Kind) {
95 return 2;
96 case FK_SecRel_1:
97 case FK_Data_1:
98 return 1;
99 case FK_SecRel_2:
100 case FK_Data_2:
101 return 2;
102 case FK_SecRel_4:
103 case FK_Data_4:
104 case FK_PCRel_4:
105 return 4;
106 case FK_SecRel_8:
107 case FK_Data_8:
108 return 8;
109 default:
110 llvm_unreachable("Unknown fixup kind!");
111 }
112}
113
115 MCContext *Ctx) {
116 int64_t SignedValue = static_cast<int64_t>(Value);
117
118 switch (Fixup.getTargetKind()) {
120 int64_t BrImm = (SignedValue - 4) / 4;
121
122 if (Ctx && !isInt<16>(BrImm))
123 Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");
124
125 return BrImm;
126 }
127 case FK_Data_1:
128 case FK_Data_2:
129 case FK_Data_4:
130 case FK_Data_8:
131 case FK_PCRel_4:
132 case FK_SecRel_4:
133 return Value;
134 default:
135 llvm_unreachable("unhandled fixup kind");
136 }
137}
138
139void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
140 const MCValue &Target,
142 bool IsResolved,
143 const MCSubtargetInfo *STI) const {
144 if (Fixup.getKind() >= FirstLiteralRelocationKind)
145 return;
146
147 Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
148 if (!Value)
149 return; // Doesn't change encoding.
150
151 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
152
153 // Shift the value into position.
154 Value <<= Info.TargetOffset;
155
156 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
157 uint32_t Offset = Fixup.getOffset();
158 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
159
160 // For each byte of the fragment that the fixup touches, mask in the bits from
161 // the fixup value.
162 for (unsigned i = 0; i != NumBytes; ++i)
163 Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
164}
165
166std::optional<MCFixupKind>
167AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
169#define ELF_RELOC(Name, Value) \
171#include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
172#undef ELF_RELOC
173 .Default(std::nullopt);
174}
175
176const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
177 MCFixupKind Kind) const {
178 const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
179 // name offset bits flags
180 { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
181 };
182
183 if (Kind >= FirstLiteralRelocationKind)
185
186 if (Kind < FirstTargetFixupKind)
188
189 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
190 "Invalid kind!");
191 return Infos[Kind - FirstTargetFixupKind];
192}
193
194bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &,
195 const MCFixup &Fixup,
196 const MCValue &,
197 const MCSubtargetInfo *STI) {
198 return Fixup.getKind() >= FirstLiteralRelocationKind;
199}
200
201unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
202 return 4;
203}
204
205bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
206 const MCSubtargetInfo *STI) const {
207 // If the count is not 4-byte aligned, we must be writing data into the text
208 // section (otherwise we have unaligned instructions, and thus have far
209 // bigger problems), so just write zeros instead.
210 OS.write_zeros(Count % 4);
211
212 // We are properly aligned, so write NOPs as requested.
213 Count /= 4;
214
215 // FIXME: R600 support.
216 // s_nop 0
217 const uint32_t Encoded_S_NOP_0 = 0xbf800000;
218
219 for (uint64_t I = 0; I != Count; ++I)
220 support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian);
221
222 return true;
223}
224
225//===----------------------------------------------------------------------===//
226// ELFAMDGPUAsmBackend class
227//===----------------------------------------------------------------------===//
228
229namespace {
230
231class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
232 bool Is64Bit;
233 bool HasRelocationAddend;
234 uint8_t OSABI = ELF::ELFOSABI_NONE;
235
236public:
237 ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)
238 : AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
239 HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
240 switch (TT.getOS()) {
241 case Triple::AMDHSA:
243 break;
244 case Triple::AMDPAL:
246 break;
247 case Triple::Mesa3D:
249 break;
250 default:
251 break;
252 }
253 }
254
255 std::unique_ptr<MCObjectTargetWriter>
256 createObjectTargetWriter() const override {
257 return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend);
258 }
259};
260
261} // end anonymous namespace
262
264 const MCSubtargetInfo &STI,
265 const MCRegisterInfo &MRI,
266 const MCTargetOptions &Options) {
267 return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
268}
unsigned const MachineRegisterInfo * MRI
#define ELF_RELOC(Name, Value)
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
static unsigned getFixupKindNumBytes(unsigned Kind)
Provides AMDGPU specific target descriptions.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
@ Default
Definition: DwarfDebug.cpp:87
std::string Name
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:43
virtual unsigned getMinimumNopSize() const
Returns the minimum size of a nop in bytes on this target.
Definition: MCAsmBackend.h:212
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:186
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
Definition: MCAsmBackend.h:163
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
Definition: MCAsmBackend.h:102
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Context object for machine code objects.
Definition: MCContext.h:76
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1064
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:274
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
@ ELFOSABI_AMDGPU_HSA
Definition: ELF.h:361
@ ELFOSABI_AMDGPU_MESA3D
Definition: ELF.h:363
@ ELFOSABI_NONE
Definition: ELF.h:341
@ ELFOSABI_AMDGPU_PAL
Definition: ELF.h:362
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
@ FK_SecRel_2
A two-byte section relative fixup.
Definition: MCFixup.h:41
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_SecRel_8
A eight-byte section relative fixup.
Definition: MCFixup.h:43
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
@ FK_SecRel_1
A one-byte section relative fixup.
Definition: MCFixup.h:40
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
endianness
Definition: bit.h:70
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...