LLVM  9.0.0svn
AMDGPUBaseInfo.cpp
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1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPUBaseInfo.h"
11 #include "AMDGPU.h"
12 #include "SIDefines.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/BinaryFormat/ELF.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Constants.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/GlobalValue.h"
21 #include "llvm/IR/Instruction.h"
22 #include "llvm/IR/LLVMContext.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSectionELF.h"
31 #include "llvm/Support/Casting.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstdint>
37 #include <cstring>
38 #include <utility>
39 
41 
42 #define GET_INSTRINFO_NAMED_OPS
43 #define GET_INSTRMAP_INFO
44 #include "AMDGPUGenInstrInfo.inc"
45 #undef GET_INSTRMAP_INFO
46 #undef GET_INSTRINFO_NAMED_OPS
47 
48 namespace {
49 
50 /// \returns Bit mask for given bit \p Shift and bit \p Width.
51 unsigned getBitMask(unsigned Shift, unsigned Width) {
52  return ((1 << Width) - 1) << Shift;
53 }
54 
55 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
56 ///
57 /// \returns Packed \p Dst.
58 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
59  Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
60  Dst |= (Src << Shift) & getBitMask(Shift, Width);
61  return Dst;
62 }
63 
64 /// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
65 ///
66 /// \returns Unpacked bits.
67 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
68  return (Src & getBitMask(Shift, Width)) >> Shift;
69 }
70 
71 /// \returns Vmcnt bit shift (lower bits).
72 unsigned getVmcntBitShiftLo() { return 0; }
73 
74 /// \returns Vmcnt bit width (lower bits).
75 unsigned getVmcntBitWidthLo() { return 4; }
76 
77 /// \returns Expcnt bit shift.
78 unsigned getExpcntBitShift() { return 4; }
79 
80 /// \returns Expcnt bit width.
81 unsigned getExpcntBitWidth() { return 3; }
82 
83 /// \returns Lgkmcnt bit shift.
84 unsigned getLgkmcntBitShift() { return 8; }
85 
86 /// \returns Lgkmcnt bit width.
87 unsigned getLgkmcntBitWidth(unsigned VersionMajor) {
88  return (VersionMajor >= 10) ? 6 : 4;
89 }
90 
91 /// \returns Vmcnt bit shift (higher bits).
92 unsigned getVmcntBitShiftHi() { return 14; }
93 
94 /// \returns Vmcnt bit width (higher bits).
95 unsigned getVmcntBitWidthHi() { return 2; }
96 
97 } // end namespace anonymous
98 
99 namespace llvm {
100 
101 namespace AMDGPU {
102 
103 #define GET_MIMGBaseOpcodesTable_IMPL
104 #define GET_MIMGDimInfoTable_IMPL
105 #define GET_MIMGInfoTable_IMPL
106 #define GET_MIMGLZMappingTable_IMPL
107 #include "AMDGPUGenSearchableTables.inc"
108 
109 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
110  unsigned VDataDwords, unsigned VAddrDwords) {
111  const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
112  VDataDwords, VAddrDwords);
113  return Info ? Info->Opcode : -1;
114 }
115 
116 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) {
117  const MIMGInfo *Info = getMIMGInfo(Opc);
118  return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr;
119 }
120 
121 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) {
122  const MIMGInfo *OrigInfo = getMIMGInfo(Opc);
123  const MIMGInfo *NewInfo =
124  getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
125  NewChannels, OrigInfo->VAddrDwords);
126  return NewInfo ? NewInfo->Opcode : -1;
127 }
128 
129 struct MUBUFInfo {
130  uint16_t Opcode;
131  uint16_t BaseOpcode;
132  uint8_t dwords;
133  bool has_vaddr;
134  bool has_srsrc;
136 };
137 
138 #define GET_MUBUFInfoTable_DECL
139 #define GET_MUBUFInfoTable_IMPL
140 #include "AMDGPUGenSearchableTables.inc"
141 
142 int getMUBUFBaseOpcode(unsigned Opc) {
143  const MUBUFInfo *Info = getMUBUFInfoFromOpcode(Opc);
144  return Info ? Info->BaseOpcode : -1;
145 }
146 
147 int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords) {
148  const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndDwords(BaseOpc, Dwords);
149  return Info ? Info->Opcode : -1;
150 }
151 
152 int getMUBUFDwords(unsigned Opc) {
153  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
154  return Info ? Info->dwords : 0;
155 }
156 
157 bool getMUBUFHasVAddr(unsigned Opc) {
158  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
159  return Info ? Info->has_vaddr : false;
160 }
161 
162 bool getMUBUFHasSrsrc(unsigned Opc) {
163  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
164  return Info ? Info->has_srsrc : false;
165 }
166 
167 bool getMUBUFHasSoffset(unsigned Opc) {
168  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
169  return Info ? Info->has_soffset : false;
170 }
171 
172 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
173 // header files, so we need to wrap it in a function that takes unsigned
174 // instead.
175 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
176  return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
177 }
178 
179 namespace IsaInfo {
180 
181 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
182  auto TargetTriple = STI->getTargetTriple();
183  auto Version = getIsaVersion(STI->getCPU());
184 
185  Stream << TargetTriple.getArchName() << '-'
186  << TargetTriple.getVendorName() << '-'
187  << TargetTriple.getOSName() << '-'
188  << TargetTriple.getEnvironmentName() << '-'
189  << "gfx"
190  << Version.Major
191  << Version.Minor
192  << Version.Stepping;
193 
194  if (hasXNACK(*STI))
195  Stream << "+xnack";
196  if (hasSRAMECC(*STI))
197  Stream << "+sram-ecc";
198 
199  Stream.flush();
200 }
201 
203  return STI->getTargetTriple().getOS() == Triple::AMDHSA &&
204  STI->getFeatureBits().test(FeatureCodeObjectV3);
205 }
206 
207 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
208  if (STI->getFeatureBits().test(FeatureWavefrontSize16))
209  return 16;
210  if (STI->getFeatureBits().test(FeatureWavefrontSize32))
211  return 32;
212 
213  return 64;
214 }
215 
216 unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
217  if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
218  return 32768;
219  if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
220  return 65536;
221 
222  return 0;
223 }
224 
225 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
226  return 4;
227 }
228 
230  unsigned FlatWorkGroupSize) {
231  assert(FlatWorkGroupSize != 0);
232  if (STI->getTargetTriple().getArch() != Triple::amdgcn)
233  return 8;
234  unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
235  if (N == 1)
236  return 40;
237  N = 40 / N;
238  return std::min(N, 16u);
239 }
240 
241 unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI) {
242  return getMaxWavesPerEU() * getEUsPerCU(STI);
243 }
244 
245 unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI,
246  unsigned FlatWorkGroupSize) {
247  return getWavesPerWorkGroup(STI, FlatWorkGroupSize);
248 }
249 
250 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
251  return 1;
252 }
253 
254 unsigned getMaxWavesPerEU() {
255  // FIXME: Need to take scratch memory into account.
256  return 10;
257 }
258 
259 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,
260  unsigned FlatWorkGroupSize) {
261  return alignTo(getMaxWavesPerCU(STI, FlatWorkGroupSize),
262  getEUsPerCU(STI)) / getEUsPerCU(STI);
263 }
264 
266  return 1;
267 }
268 
270  return 2048;
271 }
272 
274  unsigned FlatWorkGroupSize) {
275  return alignTo(FlatWorkGroupSize, getWavefrontSize(STI)) /
276  getWavefrontSize(STI);
277 }
278 
279 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
281  if (Version.Major >= 10)
282  return getAddressableNumSGPRs(STI);
283  if (Version.Major >= 8)
284  return 16;
285  return 8;
286 }
287 
289  return 8;
290 }
291 
292 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
294  if (Version.Major >= 8)
295  return 800;
296  return 512;
297 }
298 
300  if (STI->getFeatureBits().test(FeatureSGPRInitBug))
302 
304  if (Version.Major >= 10)
305  return 106;
306  if (Version.Major >= 8)
307  return 102;
308  return 104;
309 }
310 
311 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
312  assert(WavesPerEU != 0);
313 
315  if (Version.Major >= 10)
316  return 0;
317 
318  if (WavesPerEU >= getMaxWavesPerEU())
319  return 0;
320 
321  unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
322  if (STI->getFeatureBits().test(FeatureTrapHandler))
323  MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
324  MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
325  return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
326 }
327 
328 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
329  bool Addressable) {
330  assert(WavesPerEU != 0);
331 
332  unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
334  if (Version.Major >= 10)
335  return Addressable ? AddressableNumSGPRs : 108;
336  if (Version.Major >= 8 && !Addressable)
337  AddressableNumSGPRs = 112;
338  unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
339  if (STI->getFeatureBits().test(FeatureTrapHandler))
340  MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
341  MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
342  return std::min(MaxNumSGPRs, AddressableNumSGPRs);
343 }
344 
345 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
346  bool FlatScrUsed, bool XNACKUsed) {
347  unsigned ExtraSGPRs = 0;
348  if (VCCUsed)
349  ExtraSGPRs = 2;
350 
352  if (Version.Major >= 10)
353  return ExtraSGPRs;
354 
355  if (Version.Major < 8) {
356  if (FlatScrUsed)
357  ExtraSGPRs = 4;
358  } else {
359  if (XNACKUsed)
360  ExtraSGPRs = 4;
361 
362  if (FlatScrUsed)
363  ExtraSGPRs = 6;
364  }
365 
366  return ExtraSGPRs;
367 }
368 
369 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
370  bool FlatScrUsed) {
371  return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
372  STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
373 }
374 
375 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
376  NumSGPRs = alignTo(std::max(1u, NumSGPRs), getSGPREncodingGranule(STI));
377  // SGPRBlocks is actual number of SGPR blocks minus 1.
378  return NumSGPRs / getSGPREncodingGranule(STI) - 1;
379 }
380 
381 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI) {
382  return 4;
383 }
384 
386  return getVGPRAllocGranule(STI);
387 }
388 
389 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
390  return 256;
391 }
392 
394  return getTotalNumVGPRs(STI);
395 }
396 
397 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
398  assert(WavesPerEU != 0);
399 
400  if (WavesPerEU >= getMaxWavesPerEU())
401  return 0;
402  unsigned MinNumVGPRs =
403  alignDown(getTotalNumVGPRs(STI) / (WavesPerEU + 1),
404  getVGPRAllocGranule(STI)) + 1;
405  return std::min(MinNumVGPRs, getAddressableNumVGPRs(STI));
406 }
407 
408 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
409  assert(WavesPerEU != 0);
410 
411  unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
412  getVGPRAllocGranule(STI));
413  unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
414  return std::min(MaxNumVGPRs, AddressableNumVGPRs);
415 }
416 
417 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs) {
418  NumVGPRs = alignTo(std::max(1u, NumVGPRs), getVGPREncodingGranule(STI));
419  // VGPRBlocks is actual number of VGPR blocks minus 1.
420  return NumVGPRs / getVGPREncodingGranule(STI) - 1;
421 }
422 
423 } // end namespace IsaInfo
424 
426  const MCSubtargetInfo *STI) {
428 
429  memset(&Header, 0, sizeof(Header));
430 
433  Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
434  Header.amd_machine_version_major = Version.Major;
435  Header.amd_machine_version_minor = Version.Minor;
436  Header.amd_machine_version_stepping = Version.Stepping;
437  Header.kernel_code_entry_byte_offset = sizeof(Header);
438  // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
439  Header.wavefront_size = 6;
440 
441  // If the code object does not support indirect functions, then the value must
442  // be 0xffffffff.
443  Header.call_convention = -1;
444 
445  // These alignment values are specified in powers of two, so alignment =
446  // 2^n. The minimum alignment is 2^4 = 16.
447  Header.kernarg_segment_alignment = 4;
448  Header.group_segment_alignment = 4;
449  Header.private_segment_alignment = 4;
450 
451  if (Version.Major >= 10) {
453  S_00B848_WGP_MODE(STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1) |
455  }
456 }
457 
459  const MCSubtargetInfo *STI) {
461 
463  memset(&KD, 0, sizeof(KD));
464 
465  AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
466  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
468  AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
469  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1);
470  AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
471  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1);
472  AMDHSA_BITS_SET(KD.compute_pgm_rsrc2,
473  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1);
474  if (Version.Major >= 10) {
475  AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
476  amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE,
477  STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1);
478  AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
479  amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED, 1);
480  }
481  return KD;
482 }
483 
484 bool isGroupSegment(const GlobalValue *GV) {
486 }
487 
488 bool isGlobalSegment(const GlobalValue *GV) {
490 }
491 
495 }
496 
498  return TT.getOS() != Triple::AMDHSA;
499 }
500 
501 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
502  Attribute A = F.getFnAttribute(Name);
503  int Result = Default;
504 
505  if (A.isStringAttribute()) {
506  StringRef Str = A.getValueAsString();
507  if (Str.getAsInteger(0, Result)) {
508  LLVMContext &Ctx = F.getContext();
509  Ctx.emitError("can't parse integer attribute " + Name);
510  }
511  }
512 
513  return Result;
514 }
515 
516 std::pair<int, int> getIntegerPairAttribute(const Function &F,
517  StringRef Name,
518  std::pair<int, int> Default,
519  bool OnlyFirstRequired) {
520  Attribute A = F.getFnAttribute(Name);
521  if (!A.isStringAttribute())
522  return Default;
523 
524  LLVMContext &Ctx = F.getContext();
525  std::pair<int, int> Ints = Default;
526  std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
527  if (Strs.first.trim().getAsInteger(0, Ints.first)) {
528  Ctx.emitError("can't parse first integer attribute " + Name);
529  return Default;
530  }
531  if (Strs.second.trim().getAsInteger(0, Ints.second)) {
532  if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
533  Ctx.emitError("can't parse second integer attribute " + Name);
534  return Default;
535  }
536  }
537 
538  return Ints;
539 }
540 
542  unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
543  if (Version.Major < 9)
544  return VmcntLo;
545 
546  unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
547  return VmcntLo | VmcntHi;
548 }
549 
551  return (1 << getExpcntBitWidth()) - 1;
552 }
553 
555  return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
556 }
557 
559  unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
560  unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
561  unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(),
562  getLgkmcntBitWidth(Version.Major));
563  unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
564  if (Version.Major < 9)
565  return Waitcnt;
566 
567  unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
568  return Waitcnt | VmcntHi;
569 }
570 
571 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {
572  unsigned VmcntLo =
573  unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
574  if (Version.Major < 9)
575  return VmcntLo;
576 
577  unsigned VmcntHi =
578  unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
579  VmcntHi <<= getVmcntBitWidthLo();
580  return VmcntLo | VmcntHi;
581 }
582 
583 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {
584  return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
585 }
586 
587 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {
588  return unpackBits(Waitcnt, getLgkmcntBitShift(),
589  getLgkmcntBitWidth(Version.Major));
590 }
591 
592 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
593  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
594  Vmcnt = decodeVmcnt(Version, Waitcnt);
595  Expcnt = decodeExpcnt(Version, Waitcnt);
596  Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
597 }
598 
599 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
600  Waitcnt Decoded;
601  Decoded.VmCnt = decodeVmcnt(Version, Encoded);
602  Decoded.ExpCnt = decodeExpcnt(Version, Encoded);
603  Decoded.LgkmCnt = decodeLgkmcnt(Version, Encoded);
604  return Decoded;
605 }
606 
607 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
608  unsigned Vmcnt) {
609  Waitcnt =
610  packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
611  if (Version.Major < 9)
612  return Waitcnt;
613 
614  Vmcnt >>= getVmcntBitWidthLo();
615  return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
616 }
617 
618 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
619  unsigned Expcnt) {
620  return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
621 }
622 
623 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
624  unsigned Lgkmcnt) {
625  return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(),
626  getLgkmcntBitWidth(Version.Major));
627 }
628 
630  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
631  unsigned Waitcnt = getWaitcntBitMask(Version);
632  Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
633  Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
634  Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
635  return Waitcnt;
636 }
637 
638 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
639  return encodeWaitcnt(Version, Decoded.VmCnt, Decoded.ExpCnt, Decoded.LgkmCnt);
640 }
641 
642 unsigned getInitialPSInputAddr(const Function &F) {
643  return getIntegerAttribute(F, "InitialPSInputAddr", 0);
644 }
645 
647  switch(cc) {
655  return true;
656  default:
657  return false;
658  }
659 }
660 
662  return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
663 }
664 
666  switch (CC) {
676  return true;
677  default:
678  return false;
679  }
680 }
681 
682 bool hasXNACK(const MCSubtargetInfo &STI) {
683  return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
684 }
685 
686 bool hasSRAMECC(const MCSubtargetInfo &STI) {
687  return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
688 }
689 
690 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
691  return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128];
692 }
693 
694 bool hasPackedD16(const MCSubtargetInfo &STI) {
695  return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
696 }
697 
698 bool isSI(const MCSubtargetInfo &STI) {
699  return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
700 }
701 
702 bool isCI(const MCSubtargetInfo &STI) {
703  return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
704 }
705 
706 bool isVI(const MCSubtargetInfo &STI) {
707  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
708 }
709 
710 bool isGFX9(const MCSubtargetInfo &STI) {
711  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
712 }
713 
714 bool isGFX10(const MCSubtargetInfo &STI) {
715  return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
716 }
717 
718 bool isGCN3Encoding(const MCSubtargetInfo &STI) {
719  return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
720 }
721 
722 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
723  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
724  const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
725  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
726  Reg == AMDGPU::SCC;
727 }
728 
729 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
730  for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
731  if (*R == Reg1) return true;
732  }
733  return false;
734 }
735 
736 #define MAP_REG2REG \
737  using namespace AMDGPU; \
738  switch(Reg) { \
739  default: return Reg; \
740  CASE_CI_VI(FLAT_SCR) \
741  CASE_CI_VI(FLAT_SCR_LO) \
742  CASE_CI_VI(FLAT_SCR_HI) \
743  CASE_VI_GFX9_GFX10(TTMP0) \
744  CASE_VI_GFX9_GFX10(TTMP1) \
745  CASE_VI_GFX9_GFX10(TTMP2) \
746  CASE_VI_GFX9_GFX10(TTMP3) \
747  CASE_VI_GFX9_GFX10(TTMP4) \
748  CASE_VI_GFX9_GFX10(TTMP5) \
749  CASE_VI_GFX9_GFX10(TTMP6) \
750  CASE_VI_GFX9_GFX10(TTMP7) \
751  CASE_VI_GFX9_GFX10(TTMP8) \
752  CASE_VI_GFX9_GFX10(TTMP9) \
753  CASE_VI_GFX9_GFX10(TTMP10) \
754  CASE_VI_GFX9_GFX10(TTMP11) \
755  CASE_VI_GFX9_GFX10(TTMP12) \
756  CASE_VI_GFX9_GFX10(TTMP13) \
757  CASE_VI_GFX9_GFX10(TTMP14) \
758  CASE_VI_GFX9_GFX10(TTMP15) \
759  CASE_VI_GFX9_GFX10(TTMP0_TTMP1) \
760  CASE_VI_GFX9_GFX10(TTMP2_TTMP3) \
761  CASE_VI_GFX9_GFX10(TTMP4_TTMP5) \
762  CASE_VI_GFX9_GFX10(TTMP6_TTMP7) \
763  CASE_VI_GFX9_GFX10(TTMP8_TTMP9) \
764  CASE_VI_GFX9_GFX10(TTMP10_TTMP11) \
765  CASE_VI_GFX9_GFX10(TTMP12_TTMP13) \
766  CASE_VI_GFX9_GFX10(TTMP14_TTMP15) \
767  CASE_VI_GFX9_GFX10(TTMP0_TTMP1_TTMP2_TTMP3) \
768  CASE_VI_GFX9_GFX10(TTMP4_TTMP5_TTMP6_TTMP7) \
769  CASE_VI_GFX9_GFX10(TTMP8_TTMP9_TTMP10_TTMP11) \
770  CASE_VI_GFX9_GFX10(TTMP12_TTMP13_TTMP14_TTMP15) \
771  CASE_VI_GFX9_GFX10(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
772  CASE_VI_GFX9_GFX10(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
773  CASE_VI_GFX9_GFX10(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
774  CASE_VI_GFX9_GFX10(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
775  }
776 
777 #define CASE_CI_VI(node) \
778  assert(!isSI(STI)); \
779  case node: return isCI(STI) ? node##_ci : node##_vi;
780 
781 #define CASE_VI_GFX9_GFX10(node) \
782  case node: return (isGFX9(STI) || isGFX10(STI)) ? node##_gfx9_gfx10 : node##_vi;
783 
784 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
785  if (STI.getTargetTriple().getArch() == Triple::r600)
786  return Reg;
788 }
789 
790 #undef CASE_CI_VI
791 #undef CASE_VI_GFX9_GFX10
792 
793 #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
794 #define CASE_VI_GFX9_GFX10(node) case node##_vi: case node##_gfx9_gfx10: return node;
795 
796 unsigned mc2PseudoReg(unsigned Reg) {
798 }
799 
800 #undef CASE_CI_VI
801 #undef CASE_VI_GFX9_GFX10
802 #undef MAP_REG2REG
803 
804 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
805  assert(OpNo < Desc.NumOperands);
806  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
807  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
808  OpType <= AMDGPU::OPERAND_SRC_LAST;
809 }
810 
811 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
812  assert(OpNo < Desc.NumOperands);
813  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
814  switch (OpType) {
825  return true;
826  default:
827  return false;
828  }
829 }
830 
831 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
832  assert(OpNo < Desc.NumOperands);
833  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
834  return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
836 }
837 
838 // Avoid using MCRegisterClass::getSize, since that function will go away
839 // (move from MC* level to Target* level). Return size in bits.
840 unsigned getRegBitWidth(unsigned RCID) {
841  switch (RCID) {
842  case AMDGPU::SGPR_32RegClassID:
843  case AMDGPU::VGPR_32RegClassID:
844  case AMDGPU::VRegOrLds_32RegClassID:
845  case AMDGPU::VS_32RegClassID:
846  case AMDGPU::SReg_32RegClassID:
847  case AMDGPU::SReg_32_XM0RegClassID:
848  case AMDGPU::SRegOrLds_32RegClassID:
849  return 32;
850  case AMDGPU::SGPR_64RegClassID:
851  case AMDGPU::VS_64RegClassID:
852  case AMDGPU::SReg_64RegClassID:
853  case AMDGPU::VReg_64RegClassID:
854  case AMDGPU::SReg_64_XEXECRegClassID:
855  return 64;
856  case AMDGPU::SGPR_96RegClassID:
857  case AMDGPU::SReg_96RegClassID:
858  case AMDGPU::VReg_96RegClassID:
859  return 96;
860  case AMDGPU::SGPR_128RegClassID:
861  case AMDGPU::SReg_128RegClassID:
862  case AMDGPU::VReg_128RegClassID:
863  return 128;
864  case AMDGPU::SGPR_160RegClassID:
865  case AMDGPU::SReg_160RegClassID:
866  case AMDGPU::VReg_160RegClassID:
867  return 160;
868  case AMDGPU::SReg_256RegClassID:
869  case AMDGPU::VReg_256RegClassID:
870  return 256;
871  case AMDGPU::SReg_512RegClassID:
872  case AMDGPU::VReg_512RegClassID:
873  return 512;
874  default:
875  llvm_unreachable("Unexpected register class");
876  }
877 }
878 
879 unsigned getRegBitWidth(const MCRegisterClass &RC) {
880  return getRegBitWidth(RC.getID());
881 }
882 
883 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
884  unsigned OpNo) {
885  assert(OpNo < Desc.NumOperands);
886  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
887  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
888 }
889 
890 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
891  if (Literal >= -16 && Literal <= 64)
892  return true;
893 
894  uint64_t Val = static_cast<uint64_t>(Literal);
895  return (Val == DoubleToBits(0.0)) ||
896  (Val == DoubleToBits(1.0)) ||
897  (Val == DoubleToBits(-1.0)) ||
898  (Val == DoubleToBits(0.5)) ||
899  (Val == DoubleToBits(-0.5)) ||
900  (Val == DoubleToBits(2.0)) ||
901  (Val == DoubleToBits(-2.0)) ||
902  (Val == DoubleToBits(4.0)) ||
903  (Val == DoubleToBits(-4.0)) ||
904  (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
905 }
906 
907 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
908  if (Literal >= -16 && Literal <= 64)
909  return true;
910 
911  // The actual type of the operand does not seem to matter as long
912  // as the bits match one of the inline immediate values. For example:
913  //
914  // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
915  // so it is a legal inline immediate.
916  //
917  // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
918  // floating-point, so it is a legal inline immediate.
919 
920  uint32_t Val = static_cast<uint32_t>(Literal);
921  return (Val == FloatToBits(0.0f)) ||
922  (Val == FloatToBits(1.0f)) ||
923  (Val == FloatToBits(-1.0f)) ||
924  (Val == FloatToBits(0.5f)) ||
925  (Val == FloatToBits(-0.5f)) ||
926  (Val == FloatToBits(2.0f)) ||
927  (Val == FloatToBits(-2.0f)) ||
928  (Val == FloatToBits(4.0f)) ||
929  (Val == FloatToBits(-4.0f)) ||
930  (Val == 0x3e22f983 && HasInv2Pi);
931 }
932 
933 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
934  if (!HasInv2Pi)
935  return false;
936 
937  if (Literal >= -16 && Literal <= 64)
938  return true;
939 
940  uint16_t Val = static_cast<uint16_t>(Literal);
941  return Val == 0x3C00 || // 1.0
942  Val == 0xBC00 || // -1.0
943  Val == 0x3800 || // 0.5
944  Val == 0xB800 || // -0.5
945  Val == 0x4000 || // 2.0
946  Val == 0xC000 || // -2.0
947  Val == 0x4400 || // 4.0
948  Val == 0xC400 || // -4.0
949  Val == 0x3118; // 1/2pi
950 }
951 
952 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
953  assert(HasInv2Pi);
954 
955  if (isInt<16>(Literal) || isUInt<16>(Literal)) {
956  int16_t Trunc = static_cast<int16_t>(Literal);
957  return AMDGPU::isInlinableLiteral16(Trunc, HasInv2Pi);
958  }
959  if (!(Literal & 0xffff))
960  return AMDGPU::isInlinableLiteral16(Literal >> 16, HasInv2Pi);
961 
962  int16_t Lo16 = static_cast<int16_t>(Literal);
963  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
964  return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
965 }
966 
967 bool isArgPassedInSGPR(const Argument *A) {
968  const Function *F = A->getParent();
969 
970  // Arguments to compute shaders are never a source of divergence.
972  switch (CC) {
975  return true;
983  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
984  // Everything else is in VGPRs.
985  return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
986  F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
987  default:
988  // TODO: Should calls support inreg for SGPR inputs?
989  return false;
990  }
991 }
992 
993 static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
994  return isGCN3Encoding(ST) || isGFX10(ST);
995 }
996 
997 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
998  if (hasSMEMByteOffset(ST))
999  return ByteOffset;
1000  return ByteOffset >> 2;
1001 }
1002 
1003 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
1004  int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
1005  return (hasSMEMByteOffset(ST)) ?
1006  isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
1007 }
1008 
1009 // Given Imm, split it into the values to put into the SOffset and ImmOffset
1010 // fields in an MUBUF instruction. Return false if it is not possible (due to a
1011 // hardware bug needing a workaround).
1012 //
1013 // The required alignment ensures that individual address components remain
1014 // aligned if they are aligned to begin with. It also ensures that additional
1015 // offsets within the given alignment can be added to the resulting ImmOffset.
1016 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1017  const GCNSubtarget *Subtarget, uint32_t Align) {
1018  const uint32_t MaxImm = alignDown(4095, Align);
1019  uint32_t Overflow = 0;
1020 
1021  if (Imm > MaxImm) {
1022  if (Imm <= MaxImm + 64) {
1023  // Use an SOffset inline constant for 4..64
1024  Overflow = Imm - MaxImm;
1025  Imm = MaxImm;
1026  } else {
1027  // Try to keep the same value in SOffset for adjacent loads, so that
1028  // the corresponding register contents can be re-used.
1029  //
1030  // Load values with all low-bits (except for alignment bits) set into
1031  // SOffset, so that a larger range of values can be covered using
1032  // s_movk_i32.
1033  //
1034  // Atomic operations fail to work correctly when individual address
1035  // components are unaligned, even if their sum is aligned.
1036  uint32_t High = (Imm + Align) & ~4095;
1037  uint32_t Low = (Imm + Align) & 4095;
1038  Imm = Low;
1039  Overflow = High - Align;
1040  }
1041  }
1042 
1043  // There is a hardware bug in SI and CI which prevents address clamping in
1044  // MUBUF instructions from working correctly with SOffsets. The immediate
1045  // offset is unaffected.
1046  if (Overflow > 0 &&
1048  return false;
1049 
1050  ImmOffset = Imm;
1051  SOffset = Overflow;
1052  return true;
1053 }
1054 
1056  *this = getDefaultForCallingConv(F.getCallingConv());
1057 
1058  StringRef IEEEAttr = F.getFnAttribute("amdgpu-ieee").getValueAsString();
1059  if (!IEEEAttr.empty())
1060  IEEE = IEEEAttr == "true";
1061 
1062  StringRef DX10ClampAttr
1063  = F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString();
1064  if (!DX10ClampAttr.empty())
1065  DX10Clamp = DX10ClampAttr == "true";
1066 }
1067 
1068 namespace {
1069 
1070 struct SourceOfDivergence {
1071  unsigned Intr;
1072 };
1073 const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
1074 
1075 #define GET_SourcesOfDivergence_IMPL
1076 #include "AMDGPUGenSearchableTables.inc"
1077 
1078 } // end anonymous namespace
1079 
1080 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
1081  return lookupSourceOfDivergence(IntrID);
1082 }
1083 
1084 } // namespace AMDGPU
1085 } // namespace llvm
int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords)
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
This file a TargetTransformInfo::Concept conforming object specific to the AMDGPU target machine...
bool hasPackedD16(const MCSubtargetInfo &STI)
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
bool getMUBUFHasSrsrc(unsigned Opc)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:200
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getExpcntBitMask(const IsaVersion &Version)
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:301
Represents the counter values to wait for in an s_waitcnt instruction.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Instruction set architecture version.
Definition: TargetParser.h:133
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
#define S_00B848_WGP_MODE(x)
Definition: SIDefines.h:540
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
Address space for 32-bit constant memory.
Definition: AMDGPU.h:261
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
int getMUBUFDwords(unsigned Opc)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
uint64_t High
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
const Triple & getTargetTriple() const
bool isGlobalSegment(const GlobalValue *GV)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
unsigned getID() const
getID() - Return the register class ID number.
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
#define S_00B848_MEM_ORDERED(x)
Definition: SIDefines.h:543
uint32_t amd_kernel_code_version_major
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:717
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
bool isStringAttribute() const
Return true if the attribute is a string (target-dependent) attribute.
Definition: Attributes.cpp:169
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
AMD Kernel Code Object (amd_kernel_code_t).
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
uint16_t amd_machine_version_major
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs)
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned Intr
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
bool hasCodeObjectV3(const MCSubtargetInfo *STI)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:78
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment...
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, uint32_t Align)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:292
Address space for local memory.
Definition: AMDGPU.h:258
uint8_t group_segment_alignment
bool isGroupSegment(const GlobalValue *GV)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
bool isReadOnlySegment(const GlobalValue *GV)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
uint16_t amd_machine_version_minor
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint32_t amd_kernel_code_version_minor
MCRegisterClass - Base class of TargetRegisterClass.
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
unsigned short NumOperands
Definition: MCInstrDesc.h:166
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:600
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:215
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
bool hasSRAMECC(const MCSubtargetInfo &STI)
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isCompute(CallingConv::ID cc)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
bool isSI(const MCSubtargetInfo &STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:342
unsigned const MachineRegisterInfo * MRI
bool getMUBUFHasSoffset(unsigned Opc)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
bool isGFX10(const MCSubtargetInfo &STI)
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
bool hasMIMG_R128(const MCSubtargetInfo &STI)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isEntryFunctionCC(CallingConv::ID CC)
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
int getMUBUFBaseOpcode(unsigned Opc)
uint8_t private_segment_alignment
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:254
MCRegAliasIterator enumerates all registers aliasing Reg.
Generation getGeneration() const
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:526
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:196
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
#define AMDHSA_BITS_SET(DST, MSK, VAL)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:136
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
IsaVersion getIsaVersion(StringRef GPU)
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI)
bool hasParamAttribute(unsigned ArgNo, Attribute::AttrKind Kind) const
Equivalent to hasAttribute(ArgNo + FirstArgIndex, Kind).
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Address space for constant memory (VTX2).
Definition: AMDGPU.h:257
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Module.h This file contains the declarations for the Module class.
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:188
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
uint16_t amd_machine_version_stepping
uint8_t wavefront_size
Wavefront size expressed as a power of two.
bool isArgPassedInSGPR(const Argument *A)
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:590
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed)
StringRef getCPU() const
bool isShader(CallingConv::ID cc)
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:197
unsigned getArgNo() const
Return the index of this formal argument in its containing function.
Definition: Argument.h:47
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
constexpr char NumVGPRs[]
Key for Kernel::CodeProps::Metadata::mNumVGPRs.
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:220
bool isGCN3Encoding(const MCSubtargetInfo &STI)
#define MAP_REG2REG
bool isCI(const MCSubtargetInfo &STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getInitialPSInputAddr(const Function &F)
bool isGFX9(const MCSubtargetInfo &STI)
Provides AMDGPU specific target descriptions.
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
const Function * getParent() const
Definition: Argument.h:41
bool isVI(const MCSubtargetInfo &STI)
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
bool hasXNACK(const MCSubtargetInfo &STI)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
#define N
Generic base class for all target subtargets.
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool shouldEmitConstantsToTextSection(const Triple &TT)
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
int64_t kernel_code_entry_byte_offset
Byte offset (possibly negative) from start of amd_kernel_code_t object to kernel&#39;s entry point instru...
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
uint16_t amd_machine_kind
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFHasVAddr(unsigned Opc)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
const uint64_t Version
Definition: InstrProf.h:984
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:273
constexpr uint32_t VersionMajor
HSA metadata major version.
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned getVmcntBitMask(const IsaVersion &Version)
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...