LLVM  10.0.0svn
AMDGPUInstructionSelector.h
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1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
22 #include "llvm/IR/InstrTypes.h"
23 
24 namespace {
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
30 }
31 
32 namespace llvm {
33 
34 class AMDGPUInstrInfo;
35 class AMDGPURegisterBankInfo;
36 class GCNSubtarget;
37 class MachineInstr;
38 class MachineIRBuilder;
39 class MachineOperand;
40 class MachineRegisterInfo;
41 class SIInstrInfo;
42 class SIMachineFunctionInfo;
43 class SIRegisterInfo;
44 
46 private:
48 
49 public:
51  const AMDGPURegisterBankInfo &RBI,
52  const AMDGPUTargetMachine &TM);
53 
54  bool select(MachineInstr &I) override;
55  static const char *getName();
56 
58  CodeGenCoverage &CoverageInfo) override;
59 
60 private:
61  struct GEPInfo {
62  const MachineInstr &GEP;
63  SmallVector<unsigned, 2> SgprParts;
64  SmallVector<unsigned, 2> VgprParts;
65  int64_t Imm;
66  GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
67  };
68 
69  bool isInstrUniform(const MachineInstr &MI) const;
70  bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
71 
72  /// tblgen-erated 'select' implementation.
73  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
74 
75  MachineOperand getSubOperand64(MachineOperand &MO,
76  const TargetRegisterClass &SubRC,
77  unsigned SubIdx) const;
78  bool selectCOPY(MachineInstr &I) const;
79  bool selectPHI(MachineInstr &I) const;
80  bool selectG_TRUNC(MachineInstr &I) const;
81  bool selectG_SZA_EXT(MachineInstr &I) const;
82  bool selectG_SITOFP_UITOFP(MachineInstr &I) const;
83  bool selectG_CONSTANT(MachineInstr &I) const;
84  bool selectG_AND_OR_XOR(MachineInstr &I) const;
85  bool selectG_ADD_SUB(MachineInstr &I) const;
86  bool selectG_UADDO_USUBO(MachineInstr &I) const;
87  bool selectG_EXTRACT(MachineInstr &I) const;
88  bool selectG_MERGE_VALUES(MachineInstr &I) const;
89  bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
90  bool selectG_GEP(MachineInstr &I) const;
91  bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
92  bool selectG_INSERT(MachineInstr &I) const;
93  bool selectG_INTRINSIC(MachineInstr &I) const;
94 
95  std::tuple<Register, unsigned, unsigned>
96  splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
97 
98  bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
99 
100  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
101  int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
102  bool selectG_ICMP(MachineInstr &I) const;
103  bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
104  void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
105  SmallVectorImpl<GEPInfo> &AddrInfo) const;
106  bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
107 
108  void initM0(MachineInstr &I) const;
109  bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
110  bool selectG_STORE(MachineInstr &I) const;
111  bool selectG_SELECT(MachineInstr &I) const;
112  bool selectG_BRCOND(MachineInstr &I) const;
113  bool selectG_FRAME_INDEX(MachineInstr &I) const;
114  bool selectG_PTR_MASK(MachineInstr &I) const;
115 
116  std::pair<Register, unsigned>
117  selectVOP3ModsImpl(Register Src) const;
118 
120  selectVCSRC(MachineOperand &Root) const;
121 
123  selectVSRC0(MachineOperand &Root) const;
124 
126  selectVOP3Mods0(MachineOperand &Root) const;
128  selectVOP3Mods0Clamp0OMod(MachineOperand &Root) const;
130  selectVOP3OMods(MachineOperand &Root) const;
132  selectVOP3Mods(MachineOperand &Root) const;
133 
135  selectVOP3OpSelMods0(MachineOperand &Root) const;
137  selectVOP3OpSelMods(MachineOperand &Root) const;
138 
140  selectSmrdImm(MachineOperand &Root) const;
142  selectSmrdImm32(MachineOperand &Root) const;
144  selectSmrdSgpr(MachineOperand &Root) const;
145 
146  template <bool Signed>
148  selectFlatOffsetImpl(MachineOperand &Root) const;
150  selectFlatOffset(MachineOperand &Root) const;
151 
153  selectFlatOffsetSigned(MachineOperand &Root) const;
154 
156  selectMUBUFScratchOffen(MachineOperand &Root) const;
158  selectMUBUFScratchOffset(MachineOperand &Root) const;
159 
160  bool isDSOffsetLegal(const MachineRegisterInfo &MRI,
161  const MachineOperand &Base,
162  int64_t Offset, unsigned OffsetBits) const;
163 
165  selectDS1Addr1Offset(MachineOperand &Root) const;
166 
167  void renderTruncImm32(MachineInstrBuilder &MIB,
168  const MachineInstr &MI) const;
169 
170  const SIInstrInfo &TII;
171  const SIRegisterInfo &TRI;
172  const AMDGPURegisterBankInfo &RBI;
173  const AMDGPUTargetMachine &TM;
174  const GCNSubtarget &STI;
175  bool EnableLateStructurizeCFG;
176 #define GET_GLOBALISEL_PREDICATES_DECL
177 #define AMDGPUSubtarget GCNSubtarget
178 #include "AMDGPUGenGlobalISel.inc"
179 #undef GET_GLOBALISEL_PREDICATES_DECL
180 #undef AMDGPUSubtarget
181 
182 #define GET_GLOBALISEL_TEMPORARIES_DECL
183 #include "AMDGPUGenGlobalISel.inc"
184 #undef GET_GLOBALISEL_TEMPORARIES_DECL
185 };
186 
187 } // End llvm namespace.
188 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
unsigned Reg
unsigned const TargetRegisterInfo * TRI
Hexagon Common GEP
static const char * getName()
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
void setupMF(MachineFunction &MF, GISelKnownBits &KB, CodeGenCoverage &CoverageInfo) override
Setup per-MF selector state.
#define P(N)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Helper class to build MachineInstr.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t Size
Definition: Profile.cpp:46
IRTranslator LLVM IR MI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19