LLVM  9.0.0svn
AMDGPUMCInstLower.cpp
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1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
15 #include "AMDGPUAsmPrinter.h"
16 #include "AMDGPUSubtarget.h"
17 #include "AMDGPUTargetMachine.h"
20 #include "R600AsmPrinter.h"
21 #include "SIInstrInfo.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCCodeEmitter.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
32 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/Support/Format.h"
35 #include <algorithm>
36 
37 using namespace llvm;
38 
39 namespace {
40 
41 class AMDGPUMCInstLower {
42  MCContext &Ctx;
43  const TargetSubtargetInfo &ST;
44  const AsmPrinter &AP;
45 
46  const MCExpr *getLongBranchBlockExpr(const MachineBasicBlock &SrcBB,
47  const MachineOperand &MO) const;
48 
49 public:
50  AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST,
51  const AsmPrinter &AP);
52 
53  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
54 
55  /// Lower a MachineInstr to an MCInst
56  void lower(const MachineInstr *MI, MCInst &OutMI) const;
57 
58 };
59 
60 class R600MCInstLower : public AMDGPUMCInstLower {
61 public:
62  R600MCInstLower(MCContext &ctx, const R600Subtarget &ST,
63  const AsmPrinter &AP);
64 
65  /// Lower a MachineInstr to an MCInst
66  void lower(const MachineInstr *MI, MCInst &OutMI) const;
67 };
68 
69 
70 } // End anonymous namespace
71 
72 #include "AMDGPUGenMCPseudoLowering.inc"
73 
74 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx,
75  const TargetSubtargetInfo &st,
76  const AsmPrinter &ap):
77  Ctx(ctx), ST(st), AP(ap) { }
78 
79 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
80  switch (MOFlags) {
81  default:
93  }
94 }
95 
96 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
97  const MachineBasicBlock &SrcBB,
98  const MachineOperand &MO) const {
99  const MCExpr *DestBBSym
100  = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
101  const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
102 
103  // FIXME: The first half of this assert should be removed. This should
104  // probably be PC relative instead of using the source block symbol, and
105  // therefore the indirect branch expansion should use a bundle.
106  assert(
107  skipDebugInstructionsForward(SrcBB.begin(), SrcBB.end())->getOpcode() ==
108  AMDGPU::S_GETPC_B64 &&
109  ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
110 
111  // s_getpc_b64 returns the address of next instruction.
112  const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
113  SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
114 
116  return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
117 
119  return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
120 }
121 
122 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
123  MCOperand &MCOp) const {
124  switch (MO.getType()) {
125  default:
126  llvm_unreachable("unknown operand type");
128  MCOp = MCOperand::createImm(MO.getImm());
129  return true;
132  return true;
134  if (MO.getTargetFlags() != 0) {
135  MCOp = MCOperand::createExpr(
136  getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
137  } else {
138  MCOp = MCOperand::createExpr(
140  }
141 
142  return true;
143  }
145  const GlobalValue *GV = MO.getGlobal();
147  AP.getNameWithPrefix(SymbolName, GV);
148  MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
149  const MCExpr *SymExpr =
151  const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
152  MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
153  MCOp = MCOperand::createExpr(Expr);
154  return true;
155  }
157  MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
158  Sym->setExternal(true);
159  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
160  MCOp = MCOperand::createExpr(Expr);
161  return true;
162  }
164  // Regmasks are like implicit defs.
165  return false;
166  }
167 }
168 
169 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
170  unsigned Opcode = MI->getOpcode();
171  const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
172 
173  // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
174  // need to select it to the subtarget specific version, and there's no way to
175  // do that with a single pseudo source operation.
176  if (Opcode == AMDGPU::S_SETPC_B64_return)
177  Opcode = AMDGPU::S_SETPC_B64;
178  else if (Opcode == AMDGPU::SI_CALL) {
179  // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
180  // called function (which we need to remove here).
181  OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
182  MCOperand Dest, Src;
183  lowerOperand(MI->getOperand(0), Dest);
184  lowerOperand(MI->getOperand(1), Src);
185  OutMI.addOperand(Dest);
186  OutMI.addOperand(Src);
187  return;
188  } else if (Opcode == AMDGPU::SI_TCRETURN) {
189  // TODO: How to use branch immediate and avoid register+add?
190  Opcode = AMDGPU::S_SETPC_B64;
191  }
192 
193  int MCOpcode = TII->pseudoToMCOpcode(Opcode);
194  if (MCOpcode == -1) {
196  C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
197  "a target-specific version: " + Twine(MI->getOpcode()));
198  }
199 
200  OutMI.setOpcode(MCOpcode);
201 
202  for (const MachineOperand &MO : MI->explicit_operands()) {
203  MCOperand MCOp;
204  lowerOperand(MO, MCOp);
205  OutMI.addOperand(MCOp);
206  }
207 }
208 
210  MCOperand &MCOp) const {
211  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
212  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
213  return MCInstLowering.lowerOperand(MO, MCOp);
214 }
215 
217  const Constant *CV,
219  // TargetMachine does not support llvm-style cast. Use C++-style cast.
220  // This is safe since TM is always of type AMDGPUTargetMachine or its
221  // derived class.
222  auto &AT = static_cast<const AMDGPUTargetMachine&>(TM);
223  auto *CE = dyn_cast<ConstantExpr>(CV);
224 
225  // Lower null pointers in private and local address space.
226  // Clang generates addrspacecast for null pointers in private and local
227  // address space, which needs to be lowered.
228  if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
229  auto Op = CE->getOperand(0);
230  auto SrcAddr = Op->getType()->getPointerAddressSpace();
231  if (Op->isNullValue() && AT.getNullPointerValue(SrcAddr) == 0) {
232  auto DstAddr = CE->getType()->getPointerAddressSpace();
233  return MCConstantExpr::create(AT.getNullPointerValue(DstAddr),
234  OutContext);
235  }
236  }
237  return nullptr;
238 }
239 
241  if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
242  return E;
243  return AsmPrinter::lowerConstant(CV);
244 }
245 
248  return;
249 
250  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
251  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
252 
253  StringRef Err;
254  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
256  C.emitError("Illegal instruction detected: " + Err);
257  MI->print(errs());
258  }
259 
260  if (MI->isBundle()) {
261  const MachineBasicBlock *MBB = MI->getParent();
263  while (I != MBB->instr_end() && I->isInsideBundle()) {
264  EmitInstruction(&*I);
265  ++I;
266  }
267  } else {
268  // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
269  // placeholder terminator instructions and should only be printed as
270  // comments.
271  if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
272  if (isVerbose()) {
273  SmallVector<char, 16> BBStr;
274  raw_svector_ostream Str(BBStr);
275 
276  const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
277  const MCSymbolRefExpr *Expr
279  Expr->print(Str, MAI);
280  OutStreamer->emitRawComment(Twine(" mask branch ") + BBStr);
281  }
282 
283  return;
284  }
285 
286  if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
287  if (isVerbose())
288  OutStreamer->emitRawComment(" return to shader part epilog");
289  return;
290  }
291 
292  if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
293  if (isVerbose())
294  OutStreamer->emitRawComment(" wave barrier");
295  return;
296  }
297 
298  if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
299  if (isVerbose())
300  OutStreamer->emitRawComment(" divergent unreachable");
301  return;
302  }
303 
304  MCInst TmpInst;
305  MCInstLowering.lower(MI, TmpInst);
306  EmitToStreamer(*OutStreamer, TmpInst);
307 
308 #ifdef EXPENSIVE_CHECKS
309  // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
310  // work correctly for the generic CPU).
311  //
312  // The isPseudo check really shouldn't be here, but unfortunately there are
313  // some negative lit tests that depend on being able to continue through
314  // here even when pseudo instructions haven't been lowered.
315  if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU())) {
317  SmallVector<char, 16> CodeBytes;
318  raw_svector_ostream CodeStream(CodeBytes);
319 
320  std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
322  InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
323 
324  assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
325  }
326 #endif
327 
328  if (DumpCodeInstEmitter) {
329  // Disassemble instruction/operands to text
330  DisasmLines.resize(DisasmLines.size() + 1);
331  std::string &DisasmLine = DisasmLines.back();
332  raw_string_ostream DisasmStream(DisasmLine);
333 
334  AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
335  *STI.getRegisterInfo());
336  InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
337 
338  // Disassemble instruction/operands to hex representation.
340  SmallVector<char, 16> CodeBytes;
341  raw_svector_ostream CodeStream(CodeBytes);
342 
343  DumpCodeInstEmitter->encodeInstruction(
344  TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
345  HexLines.resize(HexLines.size() + 1);
346  std::string &HexLine = HexLines.back();
347  raw_string_ostream HexStream(HexLine);
348 
349  for (size_t i = 0; i < CodeBytes.size(); i += 4) {
350  unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
351  HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
352  }
353 
354  DisasmStream.flush();
355  DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
356  }
357  }
358 }
359 
360 R600MCInstLower::R600MCInstLower(MCContext &Ctx, const R600Subtarget &ST,
361  const AsmPrinter &AP) :
362  AMDGPUMCInstLower(Ctx, ST, AP) { }
363 
364 void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
365  OutMI.setOpcode(MI->getOpcode());
366  for (const MachineOperand &MO : MI->explicit_operands()) {
367  MCOperand MCOp;
368  lowerOperand(MO, MCOp);
369  OutMI.addOperand(MCOp);
370  }
371 }
372 
374  const R600Subtarget &STI = MF->getSubtarget<R600Subtarget>();
375  R600MCInstLower MCInstLowering(OutContext, STI, *this);
376 
377  StringRef Err;
378  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
380  C.emitError("Illegal instruction detected: " + Err);
381  MI->print(errs());
382  }
383 
384  if (MI->isBundle()) {
385  const MachineBasicBlock *MBB = MI->getParent();
387  while (I != MBB->instr_end() && I->isInsideBundle()) {
388  EmitInstruction(&*I);
389  ++I;
390  }
391  } else {
392  MCInst TmpInst;
393  MCInstLowering.lower(MI, TmpInst);
394  EmitToStreamer(*OutStreamer, TmpInst);
395  }
396 }
397 
399  if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
400  return E;
401  return AsmPrinter::lowerConstant(CV);
402 }
unsigned getTargetFlags() const
uint64_t CallInst * C
void EmitInstruction(const MachineInstr *MI) override
Implemented in AMDGPUMCInstLower.cpp.
const MCExpr * lowerConstant(const Constant *CV) override
Lower the specified LLVM Constant to an MCExpr.
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
AMDGPU specific subclass of TargetSubtarget.
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const MCExpr * lowerConstant(const Constant *CV) override
Lower the specified LLVM Constant to an MCExpr.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:464
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI)
tblgen&#39;erated driver function for lowering simple MI->MC pseudo instructions.
unsigned getReg() const
getReg - Returns the register number.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:123
const SIInstrInfo * getInstrInfo() const override
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
MachineBasicBlock reference.
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
Mask of preserved registers.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
void setExternal(bool Value) const
Definition: MCSymbol.h:393
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
const HexagonInstrInfo * TII
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:196
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Name of external global symbol.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
const char * getSymbolName() const
Context object for machine code objects.
Definition: MCContext.h:62
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:888
void EmitInstruction(const MachineInstr *MI) override
Implemented in AMDGPUMCInstLower.cpp.
bool isBundle() const
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:544
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:459
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:199
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
Address of a global value.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:618
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const GlobalValue * getGlobal() const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
const R600InstrInfo * getInstrInfo() const override
self_iterator getIterator()
Definition: ilist_node.h:81
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
The AMDGPU TargetMachine interface definition for hw codgen targets.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:196
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags)
Iterator for intrusive lists based on ilist_node.
std::vector< std::string > HexLines
void setOpcode(unsigned Op)
Definition: MCInst.h:170
virtual const MCExpr * lowerConstant(const Constant *CV)
Lower the specified LLVM Constant to an MCExpr.
R600 Assembly printer class.
MachineOperand class - Representation of each machine instruction operand.
static const MCExpr * lowerAddrSpaceCast(const TargetMachine &TM, const Constant *CV, MCContext &OutContext)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:231
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
std::vector< std::string > DisasmLines
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
TargetSubtargetInfo - Generic base class for all target subtargets.
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Interface definition for SIInstrInfo.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
AMDGPU Assembly printer class.
Generic base class for all target subtargets.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
Wrapper for MCInstLowering.lowerOperand() for the tblgen&#39;erated pseudo lowering.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
const SIRegisterInfo * getRegisterInfo() const override