LLVM  10.0.0svn
Macros | Functions
AMDGPURegisterBankInfo.cpp File Reference

This file implements the targeting of the RegisterBankInfo class for AMDGPU. More...

#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "AMDGPUGenRegisterBank.inc"
#include "AMDGPUGenRegisterBankInfo.def"
Include dependency graph for AMDGPURegisterBankInfo.cpp:

Go to the source code of this file.

Macros

#define GET_TARGET_REGBANK_IMPL
 

Functions

static bool isInstrUniform (const MachineInstr &MI)
 
static void setRegsToType (MachineRegisterInfo &MRI, ArrayRef< Register > Regs, LLT NewTy)
 Replace the current type each register in Regs has with NewTy. More...
 
static LLT getHalfSizedType (LLT Ty)
 
static MachineInstrgetOtherVRegDef (const MachineRegisterInfo &MRI, Register Reg, const MachineInstr &MI)
 
static void substituteSimpleCopyRegs (const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper, unsigned OpIdx)
 

Detailed Description

This file implements the targeting of the RegisterBankInfo class for AMDGPU.

Todo:
This should be generated by TableGen.

Definition in file AMDGPURegisterBankInfo.cpp.

Macro Definition Documentation

◆ GET_TARGET_REGBANK_IMPL

#define GET_TARGET_REGBANK_IMPL

Definition at line 29 of file AMDGPURegisterBankInfo.cpp.

Function Documentation

◆ getHalfSizedType()

static LLT getHalfSizedType ( LLT  Ty)
static

Definition at line 607 of file AMDGPURegisterBankInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), B, llvm::MachineBasicBlock::begin(), llvm::MachineIRBuilder::buildBuildVector(), llvm::MachineIRBuilder::buildInstr(), llvm::MachineIRBuilder::buildMerge(), llvm::BuildMI(), llvm::MachineIRBuilder::buildUndef(), llvm::MachineIRBuilder::buildUnmerge(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::SmallSet< T, N, C >::count(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::tgtok::Def, llvm::MachineInstr::defs(), llvm::SmallSet< T, N, C >::empty(), llvm::MachineBasicBlock::end(), llvm::MDNode::get(), llvm::MachineInstr::getDebugLoc(), llvm::LLT::getElementType(), llvm::RegisterBank::getID(), llvm::GCNSubtarget::getInstrInfo(), llvm::LLT::getNumElements(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), llvm::MachineOperand::getReg(), getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getScalarSizeInBits(), llvm::LLT::getSizeInBits(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getType(), I, llvm::SmallSet< T, N, C >::insert(), llvm::MachineFunction::insert(), llvm::MachineOperand::isUse(), llvm::LLT::isVector(), llvm::RegState::Kill, Merge, MRI, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::LLT::scalar(), llvm::LLT::scalarOrVector(), llvm::MachineIRBuilder::setInsertPt(), llvm::MachineIRBuilder::setInstr(), llvm::MachineIRBuilder::setMBB(), llvm::MachineOperand::setReg(), llvm::MachineRegisterInfo::setRegBank(), llvm::MachineRegisterInfo::setRegClass(), llvm::MachineRegisterInfo::setSimpleHint(), llvm::MachineRegisterInfo::setType(), llvm::MachineBasicBlock::splice(), llvm::ARM_MB::ST, TII, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), llvm::MachineInstr::uses(), and llvm::zip().

Referenced by substituteSimpleCopyRegs().

◆ getOtherVRegDef()

static MachineInstr* getOtherVRegDef ( const MachineRegisterInfo MRI,
Register  Reg,
const MachineInstr MI 
)
static

◆ isInstrUniform()

static bool isInstrUniform ( const MachineInstr MI)
static

◆ setRegsToType()

static void setRegsToType ( MachineRegisterInfo MRI,
ArrayRef< Register Regs,
LLT  NewTy 
)
static

Replace the current type each register in Regs has with NewTy.

Definition at line 599 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), and llvm::MachineRegisterInfo::setType().

Referenced by substituteSimpleCopyRegs().

◆ substituteSimpleCopyRegs()

static void substituteSimpleCopyRegs ( const AMDGPURegisterBankInfo::OperandsMapper &  OpdMapper,
unsigned  OpIdx 
)
static

Definition at line 1030 of file AMDGPURegisterBankInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), llvm::RegisterBankInfo::applyDefaultMapping(), assert(), B, llvm::MachineIRBuilder::buildAnyExt(), llvm::MachineIRBuilder::buildAShr(), llvm::MachineIRBuilder::buildConstant(), llvm::MachineIRBuilder::buildCopy(), llvm::MachineIRBuilder::buildInstr(), llvm::MachineIRBuilder::buildLShr(), llvm::MachineIRBuilder::buildSelect(), llvm::MachineIRBuilder::buildSExtOrTrunc(), llvm::MachineIRBuilder::buildShl(), llvm::MachineIRBuilder::buildTrunc(), llvm::MachineIRBuilder::buildZExtOrTrunc(), llvm::Default, E, llvm::empty(), llvm::MachineInstr::eraseFromParent(), llvm::MipsISD::Ext, getHalfSizedType(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getInstructionMapping(), getIntrinsicID(), OperandsMapper::getMI(), OperandsMapper::getMRI(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::getSizeInBits(), llvm::MachineRegisterInfo::getType(), getValueMapping(), OperandsMapper::getVRegs(), I, isInstrUniform(), llvm::MachineOperand::isIntrinsicID(), llvm::MachineOperand::isReg(), llvm::LLT::isScalar(), llvm::LegalizerHelper::Legalized, llvm_unreachable, llvm::LegalizerHelper::lower(), MRI, llvm::LLT::scalar(), llvm::MachineRegisterInfo::setRegBank(), setRegsToType(), Signed, Size, and llvm::LegalizerHelper::widenScalar().