LLVM  10.0.0svn
AMDGPURegisterInfo.cpp
Go to the documentation of this file.
1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Parent TargetRegisterInfo class common to all hw codegen targets.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPURegisterInfo.h"
15 #include "AMDGPUTargetMachine.h"
16 #include "SIMachineFunctionInfo.h"
17 #include "SIRegisterInfo.h"
19 
20 using namespace llvm;
21 
23 
24 //===----------------------------------------------------------------------===//
25 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
26 // they are not supported at this time.
27 //===----------------------------------------------------------------------===//
28 
29 // Table of NumRegs sized pieces at every 32-bit offset.
30 static const uint16_t SubRegFromChannelTable[][32] = {
31  { AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
32  AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
33  AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
34  AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
35  AMDGPU::sub16, AMDGPU::sub17, AMDGPU::sub18, AMDGPU::sub19,
36  AMDGPU::sub20, AMDGPU::sub21, AMDGPU::sub22, AMDGPU::sub23,
37  AMDGPU::sub24, AMDGPU::sub25, AMDGPU::sub26, AMDGPU::sub27,
38  AMDGPU::sub28, AMDGPU::sub29, AMDGPU::sub30, AMDGPU::sub31
39  },
40  {
41  AMDGPU::sub0_sub1, AMDGPU::sub1_sub2, AMDGPU::sub2_sub3, AMDGPU::sub3_sub4,
42  AMDGPU::sub4_sub5, AMDGPU::sub5_sub6, AMDGPU::sub6_sub7, AMDGPU::sub7_sub8,
43  AMDGPU::sub8_sub9, AMDGPU::sub9_sub10, AMDGPU::sub10_sub11, AMDGPU::sub11_sub12,
44  AMDGPU::sub12_sub13, AMDGPU::sub13_sub14, AMDGPU::sub14_sub15, AMDGPU::sub15_sub16,
45  AMDGPU::sub16_sub17, AMDGPU::sub17_sub18, AMDGPU::sub18_sub19, AMDGPU::sub19_sub20,
46  AMDGPU::sub20_sub21, AMDGPU::sub21_sub22, AMDGPU::sub22_sub23, AMDGPU::sub23_sub24,
47  AMDGPU::sub24_sub25, AMDGPU::sub25_sub26, AMDGPU::sub26_sub27, AMDGPU::sub27_sub28,
48  AMDGPU::sub28_sub29, AMDGPU::sub29_sub30, AMDGPU::sub30_sub31, AMDGPU::NoSubRegister
49  },
50  {
51  AMDGPU::sub0_sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub3_sub4_sub5,
52  AMDGPU::sub4_sub5_sub6, AMDGPU::sub5_sub6_sub7, AMDGPU::sub6_sub7_sub8, AMDGPU::sub7_sub8_sub9,
53  AMDGPU::sub8_sub9_sub10, AMDGPU::sub9_sub10_sub11, AMDGPU::sub10_sub11_sub12, AMDGPU::sub11_sub12_sub13,
54  AMDGPU::sub12_sub13_sub14, AMDGPU::sub13_sub14_sub15, AMDGPU::sub14_sub15_sub16, AMDGPU::sub15_sub16_sub17,
55  AMDGPU::sub16_sub17_sub18, AMDGPU::sub17_sub18_sub19, AMDGPU::sub18_sub19_sub20, AMDGPU::sub19_sub20_sub21,
56  AMDGPU::sub20_sub21_sub22, AMDGPU::sub21_sub22_sub23, AMDGPU::sub22_sub23_sub24, AMDGPU::sub23_sub24_sub25,
57  AMDGPU::sub24_sub25_sub26, AMDGPU::sub25_sub26_sub27, AMDGPU::sub26_sub27_sub28, AMDGPU::sub27_sub28_sub29,
58  AMDGPU::sub28_sub29_sub30, AMDGPU::sub29_sub30_sub31, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister
59  },
60  {
61  AMDGPU::sub0_sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6,
62  AMDGPU::sub4_sub5_sub6_sub7, AMDGPU::sub5_sub6_sub7_sub8, AMDGPU::sub6_sub7_sub8_sub9, AMDGPU::sub7_sub8_sub9_sub10,
63  AMDGPU::sub8_sub9_sub10_sub11, AMDGPU::sub9_sub10_sub11_sub12, AMDGPU::sub10_sub11_sub12_sub13, AMDGPU::sub11_sub12_sub13_sub14,
64  AMDGPU::sub12_sub13_sub14_sub15, AMDGPU::sub13_sub14_sub15_sub16, AMDGPU::sub14_sub15_sub16_sub17, AMDGPU::sub15_sub16_sub17_sub18,
65  AMDGPU::sub16_sub17_sub18_sub19, AMDGPU::sub17_sub18_sub19_sub20, AMDGPU::sub18_sub19_sub20_sub21, AMDGPU::sub19_sub20_sub21_sub22,
66  AMDGPU::sub20_sub21_sub22_sub23, AMDGPU::sub21_sub22_sub23_sub24, AMDGPU::sub22_sub23_sub24_sub25, AMDGPU::sub23_sub24_sub25_sub26,
67  AMDGPU::sub24_sub25_sub26_sub27, AMDGPU::sub25_sub26_sub27_sub28, AMDGPU::sub26_sub27_sub28_sub29, AMDGPU::sub27_sub28_sub29_sub30,
68  AMDGPU::sub28_sub29_sub30_sub31, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister, AMDGPU::NoSubRegister
69  }
70 };
71 
72 // FIXME: TableGen should generate something to make this manageable for all
73 // register classes. At a minimum we could use the opposite of
74 // composeSubRegIndices and go up from the base 32-bit subreg.
75 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel, unsigned NumRegs) {
76  const unsigned NumRegIndex = NumRegs - 1;
77 
79  "Not implemented");
81  return SubRegFromChannelTable[NumRegIndex][Channel];
82 }
83 
84 void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
85  MCRegAliasIterator R(Reg, this, true);
86 
87  for (; R.isValid(); ++R)
88  Reserved.set(*R);
89 }
90 
91 #define GET_REGINFO_TARGET_DESC
92 #include "AMDGPUGenRegisterInfo.inc"
93 
94 // Forced to be here by one .inc
96  const MachineFunction *MF) const {
98  switch (CC) {
99  case CallingConv::C:
100  case CallingConv::Fast:
101  case CallingConv::Cold:
102  return CSR_AMDGPU_HighRegs_SaveList;
103  default: {
104  // Dummy to not crash RegisterClassInfo.
105  static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
106  return &NoCalleeSavedReg;
107  }
108  }
109 }
110 
111 const MCPhysReg *
113  return nullptr;
114 }
115 
117  CallingConv::ID CC) const {
118  switch (CC) {
119  case CallingConv::C:
120  case CallingConv::Fast:
121  case CallingConv::Cold:
122  return CSR_AMDGPU_HighRegs_RegMask;
123  default:
124  return nullptr;
125  }
126 }
127 
129  const SIFrameLowering *TFI =
130  MF.getSubtarget<GCNSubtarget>().getFrameLowering();
131  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
132  return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
133  : FuncInfo->getStackPtrOffsetReg();
134 }
135 
137  return CSR_AMDGPU_AllVGPRs_RegMask;
138 }
139 
141  return CSR_AMDGPU_AllAllocatableSRegs_RegMask;
142 }
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
BitVector & set()
Definition: BitVector.h:397
Interface definition for SIRegisterInfo.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned Reg
static const uint16_t SubRegFromChannelTable[][32]
TargetRegisterInfo interface that is implemented by all hw codegen targets.
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
const uint32_t * getAllAllocatableSRegMask() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
MCRegAliasIterator enumerates all registers aliasing Reg.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
The AMDGPU TargetMachine interface definition for hw codgen targets.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Provides AMDGPU specific target descriptions.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
void reserveRegisterTuples(BitVector &, unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Register getFrameRegister(const MachineFunction &MF) const override
const uint32_t * getAllVGPRRegMask() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19