LLVM  9.0.0svn
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMAsmPrinter.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMTargetObjectFile.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/BinaryFormat/COFF.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/Debug.h"
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "asm-printer"
54 
56  std::unique_ptr<MCStreamer> Streamer)
57  : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
58  InConstantPool(false), OptimizationGoals(-1) {}
59 
61  // Make sure to terminate any constant pools that were at the end
62  // of the function.
63  if (!InConstantPool)
64  return;
65  InConstantPool = false;
66  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
67 }
68 
70  if (AFI->isThumbFunction()) {
71  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
72  OutStreamer->EmitThumbFunc(CurrentFnSym);
73  } else {
74  OutStreamer->EmitAssemblerFlag(MCAF_Code32);
75  }
76  OutStreamer->EmitLabel(CurrentFnSym);
77 }
78 
80  uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
81  assert(Size && "C++ constructor pointer had zero size!");
82 
84  assert(GV && "C++ constructor pointer was not a GlobalValue!");
85 
86  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
88  (Subtarget->isTargetELF()
91  OutContext);
92 
93  OutStreamer->EmitValue(E, Size);
94 }
95 
97  if (PromotedGlobals.count(GV))
98  // The global was promoted into a constant pool. It should not be emitted.
99  return;
101 }
102 
103 /// runOnMachineFunction - This uses the EmitInstruction()
104 /// method to print assembly for each instruction.
105 ///
107  AFI = MF.getInfo<ARMFunctionInfo>();
108  MCP = MF.getConstantPool();
109  Subtarget = &MF.getSubtarget<ARMSubtarget>();
110 
112  const Function &F = MF.getFunction();
113  const TargetMachine& TM = MF.getTarget();
114 
115  // Collect all globals that had their storage promoted to a constant pool.
116  // Functions are emitted before variables, so this accumulates promoted
117  // globals from all functions in PromotedGlobals.
118  for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
119  PromotedGlobals.insert(GV);
120 
121  // Calculate this function's optimization goal.
122  unsigned OptimizationGoal;
123  if (F.hasOptNone())
124  // For best debugging illusion, speed and small size sacrificed
125  OptimizationGoal = 6;
126  else if (F.hasMinSize())
127  // Aggressively for small size, speed and debug illusion sacrificed
128  OptimizationGoal = 4;
129  else if (F.hasOptSize())
130  // For small size, but speed and debugging illusion preserved
131  OptimizationGoal = 3;
132  else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
133  // Aggressively for speed, small size and debug illusion sacrificed
134  OptimizationGoal = 2;
135  else if (TM.getOptLevel() > CodeGenOpt::None)
136  // For speed, but small size and good debug illusion preserved
137  OptimizationGoal = 1;
138  else // TM.getOptLevel() == CodeGenOpt::None
139  // For good debugging, but speed and small size preserved
140  OptimizationGoal = 5;
141 
142  // Combine a new optimization goal with existing ones.
143  if (OptimizationGoals == -1) // uninitialized goals
144  OptimizationGoals = OptimizationGoal;
145  else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
146  OptimizationGoals = 0;
147 
148  if (Subtarget->isTargetCOFF()) {
149  bool Internal = F.hasInternalLinkage();
153 
154  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
155  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
156  OutStreamer->EmitCOFFSymbolType(Type);
157  OutStreamer->EndCOFFSymbolDef();
158  }
159 
160  // Emit the rest of the function body.
162 
163  // Emit the XRay table for this function.
164  emitXRayTable();
165 
166  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
167  // These are created per function, rather than per TU, since it's
168  // relatively easy to exceed the thumb branch range within a TU.
169  if (! ThumbIndirectPads.empty()) {
170  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
171  EmitAlignment(1);
172  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
173  OutStreamer->EmitLabel(TIP.second);
175  .addReg(TIP.first)
176  // Add predicate operands.
177  .addImm(ARMCC::AL)
178  .addReg(0));
179  }
180  ThumbIndirectPads.clear();
181  }
182 
183  // We didn't modify anything.
184  return false;
185 }
186 
188  raw_ostream &O) {
189  assert(MO.isGlobal() && "caller should check MO.isGlobal");
190  unsigned TF = MO.getTargetFlags();
191  if (TF & ARMII::MO_LO16)
192  O << ":lower16:";
193  else if (TF & ARMII::MO_HI16)
194  O << ":upper16:";
195  GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
196  printOffset(MO.getOffset(), O);
197 }
198 
200  raw_ostream &O) {
201  const MachineOperand &MO = MI->getOperand(OpNum);
202 
203  switch (MO.getType()) {
204  default: llvm_unreachable("<unknown operand type>");
206  unsigned Reg = MO.getReg();
208  assert(!MO.getSubReg() && "Subregs should be eliminated!");
209  if(ARM::GPRPairRegClass.contains(Reg)) {
210  const MachineFunction &MF = *MI->getParent()->getParent();
212  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
213  }
215  break;
216  }
218  O << '#';
219  unsigned TF = MO.getTargetFlags();
220  if (TF == ARMII::MO_LO16)
221  O << ":lower16:";
222  else if (TF == ARMII::MO_HI16)
223  O << ":upper16:";
224  O << MO.getImm();
225  break;
226  }
228  MO.getMBB()->getSymbol()->print(O, MAI);
229  return;
231  PrintSymbolOperand(MO, O);
232  break;
233  }
235  if (Subtarget->genExecuteOnly())
236  llvm_unreachable("execute-only should not generate constant pools");
237  GetCPISymbol(MO.getIndex())->print(O, MAI);
238  break;
239  }
240 }
241 
242 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
243  // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
244  // indexes in MachineConstantPool, which isn't in sync with indexes used here.
245  const DataLayout &DL = getDataLayout();
247  "CPI" + Twine(getFunctionNumber()) + "_" +
248  Twine(CPID));
249 }
250 
251 //===--------------------------------------------------------------------===//
252 
253 MCSymbol *ARMAsmPrinter::
254 GetARMJTIPICJumpTableLabel(unsigned uid) const {
255  const DataLayout &DL = getDataLayout();
257  raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
258  << getFunctionNumber() << '_' << uid;
259  return OutContext.getOrCreateSymbol(Name);
260 }
261 
262 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
263  const char *ExtraCode, raw_ostream &O) {
264  // Does this asm operand have a single letter operand modifier?
265  if (ExtraCode && ExtraCode[0]) {
266  if (ExtraCode[1] != 0) return true; // Unknown modifier.
267 
268  switch (ExtraCode[0]) {
269  default:
270  // See if this is a generic print operand
271  return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
272  case 'P': // Print a VFP double precision register.
273  case 'q': // Print a NEON quad precision register.
274  printOperand(MI, OpNum, O);
275  return false;
276  case 'y': // Print a VFP single precision register as indexed double.
277  if (MI->getOperand(OpNum).isReg()) {
278  unsigned Reg = MI->getOperand(OpNum).getReg();
280  // Find the 'd' register that has this 's' register as a sub-register,
281  // and determine the lane number.
282  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
283  if (!ARM::DPRRegClass.contains(*SR))
284  continue;
285  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
286  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
287  return false;
288  }
289  }
290  return true;
291  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
292  if (!MI->getOperand(OpNum).isImm())
293  return true;
294  O << ~(MI->getOperand(OpNum).getImm());
295  return false;
296  case 'L': // The low 16 bits of an immediate constant.
297  if (!MI->getOperand(OpNum).isImm())
298  return true;
299  O << (MI->getOperand(OpNum).getImm() & 0xffff);
300  return false;
301  case 'M': { // A register range suitable for LDM/STM.
302  if (!MI->getOperand(OpNum).isReg())
303  return true;
304  const MachineOperand &MO = MI->getOperand(OpNum);
305  unsigned RegBegin = MO.getReg();
306  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
307  // already got the operands in registers that are operands to the
308  // inline asm statement.
309  O << "{";
310  if (ARM::GPRPairRegClass.contains(RegBegin)) {
312  unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
313  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
314  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
315  }
316  O << ARMInstPrinter::getRegisterName(RegBegin);
317 
318  // FIXME: The register allocator not only may not have given us the
319  // registers in sequence, but may not be in ascending registers. This
320  // will require changes in the register allocator that'll need to be
321  // propagated down here if the operands change.
322  unsigned RegOps = OpNum + 1;
323  while (MI->getOperand(RegOps).isReg()) {
324  O << ", "
326  RegOps++;
327  }
328 
329  O << "}";
330 
331  return false;
332  }
333  case 'R': // The most significant register of a pair.
334  case 'Q': { // The least significant register of a pair.
335  if (OpNum == 0)
336  return true;
337  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
338  if (!FlagsOP.isImm())
339  return true;
340  unsigned Flags = FlagsOP.getImm();
341 
342  // This operand may not be the one that actually provides the register. If
343  // it's tied to a previous one then we should refer instead to that one
344  // for registers and their classes.
345  unsigned TiedIdx;
346  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
347  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
348  unsigned OpFlags = MI->getOperand(OpNum).getImm();
349  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
350  }
351  Flags = MI->getOperand(OpNum).getImm();
352 
353  // Later code expects OpNum to be pointing at the register rather than
354  // the flags.
355  OpNum += 1;
356  }
357 
358  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
359  unsigned RC;
360  bool FirstHalf;
361  const ARMBaseTargetMachine &ATM =
362  static_cast<const ARMBaseTargetMachine &>(TM);
363 
364  // 'Q' should correspond to the low order register and 'R' to the high
365  // order register. Whether this corresponds to the upper or lower half
366  // depends on the endianess mode.
367  if (ExtraCode[0] == 'Q')
368  FirstHalf = ATM.isLittleEndian();
369  else
370  // ExtraCode[0] == 'R'.
371  FirstHalf = !ATM.isLittleEndian();
373  if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
374  ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
375  if (NumVals != 1)
376  return true;
377  const MachineOperand &MO = MI->getOperand(OpNum);
378  if (!MO.isReg())
379  return true;
381  unsigned Reg = TRI->getSubReg(MO.getReg(), FirstHalf ?
382  ARM::gsub_0 : ARM::gsub_1);
384  return false;
385  }
386  if (NumVals != 2)
387  return true;
388  unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
389  if (RegOp >= MI->getNumOperands())
390  return true;
391  const MachineOperand &MO = MI->getOperand(RegOp);
392  if (!MO.isReg())
393  return true;
394  unsigned Reg = MO.getReg();
396  return false;
397  }
398 
399  case 'e': // The low doubleword register of a NEON quad register.
400  case 'f': { // The high doubleword register of a NEON quad register.
401  if (!MI->getOperand(OpNum).isReg())
402  return true;
403  unsigned Reg = MI->getOperand(OpNum).getReg();
404  if (!ARM::QPRRegClass.contains(Reg))
405  return true;
407  unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
408  ARM::dsub_0 : ARM::dsub_1);
409  O << ARMInstPrinter::getRegisterName(SubReg);
410  return false;
411  }
412 
413  // This modifier is not yet supported.
414  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
415  return true;
416  case 'H': { // The highest-numbered register of a pair.
417  const MachineOperand &MO = MI->getOperand(OpNum);
418  if (!MO.isReg())
419  return true;
420  const MachineFunction &MF = *MI->getParent()->getParent();
422  unsigned Reg = MO.getReg();
423  if(!ARM::GPRPairRegClass.contains(Reg))
424  return false;
425  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
427  return false;
428  }
429  }
430  }
431 
432  printOperand(MI, OpNum, O);
433  return false;
434 }
435 
437  unsigned OpNum, const char *ExtraCode,
438  raw_ostream &O) {
439  // Does this asm operand have a single letter operand modifier?
440  if (ExtraCode && ExtraCode[0]) {
441  if (ExtraCode[1] != 0) return true; // Unknown modifier.
442 
443  switch (ExtraCode[0]) {
444  case 'A': // A memory operand for a VLD1/VST1 instruction.
445  default: return true; // Unknown modifier.
446  case 'm': // The base register of a memory operand.
447  if (!MI->getOperand(OpNum).isReg())
448  return true;
450  return false;
451  }
452  }
453 
454  const MachineOperand &MO = MI->getOperand(OpNum);
455  assert(MO.isReg() && "unexpected inline asm memory operand");
456  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
457  return false;
458 }
459 
460 static bool isThumb(const MCSubtargetInfo& STI) {
461  return STI.getFeatureBits()[ARM::ModeThumb];
462 }
463 
465  const MCSubtargetInfo *EndInfo) const {
466  // If either end mode is unknown (EndInfo == NULL) or different than
467  // the start mode, then restore the start mode.
468  const bool WasThumb = isThumb(StartInfo);
469  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
470  OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
471  }
472 }
473 
475  const Triple &TT = TM.getTargetTriple();
476  // Use unified assembler syntax.
477  OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
478 
479  // Emit ARM Build Attributes
480  if (TT.isOSBinFormatELF())
481  emitAttributes();
482 
483  // Use the triple's architecture and subarchitecture to determine
484  // if we're thumb for the purposes of the top level code16 assembler
485  // flag.
486  if (!M.getModuleInlineAsm().empty() && TT.isThumb())
487  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
488 }
489 
490 static void
493  // L_foo$stub:
494  OutStreamer.EmitLabel(StubLabel);
495  // .indirect_symbol _foo
496  OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
497 
498  if (MCSym.getInt())
499  // External to current translation unit.
500  OutStreamer.EmitIntValue(0, 4/*size*/);
501  else
502  // Internal to current translation unit.
503  //
504  // When we place the LSDA into the TEXT section, the type info
505  // pointers need to be indirect and pc-rel. We accomplish this by
506  // using NLPs; however, sometimes the types are local to the file.
507  // We need to fill in the value for the NLP in those cases.
508  OutStreamer.EmitValue(
509  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
510  4 /*size*/);
511 }
512 
513 
515  const Triple &TT = TM.getTargetTriple();
516  if (TT.isOSBinFormatMachO()) {
517  // All darwin targets use mach-o.
518  const TargetLoweringObjectFileMachO &TLOFMacho =
519  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
520  MachineModuleInfoMachO &MMIMacho =
522 
523  // Output non-lazy-pointers for external and common global variables.
525 
526  if (!Stubs.empty()) {
527  // Switch with ".non_lazy_symbol_pointer" directive.
528  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
529  EmitAlignment(2);
530 
531  for (auto &Stub : Stubs)
532  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
533 
534  Stubs.clear();
535  OutStreamer->AddBlankLine();
536  }
537 
538  Stubs = MMIMacho.GetThreadLocalGVStubList();
539  if (!Stubs.empty()) {
540  // Switch with ".non_lazy_symbol_pointer" directive.
541  OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
542  EmitAlignment(2);
543 
544  for (auto &Stub : Stubs)
545  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
546 
547  Stubs.clear();
548  OutStreamer->AddBlankLine();
549  }
550 
551  // Funny Darwin hack: This flag tells the linker that no global symbols
552  // contain code that falls through to other global symbols (e.g. the obvious
553  // implementation of multiple entry points). If this doesn't occur, the
554  // linker can safely perform dead code stripping. Since LLVM never
555  // generates code that does this, it is always safe to set.
556  OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
557  }
558 
559  // The last attribute to be emitted is ABI_optimization_goals
560  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
561  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
562 
563  if (OptimizationGoals > 0 &&
564  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
565  Subtarget->isTargetMuslAEABI()))
567  OptimizationGoals = -1;
568 
570 }
571 
572 //===----------------------------------------------------------------------===//
573 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
574 // FIXME:
575 // The following seem like one-off assembler flags, but they actually need
576 // to appear in the .ARM.attributes section in ELF.
577 // Instead of subclassing the MCELFStreamer, we do the work here.
578 
579 // Returns true if all functions have the same function attribute value.
580 // It also returns true when the module has no functions.
582  StringRef Value) {
583  return !any_of(M, [&](const Function &F) {
584  return F.getFnAttribute(Attr).getValueAsString() != Value;
585  });
586 }
587 
588 void ARMAsmPrinter::emitAttributes() {
589  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
590  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
591 
593 
594  ATS.switchVendor("aeabi");
595 
596  // Compute ARM ELF Attributes based on the default subtarget that
597  // we'd have constructed. The existing ARM behavior isn't LTO clean
598  // anyhow.
599  // FIXME: For ifunc related functions we could iterate over and look
600  // for a feature string that doesn't match the default one.
601  const Triple &TT = TM.getTargetTriple();
602  StringRef CPU = TM.getTargetCPU();
604  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
605  if (!FS.empty()) {
606  if (!ArchFS.empty())
607  ArchFS = (Twine(ArchFS) + "," + FS).str();
608  else
609  ArchFS = FS;
610  }
611  const ARMBaseTargetMachine &ATM =
612  static_cast<const ARMBaseTargetMachine &>(TM);
613  const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
614 
615  // Emit build attributes for the available hardware.
616  ATS.emitTargetAttributes(STI);
617 
618  // RW data addressing.
619  if (isPositionIndependent()) {
622  } else if (STI.isRWPI()) {
623  // RWPI specific attributes.
626  }
627 
628  // RO data addressing.
629  if (isPositionIndependent() || STI.isROPI()) {
632  }
633 
634  // GOT use.
635  if (isPositionIndependent()) {
638  } else {
641  }
642 
643  // Set FP Denormals.
645  "denormal-fp-math",
646  "preserve-sign") ||
651  "denormal-fp-math",
652  "positive-zero") ||
656  else if (!TM.Options.UnsafeFPMath)
659  else {
660  if (!STI.hasVFP2()) {
661  // When the target doesn't have an FPU (by design or
662  // intention), the assumptions made on the software support
663  // mirror that of the equivalent hardware support *if it
664  // existed*. For v7 and better we indicate that denormals are
665  // flushed preserving sign, and for V6 we indicate that
666  // denormals are flushed to positive zero.
667  if (STI.hasV7Ops())
670  } else if (STI.hasVFP3()) {
671  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
672  // the sign bit of the zero matches the sign bit of the input or
673  // result that is being flushed to zero.
676  }
677  // For VFPv2 implementations it is implementation defined as
678  // to whether denormals are flushed to positive zero or to
679  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
680  // LLVM has chosen to flush this to positive zero (most likely for
681  // GCC compatibility), so that's the chosen value here (the
682  // absence of its emission implies zero).
683  }
684 
685  // Set FP exceptions and rounding
687  "no-trapping-math", "true") ||
691  else if (!TM.Options.UnsafeFPMath) {
693 
694  // If the user has permitted this code to choose the IEEE 754
695  // rounding at run-time, emit the rounding attribute.
698  }
699 
700  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
701  // equivalent of GCC's -ffinite-math-only flag.
705  else
708 
709  // FIXME: add more flags to ARMBuildAttributes.h
710  // 8-bytes alignment stuff.
713 
714  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
715  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
717 
718  // FIXME: To support emitting this build attribute as GCC does, the
719  // -mfp16-format option and associated plumbing must be
720  // supported. For now the __fp16 type is exposed by default, so this
721  // attribute should be emitted with value 1.
724 
725  if (MMI) {
726  if (const Module *SourceModule = MMI->getModule()) {
727  // ABI_PCS_wchar_t to indicate wchar_t width
728  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
729  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
730  SourceModule->getModuleFlag("wchar_size"))) {
731  int WCharWidth = WCharWidthValue->getZExtValue();
732  assert((WCharWidth == 2 || WCharWidth == 4) &&
733  "wchar_t width must be 2 or 4 bytes");
735  }
736 
737  // ABI_enum_size to indicate enum width
738  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
739  // (all enums contain a value needing 32 bits to encode).
740  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
741  SourceModule->getModuleFlag("min_enum_size"))) {
742  int EnumWidth = EnumWidthValue->getZExtValue();
743  assert((EnumWidth == 1 || EnumWidth == 4) &&
744  "Minimum enum width must be 1 or 4 bytes");
745  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
746  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
747  }
748  }
749  }
750 
751  // We currently do not support using R9 as the TLS pointer.
752  if (STI.isRWPI())
755  else if (STI.isR9Reserved())
758  else
761 }
762 
763 //===----------------------------------------------------------------------===//
764 
766  unsigned LabelId, MCContext &Ctx) {
767 
768  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
769  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
770  return Label;
771 }
772 
775  switch (Modifier) {
776  case ARMCP::no_modifier:
778  case ARMCP::TLSGD:
780  case ARMCP::TPOFF:
782  case ARMCP::GOTTPOFF:
784  case ARMCP::SBREL:
786  case ARMCP::GOT_PREL:
788  case ARMCP::SECREL:
790  }
791  llvm_unreachable("Invalid ARMCPModifier!");
792 }
793 
794 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
795  unsigned char TargetFlags) {
796  if (Subtarget->isTargetMachO()) {
797  bool IsIndirect =
798  (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
799 
800  if (!IsIndirect)
801  return getSymbol(GV);
802 
803  // FIXME: Remove this when Darwin transition to @GOT like syntax.
804  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
805  MachineModuleInfoMachO &MMIMachO =
808  GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
809  : MMIMachO.getGVStubEntry(MCSym);
810 
811  if (!StubSym.getPointer())
813  !GV->hasInternalLinkage());
814  return MCSym;
815  } else if (Subtarget->isTargetCOFF()) {
816  assert(Subtarget->isTargetWindows() &&
817  "Windows is the only supported COFF target");
818 
819  bool IsIndirect =
820  (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
821  if (!IsIndirect)
822  return getSymbol(GV);
823 
825  if (TargetFlags & ARMII::MO_DLLIMPORT)
826  Name = "__imp_";
827  else if (TargetFlags & ARMII::MO_COFFSTUB)
828  Name = ".refptr.";
829  getNameWithPrefix(Name, GV);
830 
831  MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
832 
833  if (TargetFlags & ARMII::MO_COFFSTUB) {
834  MachineModuleInfoCOFF &MMICOFF =
837  MMICOFF.getGVStubEntry(MCSym);
838 
839  if (!StubSym.getPointer())
840  StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
841  }
842 
843  return MCSym;
844  } else if (Subtarget->isTargetELF()) {
845  return getSymbol(GV);
846  }
847  llvm_unreachable("unexpected target");
848 }
849 
850 void ARMAsmPrinter::
852  const DataLayout &DL = getDataLayout();
853  int Size = DL.getTypeAllocSize(MCPV->getType());
854 
855  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
856 
857  if (ACPV->isPromotedGlobal()) {
858  // This constant pool entry is actually a global whose storage has been
859  // promoted into the constant pool. This global may be referenced still
860  // by debug information, and due to the way AsmPrinter is set up, the debug
861  // info is immutable by the time we decide to promote globals to constant
862  // pools. Because of this, we need to ensure we emit a symbol for the global
863  // with private linkage (the default) so debug info can refer to it.
864  //
865  // However, if this global is promoted into several functions we must ensure
866  // we don't try and emit duplicate symbols!
867  auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
868  for (const auto *GV : ACPC->promotedGlobals()) {
869  if (!EmittedPromotedGlobalLabels.count(GV)) {
870  MCSymbol *GVSym = getSymbol(GV);
871  OutStreamer->EmitLabel(GVSym);
872  EmittedPromotedGlobalLabels.insert(GV);
873  }
874  }
875  return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
876  }
877 
878  MCSymbol *MCSym;
879  if (ACPV->isLSDA()) {
880  MCSym = getCurExceptionSym();
881  } else if (ACPV->isBlockAddress()) {
882  const BlockAddress *BA =
883  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
884  MCSym = GetBlockAddressSymbol(BA);
885  } else if (ACPV->isGlobalValue()) {
886  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
887 
888  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
889  // flag the global as MO_NONLAZY.
890  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
891  MCSym = GetARMGVSymbol(GV, TF);
892  } else if (ACPV->isMachineBasicBlock()) {
893  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
894  MCSym = MBB->getSymbol();
895  } else {
896  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
897  auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
898  MCSym = GetExternalSymbolSymbol(Sym);
899  }
900 
901  // Create an MCSymbol for the reference.
902  const MCExpr *Expr =
904  OutContext);
905 
906  if (ACPV->getPCAdjustment()) {
907  MCSymbol *PCLabel =
909  ACPV->getLabelId(), OutContext);
910  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
911  PCRelExpr =
912  MCBinaryExpr::createAdd(PCRelExpr,
914  OutContext),
915  OutContext);
916  if (ACPV->mustAddCurrentAddress()) {
917  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
918  // label, so just emit a local label end reference that instead.
920  OutStreamer->EmitLabel(DotSym);
921  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
922  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
923  }
924  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
925  }
926  OutStreamer->EmitValue(Expr, Size);
927 }
928 
930  const MachineOperand &MO1 = MI->getOperand(1);
931  unsigned JTI = MO1.getIndex();
932 
933  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
934  // ARM mode tables.
935  EmitAlignment(2);
936 
937  // Emit a label for the jump table.
938  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
939  OutStreamer->EmitLabel(JTISymbol);
940 
941  // Mark the jump table as data-in-code.
942  OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
943 
944  // Emit each entry of the table.
945  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
946  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
947  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
948 
949  for (MachineBasicBlock *MBB : JTBBs) {
950  // Construct an MCExpr for the entry. We want a value of the form:
951  // (BasicBlockAddr - TableBeginAddr)
952  //
953  // For example, a table with entries jumping to basic blocks BB0 and BB1
954  // would look like:
955  // LJTI_0_0:
956  // .word (LBB0 - LJTI_0_0)
957  // .word (LBB1 - LJTI_0_0)
958  const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
959 
960  if (isPositionIndependent() || Subtarget->isROPI())
961  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
962  OutContext),
963  OutContext);
964  // If we're generating a table of Thumb addresses in static relocation
965  // model, we need to add one to keep interworking correctly.
966  else if (AFI->isThumbFunction())
968  OutContext);
969  OutStreamer->EmitValue(Expr, 4);
970  }
971  // Mark the end of jump table data-in-code region.
972  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
973 }
974 
976  const MachineOperand &MO1 = MI->getOperand(1);
977  unsigned JTI = MO1.getIndex();
978 
979  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
980  // ARM mode tables.
981  EmitAlignment(2);
982 
983  // Emit a label for the jump table.
984  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
985  OutStreamer->EmitLabel(JTISymbol);
986 
987  // Emit each entry of the table.
988  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
989  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
990  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
991 
992  for (MachineBasicBlock *MBB : JTBBs) {
993  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
994  OutContext);
995  // If this isn't a TBB or TBH, the entries are direct branch instructions.
997  .addExpr(MBBSymbolExpr)
998  .addImm(ARMCC::AL)
999  .addReg(0));
1000  }
1001 }
1002 
1004  unsigned OffsetWidth) {
1005  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1006  const MachineOperand &MO1 = MI->getOperand(1);
1007  unsigned JTI = MO1.getIndex();
1008 
1009  if (Subtarget->isThumb1Only())
1010  EmitAlignment(2);
1011 
1012  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1013  OutStreamer->EmitLabel(JTISymbol);
1014 
1015  // Emit each entry of the table.
1016  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1017  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1018  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1019 
1020  // Mark the jump table as data-in-code.
1021  OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1023 
1024  for (auto MBB : JTBBs) {
1025  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1026  OutContext);
1027  // Otherwise it's an offset from the dispatch instruction. Construct an
1028  // MCExpr for the entry. We want a value of the form:
1029  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1030  //
1031  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1032  // would look like:
1033  // LJTI_0_0:
1034  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1035  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1036  // where LCPI0_0 is a label defined just before the TBB instruction using
1037  // this table.
1038  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1039  const MCExpr *Expr = MCBinaryExpr::createAdd(
1042  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1044  OutContext);
1045  OutStreamer->EmitValue(Expr, OffsetWidth);
1046  }
1047  // Mark the end of jump table data-in-code region. 32-bit offsets use
1048  // actual branch instructions here, so we don't mark those as a data-region
1049  // at all.
1050  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1051 
1052  // Make sure the next instruction is 2-byte aligned.
1053  EmitAlignment(1);
1054 }
1055 
1056 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1058  "Only instruction which are involved into frame setup code are allowed");
1059 
1060  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1061  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1062  const MachineFunction &MF = *MI->getParent()->getParent();
1063  const TargetRegisterInfo *TargetRegInfo =
1065  const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1066  const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1067 
1068  unsigned FramePtr = TargetRegInfo->getFrameRegister(MF);
1069  unsigned Opc = MI->getOpcode();
1070  unsigned SrcReg, DstReg;
1071 
1072  if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1073  // Two special cases:
1074  // 1) tPUSH does not have src/dst regs.
1075  // 2) for Thumb1 code we sometimes materialize the constant via constpool
1076  // load. Yes, this is pretty fragile, but for now I don't see better
1077  // way... :(
1078  SrcReg = DstReg = ARM::SP;
1079  } else {
1080  SrcReg = MI->getOperand(1).getReg();
1081  DstReg = MI->getOperand(0).getReg();
1082  }
1083 
1084  // Try to figure out the unwinding opcode out of src / dst regs.
1085  if (MI->mayStore()) {
1086  // Register saves.
1087  assert(DstReg == ARM::SP &&
1088  "Only stack pointer as a destination reg is supported");
1089 
1090  SmallVector<unsigned, 4> RegList;
1091  // Skip src & dst reg, and pred ops.
1092  unsigned StartOp = 2 + 2;
1093  // Use all the operands.
1094  unsigned NumOffset = 0;
1095  // Amount of SP adjustment folded into a push.
1096  unsigned Pad = 0;
1097 
1098  switch (Opc) {
1099  default:
1100  MI->print(errs());
1101  llvm_unreachable("Unsupported opcode for unwinding information");
1102  case ARM::tPUSH:
1103  // Special case here: no src & dst reg, but two extra imp ops.
1104  StartOp = 2; NumOffset = 2;
1106  case ARM::STMDB_UPD:
1107  case ARM::t2STMDB_UPD:
1108  case ARM::VSTMDDB_UPD:
1109  assert(SrcReg == ARM::SP &&
1110  "Only stack pointer as a source reg is supported");
1111  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1112  i != NumOps; ++i) {
1113  const MachineOperand &MO = MI->getOperand(i);
1114  // Actually, there should never be any impdef stuff here. Skip it
1115  // temporary to workaround PR11902.
1116  if (MO.isImplicit())
1117  continue;
1118  // Registers, pushed as a part of folding an SP update into the
1119  // push instruction are marked as undef and should not be
1120  // restored when unwinding, because the function can modify the
1121  // corresponding stack slots.
1122  if (MO.isUndef()) {
1123  assert(RegList.empty() &&
1124  "Pad registers must come before restored ones");
1125  unsigned Width =
1126  TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1127  Pad += Width;
1128  continue;
1129  }
1130  RegList.push_back(MO.getReg());
1131  }
1132  break;
1133  case ARM::STR_PRE_IMM:
1134  case ARM::STR_PRE_REG:
1135  case ARM::t2STR_PRE:
1136  assert(MI->getOperand(2).getReg() == ARM::SP &&
1137  "Only stack pointer as a source reg is supported");
1138  RegList.push_back(SrcReg);
1139  break;
1140  }
1142  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1143  // Account for the SP adjustment, folded into the push.
1144  if (Pad)
1145  ATS.emitPad(Pad);
1146  }
1147  } else {
1148  // Changes of stack / frame pointer.
1149  if (SrcReg == ARM::SP) {
1150  int64_t Offset = 0;
1151  switch (Opc) {
1152  default:
1153  MI->print(errs());
1154  llvm_unreachable("Unsupported opcode for unwinding information");
1155  case ARM::MOVr:
1156  case ARM::tMOVr:
1157  Offset = 0;
1158  break;
1159  case ARM::ADDri:
1160  case ARM::t2ADDri:
1161  Offset = -MI->getOperand(2).getImm();
1162  break;
1163  case ARM::SUBri:
1164  case ARM::t2SUBri:
1165  Offset = MI->getOperand(2).getImm();
1166  break;
1167  case ARM::tSUBspi:
1168  Offset = MI->getOperand(2).getImm()*4;
1169  break;
1170  case ARM::tADDspi:
1171  case ARM::tADDrSPi:
1172  Offset = -MI->getOperand(2).getImm()*4;
1173  break;
1174  case ARM::tLDRpci: {
1175  // Grab the constpool index and check, whether it corresponds to
1176  // original or cloned constpool entry.
1177  unsigned CPI = MI->getOperand(1).getIndex();
1178  const MachineConstantPool *MCP = MF.getConstantPool();
1179  if (CPI >= MCP->getConstants().size())
1180  CPI = AFI.getOriginalCPIdx(CPI);
1181  assert(CPI != -1U && "Invalid constpool index");
1182 
1183  // Derive the actual offset.
1184  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1185  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1186  // FIXME: Check for user, it should be "add" instruction!
1187  Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1188  break;
1189  }
1190  }
1191 
1193  if (DstReg == FramePtr && FramePtr != ARM::SP)
1194  // Set-up of the frame pointer. Positive values correspond to "add"
1195  // instruction.
1196  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1197  else if (DstReg == ARM::SP) {
1198  // Change of SP by an offset. Positive values correspond to "sub"
1199  // instruction.
1200  ATS.emitPad(Offset);
1201  } else {
1202  // Move of SP to a register. Positive values correspond to an "add"
1203  // instruction.
1204  ATS.emitMovSP(DstReg, -Offset);
1205  }
1206  }
1207  } else if (DstReg == ARM::SP) {
1208  MI->print(errs());
1209  llvm_unreachable("Unsupported opcode for unwinding information");
1210  }
1211  else {
1212  MI->print(errs());
1213  llvm_unreachable("Unsupported opcode for unwinding information");
1214  }
1215  }
1216 }
1217 
1218 // Simple pseudo-instructions have their lowering (with expansion to real
1219 // instructions) auto-generated.
1220 #include "ARMGenMCPseudoLowering.inc"
1221 
1223  const DataLayout &DL = getDataLayout();
1224  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1225  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1226 
1227  const MachineFunction &MF = *MI->getParent()->getParent();
1228  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
1229  unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
1230 
1231  // If we just ended a constant pool, mark it as such.
1232  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1233  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1234  InConstantPool = false;
1235  }
1236 
1237  // Emit unwinding stuff for frame-related instructions
1238  if (Subtarget->isTargetEHABICompatible() &&
1240  EmitUnwindingInstruction(MI);
1241 
1242  // Do any auto-generated pseudo lowerings.
1243  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1244  return;
1245 
1247  "Pseudo flag setting opcode should be expanded early");
1248 
1249  // Check for manual lowerings.
1250  unsigned Opc = MI->getOpcode();
1251  switch (Opc) {
1252  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1253  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1254  case ARM::LEApcrel:
1255  case ARM::tLEApcrel:
1256  case ARM::t2LEApcrel: {
1257  // FIXME: Need to also handle globals and externals
1258  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1260  ARM::t2LEApcrel ? ARM::t2ADR
1261  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1262  : ARM::ADR))
1263  .addReg(MI->getOperand(0).getReg())
1264  .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1265  // Add predicate operands.
1266  .addImm(MI->getOperand(2).getImm())
1267  .addReg(MI->getOperand(3).getReg()));
1268  return;
1269  }
1270  case ARM::LEApcrelJT:
1271  case ARM::tLEApcrelJT:
1272  case ARM::t2LEApcrelJT: {
1273  MCSymbol *JTIPICSymbol =
1274  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1276  ARM::t2LEApcrelJT ? ARM::t2ADR
1277  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1278  : ARM::ADR))
1279  .addReg(MI->getOperand(0).getReg())
1280  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1281  // Add predicate operands.
1282  .addImm(MI->getOperand(2).getImm())
1283  .addReg(MI->getOperand(3).getReg()));
1284  return;
1285  }
1286  // Darwin call instructions are just normal call instructions with different
1287  // clobber semantics (they clobber R9).
1288  case ARM::BX_CALL: {
1290  .addReg(ARM::LR)
1291  .addReg(ARM::PC)
1292  // Add predicate operands.
1293  .addImm(ARMCC::AL)
1294  .addReg(0)
1295  // Add 's' bit operand (always reg0 for this)
1296  .addReg(0));
1297 
1298  assert(Subtarget->hasV4TOps());
1300  .addReg(MI->getOperand(0).getReg()));
1301  return;
1302  }
1303  case ARM::tBX_CALL: {
1304  if (Subtarget->hasV5TOps())
1305  llvm_unreachable("Expected BLX to be selected for v5t+");
1306 
1307  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1308  // that the saved lr has its LSB set correctly (the arch doesn't
1309  // have blx).
1310  // So here we generate a bl to a small jump pad that does bx rN.
1311  // The jump pads are emitted after the function body.
1312 
1313  unsigned TReg = MI->getOperand(0).getReg();
1314  MCSymbol *TRegSym = nullptr;
1315  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1316  if (TIP.first == TReg) {
1317  TRegSym = TIP.second;
1318  break;
1319  }
1320  }
1321 
1322  if (!TRegSym) {
1323  TRegSym = OutContext.createTempSymbol();
1324  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1325  }
1326 
1327  // Create a link-saving branch to the Reg Indirect Jump Pad.
1329  // Predicate comes first here.
1330  .addImm(ARMCC::AL).addReg(0)
1331  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1332  return;
1333  }
1334  case ARM::BMOVPCRX_CALL: {
1336  .addReg(ARM::LR)
1337  .addReg(ARM::PC)
1338  // Add predicate operands.
1339  .addImm(ARMCC::AL)
1340  .addReg(0)
1341  // Add 's' bit operand (always reg0 for this)
1342  .addReg(0));
1343 
1345  .addReg(ARM::PC)
1346  .addReg(MI->getOperand(0).getReg())
1347  // Add predicate operands.
1348  .addImm(ARMCC::AL)
1349  .addReg(0)
1350  // Add 's' bit operand (always reg0 for this)
1351  .addReg(0));
1352  return;
1353  }
1354  case ARM::BMOVPCB_CALL: {
1356  .addReg(ARM::LR)
1357  .addReg(ARM::PC)
1358  // Add predicate operands.
1359  .addImm(ARMCC::AL)
1360  .addReg(0)
1361  // Add 's' bit operand (always reg0 for this)
1362  .addReg(0));
1363 
1364  const MachineOperand &Op = MI->getOperand(0);
1365  const GlobalValue *GV = Op.getGlobal();
1366  const unsigned TF = Op.getTargetFlags();
1367  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1368  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1370  .addExpr(GVSymExpr)
1371  // Add predicate operands.
1372  .addImm(ARMCC::AL)
1373  .addReg(0));
1374  return;
1375  }
1376  case ARM::MOVi16_ga_pcrel:
1377  case ARM::t2MOVi16_ga_pcrel: {
1378  MCInst TmpInst;
1379  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1380  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1381 
1382  unsigned TF = MI->getOperand(1).getTargetFlags();
1383  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1384  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1385  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1386 
1387  MCSymbol *LabelSym =
1389  MI->getOperand(2).getImm(), OutContext);
1390  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1391  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1392  const MCExpr *PCRelExpr =
1394  MCBinaryExpr::createAdd(LabelSymExpr,
1397  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1398 
1399  // Add predicate operands.
1401  TmpInst.addOperand(MCOperand::createReg(0));
1402  // Add 's' bit operand (always reg0 for this)
1403  TmpInst.addOperand(MCOperand::createReg(0));
1404  EmitToStreamer(*OutStreamer, TmpInst);
1405  return;
1406  }
1407  case ARM::MOVTi16_ga_pcrel:
1408  case ARM::t2MOVTi16_ga_pcrel: {
1409  MCInst TmpInst;
1410  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1411  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1412  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1413  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1414 
1415  unsigned TF = MI->getOperand(2).getTargetFlags();
1416  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1417  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1418  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1419 
1420  MCSymbol *LabelSym =
1422  MI->getOperand(3).getImm(), OutContext);
1423  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1424  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1425  const MCExpr *PCRelExpr =
1427  MCBinaryExpr::createAdd(LabelSymExpr,
1430  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1431  // Add predicate operands.
1433  TmpInst.addOperand(MCOperand::createReg(0));
1434  // Add 's' bit operand (always reg0 for this)
1435  TmpInst.addOperand(MCOperand::createReg(0));
1436  EmitToStreamer(*OutStreamer, TmpInst);
1437  return;
1438  }
1439  case ARM::tPICADD: {
1440  // This is a pseudo op for a label + instruction sequence, which looks like:
1441  // LPC0:
1442  // add r0, pc
1443  // This adds the address of LPC0 to r0.
1444 
1445  // Emit the label.
1448  MI->getOperand(2).getImm(), OutContext));
1449 
1450  // Form and emit the add.
1451  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1452  .addReg(MI->getOperand(0).getReg())
1453  .addReg(MI->getOperand(0).getReg())
1454  .addReg(ARM::PC)
1455  // Add predicate operands.
1456  .addImm(ARMCC::AL)
1457  .addReg(0));
1458  return;
1459  }
1460  case ARM::PICADD: {
1461  // This is a pseudo op for a label + instruction sequence, which looks like:
1462  // LPC0:
1463  // add r0, pc, r0
1464  // This adds the address of LPC0 to r0.
1465 
1466  // Emit the label.
1469  MI->getOperand(2).getImm(), OutContext));
1470 
1471  // Form and emit the add.
1473  .addReg(MI->getOperand(0).getReg())
1474  .addReg(ARM::PC)
1475  .addReg(MI->getOperand(1).getReg())
1476  // Add predicate operands.
1477  .addImm(MI->getOperand(3).getImm())
1478  .addReg(MI->getOperand(4).getReg())
1479  // Add 's' bit operand (always reg0 for this)
1480  .addReg(0));
1481  return;
1482  }
1483  case ARM::PICSTR:
1484  case ARM::PICSTRB:
1485  case ARM::PICSTRH:
1486  case ARM::PICLDR:
1487  case ARM::PICLDRB:
1488  case ARM::PICLDRH:
1489  case ARM::PICLDRSB:
1490  case ARM::PICLDRSH: {
1491  // This is a pseudo op for a label + instruction sequence, which looks like:
1492  // LPC0:
1493  // OP r0, [pc, r0]
1494  // The LCP0 label is referenced by a constant pool entry in order to get
1495  // a PC-relative address at the ldr instruction.
1496 
1497  // Emit the label.
1500  MI->getOperand(2).getImm(), OutContext));
1501 
1502  // Form and emit the load
1503  unsigned Opcode;
1504  switch (MI->getOpcode()) {
1505  default:
1506  llvm_unreachable("Unexpected opcode!");
1507  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1508  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1509  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1510  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1511  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1512  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1513  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1514  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1515  }
1517  .addReg(MI->getOperand(0).getReg())
1518  .addReg(ARM::PC)
1519  .addReg(MI->getOperand(1).getReg())
1520  .addImm(0)
1521  // Add predicate operands.
1522  .addImm(MI->getOperand(3).getImm())
1523  .addReg(MI->getOperand(4).getReg()));
1524 
1525  return;
1526  }
1527  case ARM::CONSTPOOL_ENTRY: {
1528  if (Subtarget->genExecuteOnly())
1529  llvm_unreachable("execute-only should not generate constant pools");
1530 
1531  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1532  /// in the function. The first operand is the ID# for this instruction, the
1533  /// second is the index into the MachineConstantPool that this is, the third
1534  /// is the size in bytes of this constant pool entry.
1535  /// The required alignment is specified on the basic block holding this MI.
1536  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1537  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1538 
1539  // If this is the first entry of the pool, mark it.
1540  if (!InConstantPool) {
1541  OutStreamer->EmitDataRegion(MCDR_DataRegion);
1542  InConstantPool = true;
1543  }
1544 
1545  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1546 
1547  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1548  if (MCPE.isMachineConstantPoolEntry())
1550  else
1551  EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1552  return;
1553  }
1554  case ARM::JUMPTABLE_ADDRS:
1555  EmitJumpTableAddrs(MI);
1556  return;
1557  case ARM::JUMPTABLE_INSTS:
1558  EmitJumpTableInsts(MI);
1559  return;
1560  case ARM::JUMPTABLE_TBB:
1561  case ARM::JUMPTABLE_TBH:
1562  EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1563  return;
1564  case ARM::t2BR_JT: {
1566  .addReg(ARM::PC)
1567  .addReg(MI->getOperand(0).getReg())
1568  // Add predicate operands.
1569  .addImm(ARMCC::AL)
1570  .addReg(0));
1571  return;
1572  }
1573  case ARM::t2TBB_JT:
1574  case ARM::t2TBH_JT: {
1575  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1576  // Lower and emit the PC label, then the instruction itself.
1577  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1579  .addReg(MI->getOperand(0).getReg())
1580  .addReg(MI->getOperand(1).getReg())
1581  // Add predicate operands.
1582  .addImm(ARMCC::AL)
1583  .addReg(0));
1584  return;
1585  }
1586  case ARM::tTBB_JT:
1587  case ARM::tTBH_JT: {
1588 
1589  bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1590  unsigned Base = MI->getOperand(0).getReg();
1591  unsigned Idx = MI->getOperand(1).getReg();
1592  assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1593 
1594  // Multiply up idx if necessary.
1595  if (!Is8Bit)
1597  .addReg(Idx)
1598  .addReg(ARM::CPSR)
1599  .addReg(Idx)
1600  .addImm(1)
1601  // Add predicate operands.
1602  .addImm(ARMCC::AL)
1603  .addReg(0));
1604 
1605  if (Base == ARM::PC) {
1606  // TBB [base, idx] =
1607  // ADDS idx, idx, base
1608  // LDRB idx, [idx, #4] ; or LDRH if TBH
1609  // LSLS idx, #1
1610  // ADDS pc, pc, idx
1611 
1612  // When using PC as the base, it's important that there is no padding
1613  // between the last ADDS and the start of the jump table. The jump table
1614  // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1615  //
1616  // FIXME: Ideally we could vary the LDRB index based on the padding
1617  // between the sequence and jump table, however that relies on MCExprs
1618  // for load indexes which are currently not supported.
1619  OutStreamer->EmitCodeAlignment(4);
1620  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1621  .addReg(Idx)
1622  .addReg(Idx)
1623  .addReg(Base)
1624  // Add predicate operands.
1625  .addImm(ARMCC::AL)
1626  .addReg(0));
1627 
1628  unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1630  .addReg(Idx)
1631  .addReg(Idx)
1632  .addImm(Is8Bit ? 4 : 2)
1633  // Add predicate operands.
1634  .addImm(ARMCC::AL)
1635  .addReg(0));
1636  } else {
1637  // TBB [base, idx] =
1638  // LDRB idx, [base, idx] ; or LDRH if TBH
1639  // LSLS idx, #1
1640  // ADDS pc, pc, idx
1641 
1642  unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1644  .addReg(Idx)
1645  .addReg(Base)
1646  .addReg(Idx)
1647  // Add predicate operands.
1648  .addImm(ARMCC::AL)
1649  .addReg(0));
1650  }
1651 
1653  .addReg(Idx)
1654  .addReg(ARM::CPSR)
1655  .addReg(Idx)
1656  .addImm(1)
1657  // Add predicate operands.
1658  .addImm(ARMCC::AL)
1659  .addReg(0));
1660 
1661  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1662  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1663  .addReg(ARM::PC)
1664  .addReg(ARM::PC)
1665  .addReg(Idx)
1666  // Add predicate operands.
1667  .addImm(ARMCC::AL)
1668  .addReg(0));
1669  return;
1670  }
1671  case ARM::tBR_JTr:
1672  case ARM::BR_JTr: {
1673  // mov pc, target
1674  MCInst TmpInst;
1675  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1676  ARM::MOVr : ARM::tMOVr;
1677  TmpInst.setOpcode(Opc);
1678  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1679  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1680  // Add predicate operands.
1682  TmpInst.addOperand(MCOperand::createReg(0));
1683  // Add 's' bit operand (always reg0 for this)
1684  if (Opc == ARM::MOVr)
1685  TmpInst.addOperand(MCOperand::createReg(0));
1686  EmitToStreamer(*OutStreamer, TmpInst);
1687  return;
1688  }
1689  case ARM::BR_JTm_i12: {
1690  // ldr pc, target
1691  MCInst TmpInst;
1692  TmpInst.setOpcode(ARM::LDRi12);
1693  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1694  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1695  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1696  // Add predicate operands.
1698  TmpInst.addOperand(MCOperand::createReg(0));
1699  EmitToStreamer(*OutStreamer, TmpInst);
1700  return;
1701  }
1702  case ARM::BR_JTm_rs: {
1703  // ldr pc, target
1704  MCInst TmpInst;
1705  TmpInst.setOpcode(ARM::LDRrs);
1706  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1707  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1708  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1709  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1710  // Add predicate operands.
1712  TmpInst.addOperand(MCOperand::createReg(0));
1713  EmitToStreamer(*OutStreamer, TmpInst);
1714  return;
1715  }
1716  case ARM::BR_JTadd: {
1717  // add pc, target, idx
1719  .addReg(ARM::PC)
1720  .addReg(MI->getOperand(0).getReg())
1721  .addReg(MI->getOperand(1).getReg())
1722  // Add predicate operands.
1723  .addImm(ARMCC::AL)
1724  .addReg(0)
1725  // Add 's' bit operand (always reg0 for this)
1726  .addReg(0));
1727  return;
1728  }
1729  case ARM::SPACE:
1730  OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1731  return;
1732  case ARM::TRAP: {
1733  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1734  // FIXME: Remove this special case when they do.
1735  if (!Subtarget->isTargetMachO()) {
1736  uint32_t Val = 0xe7ffdefeUL;
1737  OutStreamer->AddComment("trap");
1738  ATS.emitInst(Val);
1739  return;
1740  }
1741  break;
1742  }
1743  case ARM::TRAPNaCl: {
1744  uint32_t Val = 0xe7fedef0UL;
1745  OutStreamer->AddComment("trap");
1746  ATS.emitInst(Val);
1747  return;
1748  }
1749  case ARM::tTRAP: {
1750  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1751  // FIXME: Remove this special case when they do.
1752  if (!Subtarget->isTargetMachO()) {
1753  uint16_t Val = 0xdefe;
1754  OutStreamer->AddComment("trap");
1755  ATS.emitInst(Val, 'n');
1756  return;
1757  }
1758  break;
1759  }
1760  case ARM::t2Int_eh_sjlj_setjmp:
1761  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1762  case ARM::tInt_eh_sjlj_setjmp: {
1763  // Two incoming args: GPR:$src, GPR:$val
1764  // mov $val, pc
1765  // adds $val, #7
1766  // str $val, [$src, #4]
1767  // movs r0, #0
1768  // b LSJLJEH
1769  // movs r0, #1
1770  // LSJLJEH:
1771  unsigned SrcReg = MI->getOperand(0).getReg();
1772  unsigned ValReg = MI->getOperand(1).getReg();
1773  MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1774  OutStreamer->AddComment("eh_setjmp begin");
1776  .addReg(ValReg)
1777  .addReg(ARM::PC)
1778  // Predicate.
1779  .addImm(ARMCC::AL)
1780  .addReg(0));
1781 
1783  .addReg(ValReg)
1784  // 's' bit operand
1785  .addReg(ARM::CPSR)
1786  .addReg(ValReg)
1787  .addImm(7)
1788  // Predicate.
1789  .addImm(ARMCC::AL)
1790  .addReg(0));
1791 
1793  .addReg(ValReg)
1794  .addReg(SrcReg)
1795  // The offset immediate is #4. The operand value is scaled by 4 for the
1796  // tSTR instruction.
1797  .addImm(1)
1798  // Predicate.
1799  .addImm(ARMCC::AL)
1800  .addReg(0));
1801 
1803  .addReg(ARM::R0)
1804  .addReg(ARM::CPSR)
1805  .addImm(0)
1806  // Predicate.
1807  .addImm(ARMCC::AL)
1808  .addReg(0));
1809 
1810  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1812  .addExpr(SymbolExpr)
1813  .addImm(ARMCC::AL)
1814  .addReg(0));
1815 
1816  OutStreamer->AddComment("eh_setjmp end");
1818  .addReg(ARM::R0)
1819  .addReg(ARM::CPSR)
1820  .addImm(1)
1821  // Predicate.
1822  .addImm(ARMCC::AL)
1823  .addReg(0));
1824 
1825  OutStreamer->EmitLabel(Label);
1826  return;
1827  }
1828 
1829  case ARM::Int_eh_sjlj_setjmp_nofp:
1830  case ARM::Int_eh_sjlj_setjmp: {
1831  // Two incoming args: GPR:$src, GPR:$val
1832  // add $val, pc, #8
1833  // str $val, [$src, #+4]
1834  // mov r0, #0
1835  // add pc, pc, #0
1836  // mov r0, #1
1837  unsigned SrcReg = MI->getOperand(0).getReg();
1838  unsigned ValReg = MI->getOperand(1).getReg();
1839 
1840  OutStreamer->AddComment("eh_setjmp begin");
1842  .addReg(ValReg)
1843  .addReg(ARM::PC)
1844  .addImm(8)
1845  // Predicate.
1846  .addImm(ARMCC::AL)
1847  .addReg(0)
1848  // 's' bit operand (always reg0 for this).
1849  .addReg(0));
1850 
1852  .addReg(ValReg)
1853  .addReg(SrcReg)
1854  .addImm(4)
1855  // Predicate.
1856  .addImm(ARMCC::AL)
1857  .addReg(0));
1858 
1860  .addReg(ARM::R0)
1861  .addImm(0)
1862  // Predicate.
1863  .addImm(ARMCC::AL)
1864  .addReg(0)
1865  // 's' bit operand (always reg0 for this).
1866  .addReg(0));
1867 
1869  .addReg(ARM::PC)
1870  .addReg(ARM::PC)
1871  .addImm(0)
1872  // Predicate.
1873  .addImm(ARMCC::AL)
1874  .addReg(0)
1875  // 's' bit operand (always reg0 for this).
1876  .addReg(0));
1877 
1878  OutStreamer->AddComment("eh_setjmp end");
1880  .addReg(ARM::R0)
1881  .addImm(1)
1882  // Predicate.
1883  .addImm(ARMCC::AL)
1884  .addReg(0)
1885  // 's' bit operand (always reg0 for this).
1886  .addReg(0));
1887  return;
1888  }
1889  case ARM::Int_eh_sjlj_longjmp: {
1890  // ldr sp, [$src, #8]
1891  // ldr $scratch, [$src, #4]
1892  // ldr r7, [$src]
1893  // bx $scratch
1894  unsigned SrcReg = MI->getOperand(0).getReg();
1895  unsigned ScratchReg = MI->getOperand(1).getReg();
1897  .addReg(ARM::SP)
1898  .addReg(SrcReg)
1899  .addImm(8)
1900  // Predicate.
1901  .addImm(ARMCC::AL)
1902  .addReg(0));
1903 
1905  .addReg(ScratchReg)
1906  .addReg(SrcReg)
1907  .addImm(4)
1908  // Predicate.
1909  .addImm(ARMCC::AL)
1910  .addReg(0));
1911 
1912  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1913  // These platforms always use the same frame register
1915  .addReg(FramePtr)
1916  .addReg(SrcReg)
1917  .addImm(0)
1918  // Predicate.
1919  .addImm(ARMCC::AL)
1920  .addReg(0));
1921  } else {
1922  // If the calling code might use either R7 or R11 as
1923  // frame pointer register, restore it into both.
1925  .addReg(ARM::R7)
1926  .addReg(SrcReg)
1927  .addImm(0)
1928  // Predicate.
1929  .addImm(ARMCC::AL)
1930  .addReg(0));
1932  .addReg(ARM::R11)
1933  .addReg(SrcReg)
1934  .addImm(0)
1935  // Predicate.
1936  .addImm(ARMCC::AL)
1937  .addReg(0));
1938  }
1939 
1940  assert(Subtarget->hasV4TOps());
1942  .addReg(ScratchReg)
1943  // Predicate.
1944  .addImm(ARMCC::AL)
1945  .addReg(0));
1946  return;
1947  }
1948  case ARM::tInt_eh_sjlj_longjmp: {
1949  // ldr $scratch, [$src, #8]
1950  // mov sp, $scratch
1951  // ldr $scratch, [$src, #4]
1952  // ldr r7, [$src]
1953  // bx $scratch
1954  unsigned SrcReg = MI->getOperand(0).getReg();
1955  unsigned ScratchReg = MI->getOperand(1).getReg();
1956 
1958  .addReg(ScratchReg)
1959  .addReg(SrcReg)
1960  // The offset immediate is #8. The operand value is scaled by 4 for the
1961  // tLDR instruction.
1962  .addImm(2)
1963  // Predicate.
1964  .addImm(ARMCC::AL)
1965  .addReg(0));
1966 
1968  .addReg(ARM::SP)
1969  .addReg(ScratchReg)
1970  // Predicate.
1971  .addImm(ARMCC::AL)
1972  .addReg(0));
1973 
1975  .addReg(ScratchReg)
1976  .addReg(SrcReg)
1977  .addImm(1)
1978  // Predicate.
1979  .addImm(ARMCC::AL)
1980  .addReg(0));
1981 
1982  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1983  // These platforms always use the same frame register
1985  .addReg(FramePtr)
1986  .addReg(SrcReg)
1987  .addImm(0)
1988  // Predicate.
1989  .addImm(ARMCC::AL)
1990  .addReg(0));
1991  } else {
1992  // If the calling code might use either R7 or R11 as
1993  // frame pointer register, restore it into both.
1995  .addReg(ARM::R7)
1996  .addReg(SrcReg)
1997  .addImm(0)
1998  // Predicate.
1999  .addImm(ARMCC::AL)
2000  .addReg(0));
2002  .addReg(ARM::R11)
2003  .addReg(SrcReg)
2004  .addImm(0)
2005  // Predicate.
2006  .addImm(ARMCC::AL)
2007  .addReg(0));
2008  }
2009 
2011  .addReg(ScratchReg)
2012  // Predicate.
2013  .addImm(ARMCC::AL)
2014  .addReg(0));
2015  return;
2016  }
2017  case ARM::tInt_WIN_eh_sjlj_longjmp: {
2018  // ldr.w r11, [$src, #0]
2019  // ldr.w sp, [$src, #8]
2020  // ldr.w pc, [$src, #4]
2021 
2022  unsigned SrcReg = MI->getOperand(0).getReg();
2023 
2024  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2025  .addReg(ARM::R11)
2026  .addReg(SrcReg)
2027  .addImm(0)
2028  // Predicate
2029  .addImm(ARMCC::AL)
2030  .addReg(0));
2031  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2032  .addReg(ARM::SP)
2033  .addReg(SrcReg)
2034  .addImm(8)
2035  // Predicate
2036  .addImm(ARMCC::AL)
2037  .addReg(0));
2038  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2039  .addReg(ARM::PC)
2040  .addReg(SrcReg)
2041  .addImm(4)
2042  // Predicate
2043  .addImm(ARMCC::AL)
2044  .addReg(0));
2045  return;
2046  }
2047  case ARM::PATCHABLE_FUNCTION_ENTER:
2049  return;
2050  case ARM::PATCHABLE_FUNCTION_EXIT:
2052  return;
2053  case ARM::PATCHABLE_TAIL_CALL:
2055  return;
2056  }
2057 
2058  MCInst TmpInst;
2059  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2060 
2061  EmitToStreamer(*OutStreamer, TmpInst);
2062 }
2063 
2064 //===----------------------------------------------------------------------===//
2065 // Target Registry Stuff
2066 //===----------------------------------------------------------------------===//
2067 
2068 // Force static initialization.
2069 extern "C" void LLVMInitializeARMAsmPrinter() {
2074 }
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=ARM::NoRegAltName)
unsigned getTargetFlags() const
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:446
MachineConstantPoolValue * MachineCPVal
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:265
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:212
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
StringRef getTargetFeatureString() const
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:677
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const std::vector< MachineJumpTableEntry > & getJumpTables() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
This class represents lattice values for constants.
Definition: AllocatorList.h:23
PointerTy getPointer() const
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:597
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:316
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:603
void EmitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:615
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool hasV4TOps() const
Definition: ARMSubtarget.h:538
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void push_back(const T &Elt)
Definition: SmallVector.h:211
ARMConstantPoolValue - ARM specific constantpool value.
unsigned getReg() const
getReg - Returns the register number.
Target specific streamer interface.
Definition: MCStreamer.h:83
unsigned Reg
virtual void emitPad(int64_t Offset)
unsigned getSubReg() const
Global Offset Table, Thread Pointer Offset.
unsigned char getPCAdjustment() const
bool isTargetCOFF() const
Definition: ARMSubtarget.h:661
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
MachineBasicBlock reference.
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the EmitInstruction() method to print assembly for each instruction...
virtual void finishAttributeSection()
unsigned const TargetRegisterInfo * TRI
F(f)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isThumb1Only() const
Definition: ARMSubtarget.h:719
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:682
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Global Offset Table, PC Relative.
Thread Pointer Offset.
Target & getTheThumbLETarget()
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
static bool isThumb(const MCSubtargetInfo &STI)
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:341
void LLVMInitializeARMAsmPrinter()
union llvm::MachineConstantPoolEntry::@163 Val
The constant itself.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
return AArch64::GPR64RegClass contains(Reg)
bool genExecuteOnly() const
Definition: ARMSubtarget.h:638
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
bool isTargetELF() const
Definition: ARMSubtarget.h:662
ARMCP::ARMCPModifier getModifier() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
The address of a basic block.
Definition: Constants.h:839
MCContext & getContext() const
Definition: MCStreamer.h:250
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: ARMBaseInfo.h:253
Definition: BitVector.h:937
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override
Print the MachineOperand as a symbol.
virtual void emitInst(uint32_t Inst, char Suffix='\0')
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
MCSuperRegIterator enumerates all super-registers of Reg.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
const FeatureBitset & getFeatureBits() const
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:469
unsigned SubReg
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
.data_region jt16
Definition: MCDirectives.h:59
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target & getTheARMBETarget()
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
void emitXRayTable()
Emit a table with all XRay instrumentation points.
Context object for machine code objects.
Definition: MCContext.h:62
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:42
void EmitFunctionBody()
This method emits the body and trailer for a function.
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file. ...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:544
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:203
Target & getTheThumbBETarget()
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
IntType getInt() const
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:690
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
bool isTargetDarwin() const
Definition: ARMSubtarget.h:652
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
This class is a data container for one entry in a MachineConstantPool.
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
StringRef getTargetCPU() const
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: COFF.h:265
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:459
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:128
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:159
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:99
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:731
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
virtual void emitAttribute(unsigned Attribute, unsigned Value)
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:819
.data_region jt32
Definition: MCDirectives.h:60
Address of a global value.
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
Streaming machine code generation interface.
Definition: MCStreamer.h:188
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:220
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:112
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
PointerIntPair - This class implements a pair of a pointer and small integer.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const GlobalValue * getGlobal() const
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
MCSection * getNonLazySymbolPointerSection() const
void EmitAlignment(unsigned NumBits, const GlobalObject *GV=nullptr) const
Emit an alignment directive to the specified power of two boundary.
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:436
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
bool hasInternalLinkage() const
Definition: GlobalValue.h:433
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:50
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:793
Thread Local Storage (General Dynamic Mode)
const Triple & getTargetTriple() const
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an &#39;S&#39; bit onto real opcodes.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
Ty & getObjFileInfo()
Keep track of various per-function pieces of information for backends that would like to do so...
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:625
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
FPDenormal::DenormalMode FPDenormalMode
FPDenormalMode - This flags specificies which denormal numbers the code is permitted to require...
const Constant * stripPointerCasts() const
Definition: Constant.h:177
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Abstract base class for all machine specific constantpool value subclasses.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:240
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
MCSection * getThreadLocalPointerSection() const
void EmitJumpTableInsts(const MachineInstr *MI)
const std::vector< MachineConstantPoolEntry > & getConstants() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:208
void setOpcode(unsigned Op)
Definition: MCInst.h:170
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
bool isTargetAEABI() const
Definition: ARMSubtarget.h:672
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:441
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
.indirect_symbol (MachO)
Definition: MCDirectives.h:32
unsigned getOriginalCPIdx(unsigned CloneIdx) const
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:231
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: COFF.h:203
StubValueTy & getGVStubEntry(MCSymbol *Sym)
.syntax (ARM/ELF)
Definition: MCDirectives.h:49
MCSymbol * getCurExceptionSym()
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
bool isROPI() const
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
FunctionNumber(functionNumber)
Definition: LLParser.cpp:2743
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:350
Section Relative (Windows TLS)
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:461
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:686
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
TargetOptions Options
int64_t getOffset() const
Return the offset from the symbol in this operand.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
void EmitJumpTableAddrs(const MachineInstr *MI)
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:38
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:600
Generic base class for all target subtargets.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:128
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
bool hasV5TOps() const
Definition: ARMSubtarget.h:539
Type * getType() const
getType - get type of this MachineConstantPoolValue.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const Module * getModule() const
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
const std::string & getModuleInlineAsm() const
Get any module-scope inline assembly blocks.
Definition: Module.h:248
bool isTargetMachO() const
Definition: ARMSubtarget.h:663
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
.data_region jt8
Definition: MCDirectives.h:58
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:72
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:351
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:278
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:569
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
static const unsigned FramePtr
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool isTargetWindows() const
Definition: ARMSubtarget.h:659
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:216
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:246
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
Address of indexed Constant in Constant Pool.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
Target & getTheARMLETarget()
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
void EmitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:294
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
.end_data_region
Definition: MCDirectives.h:61
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:244
bool isImplicit() const
virtual void switchVendor(StringRef Vendor)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
A function that returns a base type.
Definition: COFF.h:261