LLVM  10.0.0svn
ARMBaseInstrInfo.cpp
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1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMBaseInstrInfo.h"
14 #include "ARMBaseRegisterInfo.h"
15 #include "ARMConstantPoolValue.h"
16 #include "ARMFeatures.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/Triple.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/Constants.h"
44 #include "llvm/IR/DebugLoc.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/GlobalValue.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/MC/MCInstrDesc.h"
51 #include "llvm/Support/Casting.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
58 #include <algorithm>
59 #include <cassert>
60 #include <cstdint>
61 #include <iterator>
62 #include <new>
63 #include <utility>
64 #include <vector>
65 
66 using namespace llvm;
67 
68 #define DEBUG_TYPE "arm-instrinfo"
69 
70 #define GET_INSTRINFO_CTOR_DTOR
71 #include "ARMGenInstrInfo.inc"
72 
73 static cl::opt<bool>
74 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
75  cl::desc("Enable ARM 2-addr to 3-addr conv"));
76 
77 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
78 struct ARM_MLxEntry {
79  uint16_t MLxOpc; // MLA / MLS opcode
80  uint16_t MulOpc; // Expanded multiplication opcode
81  uint16_t AddSubOpc; // Expanded add / sub opcode
82  bool NegAcc; // True if the acc is negated before the add / sub.
83  bool HasLane; // True if instruction has an extra "lane" operand.
84 };
85 
86 static const ARM_MLxEntry ARM_MLxTable[] = {
87  // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
88  // fp scalar ops
89  { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
90  { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
91  { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
92  { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
93  { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
94  { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
95  { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
96  { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
97 
98  // fp SIMD ops
99  { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
100  { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
101  { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
102  { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
103  { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
104  { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
105  { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
106  { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
107 };
108 
110  : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
111  Subtarget(STI) {
112  for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
113  if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
114  llvm_unreachable("Duplicated entries?");
115  MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
116  MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
117  }
118 }
119 
120 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
121 // currently defaults to no prepass hazard recognizer.
124  const ScheduleDAG *DAG) const {
125  if (usePreRAHazardRecognizer()) {
126  const InstrItineraryData *II =
127  static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
128  return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
129  }
131 }
132 
135  const ScheduleDAG *DAG) const {
136  if (Subtarget.isThumb2() || Subtarget.hasVFP2Base())
137  return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
139 }
140 
143  // FIXME: Thumb2 support.
144 
145  if (!EnableARM3Addr)
146  return nullptr;
147 
148  MachineFunction &MF = *MI.getParent()->getParent();
149  uint64_t TSFlags = MI.getDesc().TSFlags;
150  bool isPre = false;
151  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
152  default: return nullptr;
153  case ARMII::IndexModePre:
154  isPre = true;
155  break;
157  break;
158  }
159 
160  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
161  // operation.
162  unsigned MemOpc = getUnindexedOpcode(MI.getOpcode());
163  if (MemOpc == 0)
164  return nullptr;
165 
166  MachineInstr *UpdateMI = nullptr;
167  MachineInstr *MemMI = nullptr;
168  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
169  const MCInstrDesc &MCID = MI.getDesc();
170  unsigned NumOps = MCID.getNumOperands();
171  bool isLoad = !MI.mayStore();
172  const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
173  const MachineOperand &Base = MI.getOperand(2);
174  const MachineOperand &Offset = MI.getOperand(NumOps - 3);
175  Register WBReg = WB.getReg();
176  Register BaseReg = Base.getReg();
177  Register OffReg = Offset.getReg();
178  unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
179  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
180  switch (AddrMode) {
181  default: llvm_unreachable("Unknown indexed op!");
182  case ARMII::AddrMode2: {
183  bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
184  unsigned Amt = ARM_AM::getAM2Offset(OffImm);
185  if (OffReg == 0) {
186  if (ARM_AM::getSOImmVal(Amt) == -1)
187  // Can't encode it in a so_imm operand. This transformation will
188  // add more than 1 instruction. Abandon!
189  return nullptr;
190  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
191  get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
192  .addReg(BaseReg)
193  .addImm(Amt)
194  .add(predOps(Pred))
195  .add(condCodeOp());
196  } else if (Amt != 0) {
198  unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
199  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
200  get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
201  .addReg(BaseReg)
202  .addReg(OffReg)
203  .addReg(0)
204  .addImm(SOOpc)
205  .add(predOps(Pred))
206  .add(condCodeOp());
207  } else
208  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
209  get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
210  .addReg(BaseReg)
211  .addReg(OffReg)
212  .add(predOps(Pred))
213  .add(condCodeOp());
214  break;
215  }
216  case ARMII::AddrMode3 : {
217  bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
218  unsigned Amt = ARM_AM::getAM3Offset(OffImm);
219  if (OffReg == 0)
220  // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
221  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
222  get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
223  .addReg(BaseReg)
224  .addImm(Amt)
225  .add(predOps(Pred))
226  .add(condCodeOp());
227  else
228  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
229  get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
230  .addReg(BaseReg)
231  .addReg(OffReg)
232  .add(predOps(Pred))
233  .add(condCodeOp());
234  break;
235  }
236  }
237 
238  std::vector<MachineInstr*> NewMIs;
239  if (isPre) {
240  if (isLoad)
241  MemMI =
242  BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
243  .addReg(WBReg)
244  .addImm(0)
245  .addImm(Pred);
246  else
247  MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
248  .addReg(MI.getOperand(1).getReg())
249  .addReg(WBReg)
250  .addReg(0)
251  .addImm(0)
252  .addImm(Pred);
253  NewMIs.push_back(MemMI);
254  NewMIs.push_back(UpdateMI);
255  } else {
256  if (isLoad)
257  MemMI =
258  BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
259  .addReg(BaseReg)
260  .addImm(0)
261  .addImm(Pred);
262  else
263  MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
264  .addReg(MI.getOperand(1).getReg())
265  .addReg(BaseReg)
266  .addReg(0)
267  .addImm(0)
268  .addImm(Pred);
269  if (WB.isDead())
270  UpdateMI->getOperand(0).setIsDead();
271  NewMIs.push_back(UpdateMI);
272  NewMIs.push_back(MemMI);
273  }
274 
275  // Transfer LiveVariables states, kill / dead info.
276  if (LV) {
277  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
278  MachineOperand &MO = MI.getOperand(i);
279  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
280  Register Reg = MO.getReg();
281 
283  if (MO.isDef()) {
284  MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
285  if (MO.isDead())
286  LV->addVirtualRegisterDead(Reg, *NewMI);
287  }
288  if (MO.isUse() && MO.isKill()) {
289  for (unsigned j = 0; j < 2; ++j) {
290  // Look at the two new MI's in reverse order.
291  MachineInstr *NewMI = NewMIs[j];
292  if (!NewMI->readsRegister(Reg))
293  continue;
294  LV->addVirtualRegisterKilled(Reg, *NewMI);
295  if (VI.removeKill(MI))
296  VI.Kills.push_back(NewMI);
297  break;
298  }
299  }
300  }
301  }
302  }
303 
305  MFI->insert(MBBI, NewMIs[1]);
306  MFI->insert(MBBI, NewMIs[0]);
307  return NewMIs[0];
308 }
309 
310 // Branch analysis.
312  MachineBasicBlock *&TBB,
313  MachineBasicBlock *&FBB,
315  bool AllowModify) const {
316  TBB = nullptr;
317  FBB = nullptr;
318 
320  if (I == MBB.begin())
321  return false; // Empty blocks are easy.
322  --I;
323 
324  // Walk backwards from the end of the basic block until the branch is
325  // analyzed or we give up.
326  while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
327  // Flag to be raised on unanalyzeable instructions. This is useful in cases
328  // where we want to clean up on the end of the basic block before we bail
329  // out.
330  bool CantAnalyze = false;
331 
332  // Skip over DEBUG values and predicated nonterminators.
333  while (I->isDebugInstr() || !I->isTerminator()) {
334  if (I == MBB.begin())
335  return false;
336  --I;
337  }
338 
339  if (isIndirectBranchOpcode(I->getOpcode()) ||
340  isJumpTableBranchOpcode(I->getOpcode())) {
341  // Indirect branches and jump tables can't be analyzed, but we still want
342  // to clean up any instructions at the tail of the basic block.
343  CantAnalyze = true;
344  } else if (isUncondBranchOpcode(I->getOpcode())) {
345  TBB = I->getOperand(0).getMBB();
346  } else if (isCondBranchOpcode(I->getOpcode())) {
347  // Bail out if we encounter multiple conditional branches.
348  if (!Cond.empty())
349  return true;
350 
351  assert(!FBB && "FBB should have been null.");
352  FBB = TBB;
353  TBB = I->getOperand(0).getMBB();
354  Cond.push_back(I->getOperand(1));
355  Cond.push_back(I->getOperand(2));
356  } else if (I->isReturn()) {
357  // Returns can't be analyzed, but we should run cleanup.
358  CantAnalyze = !isPredicated(*I);
359  } else {
360  // We encountered other unrecognized terminator. Bail out immediately.
361  return true;
362  }
363 
364  // Cleanup code - to be run for unpredicated unconditional branches and
365  // returns.
366  if (!isPredicated(*I) &&
367  (isUncondBranchOpcode(I->getOpcode()) ||
368  isIndirectBranchOpcode(I->getOpcode()) ||
369  isJumpTableBranchOpcode(I->getOpcode()) ||
370  I->isReturn())) {
371  // Forget any previous condition branch information - it no longer applies.
372  Cond.clear();
373  FBB = nullptr;
374 
375  // If we can modify the function, delete everything below this
376  // unconditional branch.
377  if (AllowModify) {
378  MachineBasicBlock::iterator DI = std::next(I);
379  while (DI != MBB.end()) {
380  MachineInstr &InstToDelete = *DI;
381  ++DI;
382  InstToDelete.eraseFromParent();
383  }
384  }
385  }
386 
387  if (CantAnalyze)
388  return true;
389 
390  if (I == MBB.begin())
391  return false;
392 
393  --I;
394  }
395 
396  // We made it past the terminators without bailing out - we must have
397  // analyzed this branch successfully.
398  return false;
399 }
400 
402  int *BytesRemoved) const {
403  assert(!BytesRemoved && "code size not handled");
404 
406  if (I == MBB.end())
407  return 0;
408 
409  if (!isUncondBranchOpcode(I->getOpcode()) &&
410  !isCondBranchOpcode(I->getOpcode()))
411  return 0;
412 
413  // Remove the branch.
414  I->eraseFromParent();
415 
416  I = MBB.end();
417 
418  if (I == MBB.begin()) return 1;
419  --I;
420  if (!isCondBranchOpcode(I->getOpcode()))
421  return 1;
422 
423  // Remove the branch.
424  I->eraseFromParent();
425  return 2;
426 }
427 
429  MachineBasicBlock *TBB,
430  MachineBasicBlock *FBB,
432  const DebugLoc &DL,
433  int *BytesAdded) const {
434  assert(!BytesAdded && "code size not handled");
436  int BOpc = !AFI->isThumbFunction()
437  ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
438  int BccOpc = !AFI->isThumbFunction()
439  ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
440  bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
441 
442  // Shouldn't be a fall through.
443  assert(TBB && "insertBranch must not be told to insert a fallthrough");
444  assert((Cond.size() == 2 || Cond.size() == 0) &&
445  "ARM branch conditions have two components!");
446 
447  // For conditional branches, we use addOperand to preserve CPSR flags.
448 
449  if (!FBB) {
450  if (Cond.empty()) { // Unconditional branch?
451  if (isThumb)
452  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
453  else
454  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
455  } else
456  BuildMI(&MBB, DL, get(BccOpc))
457  .addMBB(TBB)
458  .addImm(Cond[0].getImm())
459  .add(Cond[1]);
460  return 1;
461  }
462 
463  // Two-way conditional branch.
464  BuildMI(&MBB, DL, get(BccOpc))
465  .addMBB(TBB)
466  .addImm(Cond[0].getImm())
467  .add(Cond[1]);
468  if (isThumb)
469  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
470  else
471  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
472  return 2;
473 }
474 
477  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
478  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
479  return false;
480 }
481 
483  if (MI.isBundle()) {
486  while (++I != E && I->isInsideBundle()) {
487  int PIdx = I->findFirstPredOperandIdx();
488  if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
489  return true;
490  }
491  return false;
492  }
493 
494  int PIdx = MI.findFirstPredOperandIdx();
495  return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
496 }
497 
500  unsigned Opc = MI.getOpcode();
501  if (isUncondBranchOpcode(Opc)) {
502  MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
504  .addImm(Pred[0].getImm())
505  .addReg(Pred[1].getReg());
506  return true;
507  }
508 
509  int PIdx = MI.findFirstPredOperandIdx();
510  if (PIdx != -1) {
511  MachineOperand &PMO = MI.getOperand(PIdx);
512  PMO.setImm(Pred[0].getImm());
513  MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
514  return true;
515  }
516  return false;
517 }
518 
520  ArrayRef<MachineOperand> Pred2) const {
521  if (Pred1.size() > 2 || Pred2.size() > 2)
522  return false;
523 
524  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
525  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
526  if (CC1 == CC2)
527  return true;
528 
529  switch (CC1) {
530  default:
531  return false;
532  case ARMCC::AL:
533  return true;
534  case ARMCC::HS:
535  return CC2 == ARMCC::HI;
536  case ARMCC::LS:
537  return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
538  case ARMCC::GE:
539  return CC2 == ARMCC::GT;
540  case ARMCC::LE:
541  return CC2 == ARMCC::LT;
542  }
543 }
544 
546  MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
547  bool Found = false;
548  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
549  const MachineOperand &MO = MI.getOperand(i);
550  if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
551  (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
552  Pred.push_back(MO);
553  Found = true;
554  }
555  }
556 
557  return Found;
558 }
559 
561  for (const auto &MO : MI.operands())
562  if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
563  return true;
564  return false;
565 }
566 
568  unsigned Op) const {
569  const MachineOperand &Offset = MI.getOperand(Op + 1);
570  return Offset.getReg() != 0;
571 }
572 
573 // Load with negative register offset requires additional 1cyc and +I unit
574 // for Cortex A57
576  unsigned Op) const {
577  const MachineOperand &Offset = MI.getOperand(Op + 1);
578  const MachineOperand &Opc = MI.getOperand(Op + 2);
579  assert(Opc.isImm());
580  assert(Offset.isReg());
581  int64_t OpcImm = Opc.getImm();
582 
583  bool isSub = ARM_AM::getAM3Op(OpcImm) == ARM_AM::sub;
584  return (isSub && Offset.getReg() != 0);
585 }
586 
588  unsigned Op) const {
589  const MachineOperand &Opc = MI.getOperand(Op + 2);
590  unsigned OffImm = Opc.getImm();
591  return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
592 }
593 
594 // Load, scaled register offset, not plus LSL2
596  unsigned Op) const {
597  const MachineOperand &Opc = MI.getOperand(Op + 2);
598  unsigned OffImm = Opc.getImm();
599 
600  bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add;
601  unsigned Amt = ARM_AM::getAM2Offset(OffImm);
603  if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled
604  bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2);
605  return !SimpleScaled;
606 }
607 
608 // Minus reg for ldstso addr mode
610  unsigned Op) const {
611  unsigned OffImm = MI.getOperand(Op + 2).getImm();
612  return ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
613 }
614 
615 // Load, scaled register offset
617  unsigned Op) const {
618  unsigned OffImm = MI.getOperand(Op + 2).getImm();
619  return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
620 }
621 
622 static bool isEligibleForITBlock(const MachineInstr *MI) {
623  switch (MI->getOpcode()) {
624  default: return true;
625  case ARM::tADC: // ADC (register) T1
626  case ARM::tADDi3: // ADD (immediate) T1
627  case ARM::tADDi8: // ADD (immediate) T2
628  case ARM::tADDrr: // ADD (register) T1
629  case ARM::tAND: // AND (register) T1
630  case ARM::tASRri: // ASR (immediate) T1
631  case ARM::tASRrr: // ASR (register) T1
632  case ARM::tBIC: // BIC (register) T1
633  case ARM::tEOR: // EOR (register) T1
634  case ARM::tLSLri: // LSL (immediate) T1
635  case ARM::tLSLrr: // LSL (register) T1
636  case ARM::tLSRri: // LSR (immediate) T1
637  case ARM::tLSRrr: // LSR (register) T1
638  case ARM::tMUL: // MUL T1
639  case ARM::tMVN: // MVN (register) T1
640  case ARM::tORR: // ORR (register) T1
641  case ARM::tROR: // ROR (register) T1
642  case ARM::tRSB: // RSB (immediate) T1
643  case ARM::tSBC: // SBC (register) T1
644  case ARM::tSUBi3: // SUB (immediate) T1
645  case ARM::tSUBi8: // SUB (immediate) T2
646  case ARM::tSUBrr: // SUB (register) T1
647  return !ARMBaseInstrInfo::isCPSRDefined(*MI);
648  }
649 }
650 
651 /// isPredicable - Return true if the specified instruction can be predicated.
652 /// By default, this returns true for every instruction with a
653 /// PredicateOperand.
655  if (!MI.isPredicable())
656  return false;
657 
658  if (MI.isBundle())
659  return false;
660 
661  if (!isEligibleForITBlock(&MI))
662  return false;
663 
664  const ARMFunctionInfo *AFI =
666 
667  // Neon instructions in Thumb2 IT blocks are deprecated, see ARMARM.
668  // In their ARM encoding, they can't be encoded in a conditional form.
670  return false;
671 
672  if (AFI->isThumb2Function()) {
673  if (getSubtarget().restrictIT())
674  return isV8EligibleForIT(&MI);
675  }
676 
677  return true;
678 }
679 
680 namespace llvm {
681 
682 template <> bool IsCPSRDead<MachineInstr>(const MachineInstr *MI) {
683  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
684  const MachineOperand &MO = MI->getOperand(i);
685  if (!MO.isReg() || MO.isUndef() || MO.isUse())
686  continue;
687  if (MO.getReg() != ARM::CPSR)
688  continue;
689  if (!MO.isDead())
690  return false;
691  }
692  // all definitions of CPSR are dead
693  return true;
694 }
695 
696 } // end namespace llvm
697 
698 /// GetInstSize - Return the size of the specified MachineInstr.
699 ///
701  const MachineBasicBlock &MBB = *MI.getParent();
702  const MachineFunction *MF = MBB.getParent();
703  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
704 
705  const MCInstrDesc &MCID = MI.getDesc();
706  if (MCID.getSize())
707  return MCID.getSize();
708 
709  switch (MI.getOpcode()) {
710  default:
711  // pseudo-instruction sizes are zero.
712  return 0;
713  case TargetOpcode::BUNDLE:
714  return getInstBundleLength(MI);
715  case ARM::MOVi16_ga_pcrel:
716  case ARM::MOVTi16_ga_pcrel:
717  case ARM::t2MOVi16_ga_pcrel:
718  case ARM::t2MOVTi16_ga_pcrel:
719  return 4;
720  case ARM::MOVi32imm:
721  case ARM::t2MOVi32imm:
722  return 8;
723  case ARM::CONSTPOOL_ENTRY:
724  case ARM::JUMPTABLE_INSTS:
725  case ARM::JUMPTABLE_ADDRS:
726  case ARM::JUMPTABLE_TBB:
727  case ARM::JUMPTABLE_TBH:
728  // If this machine instr is a constant pool entry, its size is recorded as
729  // operand #2.
730  return MI.getOperand(2).getImm();
731  case ARM::Int_eh_sjlj_longjmp:
732  return 16;
733  case ARM::tInt_eh_sjlj_longjmp:
734  return 10;
735  case ARM::tInt_WIN_eh_sjlj_longjmp:
736  return 12;
737  case ARM::Int_eh_sjlj_setjmp:
738  case ARM::Int_eh_sjlj_setjmp_nofp:
739  return 20;
740  case ARM::tInt_eh_sjlj_setjmp:
741  case ARM::t2Int_eh_sjlj_setjmp:
742  case ARM::t2Int_eh_sjlj_setjmp_nofp:
743  return 12;
744  case ARM::SPACE:
745  return MI.getOperand(1).getImm();
746  case ARM::INLINEASM:
747  case ARM::INLINEASM_BR: {
748  // If this machine instr is an inline asm, measure it.
749  unsigned Size = getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
750  if (!MF->getInfo<ARMFunctionInfo>()->isThumbFunction())
751  Size = alignTo(Size, 4);
752  return Size;
753  }
754  }
755 }
756 
757 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
758  unsigned Size = 0;
761  while (++I != E && I->isInsideBundle()) {
762  assert(!I->isBundle() && "No nested bundle!");
763  Size += getInstSizeInBytes(*I);
764  }
765  return Size;
766 }
767 
770  unsigned DestReg, bool KillSrc,
771  const ARMSubtarget &Subtarget) const {
772  unsigned Opc = Subtarget.isThumb()
773  ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
774  : ARM::MRS;
775 
776  MachineInstrBuilder MIB =
777  BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
778 
779  // There is only 1 A/R class MRS instruction, and it always refers to
780  // APSR. However, there are lots of other possibilities on M-class cores.
781  if (Subtarget.isMClass())
782  MIB.addImm(0x800);
783 
784  MIB.add(predOps(ARMCC::AL))
785  .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
786 }
787 
790  unsigned SrcReg, bool KillSrc,
791  const ARMSubtarget &Subtarget) const {
792  unsigned Opc = Subtarget.isThumb()
793  ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
794  : ARM::MSR;
795 
796  MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
797 
798  if (Subtarget.isMClass())
799  MIB.addImm(0x800);
800  else
801  MIB.addImm(8);
802 
803  MIB.addReg(SrcReg, getKillRegState(KillSrc))
806 }
807 
809  MIB.addImm(ARMVCC::None);
810  MIB.addReg(0);
811 }
812 
814  unsigned DestReg) {
816  MIB.addReg(DestReg, RegState::Undef);
817 }
818 
820  MIB.addImm(Cond);
821  MIB.addReg(ARM::VPR, RegState::Implicit);
822 }
823 
825  unsigned Cond, unsigned Inactive) {
826  addPredicatedMveVpredNOp(MIB, Cond);
827  MIB.addReg(Inactive);
828 }
829 
832  const DebugLoc &DL, unsigned DestReg,
833  unsigned SrcReg, bool KillSrc) const {
834  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
835  bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
836 
837  if (GPRDest && GPRSrc) {
838  BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
839  .addReg(SrcReg, getKillRegState(KillSrc))
841  .add(condCodeOp());
842  return;
843  }
844 
845  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
846  bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
847 
848  unsigned Opc = 0;
849  if (SPRDest && SPRSrc)
850  Opc = ARM::VMOVS;
851  else if (GPRDest && SPRSrc)
852  Opc = ARM::VMOVRS;
853  else if (SPRDest && GPRSrc)
854  Opc = ARM::VMOVSR;
855  else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64())
856  Opc = ARM::VMOVD;
857  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
858  Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR;
859 
860  if (Opc) {
861  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
862  MIB.addReg(SrcReg, getKillRegState(KillSrc));
863  if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR)
864  MIB.addReg(SrcReg, getKillRegState(KillSrc));
865  if (Opc == ARM::MVE_VORR)
866  addUnpredicatedMveVpredROp(MIB, DestReg);
867  else
868  MIB.add(predOps(ARMCC::AL));
869  return;
870  }
871 
872  // Handle register classes that require multiple instructions.
873  unsigned BeginIdx = 0;
874  unsigned SubRegs = 0;
875  int Spacing = 1;
876 
877  // Use VORRq when possible.
878  if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
879  Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR;
880  BeginIdx = ARM::qsub_0;
881  SubRegs = 2;
882  } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
883  Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR;
884  BeginIdx = ARM::qsub_0;
885  SubRegs = 4;
886  // Fall back to VMOVD.
887  } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
888  Opc = ARM::VMOVD;
889  BeginIdx = ARM::dsub_0;
890  SubRegs = 2;
891  } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
892  Opc = ARM::VMOVD;
893  BeginIdx = ARM::dsub_0;
894  SubRegs = 3;
895  } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
896  Opc = ARM::VMOVD;
897  BeginIdx = ARM::dsub_0;
898  SubRegs = 4;
899  } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
900  Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
901  BeginIdx = ARM::gsub_0;
902  SubRegs = 2;
903  } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
904  Opc = ARM::VMOVD;
905  BeginIdx = ARM::dsub_0;
906  SubRegs = 2;
907  Spacing = 2;
908  } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
909  Opc = ARM::VMOVD;
910  BeginIdx = ARM::dsub_0;
911  SubRegs = 3;
912  Spacing = 2;
913  } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
914  Opc = ARM::VMOVD;
915  BeginIdx = ARM::dsub_0;
916  SubRegs = 4;
917  Spacing = 2;
918  } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) &&
919  !Subtarget.hasFP64()) {
920  Opc = ARM::VMOVS;
921  BeginIdx = ARM::ssub_0;
922  SubRegs = 2;
923  } else if (SrcReg == ARM::CPSR) {
924  copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
925  return;
926  } else if (DestReg == ARM::CPSR) {
927  copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
928  return;
929  } else if (DestReg == ARM::VPR) {
930  assert(ARM::GPRRegClass.contains(SrcReg));
931  BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
932  .addReg(SrcReg, getKillRegState(KillSrc))
933  .add(predOps(ARMCC::AL));
934  return;
935  } else if (SrcReg == ARM::VPR) {
936  assert(ARM::GPRRegClass.contains(DestReg));
937  BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
938  .addReg(SrcReg, getKillRegState(KillSrc))
939  .add(predOps(ARMCC::AL));
940  return;
941  } else if (DestReg == ARM::FPSCR_NZCV) {
942  assert(ARM::GPRRegClass.contains(SrcReg));
943  BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
944  .addReg(SrcReg, getKillRegState(KillSrc))
945  .add(predOps(ARMCC::AL));
946  return;
947  } else if (SrcReg == ARM::FPSCR_NZCV) {
948  assert(ARM::GPRRegClass.contains(DestReg));
949  BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
950  .addReg(SrcReg, getKillRegState(KillSrc))
951  .add(predOps(ARMCC::AL));
952  return;
953  }
954 
955  assert(Opc && "Impossible reg-to-reg copy");
956 
959 
960  // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
961  if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
962  BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
963  Spacing = -Spacing;
964  }
965 #ifndef NDEBUG
966  SmallSet<unsigned, 4> DstRegs;
967 #endif
968  for (unsigned i = 0; i != SubRegs; ++i) {
969  Register Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
970  Register Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
971  assert(Dst && Src && "Bad sub-register");
972 #ifndef NDEBUG
973  assert(!DstRegs.count(Src) && "destructive vector copy");
974  DstRegs.insert(Dst);
975 #endif
976  Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
977  // VORR (NEON or MVE) takes two source operands.
978  if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) {
979  Mov.addReg(Src);
980  }
981  // MVE VORR takes predicate operands in place of an ordinary condition.
982  if (Opc == ARM::MVE_VORR)
983  addUnpredicatedMveVpredROp(Mov, Dst);
984  else
985  Mov = Mov.add(predOps(ARMCC::AL));
986  // MOVr can set CC.
987  if (Opc == ARM::MOVr)
988  Mov = Mov.add(condCodeOp());
989  }
990  // Add implicit super-register defs and kills to the last instruction.
991  Mov->addRegisterDefined(DestReg, TRI);
992  if (KillSrc)
993  Mov->addRegisterKilled(SrcReg, TRI);
994 }
995 
997  const MachineOperand *&Src,
998  const MachineOperand *&Dest) const {
999  // VMOVRRD is also a copy instruction but it requires
1000  // special way of handling. It is more complex copy version
1001  // and since that we are not considering it. For recognition
1002  // of such instruction isExtractSubregLike MI interface fuction
1003  // could be used.
1004  // VORRq is considered as a move only if two inputs are
1005  // the same register.
1006  if (!MI.isMoveReg() ||
1007  (MI.getOpcode() == ARM::VORRq &&
1008  MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1009  return false;
1010  Dest = &MI.getOperand(0);
1011  Src = &MI.getOperand(1);
1012  return true;
1013 }
1014 
1015 const MachineInstrBuilder &
1017  unsigned SubIdx, unsigned State,
1018  const TargetRegisterInfo *TRI) const {
1019  if (!SubIdx)
1020  return MIB.addReg(Reg, State);
1021 
1023  return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1024  return MIB.addReg(Reg, State, SubIdx);
1025 }
1026 
1027 void ARMBaseInstrInfo::
1029  unsigned SrcReg, bool isKill, int FI,
1030  const TargetRegisterClass *RC,
1031  const TargetRegisterInfo *TRI) const {
1032  MachineFunction &MF = *MBB.getParent();
1033  MachineFrameInfo &MFI = MF.getFrameInfo();
1034  unsigned Align = MFI.getObjectAlignment(FI);
1035 
1038  MFI.getObjectSize(FI), Align);
1039 
1040  switch (TRI->getSpillSize(*RC)) {
1041  case 2:
1042  if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1043  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
1044  .addReg(SrcReg, getKillRegState(isKill))
1045  .addFrameIndex(FI)
1046  .addImm(0)
1047  .addMemOperand(MMO)
1048  .add(predOps(ARMCC::AL));
1049  } else
1050  llvm_unreachable("Unknown reg class!");
1051  break;
1052  case 4:
1053  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1054  BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
1055  .addReg(SrcReg, getKillRegState(isKill))
1056  .addFrameIndex(FI)
1057  .addImm(0)
1058  .addMemOperand(MMO)
1059  .add(predOps(ARMCC::AL));
1060  } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1061  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
1062  .addReg(SrcReg, getKillRegState(isKill))
1063  .addFrameIndex(FI)
1064  .addImm(0)
1065  .addMemOperand(MMO)
1066  .add(predOps(ARMCC::AL));
1067  } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
1068  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off))
1069  .addReg(SrcReg, getKillRegState(isKill))
1070  .addFrameIndex(FI)
1071  .addImm(0)
1072  .addMemOperand(MMO)
1073  .add(predOps(ARMCC::AL));
1074  } else
1075  llvm_unreachable("Unknown reg class!");
1076  break;
1077  case 8:
1078  if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1079  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
1080  .addReg(SrcReg, getKillRegState(isKill))
1081  .addFrameIndex(FI)
1082  .addImm(0)
1083  .addMemOperand(MMO)
1084  .add(predOps(ARMCC::AL));
1085  } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1086  if (Subtarget.hasV5TEOps()) {
1087  MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
1088  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1089  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1090  MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1091  .add(predOps(ARMCC::AL));
1092  } else {
1093  // Fallback to STM instruction, which has existed since the dawn of
1094  // time.
1095  MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
1096  .addFrameIndex(FI)
1097  .addMemOperand(MMO)
1098  .add(predOps(ARMCC::AL));
1099  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1100  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1101  }
1102  } else
1103  llvm_unreachable("Unknown reg class!");
1104  break;
1105  case 16:
1106  if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
1107  // Use aligned spills if the stack can be realigned.
1108  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1109  BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
1110  .addFrameIndex(FI)
1111  .addImm(16)
1112  .addReg(SrcReg, getKillRegState(isKill))
1113  .addMemOperand(MMO)
1114  .add(predOps(ARMCC::AL));
1115  } else {
1116  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
1117  .addReg(SrcReg, getKillRegState(isKill))
1118  .addFrameIndex(FI)
1119  .addMemOperand(MMO)
1120  .add(predOps(ARMCC::AL));
1121  }
1122  } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
1123  Subtarget.hasMVEIntegerOps()) {
1124  auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
1125  MIB.addReg(SrcReg, getKillRegState(isKill))
1126  .addFrameIndex(FI)
1127  .addImm(0)
1128  .addMemOperand(MMO);
1130  } else
1131  llvm_unreachable("Unknown reg class!");
1132  break;
1133  case 24:
1134  if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1135  // Use aligned spills if the stack can be realigned.
1136  if (Align >= 16 && getRegisterInfo().canRealignStack(MF) &&
1137  Subtarget.hasNEON()) {
1138  BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
1139  .addFrameIndex(FI)
1140  .addImm(16)
1141  .addReg(SrcReg, getKillRegState(isKill))
1142  .addMemOperand(MMO)
1143  .add(predOps(ARMCC::AL));
1144  } else {
1145  MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1146  get(ARM::VSTMDIA))
1147  .addFrameIndex(FI)
1148  .add(predOps(ARMCC::AL))
1149  .addMemOperand(MMO);
1150  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1151  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1152  AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1153  }
1154  } else
1155  llvm_unreachable("Unknown reg class!");
1156  break;
1157  case 32:
1158  if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1159  if (Align >= 16 && getRegisterInfo().canRealignStack(MF) &&
1160  Subtarget.hasNEON()) {
1161  // FIXME: It's possible to only store part of the QQ register if the
1162  // spilled def has a sub-register index.
1163  BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
1164  .addFrameIndex(FI)
1165  .addImm(16)
1166  .addReg(SrcReg, getKillRegState(isKill))
1167  .addMemOperand(MMO)
1168  .add(predOps(ARMCC::AL));
1169  } else {
1170  MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1171  get(ARM::VSTMDIA))
1172  .addFrameIndex(FI)
1173  .add(predOps(ARMCC::AL))
1174  .addMemOperand(MMO);
1175  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1176  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1177  MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1178  AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1179  }
1180  } else
1181  llvm_unreachable("Unknown reg class!");
1182  break;
1183  case 64:
1184  if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1185  MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
1186  .addFrameIndex(FI)
1187  .add(predOps(ARMCC::AL))
1188  .addMemOperand(MMO);
1189  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1190  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1191  MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1192  MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1193  MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1194  MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1195  MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1196  AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1197  } else
1198  llvm_unreachable("Unknown reg class!");
1199  break;
1200  default:
1201  llvm_unreachable("Unknown reg class!");
1202  }
1203 }
1204 
1206  int &FrameIndex) const {
1207  switch (MI.getOpcode()) {
1208  default: break;
1209  case ARM::STRrs:
1210  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1211  if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1212  MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1213  MI.getOperand(3).getImm() == 0) {
1214  FrameIndex = MI.getOperand(1).getIndex();
1215  return MI.getOperand(0).getReg();
1216  }
1217  break;
1218  case ARM::STRi12:
1219  case ARM::t2STRi12:
1220  case ARM::tSTRspi:
1221  case ARM::VSTRD:
1222  case ARM::VSTRS:
1223  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1224  MI.getOperand(2).getImm() == 0) {
1225  FrameIndex = MI.getOperand(1).getIndex();
1226  return MI.getOperand(0).getReg();
1227  }
1228  break;
1229  case ARM::VSTR_P0_off:
1230  if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
1231  MI.getOperand(1).getImm() == 0) {
1232  FrameIndex = MI.getOperand(0).getIndex();
1233  return ARM::P0;
1234  }
1235  break;
1236  case ARM::VST1q64:
1237  case ARM::VST1d64TPseudo:
1238  case ARM::VST1d64QPseudo:
1239  if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1240  FrameIndex = MI.getOperand(0).getIndex();
1241  return MI.getOperand(2).getReg();
1242  }
1243  break;
1244  case ARM::VSTMQIA:
1245  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1246  FrameIndex = MI.getOperand(1).getIndex();
1247  return MI.getOperand(0).getReg();
1248  }
1249  break;
1250  }
1251 
1252  return 0;
1253 }
1254 
1256  int &FrameIndex) const {
1258  if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses) &&
1259  Accesses.size() == 1) {
1260  FrameIndex =
1261  cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
1262  ->getFrameIndex();
1263  return true;
1264  }
1265  return false;
1266 }
1267 
1268 void ARMBaseInstrInfo::
1270  unsigned DestReg, int FI,
1271  const TargetRegisterClass *RC,
1272  const TargetRegisterInfo *TRI) const {
1273  DebugLoc DL;
1274  if (I != MBB.end()) DL = I->getDebugLoc();
1275  MachineFunction &MF = *MBB.getParent();
1276  MachineFrameInfo &MFI = MF.getFrameInfo();
1277  unsigned Align = MFI.getObjectAlignment(FI);
1280  MFI.getObjectSize(FI), Align);
1281 
1282  switch (TRI->getSpillSize(*RC)) {
1283  case 2:
1284  if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1285  BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg)
1286  .addFrameIndex(FI)
1287  .addImm(0)
1288  .addMemOperand(MMO)
1289  .add(predOps(ARMCC::AL));
1290  } else
1291  llvm_unreachable("Unknown reg class!");
1292  break;
1293  case 4:
1294  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1295  BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1296  .addFrameIndex(FI)
1297  .addImm(0)
1298  .addMemOperand(MMO)
1299  .add(predOps(ARMCC::AL));
1300  } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1301  BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1302  .addFrameIndex(FI)
1303  .addImm(0)
1304  .addMemOperand(MMO)
1305  .add(predOps(ARMCC::AL));
1306  } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
1307  BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg)
1308  .addFrameIndex(FI)
1309  .addImm(0)
1310  .addMemOperand(MMO)
1311  .add(predOps(ARMCC::AL));
1312  } else
1313  llvm_unreachable("Unknown reg class!");
1314  break;
1315  case 8:
1316  if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1317  BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1318  .addFrameIndex(FI)
1319  .addImm(0)
1320  .addMemOperand(MMO)
1321  .add(predOps(ARMCC::AL));
1322  } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1323  MachineInstrBuilder MIB;
1324 
1325  if (Subtarget.hasV5TEOps()) {
1326  MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1327  AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1328  AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1329  MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1330  .add(predOps(ARMCC::AL));
1331  } else {
1332  // Fallback to LDM instruction, which has existed since the dawn of
1333  // time.
1334  MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1335  .addFrameIndex(FI)
1336  .addMemOperand(MMO)
1337  .add(predOps(ARMCC::AL));
1338  MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1339  MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1340  }
1341 
1342  if (Register::isPhysicalRegister(DestReg))
1343  MIB.addReg(DestReg, RegState::ImplicitDefine);
1344  } else
1345  llvm_unreachable("Unknown reg class!");
1346  break;
1347  case 16:
1348  if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
1349  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1350  BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1351  .addFrameIndex(FI)
1352  .addImm(16)
1353  .addMemOperand(MMO)
1354  .add(predOps(ARMCC::AL));
1355  } else {
1356  BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1357  .addFrameIndex(FI)
1358  .addMemOperand(MMO)
1359  .add(predOps(ARMCC::AL));
1360  }
1361  } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
1362  Subtarget.hasMVEIntegerOps()) {
1363  auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg);
1364  MIB.addFrameIndex(FI)
1365  .addImm(0)
1366  .addMemOperand(MMO);
1368  } else
1369  llvm_unreachable("Unknown reg class!");
1370  break;
1371  case 24:
1372  if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1373  if (Align >= 16 && getRegisterInfo().canRealignStack(MF) &&
1374  Subtarget.hasNEON()) {
1375  BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1376  .addFrameIndex(FI)
1377  .addImm(16)
1378  .addMemOperand(MMO)
1379  .add(predOps(ARMCC::AL));
1380  } else {
1381  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1382  .addFrameIndex(FI)
1383  .addMemOperand(MMO)
1384  .add(predOps(ARMCC::AL));
1385  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1386  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1387  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1388  if (Register::isPhysicalRegister(DestReg))
1389  MIB.addReg(DestReg, RegState::ImplicitDefine);
1390  }
1391  } else
1392  llvm_unreachable("Unknown reg class!");
1393  break;
1394  case 32:
1395  if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1396  if (Align >= 16 && getRegisterInfo().canRealignStack(MF) &&
1397  Subtarget.hasNEON()) {
1398  BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1399  .addFrameIndex(FI)
1400  .addImm(16)
1401  .addMemOperand(MMO)
1402  .add(predOps(ARMCC::AL));
1403  } else {
1404  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1405  .addFrameIndex(FI)
1406  .add(predOps(ARMCC::AL))
1407  .addMemOperand(MMO);
1408  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1409  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1410  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1411  MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1412  if (Register::isPhysicalRegister(DestReg))
1413  MIB.addReg(DestReg, RegState::ImplicitDefine);
1414  }
1415  } else
1416  llvm_unreachable("Unknown reg class!");
1417  break;
1418  case 64:
1419  if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1420  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1421  .addFrameIndex(FI)
1422  .add(predOps(ARMCC::AL))
1423  .addMemOperand(MMO);
1424  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1425  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1426  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1427  MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1428  MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1429  MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1430  MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1431  MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1432  if (Register::isPhysicalRegister(DestReg))
1433  MIB.addReg(DestReg, RegState::ImplicitDefine);
1434  } else
1435  llvm_unreachable("Unknown reg class!");
1436  break;
1437  default:
1438  llvm_unreachable("Unknown regclass!");
1439  }
1440 }
1441 
1443  int &FrameIndex) const {
1444  switch (MI.getOpcode()) {
1445  default: break;
1446  case ARM::LDRrs:
1447  case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1448  if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1449  MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1450  MI.getOperand(3).getImm() == 0) {
1451  FrameIndex = MI.getOperand(1).getIndex();
1452  return MI.getOperand(0).getReg();
1453  }
1454  break;
1455  case ARM::LDRi12:
1456  case ARM::t2LDRi12:
1457  case ARM::tLDRspi:
1458  case ARM::VLDRD:
1459  case ARM::VLDRS:
1460  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1461  MI.getOperand(2).getImm() == 0) {
1462  FrameIndex = MI.getOperand(1).getIndex();
1463  return MI.getOperand(0).getReg();
1464  }
1465  break;
1466  case ARM::VLDR_P0_off:
1467  if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
1468  MI.getOperand(1).getImm() == 0) {
1469  FrameIndex = MI.getOperand(0).getIndex();
1470  return ARM::P0;
1471  }
1472  break;
1473  case ARM::VLD1q64:
1474  case ARM::VLD1d8TPseudo:
1475  case ARM::VLD1d16TPseudo:
1476  case ARM::VLD1d32TPseudo:
1477  case ARM::VLD1d64TPseudo:
1478  case ARM::VLD1d8QPseudo:
1479  case ARM::VLD1d16QPseudo:
1480  case ARM::VLD1d32QPseudo:
1481  case ARM::VLD1d64QPseudo:
1482  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1483  FrameIndex = MI.getOperand(1).getIndex();
1484  return MI.getOperand(0).getReg();
1485  }
1486  break;
1487  case ARM::VLDMQIA:
1488  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1489  FrameIndex = MI.getOperand(1).getIndex();
1490  return MI.getOperand(0).getReg();
1491  }
1492  break;
1493  }
1494 
1495  return 0;
1496 }
1497 
1499  int &FrameIndex) const {
1501  if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses) &&
1502  Accesses.size() == 1) {
1503  FrameIndex =
1504  cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
1505  ->getFrameIndex();
1506  return true;
1507  }
1508  return false;
1509 }
1510 
1511 /// Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1512 /// depending on whether the result is used.
1513 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1514  bool isThumb1 = Subtarget.isThumb1Only();
1515  bool isThumb2 = Subtarget.isThumb2();
1516  const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1517 
1518  DebugLoc dl = MI->getDebugLoc();
1519  MachineBasicBlock *BB = MI->getParent();
1520 
1521  MachineInstrBuilder LDM, STM;
1522  if (isThumb1 || !MI->getOperand(1).isDead()) {
1523  MachineOperand LDWb(MI->getOperand(1));
1524  LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1525  : isThumb1 ? ARM::tLDMIA_UPD
1526  : ARM::LDMIA_UPD))
1527  .add(LDWb);
1528  } else {
1529  LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1530  }
1531 
1532  if (isThumb1 || !MI->getOperand(0).isDead()) {
1533  MachineOperand STWb(MI->getOperand(0));
1534  STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1535  : isThumb1 ? ARM::tSTMIA_UPD
1536  : ARM::STMIA_UPD))
1537  .add(STWb);
1538  } else {
1539  STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1540  }
1541 
1542  MachineOperand LDBase(MI->getOperand(3));
1543  LDM.add(LDBase).add(predOps(ARMCC::AL));
1544 
1545  MachineOperand STBase(MI->getOperand(2));
1546  STM.add(STBase).add(predOps(ARMCC::AL));
1547 
1548  // Sort the scratch registers into ascending order.
1550  SmallVector<unsigned, 6> ScratchRegs;
1551  for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1552  ScratchRegs.push_back(MI->getOperand(I).getReg());
1553  llvm::sort(ScratchRegs,
1554  [&TRI](const unsigned &Reg1, const unsigned &Reg2) -> bool {
1555  return TRI.getEncodingValue(Reg1) <
1556  TRI.getEncodingValue(Reg2);
1557  });
1558 
1559  for (const auto &Reg : ScratchRegs) {
1560  LDM.addReg(Reg, RegState::Define);
1561  STM.addReg(Reg, RegState::Kill);
1562  }
1563 
1564  BB->erase(MI);
1565 }
1566 
1568  if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1569  assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1570  "LOAD_STACK_GUARD currently supported only for MachO.");
1571  expandLoadStackGuard(MI);
1572  MI.getParent()->erase(MI);
1573  return true;
1574  }
1575 
1576  if (MI.getOpcode() == ARM::MEMCPY) {
1577  expandMEMCPY(MI);
1578  return true;
1579  }
1580 
1581  // This hook gets to expand COPY instructions before they become
1582  // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1583  // widened to VMOVD. We prefer the VMOVD when possible because it may be
1584  // changed into a VORR that can go down the NEON pipeline.
1585  if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || !Subtarget.hasFP64())
1586  return false;
1587 
1588  // Look for a copy between even S-registers. That is where we keep floats
1589  // when using NEON v2f32 instructions for f32 arithmetic.
1590  Register DstRegS = MI.getOperand(0).getReg();
1591  Register SrcRegS = MI.getOperand(1).getReg();
1592  if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1593  return false;
1594 
1596  unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1597  &ARM::DPRRegClass);
1598  unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1599  &ARM::DPRRegClass);
1600  if (!DstRegD || !SrcRegD)
1601  return false;
1602 
1603  // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1604  // legal if the COPY already defines the full DstRegD, and it isn't a
1605  // sub-register insertion.
1606  if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
1607  return false;
1608 
1609  // A dead copy shouldn't show up here, but reject it just in case.
1610  if (MI.getOperand(0).isDead())
1611  return false;
1612 
1613  // All clear, widen the COPY.
1614  LLVM_DEBUG(dbgs() << "widening: " << MI);
1615  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1616 
1617  // Get rid of the old implicit-def of DstRegD. Leave it if it defines a Q-reg
1618  // or some other super-register.
1619  int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD);
1620  if (ImpDefIdx != -1)
1621  MI.RemoveOperand(ImpDefIdx);
1622 
1623  // Change the opcode and operands.
1624  MI.setDesc(get(ARM::VMOVD));
1625  MI.getOperand(0).setReg(DstRegD);
1626  MI.getOperand(1).setReg(SrcRegD);
1627  MIB.add(predOps(ARMCC::AL));
1628 
1629  // We are now reading SrcRegD instead of SrcRegS. This may upset the
1630  // register scavenger and machine verifier, so we need to indicate that we
1631  // are reading an undefined value from SrcRegD, but a proper value from
1632  // SrcRegS.
1633  MI.getOperand(1).setIsUndef();
1634  MIB.addReg(SrcRegS, RegState::Implicit);
1635 
1636  // SrcRegD may actually contain an unrelated value in the ssub_1
1637  // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1638  if (MI.getOperand(1).isKill()) {
1639  MI.getOperand(1).setIsKill(false);
1640  MI.addRegisterKilled(SrcRegS, TRI, true);
1641  }
1642 
1643  LLVM_DEBUG(dbgs() << "replaced by: " << MI);
1644  return true;
1645 }
1646 
1647 /// Create a copy of a const pool value. Update CPI to the new index and return
1648 /// the label UID.
1649 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1652 
1653  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1654  assert(MCPE.isMachineConstantPoolEntry() &&
1655  "Expecting a machine constantpool entry!");
1656  ARMConstantPoolValue *ACPV =
1657  static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1658 
1659  unsigned PCLabelId = AFI->createPICLabelUId();
1660  ARMConstantPoolValue *NewCPV = nullptr;
1661 
1662  // FIXME: The below assumes PIC relocation model and that the function
1663  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1664  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1665  // instructions, so that's probably OK, but is PIC always correct when
1666  // we get here?
1667  if (ACPV->isGlobalValue())
1669  cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1670  4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1671  else if (ACPV->isExtSymbol())
1672  NewCPV = ARMConstantPoolSymbol::
1673  Create(MF.getFunction().getContext(),
1674  cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1675  else if (ACPV->isBlockAddress())
1676  NewCPV = ARMConstantPoolConstant::
1677  Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1679  else if (ACPV->isLSDA())
1680  NewCPV = ARMConstantPoolConstant::Create(&MF.getFunction(), PCLabelId,
1681  ARMCP::CPLSDA, 4);
1682  else if (ACPV->isMachineBasicBlock())
1683  NewCPV = ARMConstantPoolMBB::
1684  Create(MF.getFunction().getContext(),
1685  cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1686  else
1687  llvm_unreachable("Unexpected ARM constantpool value type!!");
1688  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1689  return PCLabelId;
1690 }
1691 
1694  unsigned DestReg, unsigned SubIdx,
1695  const MachineInstr &Orig,
1696  const TargetRegisterInfo &TRI) const {
1697  unsigned Opcode = Orig.getOpcode();
1698  switch (Opcode) {
1699  default: {
1700  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1701  MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1702  MBB.insert(I, MI);
1703  break;
1704  }
1705  case ARM::tLDRpci_pic:
1706  case ARM::t2LDRpci_pic: {
1707  MachineFunction &MF = *MBB.getParent();
1708  unsigned CPI = Orig.getOperand(1).getIndex();
1709  unsigned PCLabelId = duplicateCPV(MF, CPI);
1710  BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
1711  .addConstantPoolIndex(CPI)
1712  .addImm(PCLabelId)
1713  .cloneMemRefs(Orig);
1714  break;
1715  }
1716  }
1717 }
1718 
1719 MachineInstr &
1721  MachineBasicBlock::iterator InsertBefore,
1722  const MachineInstr &Orig) const {
1723  MachineInstr &Cloned = TargetInstrInfo::duplicate(MBB, InsertBefore, Orig);
1725  for (;;) {
1726  switch (I->getOpcode()) {
1727  case ARM::tLDRpci_pic:
1728  case ARM::t2LDRpci_pic: {
1729  MachineFunction &MF = *MBB.getParent();
1730  unsigned CPI = I->getOperand(1).getIndex();
1731  unsigned PCLabelId = duplicateCPV(MF, CPI);
1732  I->getOperand(1).setIndex(CPI);
1733  I->getOperand(2).setImm(PCLabelId);
1734  break;
1735  }
1736  }
1737  if (!I->isBundledWithSucc())
1738  break;
1739  ++I;
1740  }
1741  return Cloned;
1742 }
1743 
1745  const MachineInstr &MI1,
1746  const MachineRegisterInfo *MRI) const {
1747  unsigned Opcode = MI0.getOpcode();
1748  if (Opcode == ARM::t2LDRpci ||
1749  Opcode == ARM::t2LDRpci_pic ||
1750  Opcode == ARM::tLDRpci ||
1751  Opcode == ARM::tLDRpci_pic ||
1752  Opcode == ARM::LDRLIT_ga_pcrel ||
1753  Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1754  Opcode == ARM::tLDRLIT_ga_pcrel ||
1755  Opcode == ARM::MOV_ga_pcrel ||
1756  Opcode == ARM::MOV_ga_pcrel_ldr ||
1757  Opcode == ARM::t2MOV_ga_pcrel) {
1758  if (MI1.getOpcode() != Opcode)
1759  return false;
1760  if (MI0.getNumOperands() != MI1.getNumOperands())
1761  return false;
1762 
1763  const MachineOperand &MO0 = MI0.getOperand(1);
1764  const MachineOperand &MO1 = MI1.getOperand(1);
1765  if (MO0.getOffset() != MO1.getOffset())
1766  return false;
1767 
1768  if (Opcode == ARM::LDRLIT_ga_pcrel ||
1769  Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1770  Opcode == ARM::tLDRLIT_ga_pcrel ||
1771  Opcode == ARM::MOV_ga_pcrel ||
1772  Opcode == ARM::MOV_ga_pcrel_ldr ||
1773  Opcode == ARM::t2MOV_ga_pcrel)
1774  // Ignore the PC labels.
1775  return MO0.getGlobal() == MO1.getGlobal();
1776 
1777  const MachineFunction *MF = MI0.getParent()->getParent();
1778  const MachineConstantPool *MCP = MF->getConstantPool();
1779  int CPI0 = MO0.getIndex();
1780  int CPI1 = MO1.getIndex();
1781  const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1782  const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1783  bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1784  bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1785  if (isARMCP0 && isARMCP1) {
1786  ARMConstantPoolValue *ACPV0 =
1787  static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1788  ARMConstantPoolValue *ACPV1 =
1789  static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1790  return ACPV0->hasSameValue(ACPV1);
1791  } else if (!isARMCP0 && !isARMCP1) {
1792  return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1793  }
1794  return false;
1795  } else if (Opcode == ARM::PICLDR) {
1796  if (MI1.getOpcode() != Opcode)
1797  return false;
1798  if (MI0.getNumOperands() != MI1.getNumOperands())
1799  return false;
1800 
1801  Register Addr0 = MI0.getOperand(1).getReg();
1802  Register Addr1 = MI1.getOperand(1).getReg();
1803  if (Addr0 != Addr1) {
1804  if (!MRI || !Register::isVirtualRegister(Addr0) ||
1806  return false;
1807 
1808  // This assumes SSA form.
1809  MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1810  MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1811  // Check if the loaded value, e.g. a constantpool of a global address, are
1812  // the same.
1813  if (!produceSameValue(*Def0, *Def1, MRI))
1814  return false;
1815  }
1816 
1817  for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
1818  // %12 = PICLDR %11, 0, 14, %noreg
1819  const MachineOperand &MO0 = MI0.getOperand(i);
1820  const MachineOperand &MO1 = MI1.getOperand(i);
1821  if (!MO0.isIdenticalTo(MO1))
1822  return false;
1823  }
1824  return true;
1825  }
1826 
1828 }
1829 
1830 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1831 /// determine if two loads are loading from the same base address. It should
1832 /// only return true if the base pointers are the same and the only differences
1833 /// between the two addresses is the offset. It also returns the offsets by
1834 /// reference.
1835 ///
1836 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1837 /// is permanently disabled.
1839  int64_t &Offset1,
1840  int64_t &Offset2) const {
1841  // Don't worry about Thumb: just ARM and Thumb2.
1842  if (Subtarget.isThumb1Only()) return false;
1843 
1844  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1845  return false;
1846 
1847  switch (Load1->getMachineOpcode()) {
1848  default:
1849  return false;
1850  case ARM::LDRi12:
1851  case ARM::LDRBi12:
1852  case ARM::LDRD:
1853  case ARM::LDRH:
1854  case ARM::LDRSB:
1855  case ARM::LDRSH:
1856  case ARM::VLDRD:
1857  case ARM::VLDRS:
1858  case ARM::t2LDRi8:
1859  case ARM::t2LDRBi8:
1860  case ARM::t2LDRDi8:
1861  case ARM::t2LDRSHi8:
1862  case ARM::t2LDRi12:
1863  case ARM::t2LDRBi12:
1864  case ARM::t2LDRSHi12:
1865  break;
1866  }
1867 
1868  switch (Load2->getMachineOpcode()) {
1869  default:
1870  return false;
1871  case ARM::LDRi12:
1872  case ARM::LDRBi12:
1873  case ARM::LDRD:
1874  case ARM::LDRH:
1875  case ARM::LDRSB:
1876  case ARM::LDRSH:
1877  case ARM::VLDRD:
1878  case ARM::VLDRS:
1879  case ARM::t2LDRi8:
1880  case ARM::t2LDRBi8:
1881  case ARM::t2LDRSHi8:
1882  case ARM::t2LDRi12:
1883  case ARM::t2LDRBi12:
1884  case ARM::t2LDRSHi12:
1885  break;
1886  }
1887 
1888  // Check if base addresses and chain operands match.
1889  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1890  Load1->getOperand(4) != Load2->getOperand(4))
1891  return false;
1892 
1893  // Index should be Reg0.
1894  if (Load1->getOperand(3) != Load2->getOperand(3))
1895  return false;
1896 
1897  // Determine the offsets.
1898  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1899  isa<ConstantSDNode>(Load2->getOperand(1))) {
1900  Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1901  Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1902  return true;
1903  }
1904 
1905  return false;
1906 }
1907 
1908 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1909 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1910 /// be scheduled togther. On some targets if two loads are loading from
1911 /// addresses in the same cache line, it's better if they are scheduled
1912 /// together. This function takes two integers that represent the load offsets
1913 /// from the common base address. It returns true if it decides it's desirable
1914 /// to schedule the two loads together. "NumLoads" is the number of loads that
1915 /// have already been scheduled after Load1.
1916 ///
1917 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1918 /// is permanently disabled.
1920  int64_t Offset1, int64_t Offset2,
1921  unsigned NumLoads) const {
1922  // Don't worry about Thumb: just ARM and Thumb2.
1923  if (Subtarget.isThumb1Only()) return false;
1924 
1925  assert(Offset2 > Offset1);
1926 
1927  if ((Offset2 - Offset1) / 8 > 64)
1928  return false;
1929 
1930  // Check if the machine opcodes are different. If they are different
1931  // then we consider them to not be of the same base address,
1932  // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1933  // In this case, they are considered to be the same because they are different
1934  // encoding forms of the same basic instruction.
1935  if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1936  !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1937  Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1938  (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1939  Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1940  return false; // FIXME: overly conservative?
1941 
1942  // Four loads in a row should be sufficient.
1943  if (NumLoads >= 3)
1944  return false;
1945 
1946  return true;
1947 }
1948 
1950  const MachineBasicBlock *MBB,
1951  const MachineFunction &MF) const {
1952  // Debug info is never a scheduling boundary. It's necessary to be explicit
1953  // due to the special treatment of IT instructions below, otherwise a
1954  // dbg_value followed by an IT will result in the IT instruction being
1955  // considered a scheduling hazard, which is wrong. It should be the actual
1956  // instruction preceding the dbg_value instruction(s), just like it is
1957  // when debug info is not present.
1958  if (MI.isDebugInstr())
1959  return false;
1960 
1961  // Terminators and labels can't be scheduled around.
1962  if (MI.isTerminator() || MI.isPosition())
1963  return true;
1964 
1965  // Treat the start of the IT block as a scheduling boundary, but schedule
1966  // t2IT along with all instructions following it.
1967  // FIXME: This is a big hammer. But the alternative is to add all potential
1968  // true and anti dependencies to IT block instructions as implicit operands
1969  // to the t2IT instruction. The added compile time and complexity does not
1970  // seem worth it.
1972  // Make sure to skip any debug instructions
1973  while (++I != MBB->end() && I->isDebugInstr())
1974  ;
1975  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1976  return true;
1977 
1978  // Don't attempt to schedule around any instruction that defines
1979  // a stack-oriented pointer, as it's unlikely to be profitable. This
1980  // saves compile time, because it doesn't require every single
1981  // stack slot reference to depend on the instruction that does the
1982  // modification.
1983  // Calls don't actually change the stack pointer, even if they have imp-defs.
1984  // No ARM calling conventions change the stack pointer. (X86 calling
1985  // conventions sometimes do).
1986  if (!MI.isCall() && MI.definesRegister(ARM::SP))
1987  return true;
1988 
1989  return false;
1990 }
1991 
1992 bool ARMBaseInstrInfo::
1994  unsigned NumCycles, unsigned ExtraPredCycles,
1995  BranchProbability Probability) const {
1996  if (!NumCycles)
1997  return false;
1998 
1999  // If we are optimizing for size, see if the branch in the predecessor can be
2000  // lowered to cbn?z by the constant island lowering pass, and return false if
2001  // so. This results in a shorter instruction sequence.
2002  if (MBB.getParent()->getFunction().hasOptSize()) {
2003  MachineBasicBlock *Pred = *MBB.pred_begin();
2004  if (!Pred->empty()) {
2005  MachineInstr *LastMI = &*Pred->rbegin();
2006  if (LastMI->getOpcode() == ARM::t2Bcc) {
2008  MachineInstr *CmpMI = findCMPToFoldIntoCBZ(LastMI, TRI);
2009  if (CmpMI)
2010  return false;
2011  }
2012  }
2013  }
2014  return isProfitableToIfCvt(MBB, NumCycles, ExtraPredCycles,
2015  MBB, 0, 0, Probability);
2016 }
2017 
2018 bool ARMBaseInstrInfo::
2020  unsigned TCycles, unsigned TExtra,
2021  MachineBasicBlock &FBB,
2022  unsigned FCycles, unsigned FExtra,
2023  BranchProbability Probability) const {
2024  if (!TCycles)
2025  return false;
2026 
2027  // In thumb code we often end up trading one branch for a IT block, and
2028  // if we are cloning the instruction can increase code size. Prevent
2029  // blocks with multiple predecesors from being ifcvted to prevent this
2030  // cloning.
2031  if (Subtarget.isThumb2() && TBB.getParent()->getFunction().hasMinSize()) {
2032  if (TBB.pred_size() != 1 || FBB.pred_size() != 1)
2033  return false;
2034  }
2035 
2036  // Attempt to estimate the relative costs of predication versus branching.
2037  // Here we scale up each component of UnpredCost to avoid precision issue when
2038  // scaling TCycles/FCycles by Probability.
2039  const unsigned ScalingUpFactor = 1024;
2040 
2041  unsigned PredCost = (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor;
2042  unsigned UnpredCost;
2043  if (!Subtarget.hasBranchPredictor()) {
2044  // When we don't have a branch predictor it's always cheaper to not take a
2045  // branch than take it, so we have to take that into account.
2046  unsigned NotTakenBranchCost = 1;
2047  unsigned TakenBranchCost = Subtarget.getMispredictionPenalty();
2048  unsigned TUnpredCycles, FUnpredCycles;
2049  if (!FCycles) {
2050  // Triangle: TBB is the fallthrough
2051  TUnpredCycles = TCycles + NotTakenBranchCost;
2052  FUnpredCycles = TakenBranchCost;
2053  } else {
2054  // Diamond: TBB is the block that is branched to, FBB is the fallthrough
2055  TUnpredCycles = TCycles + TakenBranchCost;
2056  FUnpredCycles = FCycles + NotTakenBranchCost;
2057  // The branch at the end of FBB will disappear when it's predicated, so
2058  // discount it from PredCost.
2059  PredCost -= 1 * ScalingUpFactor;
2060  }
2061  // The total cost is the cost of each path scaled by their probabilites
2062  unsigned TUnpredCost = Probability.scale(TUnpredCycles * ScalingUpFactor);
2063  unsigned FUnpredCost = Probability.getCompl().scale(FUnpredCycles * ScalingUpFactor);
2064  UnpredCost = TUnpredCost + FUnpredCost;
2065  // When predicating assume that the first IT can be folded away but later
2066  // ones cost one cycle each
2067  if (Subtarget.isThumb2() && TCycles + FCycles > 4) {
2068  PredCost += ((TCycles + FCycles - 4) / 4) * ScalingUpFactor;
2069  }
2070  } else {
2071  unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
2072  unsigned FUnpredCost =
2073  Probability.getCompl().scale(FCycles * ScalingUpFactor);
2074  UnpredCost = TUnpredCost + FUnpredCost;
2075  UnpredCost += 1 * ScalingUpFactor; // The branch itself
2076  UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
2077  }
2078 
2079  return PredCost <= UnpredCost;
2080 }
2081 
2082 unsigned
2084  unsigned NumInsts) const {
2085  // Thumb2 needs a 2-byte IT instruction to predicate up to 4 instructions.
2086  // ARM has a condition code field in every predicable instruction, using it
2087  // doesn't change code size.
2088  return Subtarget.isThumb2() ? divideCeil(NumInsts, 4) * 2 : 0;
2089 }
2090 
2091 unsigned
2093  // If this branch is likely to be folded into the comparison to form a
2094  // CB(N)Z, then removing it won't reduce code size at all, because that will
2095  // just replace the CB(N)Z with a CMP.
2096  if (MI.getOpcode() == ARM::t2Bcc &&
2098  return 0;
2099 
2100  unsigned Size = getInstSizeInBytes(MI);
2101 
2102  // For Thumb2, all branches are 32-bit instructions during the if conversion
2103  // pass, but may be replaced with 16-bit instructions during size reduction.
2104  // Since the branches considered by if conversion tend to be forward branches
2105  // over small basic blocks, they are very likely to be in range for the
2106  // narrow instructions, so we assume the final code size will be half what it
2107  // currently is.
2108  if (Subtarget.isThumb2())
2109  Size /= 2;
2110 
2111  return Size;
2112 }
2113 
2114 bool
2116  MachineBasicBlock &FMBB) const {
2117  // Reduce false anti-dependencies to let the target's out-of-order execution
2118  // engine do its thing.
2119  return Subtarget.isProfitableToUnpredicate();
2120 }
2121 
2122 /// getInstrPredicate - If instruction is predicated, returns its predicate
2123 /// condition, otherwise returns AL. It also returns the condition code
2124 /// register by reference.
2126  unsigned &PredReg) {
2127  int PIdx = MI.findFirstPredOperandIdx();
2128  if (PIdx == -1) {
2129  PredReg = 0;
2130  return ARMCC::AL;
2131  }
2132 
2133  PredReg = MI.getOperand(PIdx+1).getReg();
2134  return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
2135 }
2136 
2137 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
2138  if (Opc == ARM::B)
2139  return ARM::Bcc;
2140  if (Opc == ARM::tB)
2141  return ARM::tBcc;
2142  if (Opc == ARM::t2B)
2143  return ARM::t2Bcc;
2144 
2145  llvm_unreachable("Unknown unconditional branch opcode!");
2146 }
2147 
2149  bool NewMI,
2150  unsigned OpIdx1,
2151  unsigned OpIdx2) const {
2152  switch (MI.getOpcode()) {
2153  case ARM::MOVCCr:
2154  case ARM::t2MOVCCr: {
2155  // MOVCC can be commuted by inverting the condition.
2156  unsigned PredReg = 0;
2157  ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
2158  // MOVCC AL can't be inverted. Shouldn't happen.
2159  if (CC == ARMCC::AL || PredReg != ARM::CPSR)
2160  return nullptr;
2161  MachineInstr *CommutedMI =
2162  TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2163  if (!CommutedMI)
2164  return nullptr;
2165  // After swapping the MOVCC operands, also invert the condition.
2166  CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx())
2167  .setImm(ARMCC::getOppositeCondition(CC));
2168  return CommutedMI;
2169  }
2170  }
2171  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2172 }
2173 
2174 /// Identify instructions that can be folded into a MOVCC instruction, and
2175 /// return the defining instruction.
2176 MachineInstr *
2177 ARMBaseInstrInfo::canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI,
2178  const TargetInstrInfo *TII) const {
2179  if (!Register::isVirtualRegister(Reg))
2180  return nullptr;
2181  if (!MRI.hasOneNonDBGUse(Reg))
2182  return nullptr;
2183  MachineInstr *MI = MRI.getVRegDef(Reg);
2184  if (!MI)
2185  return nullptr;
2186  // Check if MI can be predicated and folded into the MOVCC.
2187  if (!isPredicable(*MI))
2188  return nullptr;
2189  // Check if MI has any non-dead defs or physreg uses. This also detects
2190  // predicated instructions which will be reading CPSR.
2191  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
2192  const MachineOperand &MO = MI->getOperand(i);
2193  // Reject frame index operands, PEI can't handle the predicated pseudos.
2194  if (MO.isFI() || MO.isCPI() || MO.isJTI())
2195  return nullptr;
2196  if (!MO.isReg())
2197  continue;
2198  // MI can't have any tied operands, that would conflict with predication.
2199  if (MO.isTied())
2200  return nullptr;
2202  return nullptr;
2203  if (MO.isDef() && !MO.isDead())
2204  return nullptr;
2205  }
2206  bool DontMoveAcrossStores = true;
2207  if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
2208  return nullptr;
2209  return MI;
2210 }
2211 
2214  unsigned &TrueOp, unsigned &FalseOp,
2215  bool &Optimizable) const {
2216  assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2217  "Unknown select instruction");
2218  // MOVCC operands:
2219  // 0: Def.
2220  // 1: True use.
2221  // 2: False use.
2222  // 3: Condition code.
2223  // 4: CPSR use.
2224  TrueOp = 1;
2225  FalseOp = 2;
2226  Cond.push_back(MI.getOperand(3));
2227  Cond.push_back(MI.getOperand(4));
2228  // We can always fold a def.
2229  Optimizable = true;
2230  return false;
2231 }
2232 
2233 MachineInstr *
2236  bool PreferFalse) const {
2237  assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2238  "Unknown select instruction");
2240  MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
2241  bool Invert = !DefMI;
2242  if (!DefMI)
2243  DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
2244  if (!DefMI)
2245  return nullptr;
2246 
2247  // Find new register class to use.
2248  MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2249  Register DestReg = MI.getOperand(0).getReg();
2250  const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
2251  if (!MRI.constrainRegClass(DestReg, PreviousClass))
2252  return nullptr;
2253 
2254  // Create a new predicated version of DefMI.
2255  // Rfalse is the first use.
2256  MachineInstrBuilder NewMI =
2257  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
2258 
2259  // Copy all the DefMI operands, excluding its (null) predicate.
2260  const MCInstrDesc &DefDesc = DefMI->getDesc();
2261  for (unsigned i = 1, e = DefDesc.getNumOperands();
2262  i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
2263  NewMI.add(DefMI->getOperand(i));
2264 
2265  unsigned CondCode = MI.getOperand(3).getImm();
2266  if (Invert)
2268  else
2269  NewMI.addImm(CondCode);
2270  NewMI.add(MI.getOperand(4));
2271 
2272  // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
2273  if (NewMI->hasOptionalDef())
2274  NewMI.add(condCodeOp());
2275 
2276  // The output register value when the predicate is false is an implicit
2277  // register operand tied to the first def.
2278  // The tie makes the register allocator ensure the FalseReg is allocated the
2279  // same register as operand 0.
2280  FalseReg.setImplicit();
2281  NewMI.add(FalseReg);
2282  NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
2283 
2284  // Update SeenMIs set: register newly created MI and erase removed DefMI.
2285  SeenMIs.insert(NewMI);
2286  SeenMIs.erase(DefMI);
2287 
2288  // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
2289  // DefMI would be invalid when tranferred inside the loop. Checking for a
2290  // loop is expensive, but at least remove kill flags if they are in different
2291  // BBs.
2292  if (DefMI->getParent() != MI.getParent())
2293  NewMI->clearKillInfo();
2294 
2295  // The caller will erase MI, but not DefMI.
2296  DefMI->eraseFromParent();
2297  return NewMI;
2298 }
2299 
2300 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
2301 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
2302 /// def operand.
2303 ///
2304 /// This will go away once we can teach tblgen how to set the optional CPSR def
2305 /// operand itself.
2307  uint16_t PseudoOpc;
2308  uint16_t MachineOpc;
2309 };
2310 
2312  {ARM::ADDSri, ARM::ADDri},
2313  {ARM::ADDSrr, ARM::ADDrr},
2314  {ARM::ADDSrsi, ARM::ADDrsi},
2315  {ARM::ADDSrsr, ARM::ADDrsr},
2316 
2317  {ARM::SUBSri, ARM::SUBri},
2318  {ARM::SUBSrr, ARM::SUBrr},
2319  {ARM::SUBSrsi, ARM::SUBrsi},
2320  {ARM::SUBSrsr, ARM::SUBrsr},
2321 
2322  {ARM::RSBSri, ARM::RSBri},
2323  {ARM::RSBSrsi, ARM::RSBrsi},
2324  {ARM::RSBSrsr, ARM::RSBrsr},
2325 
2326  {ARM::tADDSi3, ARM::tADDi3},
2327  {ARM::tADDSi8, ARM::tADDi8},
2328  {ARM::tADDSrr, ARM::tADDrr},
2329  {ARM::tADCS, ARM::tADC},
2330 
2331  {ARM::tSUBSi3, ARM::tSUBi3},
2332  {ARM::tSUBSi8, ARM::tSUBi8},
2333  {ARM::tSUBSrr, ARM::tSUBrr},
2334  {ARM::tSBCS, ARM::tSBC},
2335  {ARM::tRSBS, ARM::tRSB},
2336  {ARM::tLSLSri, ARM::tLSLri},
2337 
2338  {ARM::t2ADDSri, ARM::t2ADDri},
2339  {ARM::t2ADDSrr, ARM::t2ADDrr},
2340  {ARM::t2ADDSrs, ARM::t2ADDrs},
2341 
2342  {ARM::t2SUBSri, ARM::t2SUBri},
2343  {ARM::t2SUBSrr, ARM::t2SUBrr},
2344  {ARM::t2SUBSrs, ARM::t2SUBrs},
2345 
2346  {ARM::t2RSBSri, ARM::t2RSBri},
2347  {ARM::t2RSBSrs, ARM::t2RSBrs},
2348 };
2349 
2350 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
2351  for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
2352  if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
2353  return AddSubFlagsOpcodeMap[i].MachineOpc;
2354  return 0;
2355 }
2356 
2359  const DebugLoc &dl, unsigned DestReg,
2360  unsigned BaseReg, int NumBytes,
2361  ARMCC::CondCodes Pred, unsigned PredReg,
2362  const ARMBaseInstrInfo &TII,
2363  unsigned MIFlags) {
2364  if (NumBytes == 0 && DestReg != BaseReg) {
2365  BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2366  .addReg(BaseReg, RegState::Kill)
2367  .add(predOps(Pred, PredReg))
2368  .add(condCodeOp())
2369  .setMIFlags(MIFlags);
2370  return;
2371  }
2372 
2373  bool isSub = NumBytes < 0;
2374  if (isSub) NumBytes = -NumBytes;
2375 
2376  while (NumBytes) {
2377  unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2378  unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
2379  assert(ThisVal && "Didn't extract field correctly");
2380 
2381  // We will handle these bits from offset, clear them.
2382  NumBytes &= ~ThisVal;
2383 
2384  assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2385 
2386  // Build the new ADD / SUB.
2387  unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2388  BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2389  .addReg(BaseReg, RegState::Kill)
2390  .addImm(ThisVal)
2391  .add(predOps(Pred, PredReg))
2392  .add(condCodeOp())
2393  .setMIFlags(MIFlags);
2394  BaseReg = DestReg;
2395  }
2396 }
2397 
2399  MachineFunction &MF, MachineInstr *MI,
2400  unsigned NumBytes) {
2401  // This optimisation potentially adds lots of load and store
2402  // micro-operations, it's only really a great benefit to code-size.
2403  if (!Subtarget.hasMinSize())
2404  return false;
2405 
2406  // If only one register is pushed/popped, LLVM can use an LDR/STR
2407  // instead. We can't modify those so make sure we're dealing with an
2408  // instruction we understand.
2409  bool IsPop = isPopOpcode(MI->getOpcode());
2410  bool IsPush = isPushOpcode(MI->getOpcode());
2411  if (!IsPush && !IsPop)
2412  return false;
2413 
2414  bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2415  MI->getOpcode() == ARM::VLDMDIA_UPD;
2416  bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2417  MI->getOpcode() == ARM::tPOP ||
2418  MI->getOpcode() == ARM::tPOP_RET;
2419 
2420  assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2421  MI->getOperand(1).getReg() == ARM::SP)) &&
2422  "trying to fold sp update into non-sp-updating push/pop");
2423 
2424  // The VFP push & pop act on D-registers, so we can only fold an adjustment
2425  // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2426  // if this is violated.
2427  if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2428  return false;
2429 
2430  // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2431  // pred) so the list starts at 4. Thumb1 starts after the predicate.
2432  int RegListIdx = IsT1PushPop ? 2 : 4;
2433 
2434  // Calculate the space we'll need in terms of registers.
2435  unsigned RegsNeeded;
2436  const TargetRegisterClass *RegClass;
2437  if (IsVFPPushPop) {
2438  RegsNeeded = NumBytes / 8;
2439  RegClass = &ARM::DPRRegClass;
2440  } else {
2441  RegsNeeded = NumBytes / 4;
2442  RegClass = &ARM::GPRRegClass;
2443  }
2444 
2445  // We're going to have to strip all list operands off before
2446  // re-adding them since the order matters, so save the existing ones
2447  // for later.
2449 
2450  // We're also going to need the first register transferred by this
2451  // instruction, which won't necessarily be the first register in the list.
2452  unsigned FirstRegEnc = -1;
2453 
2455  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) {
2456  MachineOperand &MO = MI->getOperand(i);
2457  RegList.push_back(MO);
2458 
2459  if (MO.isReg() && !MO.isImplicit() &&
2460  TRI->getEncodingValue(MO.getReg()) < FirstRegEnc)
2461  FirstRegEnc = TRI->getEncodingValue(MO.getReg());
2462  }
2463 
2464  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2465 
2466  // Now try to find enough space in the reglist to allocate NumBytes.
2467  for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
2468  --CurRegEnc) {
2469  unsigned CurReg = RegClass->getRegister(CurRegEnc);
2470  if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7))
2471  continue;
2472  if (!IsPop) {
2473  // Pushing any register is completely harmless, mark the register involved
2474  // as undef since we don't care about its value and must not restore it
2475  // during stack unwinding.
2476  RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2477  false, false, true));
2478  --RegsNeeded;
2479  continue;
2480  }
2481 
2482  // However, we can only pop an extra register if it's not live. For
2483  // registers live within the function we might clobber a return value
2484  // register; the other way a register can be live here is if it's
2485  // callee-saved.
2486  if (isCalleeSavedRegister(CurReg, CSRegs) ||
2487  MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2489  // VFP pops don't allow holes in the register list, so any skip is fatal
2490  // for our transformation. GPR pops do, so we should just keep looking.
2491  if (IsVFPPushPop)
2492  return false;
2493  else
2494  continue;
2495  }
2496 
2497  // Mark the unimportant registers as <def,dead> in the POP.
2498  RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2499  true));
2500  --RegsNeeded;
2501  }
2502 
2503  if (RegsNeeded > 0)
2504  return false;
2505 
2506  // Finally we know we can profitably perform the optimisation so go
2507  // ahead: strip all existing registers off and add them back again
2508  // in the right order.
2509  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2510  MI->RemoveOperand(i);
2511 
2512  // Add the complete list back in.
2513  MachineInstrBuilder MIB(MF, &*MI);
2514  for (int i = RegList.size() - 1; i >= 0; --i)
2515  MIB.add(RegList[i]);
2516 
2517  return true;
2518 }
2519 
2520 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2521  unsigned FrameReg, int &Offset,
2522  const ARMBaseInstrInfo &TII) {
2523  unsigned Opcode = MI.getOpcode();
2524  const MCInstrDesc &Desc = MI.getDesc();
2525  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2526  bool isSub = false;
2527 
2528  // Memory operands in inline assembly always use AddrMode2.
2529  if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
2530  AddrMode = ARMII::AddrMode2;
2531 
2532  if (Opcode == ARM::ADDri) {
2533  Offset += MI.getOperand(FrameRegIdx+1).getImm();
2534  if (Offset == 0) {
2535  // Turn it into a move.
2536  MI.setDesc(TII.get(ARM::MOVr));
2537  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2538  MI.RemoveOperand(FrameRegIdx+1);
2539  Offset = 0;
2540  return true;
2541  } else if (Offset < 0) {
2542  Offset = -Offset;
2543  isSub = true;
2544  MI.setDesc(TII.get(ARM::SUBri));
2545  }
2546 
2547  // Common case: small offset, fits into instruction.
2548  if (ARM_AM::getSOImmVal(Offset) != -1) {
2549  // Replace the FrameIndex with sp / fp
2550  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2551  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2552  Offset = 0;
2553  return true;
2554  }
2555 
2556  // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2557  // as possible.
2558  unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2559  unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2560 
2561  // We will handle these bits from offset, clear them.
2562  Offset &= ~ThisImmVal;
2563 
2564  // Get the properly encoded SOImmVal field.
2565  assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2566  "Bit extraction didn't work?");
2567  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2568  } else {
2569  unsigned ImmIdx = 0;
2570  int InstrOffs = 0;
2571  unsigned NumBits = 0;
2572  unsigned Scale = 1;
2573  switch (AddrMode) {
2574  case ARMII::AddrMode_i12:
2575  ImmIdx = FrameRegIdx + 1;
2576  InstrOffs = MI.getOperand(ImmIdx).getImm();
2577  NumBits = 12;
2578  break;
2579  case ARMII::AddrMode2:
2580  ImmIdx = FrameRegIdx+2;
2581  InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2582  if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2583  InstrOffs *= -1;
2584  NumBits = 12;
2585  break;
2586  case ARMII::AddrMode3:
2587  ImmIdx = FrameRegIdx+2;
2588  InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2589  if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2590  InstrOffs *= -1;
2591  NumBits = 8;
2592  break;
2593  case ARMII::AddrMode4:
2594  case ARMII::AddrMode6:
2595  // Can't fold any offset even if it's zero.
2596  return false;
2597  case ARMII::AddrMode5:
2598  ImmIdx = FrameRegIdx+1;
2599  InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2600  if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2601  InstrOffs *= -1;
2602  NumBits = 8;
2603  Scale = 4;
2604  break;
2605  case ARMII::AddrMode5FP16:
2606  ImmIdx = FrameRegIdx+1;
2607  InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2608  if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2609  InstrOffs *= -1;
2610  NumBits = 8;
2611  Scale = 2;
2612  break;
2613  case ARMII::AddrModeT2_i7:
2616  ImmIdx = FrameRegIdx+1;
2617  InstrOffs = MI.getOperand(ImmIdx).getImm();
2618  NumBits = 7;
2619  Scale = (AddrMode == ARMII::AddrModeT2_i7s2 ? 2 :
2620  AddrMode == ARMII::AddrModeT2_i7s4 ? 4 : 1);
2621  break;
2622  default:
2623  llvm_unreachable("Unsupported addressing mode!");
2624  }
2625 
2626  Offset += InstrOffs * Scale;
2627  assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2628  if (Offset < 0) {
2629  Offset = -Offset;
2630  isSub = true;
2631  }
2632 
2633  // Attempt to fold address comp. if opcode has offset bits
2634  if (NumBits > 0) {
2635  // Common case: small offset, fits into instruction.
2636  MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2637  int ImmedOffset = Offset / Scale;
2638  unsigned Mask = (1 << NumBits) - 1;
2639  if ((unsigned)Offset <= Mask * Scale) {
2640  // Replace the FrameIndex with sp
2641  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2642  // FIXME: When addrmode2 goes away, this will simplify (like the
2643  // T2 version), as the LDR.i12 versions don't need the encoding
2644  // tricks for the offset value.
2645  if (isSub) {
2646  if (AddrMode == ARMII::AddrMode_i12)
2647  ImmedOffset = -ImmedOffset;
2648  else
2649  ImmedOffset |= 1 << NumBits;
2650  }
2651  ImmOp.ChangeToImmediate(ImmedOffset);
2652  Offset = 0;
2653  return true;
2654  }
2655 
2656  // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2657  ImmedOffset = ImmedOffset & Mask;
2658  if (isSub) {
2659  if (AddrMode == ARMII::AddrMode_i12)
2660  ImmedOffset = -ImmedOffset;
2661  else
2662  ImmedOffset |= 1 << NumBits;
2663  }
2664  ImmOp.ChangeToImmediate(ImmedOffset);
2665  Offset &= ~(Mask*Scale);
2666  }
2667  }
2668 
2669  Offset = (isSub) ? -Offset : Offset;
2670  return Offset == 0;
2671 }
2672 
2673 /// analyzeCompare - For a comparison instruction, return the source registers
2674 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2675 /// compares against in CmpValue. Return true if the comparison instruction
2676 /// can be analyzed.
2677 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
2678  unsigned &SrcReg2, int &CmpMask,
2679  int &CmpValue) const {
2680  switch (MI.getOpcode()) {
2681  default: break;
2682  case ARM::CMPri:
2683  case ARM::t2CMPri:
2684  case ARM::tCMPi8:
2685  SrcReg = MI.getOperand(0).getReg();
2686  SrcReg2 = 0;
2687  CmpMask = ~0;
2688  CmpValue = MI.getOperand(1).getImm();
2689  return true;
2690  case ARM::CMPrr:
2691  case ARM::t2CMPrr:
2692  case ARM::tCMPr:
2693  SrcReg = MI.getOperand(0).getReg();
2694  SrcReg2 = MI.getOperand(1).getReg();
2695  CmpMask = ~0;
2696  CmpValue = 0;
2697  return true;
2698  case ARM::TSTri:
2699  case ARM::t2TSTri:
2700  SrcReg = MI.getOperand(0).getReg();
2701  SrcReg2 = 0;
2702  CmpMask = MI.getOperand(1).getImm();
2703  CmpValue = 0;
2704  return true;
2705  }
2706 
2707  return false;
2708 }
2709 
2710 /// isSuitableForMask - Identify a suitable 'and' instruction that
2711 /// operates on the given source register and applies the same mask
2712 /// as a 'tst' instruction. Provide a limited look-through for copies.
2713 /// When successful, MI will hold the found instruction.
2714 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2715  int CmpMask, bool CommonUse) {
2716  switch (MI->getOpcode()) {
2717  case ARM::ANDri:
2718  case ARM::t2ANDri:
2719  if (CmpMask != MI->getOperand(2).getImm())
2720  return false;
2721  if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2722  return true;
2723  break;
2724  }
2725 
2726  return false;
2727 }
2728 
2729 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2730 /// the condition code if we modify the instructions such that flags are
2731 /// set by MI(b,a).
2733  switch (CC) {
2734  default: return ARMCC::AL;
2735  case ARMCC::EQ: return ARMCC::EQ;
2736  case ARMCC::NE: return ARMCC::NE;
2737  case ARMCC::HS: return ARMCC::LS;
2738  case ARMCC::LO: return ARMCC::HI;
2739  case ARMCC::HI: return ARMCC::LO;
2740  case ARMCC::LS: return ARMCC::HS;
2741  case ARMCC::GE: return ARMCC::LE;
2742  case ARMCC::LT: return ARMCC::GT;
2743  case ARMCC::GT: return ARMCC::LT;
2744  case ARMCC::LE: return ARMCC::GE;
2745  }
2746 }
2747 
2748 /// getCmpToAddCondition - assume the flags are set by CMP(a,b), return
2749 /// the condition code if we modify the instructions such that flags are
2750 /// set by ADD(a,b,X).
2752  switch (CC) {
2753  default: return ARMCC::AL;
2754  case ARMCC::HS: return ARMCC::LO;
2755  case ARMCC::LO: return ARMCC::HS;
2756  case ARMCC::VS: return ARMCC::VS;
2757  case ARMCC::VC: return ARMCC::VC;
2758  }
2759 }
2760 
2761 /// isRedundantFlagInstr - check whether the first instruction, whose only
2762 /// purpose is to update flags, can be made redundant.
2763 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2764 /// CMPri can be made redundant by SUBri if the operands are the same.
2765 /// CMPrr(r0, r1) can be made redundant by ADDr[ri](r0, r1, X).
2766 /// This function can be extended later on.
2767 inline static bool isRedundantFlagInstr(const MachineInstr *CmpI,
2768  unsigned SrcReg, unsigned SrcReg2,
2769  int ImmValue, const MachineInstr *OI,
2770  bool &IsThumb1) {
2771  if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
2772  (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) &&
2773  ((OI->getOperand(1).getReg() == SrcReg &&
2774  OI->getOperand(2).getReg() == SrcReg2) ||
2775  (OI->getOperand(1).getReg() == SrcReg2 &&
2776  OI->getOperand(2).getReg() == SrcReg))) {
2777  IsThumb1 = false;
2778  return true;
2779  }
2780 
2781  if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr &&
2782  ((OI->getOperand(2).getReg() == SrcReg &&
2783  OI->getOperand(3).getReg() == SrcReg2) ||
2784  (OI->getOperand(2).getReg() == SrcReg2 &&
2785  OI->getOperand(3).getReg() == SrcReg))) {
2786  IsThumb1 = true;
2787  return true;
2788  }
2789 
2790  if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) &&
2791  (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) &&
2792  OI->getOperand(1).getReg() == SrcReg &&
2793  OI->getOperand(2).getImm() == ImmValue) {
2794  IsThumb1 = false;
2795  return true;
2796  }
2797 
2798  if (CmpI->getOpcode() == ARM::tCMPi8 &&
2799  (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) &&
2800  OI->getOperand(2).getReg() == SrcReg &&
2801  OI->getOperand(3).getImm() == ImmValue) {
2802  IsThumb1 = true;
2803  return true;
2804  }
2805 
2806  if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
2807  (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr ||
2808  OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) &&
2809  OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
2810  OI->getOperand(0).getReg() == SrcReg &&
2811  OI->getOperand(1).getReg() == SrcReg2) {
2812  IsThumb1 = false;
2813  return true;
2814  }
2815 
2816  if (CmpI->getOpcode() == ARM::tCMPr &&
2817  (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8 ||
2818  OI->getOpcode() == ARM::tADDrr) &&
2819  OI->getOperand(0).getReg() == SrcReg &&
2820  OI->getOperand(2).getReg() == SrcReg2) {
2821  IsThumb1 = true;
2822  return true;
2823  }
2824 
2825  return false;
2826 }
2827 
2828 static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
2829  switch (MI->getOpcode()) {
2830  default: return false;
2831  case ARM::tLSLri:
2832  case ARM::tLSRri:
2833  case ARM::tLSLrr:
2834  case ARM::tLSRrr:
2835  case ARM::tSUBrr:
2836  case ARM::tADDrr:
2837  case ARM::tADDi3:
2838  case ARM::tADDi8:
2839  case ARM::tSUBi3:
2840  case ARM::tSUBi8:
2841  case ARM::tMUL:
2842  case ARM::tADC:
2843  case ARM::tSBC:
2844  case ARM::tRSB:
2845  case ARM::tAND:
2846  case ARM::tORR:
2847  case ARM::tEOR:
2848  case ARM::tBIC:
2849  case ARM::tMVN:
2850  case ARM::tASRri:
2851  case ARM::tASRrr:
2852  case ARM::tROR:
2853  IsThumb1 = true;
2855  case ARM::RSBrr:
2856  case ARM::RSBri:
2857  case ARM::RSCrr:
2858  case ARM::RSCri:
2859  case ARM::ADDrr:
2860  case ARM::ADDri:
2861  case ARM::ADCrr:
2862  case ARM::ADCri:
2863  case ARM::SUBrr:
2864  case ARM::SUBri:
2865  case ARM::SBCrr:
2866  case ARM::SBCri:
2867  case ARM::t2RSBri:
2868  case ARM::t2ADDrr:
2869  case ARM::t2ADDri:
2870  case ARM::t2ADCrr:
2871  case ARM::t2ADCri:
2872  case ARM::t2SUBrr:
2873  case ARM::t2SUBri:
2874  case ARM::t2SBCrr:
2875  case ARM::t2SBCri:
2876  case ARM::ANDrr:
2877  case ARM::ANDri:
2878  case ARM::t2ANDrr:
2879  case ARM::t2ANDri:
2880  case ARM::ORRrr:
2881  case ARM::ORRri:
2882  case ARM::t2ORRrr:
2883  case ARM::t2ORRri:
2884  case ARM::EORrr:
2885  case ARM::EORri:
2886  case ARM::t2EORrr:
2887  case ARM::t2EORri:
2888  case ARM::t2LSRri:
2889  case ARM::t2LSRrr:
2890  case ARM::t2LSLri:
2891  case ARM::t2LSLrr:
2892  return true;
2893  }
2894 }
2895 
2896 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2897 /// comparison into one that sets the zero bit in the flags register;
2898 /// Remove a redundant Compare instruction if an earlier instruction can set the
2899 /// flags in the same way as Compare.
2900 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2901 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2902 /// condition code of instructions which use the flags.
2904  MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
2905  int CmpValue, const MachineRegisterInfo *MRI) const {
2906  // Get the unique definition of SrcReg.
2907  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2908  if (!MI) return false;
2909 
2910  // Masked compares sometimes use the same register as the corresponding 'and'.
2911  if (CmpMask != ~0) {
2912  if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
2913  MI = nullptr;
2915  UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2916  UI != UE; ++UI) {
2917  if (UI->getParent() != CmpInstr.getParent())
2918  continue;
2919  MachineInstr *PotentialAND = &*UI;
2920  if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2921  isPredicated(*PotentialAND))
2922  continue;
2923  MI = PotentialAND;
2924  break;
2925  }
2926  if (!MI) return false;
2927  }
2928  }
2929 
2930  // Get ready to iterate backward from CmpInstr.
2931  MachineBasicBlock::iterator I = CmpInstr, E = MI,
2932  B = CmpInstr.getParent()->begin();
2933 
2934  // Early exit if CmpInstr is at the beginning of the BB.
2935  if (I == B) return false;
2936 
2937  // There are two possible candidates which can be changed to set CPSR:
2938  // One is MI, the other is a SUB or ADD instruction.
2939  // For CMPrr(r1,r2), we are looking for SUB(r1,r2), SUB(r2,r1), or
2940  // ADDr[ri](r1, r2, X).
2941  // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2942  MachineInstr *SubAdd = nullptr;
2943  if (SrcReg2 != 0)
2944  // MI is not a candidate for CMPrr.
2945  MI = nullptr;
2946  else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
2947  // Conservatively refuse to convert an instruction which isn't in the same
2948  // BB as the comparison.
2949  // For CMPri w/ CmpValue != 0, a SubAdd may still be a candidate.
2950  // Thus we cannot return here.
2951  if (CmpInstr.getOpcode() == ARM::CMPri ||
2952  CmpInstr.getOpcode() == ARM::t2CMPri ||
2953  CmpInstr.getOpcode() == ARM::tCMPi8)
2954  MI = nullptr;
2955  else
2956  return false;
2957  }
2958 
2959  bool IsThumb1 = false;
2960  if (MI && !isOptimizeCompareCandidate(MI, IsThumb1))
2961  return false;
2962 
2963  // We also want to do this peephole for cases like this: if (a*b == 0),
2964  // and optimise away the CMP instruction from the generated code sequence:
2965  // MULS, MOVS, MOVS, CMP. Here the MOVS instructions load the boolean values
2966  // resulting from the select instruction, but these MOVS instructions for
2967  // Thumb1 (V6M) are flag setting and are thus preventing this optimisation.
2968  // However, if we only have MOVS instructions in between the CMP and the
2969  // other instruction (the MULS in this example), then the CPSR is dead so we
2970  // can safely reorder the sequence into: MOVS, MOVS, MULS, CMP. We do this
2971  // reordering and then continue the analysis hoping we can eliminate the
2972  // CMP. This peephole works on the vregs, so is still in SSA form. As a
2973  // consequence, the movs won't redefine/kill the MUL operands which would
2974  // make this reordering illegal.
2976  if (MI && IsThumb1) {
2977  --I;
2978  if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
2979  bool CanReorder = true;
2980  for (; I != E; --I) {
2981  if (I->getOpcode() != ARM::tMOVi8) {
2982  CanReorder = false;
2983  break;
2984  }
2985  }
2986  if (CanReorder) {
2987  MI = MI->removeFromParent();
2988  E = CmpInstr;
2989  CmpInstr.getParent()->insert(E, MI);
2990  }
2991  }
2992  I = CmpInstr;
2993  E = MI;
2994  }
2995 
2996  // Check that CPSR isn't set between the comparison instruction and the one we
2997  // want to change. At the same time, search for SubAdd.
2998  bool SubAddIsThumb1 = false;
2999  do {
3000  const MachineInstr &Instr = *--I;
3001 
3002  // Check whether CmpInstr can be made redundant by the current instruction.
3003  if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &Instr,
3004  SubAddIsThumb1)) {
3005  SubAdd = &*I;
3006  break;
3007  }
3008 
3009  // Allow E (which was initially MI) to be SubAdd but do not search before E.
3010  if (I == E)
3011  break;
3012 
3013  if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
3014  Instr.readsRegister(ARM::CPSR, TRI))
3015  // This instruction modifies or uses CPSR after the one we want to
3016  // change. We can't do this transformation.
3017  return false;
3018 
3019  if (I == B) {
3020  // In some cases, we scan the use-list of an instruction for an AND;
3021  // that AND is in the same BB, but may not be scheduled before the
3022  // corresponding TST. In that case, bail out.
3023  //
3024  // FIXME: We could try to reschedule the AND.
3025  return false;
3026  }
3027  } while (true);
3028 
3029  // Return false if no candidates exist.
3030  if (!MI && !SubAdd)
3031  return false;
3032 
3033  // If we found a SubAdd, use it as it will be closer to the CMP
3034  if (SubAdd) {
3035  MI = SubAdd;
3036  IsThumb1 = SubAddIsThumb1;
3037  }
3038 
3039  // We can't use a predicated instruction - it doesn't always write the flags.
3040  if (isPredicated(*MI))
3041  return false;
3042 
3043  // Scan forward for the use of CPSR
3044  // When checking against MI: if it's a conditional code that requires
3045  // checking of the V bit or C bit, then this is not safe to do.
3046  // It is safe to remove CmpInstr if CPSR is redefined or killed.
3047  // If we are done with the basic block, we need to check whether CPSR is
3048  // live-out.
3050  OperandsToUpdate;
3051  bool isSafe = false;
3052  I = CmpInstr;
3053  E = CmpInstr.getParent()->end();
3054  while (!isSafe && ++I != E) {
3055  const MachineInstr &Instr = *I;
3056  for (unsigned IO = 0, EO = Instr.getNumOperands();
3057  !isSafe && IO != EO; ++IO) {
3058  const MachineOperand &MO = Instr.getOperand(IO);
3059  if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
3060  isSafe = true;
3061  break;
3062  }
3063  if (!MO.isReg() || MO.getReg() != ARM::CPSR)
3064  continue;
3065  if (MO.isDef()) {
3066  isSafe = true;
3067  break;
3068  }
3069  // Condition code is after the operand before CPSR except for VSELs.
3070  ARMCC::CondCodes CC;
3071  bool IsInstrVSel = true;
3072  switch (Instr.getOpcode()) {
3073  default:
3074  IsInstrVSel = false;
3075  CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
3076  break;
3077  case ARM::VSELEQD:
3078  case ARM::VSELEQS:
3079  case ARM::VSELEQH:
3080  CC = ARMCC::EQ;
3081  break;
3082  case ARM::VSELGTD:
3083  case ARM::VSELGTS:
3084  case ARM::VSELGTH:
3085  CC = ARMCC::GT;
3086  break;
3087  case ARM::VSELGED:
3088  case ARM::VSELGES:
3089  case ARM::VSELGEH:
3090  CC = ARMCC::GE;
3091  break;
3092  case ARM::VSELVSD:
3093  case ARM::VSELVSS:
3094  case ARM::VSELVSH:
3095  CC = ARMCC::VS;
3096  break;
3097  }
3098 
3099  if (SubAdd) {
3100  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
3101  // on CMP needs to be updated to be based on SUB.
3102  // If we have ADD(r1, r2, X) and CMP(r1, r2), the condition code also
3103  // needs to be modified.
3104  // Push the condition code operands to OperandsToUpdate.
3105  // If it is safe to remove CmpInstr, the condition code of these
3106  // operands will be modified.
3107  unsigned Opc = SubAdd->getOpcode();
3108  bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr ||
3109  Opc == ARM::SUBri || Opc == ARM::t2SUBri ||
3110  Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 ||
3111  Opc == ARM::tSUBi8;
3112  unsigned OpI = Opc != ARM::tSUBrr ? 1 : 2;
3113  if (!IsSub ||
3114  (SrcReg2 != 0 && SubAdd->getOperand(OpI).getReg() == SrcReg2 &&
3115  SubAdd->getOperand(OpI + 1).getReg() == SrcReg)) {
3116  // VSel doesn't support condition code update.
3117  if (IsInstrVSel)
3118  return false;
3119  // Ensure we can swap the condition.
3120  ARMCC::CondCodes NewCC = (IsSub ? getSwappedCondition(CC) : getCmpToAddCondition(CC));
3121  if (NewCC == ARMCC::AL)
3122  return false;
3123  OperandsToUpdate.push_back(
3124  std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
3125  }
3126  } else {
3127  // No SubAdd, so this is x = <op> y, z; cmp x, 0.
3128  switch (CC) {
3129  case ARMCC::EQ: // Z
3130  case ARMCC::NE: // Z
3131  case ARMCC::MI: // N
3132  case ARMCC::PL: // N
3133  case ARMCC::AL: // none
3134  // CPSR can be used multiple times, we should continue.
3135  break;
3136  case ARMCC::HS: // C
3137  case ARMCC::LO: // C
3138  case ARMCC::VS: // V
3139  case ARMCC::VC: // V
3140  case ARMCC::HI: // C Z
3141  case ARMCC::LS: // C Z
3142  case ARMCC::GE: // N V
3143  case ARMCC::LT: // N V
3144  case ARMCC::GT: // Z N V
3145  case ARMCC::LE: // Z N V
3146  // The instruction uses the V bit or C bit which is not safe.
3147  return false;
3148  }
3149  }
3150  }
3151  }
3152 
3153  // If CPSR is not killed nor re-defined, we should check whether it is
3154  // live-out. If it is live-out, do not optimize.
3155  if (!isSafe) {
3156  MachineBasicBlock *MBB = CmpInstr.getParent();
3158  SE = MBB->succ_end(); SI != SE; ++SI)
3159  if ((*SI)->isLiveIn(ARM::CPSR))
3160  return false;
3161  }
3162 
3163  // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
3164  // set CPSR so this is represented as an explicit output)
3165  if (!IsThumb1) {
3166  MI->getOperand(5).setReg(ARM::CPSR);
3167  MI->getOperand(5).setIsDef(true);
3168  }
3169  assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
3170  CmpInstr.eraseFromParent();
3171 
3172  // Modify the condition code of operands in OperandsToUpdate.
3173  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
3174  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3175  for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
3176  OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
3177 
3178  MI->clearRegisterDeads(ARM::CPSR);
3179 
3180  return true;
3181 }
3182 
3184  // Do not sink MI if it might be used to optimize a redundant compare.
3185  // We heuristically only look at the instruction immediately following MI to
3186  // avoid potentially searching the entire basic block.
3187  if (isPredicated(MI))
3188  return true;
3190  ++Next;
3191  unsigned SrcReg, SrcReg2;
3192  int CmpMask, CmpValue;
3193  bool IsThumb1;
3194  if (Next != MI.getParent()->end() &&
3195  analyzeCompare(*Next, SrcReg, SrcReg2, CmpMask, CmpValue) &&
3196  isRedundantFlagInstr(&*Next, SrcReg, SrcReg2, CmpValue, &MI, IsThumb1))
3197  return false;
3198  return true;
3199 }
3200 
3202  unsigned Reg,
3203  MachineRegisterInfo *MRI) const {
3204  // Fold large immediates into add, sub, or, xor.
3205  unsigned DefOpc = DefMI.getOpcode();
3206  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
3207  return false;
3208  if (!DefMI.getOperand(1).isImm())
3209  // Could be t2MOVi32imm @xx
3210  return false;
3211 
3212  if (!MRI->hasOneNonDBGUse(Reg))
3213  return false;
3214 
3215  const MCInstrDesc &DefMCID = DefMI.getDesc();
3216  if (DefMCID.hasOptionalDef()) {
3217  unsigned NumOps = DefMCID.getNumOperands();
3218  const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
3219  if (MO.getReg() == ARM::CPSR && !MO.isDead())
3220  // If DefMI defines CPSR and it is not dead, it's obviously not safe
3221  // to delete DefMI.
3222  return false;
3223  }
3224 
3225  const MCInstrDesc &UseMCID = UseMI.getDesc();
3226  if (UseMCID.hasOptionalDef()) {
3227  unsigned NumOps = UseMCID.getNumOperands();
3228  if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
3229  // If the instruction sets the flag, do not attempt this optimization
3230  // since it may change the semantics of the code.
3231  return false;
3232  }
3233 
3234  unsigned UseOpc = UseMI.getOpcode();
3235  unsigned NewUseOpc = 0;
3236  uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
3237  uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
3238  bool Commute = false;
3239  switch (UseOpc) {
3240  default: return false;
3241  case ARM::SUBrr:
3242  case ARM::ADDrr:
3243  case ARM::ORRrr:
3244  case ARM::EORrr:
3245  case ARM::t2SUBrr:
3246  case ARM::t2ADDrr:
3247  case ARM::t2ORRrr:
3248  case ARM::t2EORrr: {
3249  Commute = UseMI.getOperand(2).getReg() != Reg;
3250  switch (UseOpc) {
3251  default: break;
3252  case ARM::ADDrr:
3253  case ARM::SUBrr:
3254  if (UseOpc == ARM::SUBrr && Commute)
3255  return false;
3256 
3257  // ADD/SUB are special because they're essentially the same operation, so
3258  // we can handle a larger range of immediates.
3259  if (ARM_AM::isSOImmTwoPartVal(ImmVal))
3260  NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
3261  else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
3262  ImmVal = -ImmVal;
3263  NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
3264  } else
3265  return false;
3266  SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
3267  SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
3268  break;
3269  case ARM::ORRrr:
3270  case ARM::EORrr:
3271  if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
3272  return false;
3273  SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
3274  SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
3275  switch (UseOpc) {
3276  default: break;
3277  case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
3278  case ARM::EORrr: NewUseOpc = ARM::EORri; break;
3279  }
3280  break;
3281  case ARM::t2ADDrr:
3282  case ARM::t2SUBrr:
3283  if (UseOpc == ARM::t2SUBrr && Commute)
3284  return false;
3285 
3286  // ADD/SUB are special because they're essentially the same operation, so
3287  // we can handle a larger range of immediates.
3288  if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
3289  NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
3290  else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
3291  ImmVal = -ImmVal;
3292  NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
3293  } else
3294  return false;
3295  SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
3296  SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
3297  break;
3298  case ARM::t2ORRrr:
3299  case ARM::t2EORrr:
3300  if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
3301  return false;
3302  SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
3303  SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
3304  switch (UseOpc) {
3305  default: break;
3306  case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
3307  case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
3308  }
3309  break;
3310  }
3311  }
3312  }
3313 
3314  unsigned OpIdx = Commute ? 2 : 1;
3315  Register Reg1 = UseMI.getOperand(OpIdx).getReg();
3316  bool isKill = UseMI.getOperand(OpIdx).isKill();
3317  Register NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
3318  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
3319  NewReg)
3320  .addReg(Reg1, getKillRegState(isKill))
3321  .addImm(SOImmValV1)
3322  .add(predOps(ARMCC::AL))
3323  .add(condCodeOp());
3324  UseMI.setDesc(get(NewUseOpc));
3325  UseMI.getOperand(1).setReg(NewReg);
3326  UseMI.getOperand(1).setIsKill();
3327  UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
3328  DefMI.eraseFromParent();
3329  return true;
3330 }
3331 
3332 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
3333  const MachineInstr &MI) {
3334  switch (MI.getOpcode()) {
3335  default: {
3336  const MCInstrDesc &Desc = MI.getDesc();
3337  int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3338  assert(UOps >= 0 && "bad # UOps");
3339  return UOps;
3340  }
3341 
3342  case ARM::LDRrs:
3343  case ARM::LDRBrs:
3344  case ARM::STRrs:
3345  case ARM::STRBrs: {
3346  unsigned ShOpVal = MI.getOperand(3).getImm();
3347  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3348  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3349  if (!isSub &&
3350  (ShImm == 0 ||
3351  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3352  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3353  return 1;
3354  return 2;
3355  }
3356 
3357  case ARM::LDRH:
3358  case ARM::STRH: {
3359  if (!MI.getOperand(2).getReg())
3360  return 1;
3361 
3362  unsigned ShOpVal = MI.getOperand(3).getImm();
3363  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3364  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3365  if (!isSub &&
3366  (ShImm == 0 ||
3367  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3368  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3369  return 1;
3370  return 2;
3371  }
3372 
3373  case ARM::LDRSB:
3374  case ARM::LDRSH:
3375  return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2;
3376 
3377  case ARM::LDRSB_POST:
3378  case ARM::LDRSH_POST: {
3379  Register Rt = MI.getOperand(0).getReg();
3380  Register Rm = MI.getOperand(3).getReg();
3381  return (Rt == Rm) ? 4 : 3;
3382  }
3383 
3384  case ARM::LDR_PRE_REG:
3385  case ARM::LDRB_PRE_REG: {
3386  Register Rt = MI.getOperand(0).getReg();
3387  Register Rm = MI.getOperand(3).getReg();
3388  if (Rt == Rm)
3389  return 3;
3390  unsigned ShOpVal = MI.getOperand(4).getImm();
3391  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3392  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3393  if (!isSub &&
3394  (ShImm == 0 ||
3395  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3396  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3397  return 2;
3398  return 3;
3399  }
3400 
3401  case ARM::STR_PRE_REG:
3402  case ARM::STRB_PRE_REG: {
3403  unsigned ShOpVal = MI.getOperand(4).getImm();
3404  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3405  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3406  if (!isSub &&
3407  (ShImm == 0 ||
3408  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3409  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3410  return 2;
3411  return 3;
3412  }
3413 
3414  case ARM::LDRH_PRE:
3415  case ARM::STRH_PRE: {
3416  Register Rt = MI.getOperand(0).getReg();
3417  Register Rm = MI.getOperand(3).getReg();
3418  if (!Rm)
3419  return 2;
3420  if (Rt == Rm)
3421  return 3;
3422  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2;
3423  }
3424 
3425  case ARM::LDR_POST_REG:
3426  case ARM::LDRB_POST_REG:
3427  case ARM::LDRH_POST: {
3428  Register Rt = MI.getOperand(0).getReg();
3429  Register Rm = MI.getOperand(3).getReg();
3430  return (Rt == Rm) ? 3 : 2;
3431  }
3432 
3433  case ARM::LDR_PRE_IMM:
3434  case ARM::LDRB_PRE_IMM:
3435  case ARM::LDR_POST_IMM:
3436  case ARM::LDRB_POST_IMM:
3437  case ARM::STRB_POST_IMM:
3438  case ARM::STRB_POST_REG:
3439  case ARM::STRB_PRE_IMM:
3440  case ARM::STRH_POST:
3441  case ARM::STR_POST_IMM:
3442  case ARM::STR_POST_REG:
3443  case ARM::STR_PRE_IMM:
3444  return 2;
3445 
3446  case ARM::LDRSB_PRE:
3447  case ARM::LDRSH_PRE: {
3448  Register Rm = MI.getOperand(3).getReg();
3449  if (Rm == 0)
3450  return 3;
3451  Register Rt = MI.getOperand(0).getReg();
3452  if (Rt == Rm)
3453  return 4;
3454  unsigned ShOpVal = MI.getOperand(4).getImm();
3455  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3456  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3457  if (!isSub &&
3458  (ShImm == 0 ||
3459  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3460  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3461  return 3;
3462  return 4;
3463  }
3464 
3465  case ARM::LDRD: {
3466  Register Rt = MI.getOperand(0).getReg();
3467  Register Rn = MI.getOperand(2).getReg();
3468  Register Rm = MI.getOperand(3).getReg();
3469  if (Rm)
3470  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3471  : 3;
3472  return (Rt == Rn) ? 3 : 2;
3473  }
3474 
3475  case ARM::STRD: {
3476  Register Rm = MI.getOperand(3).getReg();
3477  if (Rm)
3478  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3479  : 3;
3480  return 2;
3481  }
3482 
3483  case ARM::LDRD_POST:
3484  case ARM::t2LDRD_POST:
3485  return 3;
3486 
3487  case ARM::STRD_POST:
3488  case ARM::t2STRD_POST:
3489  return 4;
3490 
3491  case ARM::LDRD_PRE: {
3492  Register Rt = MI.getOperand(0).getReg();
3493  Register Rn = MI.getOperand(3).getReg();
3494  Register Rm = MI.getOperand(4).getReg();
3495  if (Rm)
3496  return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3497  : 4;
3498  return (Rt == Rn) ? 4 : 3;
3499  }
3500 
3501  case ARM::t2LDRD_PRE: {
3502  Register Rt = MI.getOperand(0).getReg();
3503  Register Rn = MI.getOperand(3).getReg();
3504  return (Rt == Rn) ? 4 : 3;
3505  }
3506 
3507  case ARM::STRD_PRE: {
3508  Register Rm = MI.getOperand(4).getReg();
3509  if (Rm)
3510  return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3511  : 4;
3512  return 3;
3513  }
3514 
3515  case ARM::t2STRD_PRE:
3516  return 3;
3517 
3518  case ARM::t2LDR_POST:
3519  case ARM::t2LDRB_POST:
3520  case ARM::t2LDRB_PRE:
3521  case ARM::t2LDRSBi12:
3522  case ARM::t2LDRSBi8:
3523  case ARM::t2LDRSBpci:
3524  case ARM::t2LDRSBs:
3525  case ARM::t2LDRH_POST:
3526  case ARM::t2LDRH_PRE:
3527  case ARM::t2LDRSBT:
3528  case ARM::t2LDRSB_POST:
3529  case ARM::t2LDRSB_PRE:
3530  case ARM::t2LDRSH_POST:
3531  case ARM::t2LDRSH_PRE:
3532  case ARM::t2LDRSHi12:
3533  case ARM::t2LDRSHi8:
3534  case ARM::t2LDRSHpci:
3535  case ARM::t2LDRSHs:
3536  return 2;
3537 
3538  case ARM::t2LDRDi8: {
3539  Register Rt = MI.getOperand(0).getReg();
3540  Register Rn = MI.getOperand(2).getReg();
3541  return (Rt == Rn) ? 3 : 2;
3542  }
3543 
3544  case ARM::t2STRB_POST:
3545  case ARM::t2STRB_PRE:
3546  case ARM::t2STRBs:
3547  case ARM::t2STRDi8:
3548  case ARM::t2STRH_POST:
3549  case ARM::t2STRH_PRE:
3550  case ARM::t2STRHs:
3551  case ARM::t2STR_POST:
3552  case ARM::t2STR_PRE:
3553  case ARM::t2STRs:
3554  return 2;
3555  }
3556 }
3557 
3558 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
3559 // can't be easily determined return 0 (missing MachineMemOperand).
3560 //
3561 // FIXME: The current MachineInstr design does not support relying on machine
3562 // mem operands to determine the width of a memory access. Instead, we expect
3563 // the target to provide this information based on the instruction opcode and
3564 // operands. However, using MachineMemOperand is the best solution now for
3565 // two reasons:
3566 //
3567 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
3568 // operands. This is much more dangerous than using the MachineMemOperand
3569 // sizes because CodeGen passes can insert/remove optional machine operands. In
3570 // fact, it's totally incorrect for preRA passes and appears to be wrong for
3571 // postRA passes as well.
3572 //
3573 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
3574 // machine model that calls this should handle the unknown (zero size) case.
3575 //
3576 // Long term, we should require a target hook that verifies MachineMemOperand
3577 // sizes during MC lowering. That target hook should be local to MC lowering
3578 // because we can't ensure that it is aware of other MI forms. Doing this will
3579 // ensure that MachineMemOperands are correctly propagated through all passes.
3581  unsigned Size = 0;
3583  E = MI.memoperands_end();
3584  I != E; ++I) {
3585  Size += (*I)->getSize();
3586  }
3587  // FIXME: The scheduler currently can't handle values larger than 16. But
3588  // the values can actually go up to 32 for floating-point load/store
3589  // multiple (VLDMIA etc.). Also, the way this code is reasoning about memory
3590  // operations isn't right; we could end up with "extra" memory operands for
3591  // various reasons, like tail merge merging two memory operations.
3592  return std::min(Size / 4, 16U);
3593 }
3594 
3595 static unsigned getNumMicroOpsSingleIssuePlusExtras(unsigned Opc,
3596  unsigned NumRegs) {
3597  unsigned UOps = 1 + NumRegs; // 1 for address computation.
3598  switch (Opc) {
3599  default:
3600  break;
3601  case ARM::VLDMDIA_UPD:
3602  case ARM::VLDMDDB_UPD:
3603  case ARM::VLDMSIA_UPD:
3604  case ARM::VLDMSDB_UPD:
3605  case ARM::VSTMDIA_UPD:
3606  case ARM::VSTMDDB_UPD:
3607  case ARM::VSTMSIA_UPD:
3608  case ARM::VSTMSDB_UPD:
3609  case ARM::LDMIA_UPD:
3610  case ARM::LDMDA_UPD:
3611  case ARM::LDMDB_UPD:
3612  case ARM::LDMIB_UPD:
3613  case ARM::STMIA_UPD:
3614  case ARM::STMDA_UPD:
3615  case ARM::STMDB_UPD:
3616  case ARM::STMIB_UPD:
3617  case ARM::tLDMIA_UPD:
3618  case ARM::tSTMIA_UPD:
3619  case ARM::t2LDMIA_UPD:
3620  case ARM::t2LDMDB_UPD:
3621  case ARM::t2STMIA_UPD:
3622  case ARM::t2STMDB_UPD:
3623  ++UOps; // One for base register writeback.
3624  break;
3625  case ARM::LDMIA_RET:
3626  case ARM::tPOP_RET:
3627  case ARM::t2LDMIA_RET:
3628  UOps += 2; // One for base reg wb, one for write to pc.
3629  break;
3630  }
3631  return UOps;
3632 }
3633 
3635  const MachineInstr &MI) const {
3636  if (!ItinData || ItinData->isEmpty())
3637  return 1;
3638 
3639  const MCInstrDesc &Desc = MI.getDesc();
3640  unsigned Class = Desc.getSchedClass();
3641  int ItinUOps = ItinData->getNumMicroOps(Class);
3642  if (ItinUOps >= 0) {
3643  if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3644  return getNumMicroOpsSwiftLdSt(ItinData, MI);
3645 
3646  return ItinUOps;
3647  }
3648 
3649  unsigned Opc = MI.getOpcode();
3650  switch (Opc) {
3651  default:
3652  llvm_unreachable("Unexpected multi-uops instruction!");
3653  case ARM::VLDMQIA:
3654  case ARM::VSTMQIA:
3655  return 2;
3656 
3657  // The number of uOps for load / store multiple are determined by the number
3658  // registers.
3659  //
3660  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3661  // same cycle. The scheduling for the first load / store must be done
3662  // separately by assuming the address is not 64-bit aligned.
3663  //
3664  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3665  // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3666  // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3667  case ARM::VLDMDIA:
3668  case ARM::VLDMDIA_UPD:
3669  case ARM::VLDMDDB_UPD:
3670  case ARM::VLDMSIA:
3671  case ARM::VLDMSIA_UPD:
3672  case ARM::VLDMSDB_UPD:
3673  case ARM::VSTMDIA:
3674  case ARM::VSTMDIA_UPD:
3675  case ARM::VSTMDDB_UPD:
3676  case ARM::VSTMSIA:
3677  case ARM::VSTMSIA_UPD:
3678  case ARM::VSTMSDB_UPD: {
3679  unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands();
3680  return (NumRegs / 2) + (NumRegs % 2) + 1;
3681  }
3682 
3683  case ARM::LDMIA_RET:
3684  case ARM::LDMIA:
3685  case ARM::LDMDA:
3686  case ARM::LDMDB:
3687  case ARM::LDMIB:
3688  case ARM::LDMIA_UPD:
3689  case ARM::LDMDA_UPD:
3690  case ARM::LDMDB_UPD:
3691  case ARM::LDMIB_UPD:
3692  case ARM::STMIA:
3693  case ARM::STMDA:
3694  case ARM::STMDB:
3695  case ARM::STMIB:
3696  case ARM::STMIA_UPD:
3697  case ARM::STMDA_UPD:
3698  case ARM::STMDB_UPD:
3699  case ARM::STMIB_UPD:
3700  case ARM::tLDMIA:
3701  case ARM::tLDMIA_UPD:
3702  case ARM::tSTMIA_UPD:
3703  case ARM::tPOP_RET:
3704  case ARM::tPOP:
3705  case ARM::tPUSH:
3706  case ARM::t2LDMIA_RET:
3707  case ARM::t2LDMIA:
3708  case ARM::t2LDMDB:
3709  case ARM::t2LDMIA_UPD:
3710  case ARM::t2LDMDB_UPD:
3711  case ARM::t2STMIA:
3712  case ARM::t2STMDB:
3713  case ARM::t2STMIA_UPD:
3714  case ARM::t2STMDB_UPD: {
3715  unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands() + 1;
3716  switch (Subtarget.getLdStMultipleTiming()) {
3718  return getNumMicroOpsSingleIssuePlusExtras(Opc, NumRegs);
3720  // Assume the worst.
3721  return NumRegs;
3723  if (NumRegs < 4)
3724  return 2;
3725  // 4 registers would be issued: 2, 2.
3726  // 5 registers would be issued: 2, 2, 1.
3727  unsigned UOps = (NumRegs / 2);
3728  if (NumRegs % 2)
3729  ++UOps;
3730  return UOps;
3731  }
3733  unsigned UOps = (NumRegs / 2);
3734  // If there are odd number of registers or if it's not 64-bit aligned,
3735  // then it takes an extra AGU (Address Generation Unit) cycle.
3736  if ((NumRegs % 2) || !MI.hasOneMemOperand() ||
3737  (*MI.memoperands_begin())->getAlignment() < 8)
3738  ++UOps;
3739  return UOps;
3740  }
3741  }
3742  }
3743  }
3744  llvm_unreachable("Didn't find the number of microops");
3745 }
3746 
3747 int
3748 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3749  const MCInstrDesc &DefMCID,
3750  unsigned DefClass,
3751  unsigned DefIdx, unsigned DefAlign) const {
3752  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3753  if (RegNo <= 0)
3754  // Def is the address writeback.
3755  return ItinData->getOperandCycle(DefClass, DefIdx);
3756 
3757  int DefCycle;
3758  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3759  // (regno / 2) + (regno % 2) + 1
3760  DefCycle = RegNo / 2 + 1;
3761  if (RegNo % 2)
3762  ++DefCycle;
3763  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3764  DefCycle = RegNo;
3765  bool isSLoad = false;
3766 
3767  switch (DefMCID.getOpcode()) {
3768  default: break;
3769  case ARM::VLDMSIA:
3770  case ARM::VLDMSIA_UPD:
3771  case ARM::VLDMSDB_UPD:
3772  isSLoad = true;
3773  break;
3774  }
3775 
3776  // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3777  // then it takes an extra cycle.
3778  if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3779  ++DefCycle;
3780  } else {
3781  // Assume the worst.
3782  DefCycle = RegNo + 2;
3783  }
3784 
3785  return DefCycle;
3786 }
3787 
3789  Register BaseReg = MI.getOperand(0).getReg();
3790  for (unsigned i = 1, sz = MI.getNumOperands(); i < sz; ++i) {
3791  const auto &Op = MI.getOperand(i);
3792  if (Op.isReg() && Op.getReg() == BaseReg)
3793  return true;
3794  }
3795  return false;
3796 }
3797 unsigned
3799  // ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops
3800  // (outs GPR:$wb), (ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops)
3801  return MI.getNumOperands() + 1 - MI.getDesc().getNumOperands();
3802 }
3803 
3804 int
3805 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3806  const MCInstrDesc &DefMCID,
3807  unsigned DefClass,
3808  unsigned DefIdx, unsigned DefAlign) const {
3809  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3810  if (RegNo <= 0)
3811  // Def is the address writeback.
3812  return ItinData->getOperandCycle(DefClass, DefIdx);
3813 
3814  int DefCycle;
3815  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3816  // 4 registers would be issued: 1, 2, 1.
3817  // 5 registers would be issued: 1, 2, 2.
3818  DefCycle = RegNo / 2;
3819  if (DefCycle < 1)
3820  DefCycle = 1;
3821  // Result latency is issue cycle + 2: E2.
3822  DefCycle += 2;
3823  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3824  DefCycle = (RegNo / 2);
3825  // If there are odd number of registers or if it's not 64-bit aligned,
3826  // then it takes an extra AGU (Address Generation Unit) cycle.
3827  if ((RegNo % 2) || DefAlign < 8)
3828  ++DefCycle;
3829  // Result latency is AGU cycles + 2.
3830  DefCycle += 2;
3831  } else {
3832  // Assume the worst.
3833  DefCycle = RegNo + 2;
3834  }
3835 
3836  return DefCycle;
3837 }
3838 
3839 int
3840 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3841  const MCInstrDesc &UseMCID,
3842  unsigned UseClass,
3843  unsigned UseIdx, unsigned UseAlign) const {
3844  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3845  if (RegNo <= 0)
3846  return ItinData->getOperandCycle(UseClass, UseIdx);
3847 
3848  int UseCycle;
3849  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3850  // (regno / 2) + (regno % 2) + 1
3851  UseCycle = RegNo / 2 + 1;
3852  if (RegNo % 2)
3853  ++UseCycle;
3854  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3855  UseCycle = RegNo;
3856  bool isSStore = false;
3857 
3858  switch (UseMCID.getOpcode()) {
3859  default: break;
3860  case ARM::VSTMSIA:
3861  case ARM::VSTMSIA_UPD:
3862  case ARM::VSTMSDB_UPD:
3863  isSStore = true;
3864  break;
3865  }
3866 
3867  // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3868  // then it takes an extra cycle.
3869  if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3870  ++UseCycle;
3871  } else {
3872  // Assume the worst.
3873  UseCycle = RegNo + 2;
3874  }
3875 
3876  return UseCycle;
3877 }
3878 
3879 int
3880 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3881  const MCInstrDesc &UseMCID,
3882  unsigned UseClass,
3883  unsigned UseIdx, unsigned UseAlign) const {
3884  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3885  if (RegNo <= 0)
3886  return ItinData->getOperandCycle(UseClass, UseIdx);
3887 
3888  int UseCycle;
3889  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3890  UseCycle = RegNo / 2;
3891  if (UseCycle < 2)
3892  UseCycle = 2;
3893  // Read in E3.
3894  UseCycle += 2;
3895  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3896  UseCycle = (RegNo / 2);
3897  // If there are odd number of registers or if it's not 64-bit aligned,
3898  // then it takes an extra AGU (Address Generation Unit) cycle.
3899  if ((RegNo % 2) || UseAlign < 8)
3900  ++UseCycle;
3901  } else {
3902  // Assume the worst.
3903  UseCycle = 1;
3904  }
3905  return UseCycle;
3906 }
3907 
3908 int
3910  const MCInstrDesc &DefMCID,
3911  unsigned DefIdx, unsigned DefAlign,
3912  const MCInstrDesc &UseMCID,
3913  unsigned UseIdx, unsigned UseAlign) const {
3914  unsigned DefClass = DefMCID.getSchedClass();
3915  unsigned UseClass = UseMCID.getSchedClass();
3916 
3917  if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3918  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3919 
3920  // This may be a def / use of a variable_ops instruction, the operand
3921  // latency might be determinable dynamically. Let the target try to
3922  // figure it out.
3923  int DefCycle = -1;
3924  bool LdmBypass = false;
3925  switch (DefMCID.getOpcode()) {
3926  default:
3927  DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3928  break;
3929 
3930  case ARM::VLDMDIA:
3931  case ARM::VLDMDIA_UPD:
3932  case ARM::VLDMDDB_UPD:
3933  case ARM::VLDMSIA:
3934  case ARM::VLDMSIA_UPD:
3935  case ARM::VLDMSDB_UPD:
3936  DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3937  break;
3938 
3939  case ARM::LDMIA_RET:
3940  case ARM::LDMIA:
3941  case ARM::LDMDA:
3942  case ARM::LDMDB:
3943  case ARM::LDMIB:
3944  case ARM::LDMIA_UPD:
3945  case ARM::LDMDA_UPD:
3946  case ARM::LDMDB_UPD:
3947  case ARM::LDMIB_UPD:
3948  case ARM::tLDMIA:
3949  case ARM::tLDMIA_UPD:
3950  case ARM::tPUSH:
3951  case ARM::t2LDMIA_RET:
3952  case ARM::t2LDMIA:
3953  case ARM::t2LDMDB:
3954  case ARM::t2LDMIA_UPD:
3955  case ARM::t2LDMDB_UPD:
3956  LdmBypass = true;
3957  DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3958  break;
3959  }
3960 
3961  if (DefCycle == -1)
3962  // We can't seem to determine the result latency of the def, assume it's 2.
3963  DefCycle = 2;
3964 
3965  int UseCycle = -1;
3966  switch (UseMCID.getOpcode()) {
3967  default:
3968  UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3969  break;
3970 
3971  case ARM::VSTMDIA:
3972  case ARM::VSTMDIA_UPD:
3973  case ARM::VSTMDDB_UPD:
3974  case ARM::VSTMSIA:
3975  case ARM::VSTMSIA_UPD:
3976  case ARM::VSTMSDB_UPD:
3977  UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3978  break;
3979 
3980  case ARM::STMIA:
3981  case ARM::STMDA:
3982  case ARM::STMDB:
3983  case ARM::STMIB:
3984  case ARM::STMIA_UPD:
3985  case ARM::STMDA_UPD:
3986  case ARM::STMDB_UPD:
3987  case ARM::STMIB_UPD:
3988  case ARM::tSTMIA_UPD:
3989  case ARM::tPOP_RET:
3990  case ARM::tPOP:
3991  case ARM::t2STMIA:
3992  case ARM::t2STMDB:
3993  case ARM::t2STMIA_UPD:
3994  case ARM::t2STMDB_UPD:
3995  UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3996  break;
3997  }
3998 
3999  if (UseCycle == -1)
4000  // Assume it's read in the first stage.
4001  UseCycle = 1;
4002 
4003  UseCycle = DefCycle - UseCycle + 1;
4004  if (UseCycle > 0) {
4005  if (LdmBypass) {
4006  // It's a variable_ops instruction so we can't use DefIdx here. Just use
4007  // first def operand.
4008  if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
4009  UseClass, UseIdx))
4010  --UseCycle;
4011  } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
4012  UseClass, UseIdx)) {
4013  --UseCycle;
4014  }
4015  }
4016 
4017  return UseCycle;
4018 }
4019 
4021  const MachineInstr *MI, unsigned Reg,
4022  unsigned &DefIdx, unsigned &Dist) {
4023  Dist = 0;
4024 
4027  assert(II->isInsideBundle() && "Empty bundle?");
4028 
4029  int Idx = -1;
4030  while (II->isInsideBundle()) {
4031  Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
4032  if (Idx != -1)
4033  break;
4034  --II;
4035  ++Dist;
4036  }
4037 
4038  assert(Idx != -1 && "Cannot find bundled definition!");
4039  DefIdx = Idx;
4040  return &*II;
4041 }
4042 
4044  const MachineInstr &MI, unsigned Reg,
4045  unsigned &UseIdx, unsigned &Dist) {
4046  Dist = 0;
4047 
4049  assert(II->isInsideBundle() && "Empty bundle?");
4051 
4052  // FIXME: This doesn't properly handle multiple uses.
4053  int Idx = -1;
4054  while (II != E && II->isInsideBundle()) {
4055  Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
4056  if (Idx != -1)
4057  break;
4058  if (II->getOpcode() != ARM::t2IT)
4059  ++Dist;
4060  ++II;
4061  }
4062 
4063  if (Idx == -1) {
4064  Dist = 0;
4065  return nullptr;
4066  }
4067 
4068  UseIdx = Idx;
4069  return &*II;
4070 }
4071 
4072 /// Return the number of cycles to add to (or subtract from) the static
4073 /// itinerary based on the def opcode and alignment. The caller will ensure that
4074 /// adjusted latency is at least one cycle.
4075 static int adjustDefLatency(const ARMSubtarget &Subtarget,
4076  const MachineInstr &DefMI,
4077  const MCInstrDesc &DefMCID, unsigned DefAlign) {
4078  int Adjust = 0;
4079  if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
4080  // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
4081  // variants are one cycle cheaper.
4082  switch (DefMCID.getOpcode()) {
4083  default: break;
4084  case ARM::LDRrs:
4085  case ARM::LDRBrs: {
4086  unsigned ShOpVal = DefMI.getOperand(3).getImm();
4087  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4088  if (ShImm == 0 ||
4089  (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4090  --Adjust;
4091  break;
4092  }
4093  case ARM::t2LDRs:
4094  case ARM::t2LDRBs:
4095  case ARM::t2LDRHs:
4096  case ARM::t2LDRSHs: {
4097  // Thumb2 mode: lsl only.
4098  unsigned ShAmt = DefMI.getOperand(3).getImm();
4099  if (ShAmt == 0 || ShAmt == 2)
4100  --Adjust;
4101  break;
4102  }
4103  }
4104  } else if (Subtarget.isSwift()) {
4105  // FIXME: Properly handle all of the latency adjustments for address
4106  // writeback.
4107  switch (DefMCID.getOpcode()) {
4108  default: break;
4109  case ARM::LDRrs:
4110  case ARM::LDRBrs: {
4111  unsigned ShOpVal = DefMI.getOperand(3).getImm();
4112  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
4113  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4114  if (!isSub &&
4115  (ShImm == 0 ||
4116  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
4117  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
4118  Adjust -= 2;
4119  else if (!isSub &&
4120  ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
4121  --Adjust;
4122  break;
4123  }
4124  case ARM::t2LDRs:
4125  case ARM::t2LDRBs:
4126  case ARM::t2LDRHs:
4127  case ARM::t2LDRSHs: {
4128  // Thumb2 mode: lsl only.
4129  unsigned ShAmt = DefMI.getOperand(3).getImm();
4130  if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
4131  Adjust -= 2;
4132  break;
4133  }
4134  }
4135  }
4136 
4137  if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) {
4138  switch (DefMCID.getOpcode()) {
4139  default: break;
4140  case ARM::VLD1q8:
4141  case ARM::VLD1q16:
4142  case ARM::VLD1q32:
4143  case ARM::VLD1q64:
4144  case ARM::VLD1q8wb_fixed:
4145  case ARM::VLD1q16wb_fixed:
4146  case ARM::VLD1q32wb_fixed:
4147  case ARM::VLD1q64wb_fixed:
4148  case ARM::VLD1q8wb_register:
4149  case ARM::VLD1q16wb_register:
4150  case ARM::VLD1q32wb_register:
4151  case ARM::VLD1q64wb_register:
4152  case ARM::VLD2d8:
4153  case ARM::VLD2d16:
4154  case ARM::VLD2d32:
4155  case ARM::VLD2q8:
4156  case ARM::VLD2q16:
4157  case ARM::VLD2q32:
4158  case ARM::VLD2d8wb_fixed:
4159  case ARM::VLD2d16wb_fixed:
4160  case ARM::VLD2d32wb_fixed:
4161  case ARM::VLD2q8wb_fixed:
4162  case ARM::VLD2q16wb_fixed:
4163  case ARM::VLD2q32wb_fixed:
4164  case ARM::VLD2d8wb_register:
4165  case ARM::VLD2d16wb_register:
4166  case ARM::VLD2d32wb_register:
4167  case ARM::VLD2q8wb_register:
4168  case ARM::VLD2q16wb_register:
4169  case ARM::VLD2q32wb_register:
4170  case ARM::VLD3d8:
4171  case ARM::VLD3d16:
4172  case ARM::VLD3d32:
4173  case ARM::VLD1d64T:
4174  case ARM::VLD3d8_UPD:
4175  case ARM::VLD3d16_UPD:
4176  case ARM::VLD3d32_UPD:
4177  case ARM::VLD1d64Twb_fixed:
4178  case ARM::VLD1d64Twb_register:
4179  case ARM::VLD3q8_UPD:
4180  case ARM::VLD3q16_UPD:
4181  case ARM::VLD3q32_UPD:
4182  case ARM::VLD4d8:
4183  case ARM::VLD4d16:
4184  case ARM::VLD4d32:
4185  case ARM::VLD1d64Q:
4186  case ARM::VLD4d8_UPD:
4187  case ARM::VLD4d16_UPD:
4188  case ARM::VLD4d32_UPD:
4189  case ARM::VLD1d64Qwb_fixed:
4190  case ARM::VLD1d64Qwb_register:
4191  case ARM::VLD4q8_UPD:
4192  case ARM::VLD4q16_UPD:
4193  case ARM::VLD4q32_UPD:
4194  case ARM::VLD1DUPq8:
4195  case ARM::VLD1DUPq16:
4196  case ARM::VLD1DUPq32:
4197  case ARM::VLD1DUPq8wb_fixed:
4198  case ARM::VLD1DUPq16wb_fixed:
4199  case ARM::VLD1DUPq32wb_fixed:
4200  case ARM::VLD1DUPq8wb_register:
4201  case ARM::VLD1DUPq16wb_register:
4202  case ARM::VLD1DUPq32wb_register:
4203  case ARM::VLD2DUPd8:
4204  case ARM::VLD2DUPd16:
4205  case ARM::VLD2DUPd32:
4206  case ARM::VLD2DUPd8wb_fixed:
4207  case ARM::VLD2DUPd16wb_fixed:
4208  case ARM::VLD2DUPd32wb_fixed:
4209  case ARM::VLD2DUPd8wb_register:
4210  case ARM::VLD2DUPd16wb_register:
4211  case ARM::VLD2DUPd32wb_register:
4212  case ARM::VLD4DUPd8:
4213  case ARM::VLD4DUPd16:
4214  case ARM::VLD4DUPd32:
4215  case ARM::VLD4DUPd8_UPD:
4216  case ARM::VLD4DUPd16_UPD:
4217  case ARM::VLD4DUPd32_UPD:
4218  case ARM::VLD1LNd8:
4219  case ARM::VLD1LNd16:
4220  case ARM::VLD1LNd32:
4221  case ARM::VLD1LNd8_UPD:
4222  case ARM::VLD1LNd16_UPD:
4223  case ARM::VLD1LNd32_UPD:
4224  case ARM::VLD2LNd8:
4225  case ARM::VLD2LNd16:
4226  case ARM::VLD2LNd32:
4227  case ARM::VLD2LNq16:
4228  case ARM::VLD2LNq32:
4229  case ARM::VLD2LNd8_UPD:
4230  case ARM::VLD2LNd16_UPD:
4231  case ARM::VLD2LNd32_UPD:
4232  case ARM::VLD2LNq16_UPD:
4233  case ARM::VLD2LNq32_UPD:
4234  case ARM::VLD4LNd8:
4235  case ARM::VLD4LNd16:
4236  case ARM::VLD4LNd32:
4237  case ARM::VLD4LNq16:
4238  case ARM::VLD4LNq32:
4239  case ARM::VLD4LNd8_UPD:
4240  case ARM::VLD4LNd16_UPD:
4241  case ARM::VLD4LNd32_UPD:
4242  case ARM::VLD4LNq16_UPD:
4243  case ARM::VLD4LNq32_UPD:
4244  // If the address is not 64-bit aligned, the latencies of these
4245  // instructions increases by one.
4246  ++Adjust;
4247  break;
4248  }
4249  }
4250  return Adjust;
4251 }
4252 
4254  const MachineInstr &DefMI,
4255  unsigned DefIdx,
4256  const MachineInstr &UseMI,
4257  unsigned UseIdx) const {
4258  // No operand latency. The caller may fall back to getInstrLatency.
4259  if (!ItinData || ItinData->isEmpty())
4260  return -1;
4261 
4262  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4263  Register Reg = DefMO.getReg();
4264 
4265  const MachineInstr *ResolvedDefMI = &DefMI;
4266  unsigned DefAdj = 0;
4267  if (DefMI.isBundle())
4268  ResolvedDefMI =
4269  getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);
4270  if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() ||
4271  ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) {
4272  return 1;
4273  }
4274 
4275  const MachineInstr *ResolvedUseMI = &UseMI;
4276  unsigned UseAdj = 0;
4277  if (UseMI.isBundle()) {
4278  ResolvedUseMI =
4279  getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
4280  if (!ResolvedUseMI)
4281  return -1;
4282  }
4283 
4284  return getOperandLatencyImpl(
4285  ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4286  Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
4287 }
4288 
4289 int ARMBaseInstrInfo::getOperandLatencyImpl(
4290  const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4291  unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
4292  const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
4293  unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
4294  if (Reg == ARM::CPSR) {
4295  if (DefMI.getOpcode() == ARM::FMSTAT) {
4296  // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
4297  return Subtarget.isLikeA9() ? 1 : 20;
4298  }
4299 
4300  // CPSR set and branch can be paired in the same cycle.
4301  if (UseMI.isBranch())
4302  return 0;
4303 
4304  // Otherwise it takes the instruction latency (generally one).
4305  unsigned Latency = getInstrLatency(ItinData, DefMI);
4306 
4307  // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
4308  // its uses. Instructions which are otherwise scheduled between them may
4309  // incur a code size penalty (not able to use the CPSR setting 16-bit
4310  // instructions).
4311  if (Latency > 0 && Subtarget.isThumb2()) {
4312  const MachineFunction *MF = DefMI.getParent()->getParent();
4313  // FIXME: Use Function::hasOptSize().
4314  if (MF->getFunction().hasFnAttribute(Attribute::OptimizeForSize))
4315  --Latency;
4316  }
4317  return Latency;
4318  }
4319 
4320  if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4321  return -1;
4322 
4323  unsigned DefAlign = DefMI.hasOneMemOperand()
4324  ? (*DefMI.memoperands_begin())->getAlignment()
4325  : 0;
4326  unsigned UseAlign = UseMI.hasOneMemOperand()
4327  ? (*UseMI.memoperands_begin())->getAlignment()
4328  : 0;
4329 
4330  // Get the itinerary's latency if possible, and handle variable_ops.
4331  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,
4332  UseIdx, UseAlign);
4333  // Unable to find operand latency. The caller may resort to getInstrLatency.
4334  if (Latency < 0)
4335  return Latency;
4336 
4337  // Adjust for IT block position.
4338  int Adj = DefAdj + UseAdj;
4339 
4340  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4341  Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
4342  if (Adj >= 0 || (int)Latency > -Adj) {
4343  return Latency + Adj;
4344  }
4345  // Return the itinerary latency, which may be zero but not less than zero.
4346  return Latency;
4347 }
4348 
4349 int
4351  SDNode *DefNode, unsigned DefIdx,
4352  SDNode *UseNode, unsigned UseIdx) const {
4353  if (!DefNode->isMachineOpcode())
4354  return 1;
4355 
4356  const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4357 
4358  if (isZeroCost(DefMCID.Opcode))
4359  return 0;
4360 
4361  if (!ItinData || ItinData->isEmpty())
4362  return DefMCID.mayLoad() ? 3 : 1;
4363 
4364  if (!UseNode->isMachineOpcode()) {
4365  int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4366  int Adj = Subtarget.getPreISelOperandLatencyAdjustment();
4367  int Threshold = 1 + Adj;
4368  return Latency <= Threshold ? 1 : Latency - Adj;
4369  }
4370 
4371  const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
4372  auto *DefMN = cast<MachineSDNode>(DefNode);
4373  unsigned DefAlign = !DefMN->memoperands_empty()
4374  ? (*DefMN->memoperands_begin())->getAlignment() : 0;
4375  auto *UseMN = cast<MachineSDNode>(UseNode);
4376  unsigned UseAlign = !UseMN->memoperands_empty()
4377  ? (*UseMN->memoperands_begin())->getAlignment() : 0;
4378  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
4379  UseMCID, UseIdx, UseAlign);
4380 
4381  if (Latency > 1 &&
4382  (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
4383  Subtarget.isCortexA7())) {
4384  // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
4385  // variants are one cycle cheaper.
4386  switch (DefMCID.getOpcode()) {
4387  default: break;
4388  case ARM::LDRrs:
4389  case ARM::LDRBrs: {
4390  unsigned ShOpVal =
4391  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4392  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4393  if (ShImm == 0 ||
4394  (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4395  --Latency;
4396  break;
4397  }
4398  case ARM::t2LDRs:
4399  case ARM::t2LDRBs:
4400  case ARM::t2LDRHs:
4401  case ARM::t2LDRSHs: {
4402  // Thumb2 mode: lsl only.
4403  unsigned ShAmt =
4404  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4405  if (ShAmt == 0 || ShAmt == 2)
4406  --Latency;
4407  break;
4408  }
4409  }
4410  } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
4411  // FIXME: Properly handle all of the latency adjustments for address
4412  // writeback.
4413  switch (DefMCID.getOpcode()) {
4414  default: break;
4415  case ARM::LDRrs:
4416  case ARM::LDRBrs: {
4417  unsigned ShOpVal =
4418  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4419  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4420  if (ShImm == 0 ||
4421  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
4422  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4423  Latency -= 2;
4424  else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
4425  --Latency;
4426  break;
4427  }
4428  case ARM::t2LDRs:
4429  case ARM::t2LDRBs:
4430  case ARM::t2LDRHs:
4431  case ARM::t2LDRSHs:
4432  // Thumb2 mode: lsl 0-3 only.
4433  Latency -= 2;
4434  break;
4435  }
4436  }
4437 
4438  if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment())
4439  switch (DefMCID.getOpcode()) {
4440  default: break;
4441  case ARM::VLD1q8:
4442  case ARM::VLD1q16:
4443  case ARM::VLD1q32:
4444  case ARM::VLD1q64:
4445  case ARM::VLD1q8wb_register:
4446  case ARM::VLD1q16wb_register:
4447  case ARM::VLD1q32wb_register:
4448  case ARM::VLD1q64wb_register:
4449  case ARM::VLD1q8wb_fixed:
4450  case ARM::VLD1q16wb_fixed:
4451  case ARM::VLD1q32wb_fixed:
4452  case ARM::VLD1q64wb_fixed:
4453  case ARM::VLD2d8:
4454  case ARM::VLD2d16:
4455  case ARM::VLD2d32:
4456  case ARM::VLD2q8Pseudo:
4457  case ARM::VLD2q16Pseudo:
4458  case ARM::VLD2q32Pseudo:
4459  case ARM::VLD2d8wb_fixed:
4460  case ARM::VLD2d16wb_fixed:
4461  case ARM::VLD2d32wb_fixed:
4462  case ARM::VLD2q8PseudoWB_fixed:
4463  case ARM::VLD2q16PseudoWB_fixed:
4464  case ARM::VLD2q32PseudoWB_fixed:
4465  case ARM::VLD2d8wb_register:
4466  case ARM::VLD2d16wb_register:
4467  case ARM::VLD2d32wb_register:
4468  case ARM::VLD2q8PseudoWB_register:
4469  case ARM::VLD2q16PseudoWB_register:
4470  case ARM::VLD2q32PseudoWB_register:
4471  case ARM::VLD3d8Pseudo:
4472  case ARM::VLD3d16Pseudo:
4473  case ARM::VLD3d32Pseudo:
4474  case ARM::VLD1d8TPseudo:
4475  case ARM::VLD1d16TPseudo:
4476  case ARM::VLD1d32TPseudo:
4477  case ARM::VLD1d64TPseudo:
4478  case ARM::VLD1d64TPseudoWB_fixed:
4479  case ARM::VLD1d64TPseudoWB_register:
4480  case ARM::VLD3d8Pseudo_UPD:
4481  case ARM::VLD3d16Pseudo_UPD:
4482  case ARM::VLD3d32Pseudo_UPD:
4483  case ARM::VLD3q8Pseudo_UPD:
4484  case ARM::VLD3q16Pseudo_UPD:
4485  case ARM::VLD3q32Pseudo_UPD:
4486  case ARM::VLD3q8oddPseudo:
4487  case ARM::VLD3q16oddPseudo:
4488  case ARM::VLD3q32oddPseudo:
4489  case ARM::VLD3q8oddPseudo_UPD:
4490  case ARM::VLD3q16oddPseudo_UPD:
4491  case ARM::VLD3q32oddPseudo_UPD:
4492  case ARM::VLD4d8Pseudo:
4493  case ARM::VLD4d16Pseudo:
4494  case ARM::VLD4d32Pseudo:
4495  case ARM::VLD1d8QPseudo:
4496  case ARM::VLD1d16QPseudo:
4497  case ARM::VLD1d32QPseudo:
4498  case ARM::VLD1d64QPseudo:
4499  case ARM::VLD1d64QPseudoWB_fixed:
4500  case ARM::VLD1d64QPseudoWB_register:
4501  case ARM::VLD1q8HighQPseudo:
4502  case ARM::VLD1q8LowQPseudo_UPD:
4503  case ARM::VLD1q8HighTPseudo:
4504  case ARM::VLD1q8LowTPseudo_UPD:
4505  case ARM::VLD1q16HighQPseudo:
4506  case ARM::VLD1q16LowQPseudo_UPD:
4507  case ARM::VLD1q16HighTPseudo:
4508  case ARM::VLD1q16LowTPseudo_UPD:
4509  case ARM::VLD1q32HighQPseudo:
4510  case ARM::VLD1q32LowQPseudo_UPD:
4511  case ARM::VLD1q32HighTPseudo:
4512  case ARM::VLD1q32LowTPseudo_UPD:
4513  case ARM::VLD1q64HighQPseudo:
4514  case ARM::VLD1q64LowQPseudo_UPD:
4515  case ARM::VLD1q64HighTPseudo:
4516  case ARM::VLD1q64LowTPseudo_UPD:
4517  case ARM::VLD4d8Pseudo_UPD:
4518  case ARM::VLD4d16Pseudo_UPD:
4519  case ARM::VLD4d32Pseudo_UPD:
4520  case ARM::VLD4q8Pseudo_UPD:
4521  case ARM::VLD4q16Pseudo_UPD:
4522  case ARM::VLD4q32Pseudo_UPD:
4523  case ARM::VLD4q8oddPseudo:
4524  case ARM::VLD4q16oddPseudo:
4525  case ARM::VLD4q32oddPseudo:
4526  case ARM::VLD4q8oddPseudo_UPD:
4527  case ARM::VLD4q16oddPseudo_UPD:
4528  case ARM::VLD4q32oddPseudo_UPD:
4529  case ARM::VLD1DUPq8:
4530  case ARM::VLD1DUPq16:
4531  case ARM::VLD1DUPq32:
4532  case ARM::VLD1DUPq8wb_fixed:
4533  case ARM::VLD1DUPq16wb_fixed:
4534  case ARM::VLD1DUPq32wb_fixed:
4535  case ARM::VLD1DUPq8wb_register:
4536  case ARM::VLD1DUPq16wb_register:
4537  case ARM::VLD1DUPq32wb_register:
4538  case ARM::VLD2DUPd8:
4539  case ARM::VLD2DUPd16:
4540  case ARM::VLD2DUPd32:
4541  case ARM::VLD2DUPd8wb_fixed:
4542  case ARM::VLD2DUPd16wb_fixed:
4543  case ARM::VLD2DUPd32wb_fixed:
4544  case ARM::VLD2DUPd8wb_register:
4545  case ARM::VLD2DUPd16wb_register:
4546  case ARM::VLD2DUPd32wb_register:
4547  case ARM::VLD2DUPq8EvenPseudo:
4548  case ARM::VLD2DUPq8OddPseudo:
4549  case ARM::VLD2DUPq16EvenPseudo:
4550  case ARM::VLD2DUPq16OddPseudo:
4551  case ARM::VLD2DUPq32EvenPseudo:
4552  case ARM::VLD2DUPq32OddPseudo:
4553  case ARM::VLD3DUPq8EvenPseudo:
4554  case ARM::VLD3DUPq8OddPseudo:
4555  case ARM::VLD3DUPq16EvenPseudo:
4556  case ARM::VLD3DUPq16OddPseudo:
4557  case ARM::VLD3DUPq32EvenPseudo:
4558  case ARM::VLD3DUPq32OddPseudo:
4559  case ARM::VLD4DUPd8Pseudo:
4560  case ARM::VLD4DUPd16Pseudo:
4561  case ARM::VLD4DUPd32Pseudo:
4562  case ARM::VLD4DUPd8Pseudo_UPD:
4563  case ARM::VLD4DUPd16Pseudo_UPD:
4564  case ARM::VLD4DUPd32Pseudo_UPD:
4565  case ARM::VLD4DUPq8EvenPseudo:
4566  case ARM::VLD4DUPq8OddPseudo:
4567  case ARM::VLD4DUPq16EvenPseudo:
4568  case ARM::VLD4DUPq16OddPseudo:
4569  case ARM::VLD4DUPq32EvenPseudo:
4570  case ARM::VLD4DUPq32OddPseudo:
4571  case ARM::VLD1LNq8Pseudo:
4572  case ARM::VLD1LNq16Pseudo:
4573  case ARM::VLD1LNq32Pseudo:
4574  case ARM::VLD1LNq8Pseudo_UPD:
4575  case ARM::VLD1LNq16Pseudo_UPD:
4576  case ARM::VLD1LNq32Pseudo_UPD:
4577  case ARM::VLD2LNd8Pseudo:
4578  case ARM::VLD2LNd16Pseudo:
4579  case ARM::VLD2LNd32Pseudo:
4580  case ARM::VLD2LNq16Pseudo:
4581  case ARM::VLD2LNq32Pseudo:
4582  case ARM::VLD2LNd8Pseudo_UPD:
4583  case ARM::VLD2LNd16Pseudo_UPD:
4584  case ARM::VLD2LNd32Pseudo_UPD:
4585  case ARM::VLD2LNq16Pseudo_UPD:
4586  case ARM::VLD2LNq32Pseudo_UPD:
4587  case ARM::VLD4LNd8Pseudo:
4588  case ARM::VLD4LNd16Pseudo:
4589  case ARM::VLD4LNd32Pseudo:
4590  case ARM::VLD4LNq16Pseudo:
4591  case ARM::VLD4LNq32Pseudo:
4592  case ARM::VLD4LNd8Pseudo_UPD:
4593  case ARM::VLD4LNd16Pseudo_UPD:
4594  case ARM::VLD4LNd32Pseudo_UPD:
4595  case ARM::VLD4LNq16Pseudo_UPD:
4596  case ARM::VLD4LNq32Pseudo_UPD:
4597  // If the address is not 64-bit aligned, the latencies of these
4598  // instructions increases by one.
4599  ++Latency;
4600  break;
4601  }
4602 
4603  return Latency;
4604 }
4605 
4606 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4607  if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4608  MI.isImplicitDef())
4609  return 0;
4610 
4611  if (MI.isBundle())
4612  return 0;
4613 
4614  const MCInstrDesc &MCID = MI.getDesc();
4615 
4616  if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4617  !Subtarget.cheapPredicableCPSRDef())) {
4618  // When predicated, CPSR is an additional source operand for CPSR updating
4619  // instructions, this apparently increases their latencies.
4620  return 1;
4621  }
4622  return 0;
4623 }
4624 
4625 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4626  const MachineInstr &MI,
4627  unsigned *PredCost) const {
4628  if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4629  MI.isImplicitDef())
4630  return 1;
4631 
4632  // An instruction scheduler typically runs on unbundled instructions, however
4633  // other passes may query the latency of a bundled instruction.
4634  if (MI.isBundle()) {
4635  unsigned Latency = 0;
4638  while (++I != E && I->isInsideBundle()) {
4639  if (I->getOpcode() != ARM::t2IT)
4640  Latency += getInstrLatency(ItinData, *I, PredCost);
4641  }
4642  return Latency;
4643  }
4644 
4645  const MCInstrDesc &MCID = MI.getDesc();
4646  if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4647  !Subtarget.cheapPredicableCPSRDef()))) {
4648  // When predicated, CPSR is an additional source operand for CPSR updating
4649  // instructions, this apparently increases their latencies.
4650  *PredCost = 1;
4651  }
4652  // Be sure to call getStageLatency for an empty itinerary in case it has a
4653  // valid MinLatency property.
4654  if (!ItinData)
4655  return MI.mayLoad() ? 3 : 1;
4656 
4657  unsigned Class = MCID.getSchedClass();
4658 
4659  // For instructions with variable uops, use uops as latency.
4660  if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4661  return getNumMicroOps(ItinData, MI);
4662 
4663  // For the common case, fall back on the itinerary's latency.
4664  unsigned Latency = ItinData->getStageLatency(Class);
4665 
4666  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4667  unsigned DefAlign =
4668  MI.hasOneMemOperand() ? (*MI.memoperands_begin())->getAlignment() : 0;
4669  int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign);
4670  if (Adj >= 0 || (int)Latency > -Adj) {
4671  return Latency + Adj;
4672  }
4673  return Latency;
4674 }
4675 
4676 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4677  SDNode *Node) const {
4678  if (!Node->isMachineOpcode())
4679  return 1;
4680 
4681  if (!ItinData || ItinData->isEmpty())
4682  return 1;
4683 
4684  unsigned Opcode = Node->getMachineOpcode();
4685  switch (Opcode) {
4686  default:
4687  return ItinData->getStageLatency(get(Opcode).getSchedClass());
4688  case ARM::VLDMQIA:
4689  case ARM::VSTMQIA:
4690  return 2;
4691  }
4692 }
4693 
4694 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4695  const MachineRegisterInfo *MRI,
4696  const MachineInstr &DefMI,
4697  unsigned DefIdx,
4698  const MachineInstr &UseMI,
4699  unsigned UseIdx) const {
4700  unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4701  unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
4702  if (Subtarget.nonpipelinedVFP() &&
4703  (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4704  return true;
4705 
4706  // Hoist VFP / NEON instructions with 4 or higher latency.
4707  unsigned Latency =
4708  SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4709  if (Latency <= 3)
4710  return false;
4711  return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4712  UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4713 }
4714 
4715 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4716  const MachineInstr &DefMI,
4717  unsigned DefIdx) const {
4718  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4719  if (!ItinData || ItinData->isEmpty())
4720  return false;
4721 
4722  unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4723  if (DDomain == ARMII::DomainGeneral) {
4724  unsigned DefClass = DefMI.getDesc().getSchedClass();
4725  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4726  return (DefCycle != -1 && DefCycle <= 2);
4727  }
4728  return false;
4729 }
4730 
4731 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4732  StringRef &ErrInfo) const {
4733  if (convertAddSubFlagsOpcode(MI.getOpcode())) {
4734  ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4735  return false;
4736  }
4737  if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) {
4738  // Make sure we don't generate a lo-lo mov that isn't supported.
4739  if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) &&
4740  !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) {
4741  ErrInfo = "Non-flag-setting Thumb1 mov is v6-only";
4742  return false;
4743  }
4744  }
4745  if (MI.getOpcode() == ARM::tPUSH ||
4746  MI.getOpcode() == ARM::tPOP ||
4747  MI.getOpcode() == ARM::tPOP_RET) {
4748  for (int i = 2, e = MI.getNumOperands(); i < e; ++i) {
4749  if (MI.getOperand(i).isImplicit() ||
4750  !MI.getOperand(i).isReg())
4751  continue;
4752  Register Reg = MI.getOperand(i).getReg();
4753  if (Reg < ARM::R0 || Reg > ARM::R7) {
4754  if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) &&
4755  !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) {
4756  ErrInfo = "Unsupported register in Thumb1 push/pop";
4757  return false;
4758  }
4759  }
4760  }
4761  }
4762  return true;
4763 }
4764 
4765 // LoadStackGuard has so far only been implemented for MachO. Different code
4766 // sequence is needed for other targets.
4768  unsigned LoadImmOpc,
4769  unsigned LoadOpc) const {
4770  assert(!Subtarget.isROPI() && !Subtarget.isRWPI() &&
4771  "ROPI/RWPI not currently supported with stack guard");
4772 
4773  MachineBasicBlock &MBB = *MI->getParent();
4774  DebugLoc DL = MI->getDebugLoc();
4775  Register Reg = MI->getOperand(0).getReg();
4776  const GlobalValue *GV =
4777  cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4778  MachineInstrBuilder MIB;
4779 
4780  BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4782 
4783  if (Subtarget.isGVIndirectSymbol(GV)) {
4784  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4785  MIB.addReg(Reg, RegState::Kill).addImm(0);
4786  auto Flags = MachineMemOperand::MOLoad |
4789  MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4790  MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, 4);
4791  MIB.addMemOperand(MMO).add(predOps(ARMCC::AL));
4792  }
4793 
4794  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4795  MIB.addReg(Reg, RegState::Kill)
4796  .addImm(0)
4797  .cloneMemRefs(*MI)
4798  .add(predOps(ARMCC::AL));
4799 }
4800 
4801 bool
4802 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4803  unsigned &AddSubOpc,
4804  bool &NegAcc, bool &HasLane) const {
4805  DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4806  if (I == MLxEntryMap.end())
4807  return false;
4808 
4809  const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4810  MulOpc = Entry.MulOpc;
4811  AddSubOpc = Entry.AddSubOpc;
4812  NegAcc = Entry.NegAcc;
4813  HasLane = Entry.HasLane;
4814  return true;
4815 }
4816 
4817 //===----------------------------------------------------------------------===//
4818 // Execution domains.
4819 //===----------------------------------------------------------------------===//
4820 //
4821 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4822 // and some can go down both. The vmov instructions go down the VFP pipeline,
4823 // but they can be changed to vorr equivalents that are executed by the NEON
4824 // pipeline.
4825 //
4826 // We use the following execution domain numbering:
4827 //
4830  ExeVFP = 1,
4832 };
4833 
4834 //
4835 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4836 //
4837 std::pair<uint16_t, uint16_t>
4839  // If we don't have access to NEON instructions then we won't be able
4840  // to swizzle anything to the NEON domain. Check to make sure.
4841  if (Subtarget.hasNEON()) {
4842  // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4843  // if they are not predicated.
4844  if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI))
4845  return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4846 
4847  // CortexA9 is particularly picky about mixing the two and wants these
4848  // converted.
4849  if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) &&
4850  (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR ||
4851  MI.getOpcode() == ARM::VMOVS))
4852  return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4853  }
4854  // No other instructions can be swizzled, so just determine their domain.
4855  unsigned Domain = MI.getDesc().TSFlags & ARMII::DomainMask;
4856 
4857  if (Domain & ARMII::DomainNEON)
4858  return std::make_pair(ExeNEON, 0);
4859 
4860  // Certain instructions can go either way on Cortex-A8.
4861  // Treat them as NEON instructions.
4862  if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4863  return std::make_pair(ExeNEON, 0);
4864 
4865  if (Domain & ARMII::DomainVFP)
4866  return std::make_pair(ExeVFP, 0);
4867 
4868  return std::make_pair(ExeGeneric, 0);
4869 }
4870 
4872  unsigned SReg, unsigned &Lane) {
4873  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4874  Lane = 0;
4875 
4876  if (DReg != ARM::NoRegister)
4877  return DReg;
4878 
4879  Lane = 1;
4880  DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4881 
4882  assert(DReg && "S-register with no D super-register?");
4883  return DReg;
4884 }
4885 
4886 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4887 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4888 /// zero if no register needs to be defined as implicit-use.
4889 ///
4890 /// If the function cannot determine if an SPR should be marked implicit use or
4891 /// not, it returns false.
4892 ///
4893 /// This function handles cases where an instruction is being modified from taking
4894 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4895 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4896 /// lane of the DPR).
4897 ///
4898 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4899 /// (including the case where the DPR itself is defined), it should not.
4900 ///
4902  MachineInstr &MI, unsigned DReg,
4903  unsigned Lane, unsigned &ImplicitSReg) {
4904  // If the DPR is defined or used already, the other SPR lane will be chained
4905  // correctly, so there is nothing to be done.
4906  if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
4907  ImplicitSReg = 0;
4908  return true;
4909  }
4910 
4911  // Otherwise we need to go searching to see if the SPR is set explicitly.
4912  ImplicitSReg = TRI->getSubReg(DReg,
4913  (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4915  MI.getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4916 
4917  if (LQR == MachineBasicBlock::LQR_Live)
4918  return true;
4919  else if (LQR == MachineBasicBlock::LQR_Unknown)
4920  return false;
4921 
4922  // If the register is known not to be live, there is no need to add an
4923  // implicit-use.
4924  ImplicitSReg = 0;
4925  return true;
4926 }
4927 
4929  unsigned Domain) const {
4930  unsigned DstReg, SrcReg, DReg;
4931  unsigned Lane;
4932  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4934  switch (MI.getOpcode()) {
4935  default:
4936  llvm_unreachable("cannot handle opcode!");
4937  break;
4938  case ARM::VMOVD:
4939  if (Domain != ExeNEON)
4940  break;
4941 
4942  // Zap the predicate operands.
4943  assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4944 
4945  // Make sure we've got NEON instructions.
4946  assert(Subtarget.hasNEON() && "VORRd requires NEON");
4947 
4948  // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4949  DstReg = MI.getOperand(0).getReg();
4950  SrcReg = MI.getOperand(1).getReg();
4951 
4952  for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4953  MI.RemoveOperand(i - 1);
4954 
4955  // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4956  MI.setDesc(get(ARM::VORRd));
4957  MIB.addReg(DstReg, RegState::Define)
4958  .addReg(SrcReg)
4959  .addReg(SrcReg)
4960  .add(predOps(ARMCC::AL));
4961  break;
4962  case ARM::VMOVRS:
4963  if (Domain != ExeNEON)
4964  break;
4965  assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4966 
4967  // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4968  DstReg = MI.getOperand(0).getReg();
4969  SrcReg = MI.getOperand(1).getReg();
4970 
4971  for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4972  MI.RemoveOperand(i - 1);
4973 
4974  DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4975 
4976  // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4977  // Note that DSrc has been widened and the other lane may be undef, which
4978  // contaminates the entire register.
4979  MI.setDesc(get(ARM::VGETLNi32));
4980  MIB.addReg(DstReg, RegState::Define)
4981  .addReg(DReg, RegState::Undef)
4982  .addImm(Lane)
4983  .add(predOps(ARMCC::AL));
4984 
4985  // The old source should be an implicit use, otherwise we might think it
4986  // was dead before here.
4987  MIB.addReg(SrcReg, RegState::Implicit);
4988  break;
4989  case ARM::VMOVSR: {
4990  if (Domain != ExeNEON)
4991  break;
4992  assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4993 
4994  // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4995  DstReg = MI.getOperand(0).getReg();
4996  SrcReg = MI.getOperand(1).getReg();
4997 
4998  DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4999 
5000  unsigned ImplicitSReg;
5001  if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
5002  break;
5003 
5004  for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
5005  MI.RemoveOperand(i - 1);
5006 
5007  // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
5008  // Again DDst may be undefined at the beginning of this instruction.
5009  MI.setDesc(get(ARM::VSETLNi32));
5010  MIB.addReg(DReg, RegState::Define)
5011  .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
5012  .addReg(SrcReg)
5013  .addImm(Lane)
5014  .add(predOps(ARMCC::AL));
5015 
5016  // The narrower destination must be marked as set to keep previous chains
5017  // in place.
5018  MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5019  if (ImplicitSReg != 0)
5020  MIB.addReg(ImplicitSReg, RegState::Implicit);
5021  break;
5022  }
5023  case ARM::VMOVS: {
5024  if (Domain != ExeNEON)
5025  break;
5026 
5027  // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
5028  DstReg = MI.getOperand(0).getReg();
5029  SrcReg = MI.getOperand(1).getReg();
5030 
5031  unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
5032  DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
5033  DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
5034 
5035  unsigned ImplicitSReg;
5036  if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
5037  break;
5038 
5039  for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
5040  MI.RemoveOperand(i - 1);
5041 
5042  if (DSrc == DDst) {
5043  // Destination can be:
5044  // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
5045  MI.setDesc(get(ARM::VDUPLN32d));
5046  MIB.addReg(DDst, RegState::Define)
5047  .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
5048  .addImm(SrcLane)
5049  .add(predOps(ARMCC::AL));
5050 
5051  // Neither the source or the destination are naturally represented any
5052  // more, so add them in manually.
5053  MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
5054  MIB.addReg(SrcReg, RegState::Implicit);
5055  if (ImplicitSReg != 0)
5056  MIB.addReg(ImplicitSReg, RegState::Implicit);
5057  break;
5058  }
5059 
5060  // In general there's no single instruction that can perform an S <-> S
5061  // move in NEON space, but a pair of VEXT instructions *can* do the
5062  // job. It turns out that the VEXTs needed will only use DSrc once, with
5063  // the position based purely on the combination of lane-0 and lane-1
5064  // involved. For example
5065  // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
5066  // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
5067  // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
5068  // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
5069  //
5070  // Pattern of the MachineInstrs is:
5071  // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
5072  MachineInstrBuilder NewMIB;
5073  NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
5074  DDst);
5075 
5076  // On the first instruction, both DSrc and DDst may be undef if present.
5077  // Specifically when the original instruction didn't have them as an
5078  // <imp-use>.
5079  unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
5080  bool CurUndef = !MI.readsRegister(CurReg, TRI);
5081  NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
5082 
5083  CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
5084  CurUndef = !MI.readsRegister(CurReg, TRI);
5085  NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
5086  .addImm(1)
5087  .add(predOps(ARMCC::AL));
5088 
5089  if (SrcLane == DstLane)
5090  NewMIB.addReg(SrcReg, RegState::Implicit);
5091 
5092  MI.setDesc(get(ARM::VEXTd32));
5093  MIB.addReg(DDst, RegState::Define);
5094 
5095  // On the second instruction, DDst has definitely been defined above, so
5096  // it is not undef. DSrc, if present, can be undef as above.
5097  CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
5098  CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
5099  MIB.addReg(CurReg, getUndefRegState(CurUndef));
5100 
5101  CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
5102  CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
5103  MIB.addReg(CurReg, getUndefRegState(CurUndef))
5104  .addImm(1)
5105  .add(predOps(ARMCC::AL));
5106 
5107  if (SrcLane != DstLane)
5108  MIB.addReg(SrcReg, RegState::Implicit);
5109 
5110  // As before, the original destination is no longer represented, add it
5111  // implicitly.
5112  MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5113  if (ImplicitSReg != 0)
5114  MIB.addReg(ImplicitSReg, RegState::Implicit);
5115  break;
5116  }
5117  }
5118 }
5119 
5120 //===----------------------------------------------------------------------===//
5121 // Partial register updates
5122 //===----------------------------------------------------------------------===//
5123 //
5124 // Swift renames NEON registers with 64-bit granularity. That means any
5125 // instruction writing an S-reg implicitly reads the containing D-reg. The
5126 // problem is mostly avoided by translating f32 operations to v2f32 operations
5127 // on D-registers, but f32 loads are still a problem.
5128 //
5129 // These instructions can load an f32 into a NEON register:
5130 //
5131 // VLDRS - Only writes S, partial D update.
5132 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
5133 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
5134 //
5135 // FCONSTD can be used as a dependency-breaking instruction.
5137  const MachineInstr &MI, unsigned OpNum,
5138  const TargetRegisterInfo *TRI) const {
5139  auto PartialUpdateClearance = Subtarget.getPartialUpdateClearance();
5140  if (!PartialUpdateClearance)
5141  return 0;
5142 
5143  assert(TRI && "Need TRI instance");
5144 
5145  const MachineOperand &MO = MI.getOperand(OpNum);
5146  if (MO.readsReg())
5147  return 0;
5148  Register Reg = MO.getReg();
5149  int UseOp = -1;
5150 
5151  switch (MI.getOpcode()) {
5152  // Normal instructions writing only an S-register.
5153  case ARM::VLDRS:
5154  case ARM::FCONSTS:
5155  case ARM::VMOVSR:
5156  case ARM::VMOVv8i8:
5157  case ARM::VMOVv4i16:
5158  case ARM::VMOVv2i32:
5159  case ARM::VMOVv2f32:
5160  case ARM::VMOVv1i64:
5161  UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI);
5162  break;
5163 
5164  // Explicitly reads the dependency.
5165  case ARM::VLD1LNd32:
5166  UseOp = 3;
5167  break;
5168  default:
5169  return 0;
5170  }
5171 
5172  // If this instruction actually reads a value from Reg, there is no unwanted
5173  // dependency.
5174  if (UseOp != -1 && MI.getOperand(UseOp).readsReg())
5175  return 0;
5176 
5177  // We must be able to clobber the whole D-reg.
5178  if (Register::isVirtualRegister(Reg)) {
5179  // Virtual register must be a def undef foo:ssub_0 operand.
5180  if (!MO.getSubReg() || MI.readsVirtualRegister(Reg))
5181  return 0;
5182  } else if (ARM::SPRRegClass.contains(Reg)) {
5183  // Physical register: MI must define the full D-reg.
5184  unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
5185  &ARM::DPRRegClass);
5186  if (!DReg || !MI.definesRegister(DReg, TRI))
5187  return 0;
5188  }
5189 
5190  // MI has an unwanted D-register dependency.
5191  // Avoid defs in the previous N instructrions.
5192  return PartialUpdateClearance;
5193 }
5194 
5195 // Break a partial register dependency after getPartialRegUpdateClearance
5196 // returned non-zero.
5198  MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5199  assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
5200  assert(TRI && "Need TRI instance");
5201 
5202  const MachineOperand &MO = MI.getOperand(OpNum);
5203  Register Reg = MO.getReg();
5205  "Can't break virtual register dependencies.");
5206  unsigned DReg = Reg;
5207 
5208  // If MI defines an S-reg, find the corresponding D super-register.
5209  if (ARM::SPRRegClass.contains(Reg)) {
5210  DReg = ARM::D0 + (Reg - ARM::S0) / 2;
5211  assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
5212  }
5213 
5214  assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
5215  assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
5216 
5217  // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
5218  // the full D-register by loading the same value to both lanes. The
5219  // instruction is micro-coded with 2 uops, so don't do this until we can
5220  // properly schedule micro-coded instructions. The dispatcher stalls cause
5221  // too big regressions.
5222 
5223  // Insert the dependency-breaking FCONSTD before MI.
5224  // 96 is the encoding of 0.5, but the actual value doesn't matter here.
5225  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
5226  .addImm(96)
5227  .add(predOps(ARMCC::AL));
5228  MI.addRegisterKilled(DReg, TRI, true);
5229 }
5230 
5232  return Subtarget.getFeatureBits()[ARM::HasV6KOps];
5233 }
5234 
5236  if (MI->getNumOperands() < 4)
5237  return true;
5238  unsigned ShOpVal = MI->getOperand(3).getImm();
5239  unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
5240  // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
5241  if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
5242  ((ShImm == 1 || ShImm == 2) &&
5243  ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
5244  return true;
5245 
5246  return false;
5247 }
5248 
5250  const MachineInstr &MI, unsigned DefIdx,
5251  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
5252  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
5253  assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
5254 
5255  switch (MI.getOpcode()) {
5256  case ARM::VMOVDRR:
5257  // dX = VMOVDRR rY, rZ
5258  // is the same as:
5259  // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
5260  // Populate the InputRegs accordingly.
5261  // rY
5262  const MachineOperand *MOReg = &MI.getOperand(1);
5263  if (!MOReg->isUndef())
5264  InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
5265  MOReg->getSubReg(), ARM::ssub_0));
5266  // rZ
5267  MOReg = &MI.getOperand(2);
5268  if (!MOReg->isUndef())
5269  InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
5270  MOReg->getSubReg(), ARM::ssub_1));
5271  return true;
5272  }
5273  llvm_unreachable("Target dependent opcode missing");
5274 }
5275 
5277  const MachineInstr &MI, unsigned DefIdx,
5278  RegSubRegPairAndIdx &InputReg) const {
5279  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
5280  assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
5281 
5282  switch (MI.getOpcode()) {
5283  case ARM::VMOVRRD:
5284  // rX, rY = VMOVRRD dZ
5285  // is the same as:
5286  // rX = EXTRACT_SUBREG dZ, ssub_0
5287  // rY = EXTRACT_SUBREG dZ, ssub_1
5288  const MachineOperand &MOReg = MI.getOperand(2);
5289  if (MOReg.isUndef())
5290  return false;
5291  InputReg.Reg = MOReg.getReg();
5292  InputReg.SubReg = MOReg.getSubReg();
5293  InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
5294  return true;
5295  }
5296  llvm_unreachable("Target dependent opcode missing");
5297 }
5298 
5300  const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
5301  RegSubRegPairAndIdx &InsertedReg) const {
5302  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
5303  assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
5304 
5305  switch (MI.getOpcode()) {
5306  case ARM::VSETLNi32:
5307  // dX = VSETLNi32 dY, rZ, imm
5308  const MachineOperand &MOBaseReg = MI.getOperand(1);
5309  const MachineOperand &MOInsertedReg = MI.getOperand(2);
5310  if (MOInsertedReg.isUndef())
5311  return false;
5312  const MachineOperand &MOIndex = MI.getOperand(3);
5313  BaseReg.Reg = MOBaseReg.getReg();
5314  BaseReg.SubReg = MOBaseReg.getSubReg();
5315 
5316  InsertedReg.Reg = MOInsertedReg.getReg();
5317  InsertedReg.SubReg = MOInsertedReg.getSubReg();
5318  InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
5319  return true;
5320  }
5321  llvm_unreachable("Target dependent opcode missing");
5322 }
5323 
5324 std::pair<unsigned, unsigned>
5326  const unsigned Mask = ARMII::MO_OPTION_MASK;
5327  return std::make_pair(TF & Mask, TF & ~Mask);
5328 }
5329 
5332  using namespace ARMII;
5333 
5334  static const std::pair<unsigned, const char *> TargetFlags[] = {
5335  {MO_LO16, "arm-lo16"}, {MO_HI16, "arm-hi16"}};
5336  return makeArrayRef(TargetFlags);
5337 }
5338 
5341  using namespace ARMII;
5342 
5343  static const std::pair<unsigned, const char *> TargetFlags[] = {
5344  {MO_COFFSTUB, "arm-coffstub"},
5345  {MO_GOT, "arm-got"},
5346  {MO_SBREL, "arm-sbrel"},
5347  {MO_DLLIMPORT, "arm-dllimport"},
5348  {MO_SECREL, "arm-secrel"},
5349  {MO_NONLAZY, "arm-nonlazy"}};
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