LLVM  10.0.0svn
ARMBaseRegisterInfo.cpp
Go to the documentation of this file.
1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the base ARM implementation of TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARM.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMFrameLowering.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugLoc.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/MC/MCInstrDesc.h"
42 #include "llvm/Support/Debug.h"
47 #include <cassert>
48 #include <utility>
49 
50 #define DEBUG_TYPE "arm-register-info"
51 
52 #define GET_REGINFO_TARGET_DESC
53 #include "ARMGenRegisterInfo.inc"
54 
55 using namespace llvm;
56 
58  : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
59 
60 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
61  return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
62 }
63 
64 const MCPhysReg*
66  const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
67  bool UseSplitPush = STI.splitFramePushPop(*MF);
68  const MCPhysReg *RegList =
69  STI.isTargetDarwin()
70  ? CSR_iOS_SaveList
71  : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
72 
73  const Function &F = MF->getFunction();
74  if (F.getCallingConv() == CallingConv::GHC) {
75  // GHC set of callee saved regs is empty as all those regs are
76  // used for passing STG regs around
77  return CSR_NoRegs_SaveList;
78  } else if (F.hasFnAttribute("interrupt")) {
79  if (STI.isMClass()) {
80  // M-class CPUs have hardware which saves the registers needed to allow a
81  // function conforming to the AAPCS to function as a handler.
82  return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
83  } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
84  // Fast interrupt mode gives the handler a private copy of R8-R14, so less
85  // need to be saved to restore user-mode state.
86  return CSR_FIQ_SaveList;
87  } else {
88  // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
89  // exception handling.
90  return CSR_GenericInt_SaveList;
91  }
92  }
93 
94  if (STI.getTargetLowering()->supportSwiftError() &&
95  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
96  if (STI.isTargetDarwin())
97  return CSR_iOS_SwiftError_SaveList;
98 
99  return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList :
100  CSR_AAPCS_SwiftError_SaveList;
101  }
102 
104  return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
105  ? CSR_iOS_CXX_TLS_PE_SaveList
106  : CSR_iOS_CXX_TLS_SaveList;
107  return RegList;
108 }
109 
111  const MachineFunction *MF) const {
112  assert(MF && "Invalid MachineFunction pointer.");
114  MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
115  return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
116  return nullptr;
117 }
118 
119 const uint32_t *
121  CallingConv::ID CC) const {
122  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
123  if (CC == CallingConv::GHC)
124  // This is academic because all GHC calls are (supposed to be) tail calls
125  return CSR_NoRegs_RegMask;
126 
127  if (STI.getTargetLowering()->supportSwiftError() &&
128  MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
129  return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask
130  : CSR_AAPCS_SwiftError_RegMask;
131 
132  if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
133  return CSR_iOS_CXX_TLS_RegMask;
134  return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
135 }
136 
137 const uint32_t*
139  return CSR_NoRegs_RegMask;
140 }
141 
142 const uint32_t *
145  "only know about special TLS call on Darwin");
146  return CSR_iOS_TLSCall_RegMask;
147 }
148 
149 const uint32_t *
151  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
152  if (!STI.useSoftFloat() && STI.hasVFP2Base() && !STI.isThumb1Only())
153  return CSR_NoRegs_RegMask;
154  else
155  return CSR_FPRegs_RegMask;
156 }
157 
158 const uint32_t *
160  CallingConv::ID CC) const {
161  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
162  // This should return a register mask that is the same as that returned by
163  // getCallPreservedMask but that additionally preserves the register used for
164  // the first i32 argument (which must also be the register used to return a
165  // single i32 return value)
166  //
167  // In case that the calling convention does not use the same register for
168  // both or otherwise does not want to enable this optimization, the function
169  // should return NULL
170  if (CC == CallingConv::GHC)
171  // This is academic because all GHC calls are (supposed to be) tail calls
172  return nullptr;
173  return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
174  : CSR_AAPCS_ThisReturn_RegMask;
175 }
176 
178  const MachineFunction *MF) const {
179  static const MCPhysReg IntraCallClobberedRegs[] = {ARM::R12};
180  return ArrayRef<MCPhysReg>(IntraCallClobberedRegs);
181 }
182 
185  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
186  const ARMFrameLowering *TFI = getFrameLowering(MF);
187 
188  // FIXME: avoid re-calculating this every time.
189  BitVector Reserved(getNumRegs());
190  markSuperRegs(Reserved, ARM::SP);
191  markSuperRegs(Reserved, ARM::PC);
192  markSuperRegs(Reserved, ARM::FPSCR);
193  markSuperRegs(Reserved, ARM::APSR_NZCV);
194  if (TFI->hasFP(MF) || STI.isTargetDarwin())
195  markSuperRegs(Reserved, getFramePointerReg(STI));
196  if (hasBasePointer(MF))
197  markSuperRegs(Reserved, BasePtr);
198  // Some targets reserve R9.
199  if (STI.isR9Reserved())
200  markSuperRegs(Reserved, ARM::R9);
201  // Reserve D16-D31 if the subtarget doesn't support them.
202  if (!STI.hasD32()) {
203  static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
204  for (unsigned R = 0; R < 16; ++R)
205  markSuperRegs(Reserved, ARM::D16 + R);
206  }
207  const TargetRegisterClass &RC = ARM::GPRPairRegClass;
208  for (unsigned Reg : RC)
209  for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
210  if (Reserved.test(*SI))
211  markSuperRegs(Reserved, Reg);
212  // For v8.1m architecture
213  markSuperRegs(Reserved, ARM::ZR);
214 
215  assert(checkAllSuperRegsMarked(Reserved));
216  return Reserved;
217 }
218 
220 isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const {
221  return !getReservedRegs(MF).test(PhysReg);
222 }
223 
224 const TargetRegisterClass *
226  const MachineFunction &MF) const {
227  const TargetRegisterClass *Super = RC;
229  do {
230  switch (Super->getID()) {
231  case ARM::GPRRegClassID:
232  case ARM::SPRRegClassID:
233  case ARM::DPRRegClassID:
234  case ARM::GPRPairRegClassID:
235  return Super;
236  case ARM::QPRRegClassID:
237  case ARM::QQPRRegClassID:
238  case ARM::QQQQPRRegClassID:
239  if (MF.getSubtarget<ARMSubtarget>().hasNEON())
240  return Super;
241  }
242  Super = *I++;
243  } while (Super);
244  return RC;
245 }
246 
247 const TargetRegisterClass *
249  const {
250  return &ARM::GPRRegClass;
251 }
252 
253 const TargetRegisterClass *
255  if (RC == &ARM::CCRRegClass)
256  return &ARM::rGPRRegClass; // Can't copy CCR registers.
257  return RC;
258 }
259 
260 unsigned
262  MachineFunction &MF) const {
263  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
264  const ARMFrameLowering *TFI = getFrameLowering(MF);
265 
266  switch (RC->getID()) {
267  default:
268  return 0;
269  case ARM::tGPRRegClassID: {
270  // hasFP ends up calling getMaxCallFrameComputed() which may not be
271  // available when getPressureLimit() is called as part of
272  // ScheduleDAGRRList.
273  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
274  ? TFI->hasFP(MF) : true;
275  return 5 - HasFP;
276  }
277  case ARM::GPRRegClassID: {
278  bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
279  ? TFI->hasFP(MF) : true;
280  return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
281  }
282  case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
283  case ARM::DPRRegClassID:
284  return 32 - 10;
285  }
286 }
287 
288 // Get the other register in a GPRPair.
289 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
290  for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
291  if (ARM::GPRPairRegClass.contains(*Supers))
292  return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
293  return 0;
294 }
295 
296 // Resolve the RegPairEven / RegPairOdd register allocator hints.
297 bool
299  ArrayRef<MCPhysReg> Order,
301  const MachineFunction &MF,
302  const VirtRegMap *VRM,
303  const LiveRegMatrix *Matrix) const {
304  const MachineRegisterInfo &MRI = MF.getRegInfo();
305  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
306 
307  unsigned Odd;
308  switch (Hint.first) {
309  case ARMRI::RegPairEven:
310  Odd = 0;
311  break;
312  case ARMRI::RegPairOdd:
313  Odd = 1;
314  break;
315  default:
316  TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
317  return false;
318  }
319 
320  // This register should preferably be even (Odd == 0) or odd (Odd == 1).
321  // Check if the other part of the pair has already been assigned, and provide
322  // the paired register as the first hint.
323  unsigned Paired = Hint.second;
324  if (Paired == 0)
325  return false;
326 
327  unsigned PairedPhys = 0;
328  if (Register::isPhysicalRegister(Paired)) {
329  PairedPhys = Paired;
330  } else if (VRM && VRM->hasPhys(Paired)) {
331  PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
332  }
333 
334  // First prefer the paired physreg.
335  if (PairedPhys && is_contained(Order, PairedPhys))
336  Hints.push_back(PairedPhys);
337 
338  // Then prefer even or odd registers.
339  for (unsigned Reg : Order) {
340  if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
341  continue;
342  // Don't provide hints that are paired to a reserved register.
343  unsigned Paired = getPairedGPR(Reg, !Odd, this);
344  if (!Paired || MRI.isReserved(Paired))
345  continue;
346  Hints.push_back(Reg);
347  }
348  return false;
349 }
350 
351 void
353  MachineFunction &MF) const {
355  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
356  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
357  Hint.first == (unsigned)ARMRI::RegPairEven) &&
358  Register::isVirtualRegister(Hint.second)) {
359  // If 'Reg' is one of the even / odd register pair and it's now changed
360  // (e.g. coalesced) into a different register. The other register of the
361  // pair allocation hint must be updated to reflect the relationship
362  // change.
363  unsigned OtherReg = Hint.second;
364  Hint = MRI->getRegAllocationHint(OtherReg);
365  // Make sure the pair has not already divorced.
366  if (Hint.second == Reg) {
367  MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
368  if (Register::isVirtualRegister(NewReg))
369  MRI->setRegAllocationHint(NewReg,
370  Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
371  : ARMRI::RegPairOdd, OtherReg);
372  }
373  }
374 }
375 
377  const MachineFrameInfo &MFI = MF.getFrameInfo();
378  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
379  const ARMFrameLowering *TFI = getFrameLowering(MF);
380 
381  // If we have stack realignment and VLAs, we have no pointer to use to
382  // access the stack. If we have stack realignment, and a large call frame,
383  // we have no place to allocate the emergency spill slot.
384  if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
385  return true;
386 
387  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
388  // negative range for ldr/str (255), and thumb1 is positive offsets only.
389  //
390  // It's going to be better to use the SP or Base Pointer instead. When there
391  // are variable sized objects, we can't reference off of the SP, so we
392  // reserve a Base Pointer.
393  //
394  // For Thumb2, estimate whether a negative offset from the frame pointer
395  // will be sufficient to reach the whole stack frame. If a function has a
396  // smallish frame, it's less likely to have lots of spills and callee saved
397  // space, so it's all more likely to be within range of the frame pointer.
398  // If it's wrong, the scavenger will still enable access to work, it just
399  // won't be optimal. (We should always be able to reach the emergency
400  // spill slot from the frame pointer.)
401  if (AFI->isThumb2Function() && MFI.hasVarSizedObjects() &&
402  MFI.getLocalFrameSize() >= 128)
403  return true;
404  // For Thumb1, if sp moves, nothing is in range, so force a base pointer.
405  // This is necessary for correctness in cases where we need an emergency
406  // spill slot. (In Thumb1, we can't use a negative offset from the frame
407  // pointer.)
408  if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF))
409  return true;
410  return false;
411 }
412 
414  const MachineRegisterInfo *MRI = &MF.getRegInfo();
415  const ARMFrameLowering *TFI = getFrameLowering(MF);
416  // We can't realign the stack if:
417  // 1. Dynamic stack realignment is explicitly disabled,
418  // 2. There are VLAs in the function and the base pointer is disabled.
420  return false;
421  // Stack realignment requires a frame pointer. If we already started
422  // register allocation with frame pointer elimination, it is too late now.
424  return false;
425  // We may also need a base pointer if there are dynamic allocas or stack
426  // pointer adjustments around calls.
427  if (TFI->hasReservedCallFrame(MF))
428  return true;
429  // A base pointer is required and allowed. Check that it isn't too late to
430  // reserve it.
431  return MRI->canReserveReg(BasePtr);
432 }
433 
436  const MachineFrameInfo &MFI = MF.getFrameInfo();
438  return true;
439  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
440  || needsStackRealignment(MF);
441 }
442 
443 Register
445  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
446  const ARMFrameLowering *TFI = getFrameLowering(MF);
447 
448  if (TFI->hasFP(MF))
449  return getFramePointerReg(STI);
450  return ARM::SP;
451 }
452 
453 /// emitLoadConstPool - Emits a load from constpool to materialize the
454 /// specified immediate.
457  const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
458  ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
459  MachineFunction &MF = *MBB.getParent();
460  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
462  const Constant *C =
464  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
465 
466  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
467  .addReg(DestReg, getDefRegState(true), SubIdx)
468  .addConstantPoolIndex(Idx)
469  .addImm(0)
470  .add(predOps(Pred, PredReg))
471  .setMIFlags(MIFlags);
472 }
473 
476  return true;
477 }
478 
481  return true;
482 }
483 
486  return true;
487 }
488 
491  return true;
492 }
493 
494 int64_t ARMBaseRegisterInfo::
495 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
496  const MCInstrDesc &Desc = MI->getDesc();
497  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
498  int64_t InstrOffs = 0;
499  int Scale = 1;
500  unsigned ImmIdx = 0;
501  switch (AddrMode) {
504  case ARMII::AddrMode_i12:
505  InstrOffs = MI->getOperand(Idx+1).getImm();
506  Scale = 1;
507  break;
508  case ARMII::AddrMode5: {
509  // VFP address mode.
510  const MachineOperand &OffOp = MI->getOperand(Idx+1);
511  InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
512  if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
513  InstrOffs = -InstrOffs;
514  Scale = 4;
515  break;
516  }
517  case ARMII::AddrMode2:
518  ImmIdx = Idx+2;
519  InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
520  if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
521  InstrOffs = -InstrOffs;
522  break;
523  case ARMII::AddrMode3:
524  ImmIdx = Idx+2;
525  InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
526  if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
527  InstrOffs = -InstrOffs;
528  break;
529  case ARMII::AddrModeT1_s:
530  ImmIdx = Idx+1;
531  InstrOffs = MI->getOperand(ImmIdx).getImm();
532  Scale = 4;
533  break;
534  default:
535  llvm_unreachable("Unsupported addressing mode!");
536  }
537 
538  return InstrOffs * Scale;
539 }
540 
541 /// needsFrameBaseReg - Returns true if the instruction's frame index
542 /// reference would be better served by a base register other than FP
543 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
544 /// references it should create new base registers for.
547  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
548  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
549  }
550 
551  // It's the load/store FI references that cause issues, as it can be difficult
552  // to materialize the offset if it won't fit in the literal field. Estimate
553  // based on the size of the local frame and some conservative assumptions
554  // about the rest of the stack frame (note, this is pre-regalloc, so
555  // we don't know everything for certain yet) whether this offset is likely
556  // to be out of range of the immediate. Return true if so.
557 
558  // We only generate virtual base registers for loads and stores, so
559  // return false for everything else.
560  unsigned Opc = MI->getOpcode();
561  switch (Opc) {
562  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
563  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
564  case ARM::t2LDRi12: case ARM::t2LDRi8:
565  case ARM::t2STRi12: case ARM::t2STRi8:
566  case ARM::VLDRS: case ARM::VLDRD:
567  case ARM::VSTRS: case ARM::VSTRD:
568  case ARM::tSTRspi: case ARM::tLDRspi:
569  break;
570  default:
571  return false;
572  }
573 
574  // Without a virtual base register, if the function has variable sized
575  // objects, all fixed-size local references will be via the frame pointer,
576  // Approximate the offset and see if it's legal for the instruction.
577  // Note that the incoming offset is based on the SP value at function entry,
578  // so it'll be negative.
579  MachineFunction &MF = *MI->getParent()->getParent();
580  const ARMFrameLowering *TFI = getFrameLowering(MF);
581  MachineFrameInfo &MFI = MF.getFrameInfo();
583 
584  // Estimate an offset from the frame pointer.
585  // Conservatively assume all callee-saved registers get pushed. R4-R6
586  // will be earlier than the FP, so we ignore those.
587  // R7, LR
588  int64_t FPOffset = Offset - 8;
589  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
590  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
591  FPOffset -= 80;
592  // Estimate an offset from the stack pointer.
593  // The incoming offset is relating to the SP at the start of the function,
594  // but when we access the local it'll be relative to the SP after local
595  // allocation, so adjust our SP-relative offset by that allocation size.
596  Offset += MFI.getLocalFrameSize();
597  // Assume that we'll have at least some spill slots allocated.
598  // FIXME: This is a total SWAG number. We should run some statistics
599  // and pick a real one.
600  Offset += 128; // 128 bytes of spill slots
601 
602  // If there's a frame pointer and the addressing mode allows it, try using it.
603  // The FP is only available if there is no dynamic realignment. We
604  // don't know for sure yet whether we'll need that, so we guess based
605  // on whether there are any local variables that would trigger it.
606  unsigned StackAlign = TFI->getStackAlignment();
607  if (TFI->hasFP(MF) &&
608  !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
609  if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
610  return false;
611  }
612  // If we can reference via the stack pointer, try that.
613  // FIXME: This (and the code that resolves the references) can be improved
614  // to only disallow SP relative references in the live range of
615  // the VLA(s). In practice, it's unclear how much difference that
616  // would make, but it may be worth doing.
617  if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
618  return false;
619 
620  // The offset likely isn't legal, we want to allocate a virtual base register.
621  return true;
622 }
623 
624 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
625 /// be a pointer to FrameIdx at the beginning of the basic block.
628  unsigned BaseReg, int FrameIdx,
629  int64_t Offset) const {
631  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
632  (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
633 
635  DebugLoc DL; // Defaults to "unknown"
636  if (Ins != MBB->end())
637  DL = Ins->getDebugLoc();
638 
639  const MachineFunction &MF = *MBB->getParent();
641  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
642  const MCInstrDesc &MCID = TII.get(ADDriOpc);
643  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
644 
645  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
646  .addFrameIndex(FrameIdx).addImm(Offset);
647 
648  if (!AFI->isThumb1OnlyFunction())
650 }
651 
653  int64_t Offset) const {
654  MachineBasicBlock &MBB = *MI.getParent();
655  MachineFunction &MF = *MBB.getParent();
656  const ARMBaseInstrInfo &TII =
657  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
659  int Off = Offset; // ARM doesn't need the general 64-bit offsets
660  unsigned i = 0;
661 
662  assert(!AFI->isThumb1OnlyFunction() &&
663  "This resolveFrameIndex does not support Thumb1!");
664 
665  while (!MI.getOperand(i).isFI()) {
666  ++i;
667  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
668  }
669  bool Done = false;
670  if (!AFI->isThumbFunction())
671  Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
672  else {
673  assert(AFI->isThumb2Function());
674  Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this);
675  }
676  assert(Done && "Unable to resolve frame index!");
677  (void)Done;
678 }
679 
681  int64_t Offset) const {
682  const MCInstrDesc &Desc = MI->getDesc();
683  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
684  unsigned i = 0;
685  for (; !MI->getOperand(i).isFI(); ++i)
686  assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
687 
688  // AddrMode4 and AddrMode6 cannot handle any offset.
689  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
690  return Offset == 0;
691 
692  unsigned NumBits = 0;
693  unsigned Scale = 1;
694  bool isSigned = true;
695  switch (AddrMode) {
698  // i8 supports only negative, and i12 supports only positive, so
699  // based on Offset sign, consider the appropriate instruction
700  Scale = 1;
701  if (Offset < 0) {
702  NumBits = 8;
703  Offset = -Offset;
704  } else {
705  NumBits = 12;
706  }
707  break;
708  case ARMII::AddrMode5:
709  // VFP address mode.
710  NumBits = 8;
711  Scale = 4;
712  break;
713  case ARMII::AddrMode_i12:
714  case ARMII::AddrMode2:
715  NumBits = 12;
716  break;
717  case ARMII::AddrMode3:
718  NumBits = 8;
719  break;
720  case ARMII::AddrModeT1_s:
721  NumBits = (BaseReg == ARM::SP ? 8 : 5);
722  Scale = 4;
723  isSigned = false;
724  break;
725  default:
726  llvm_unreachable("Unsupported addressing mode!");
727  }
728 
729  Offset += getFrameIndexInstrOffset(MI, i);
730  // Make sure the offset is encodable for instructions that scale the
731  // immediate.
732  if ((Offset & (Scale-1)) != 0)
733  return false;
734 
735  if (isSigned && Offset < 0)
736  Offset = -Offset;
737 
738  unsigned Mask = (1 << NumBits) - 1;
739  if ((unsigned)Offset <= Mask * Scale)
740  return true;
741 
742  return false;
743 }
744 
745 void
747  int SPAdj, unsigned FIOperandNum,
748  RegScavenger *RS) const {
749  MachineInstr &MI = *II;
750  MachineBasicBlock &MBB = *MI.getParent();
751  MachineFunction &MF = *MBB.getParent();
752  const ARMBaseInstrInfo &TII =
753  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
754  const ARMFrameLowering *TFI = getFrameLowering(MF);
756  assert(!AFI->isThumb1OnlyFunction() &&
757  "This eliminateFrameIndex does not support Thumb1!");
758  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
759  unsigned FrameReg;
760 
761  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
762 
763  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
764  // call frame setup/destroy instructions have already been eliminated. That
765  // means the stack pointer cannot be used to access the emergency spill slot
766  // when !hasReservedCallFrame().
767 #ifndef NDEBUG
768  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
769  assert(TFI->hasReservedCallFrame(MF) &&
770  "Cannot use SP to access the emergency spill slot in "
771  "functions without a reserved call frame");
773  "Cannot use SP to access the emergency spill slot in "
774  "functions with variable sized frame objects");
775  }
776 #endif // NDEBUG
777 
778  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
779 
780  // Modify MI as necessary to handle as much of 'Offset' as possible
781  bool Done = false;
782  if (!AFI->isThumbFunction())
783  Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
784  else {
785  assert(AFI->isThumb2Function());
786  Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII, this);
787  }
788  if (Done)
789  return;
790 
791  // If we get here, the immediate doesn't fit into the instruction. We folded
792  // as much as possible above, handle the rest, providing a register that is
793  // SP+LargeImm.
794  assert(
795  (Offset ||
802  "This code isn't needed if offset already handled!");
803 
804  unsigned ScratchReg = 0;
805  int PIdx = MI.findFirstPredOperandIdx();
806  ARMCC::CondCodes Pred = (PIdx == -1)
808  Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
809 
810  const MCInstrDesc &MCID = MI.getDesc();
811  const TargetRegisterClass *RegClass =
812  TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());
813 
814  if (Offset == 0 &&
815  (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
816  // Must be addrmode4/6.
817  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
818  else {
819  ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
820  if (!AFI->isThumbFunction())
821  emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
822  Offset, Pred, PredReg, TII);
823  else {
824  assert(AFI->isThumb2Function());
825  emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
826  Offset, Pred, PredReg, TII);
827  }
828  // Update the original instruction to use the scratch register.
829  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
830  }
831 }
832 
834  const TargetRegisterClass *SrcRC,
835  unsigned SubReg,
836  const TargetRegisterClass *DstRC,
837  unsigned DstSubReg,
838  const TargetRegisterClass *NewRC,
839  LiveIntervals &LIS) const {
840  auto MBB = MI->getParent();
841  auto MF = MBB->getParent();
842  const MachineRegisterInfo &MRI = MF->getRegInfo();
843  // If not copying into a sub-register this should be ok because we shouldn't
844  // need to split the reg.
845  if (!DstSubReg)
846  return true;
847  // Small registers don't frequently cause a problem, so we can coalesce them.
848  if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
849  getRegSizeInBits(*SrcRC) < 256)
850  return true;
851 
852  auto NewRCWeight =
854  auto SrcRCWeight =
856  auto DstRCWeight =
858  // If the source register class is more expensive than the destination, the
859  // coalescing is probably profitable.
860  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
861  return true;
862  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
863  return true;
864 
865  // If the register allocator isn't constrained, we can always allow coalescing
866  // unfortunately we don't know yet if we will be constrained.
867  // The goal of this heuristic is to restrict how many expensive registers
868  // we allow to coalesce in a given basic block.
869  auto AFI = MF->getInfo<ARMFunctionInfo>();
870  auto It = AFI->getCoalescedWeight(MBB);
871 
872  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
873  << It->second << "\n");
874  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
875  << NewRCWeight.RegWeight << "\n");
876 
877  // This number is the largest round number that which meets the criteria:
878  // (1) addresses PR18825
879  // (2) generates better code in some test cases (like vldm-shed-a9.ll)
880  // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
881  // In practice the SizeMultiplier will only factor in for straight line code
882  // that uses a lot of NEON vectors, which isn't terribly common.
883  unsigned SizeMultiplier = MBB->size()/100;
884  SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
885  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
886  It->second += NewRCWeight.RegWeight;
887  return true;
888  }
889  return false;
890 }
uint64_t CallInst * C
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const MachineInstrBuilder & add(const MachineOperand &MO) const
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool hasD32() const
Definition: ARMSubtarget.h:677
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isReserved(Register PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
void push_back(const T &Elt)
Definition: SmallVector.h:211
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
int64_t getLocalFrameSize() const
Get the size of the local object blob.
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:529
unsigned Reg
Register getFrameRegister(const MachineFunction &MF) const override
bool test(unsigned Idx) const
Definition: BitVector.h:501
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
A debug info location.
Definition: DebugLoc.h:33
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool isThumb1Only() const
Definition: ARMSubtarget.h:755
ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const override
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:96
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction&#39;s frame index reference would be better served by...
Live Register Matrix
const uint32_t * getNoPreservedMask() const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI)
MCSuperRegIterator enumerates all super-registers of Reg.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned SubReg
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP...
This file contains the simple types necessary to represent the attributes associated with functions a...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
unsigned char getAM3Offset(unsigned AM3Opc)
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:775
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:688
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:767
bool isR9Reserved() const
Definition: ARMSubtarget.h:763
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
AddrOpc getAM2Op(unsigned AM2Opc)
unsigned getDefRegState(bool B)
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
unsigned char getAM5Offset(unsigned AM5Opc)
This file declares the machine register scavenger class.
const TargetRegisterInfo * getTargetRegisterInfo() const
AddrOpc getAM3Op(unsigned AM3Opc)
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
unsigned const MachineRegisterInfo * MRI
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that &#39;returned&#39; is on...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool cannotEliminateFrame(const MachineFunction &MF) const
bool isMClass() const
Definition: ARMSubtarget.h:758
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasBasePointer(const MachineFunction &MF) const
bool hasVFP2Base() const
Definition: ARMSubtarget.h:607
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
static unsigned getFramePointerReg(const ARMSubtarget &STI)
MCSubRegIterator enumerates all sub-registers of Reg.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
std::pair< unsigned, unsigned > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool useSoftFloat() const
Definition: ARMSubtarget.h:752
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
bool isDebugValue() const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool hasNEON() const
Definition: ARMSubtarget.h:611
Promote Memory to Register
Definition: Mem2Reg.cpp:109
unsigned getAM2Offset(unsigned AM2Opc)
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:653
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool canRealignStack(const MachineFunction &MF) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const override
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:180
Register getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:102
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:220
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
TargetOptions Options
#define I(x, y, z)
Definition: MD5.cpp:58
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Align getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
bool isMaxCallFrameSizeComputed() const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
IRTranslator LLVM IR MI
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
AddrOpc getAM5Op(unsigned AM5Opc)
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1224