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ARMFastISel.cpp
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1 //===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the ARM-specific support for the FastISel class. Some
10 // of the target-specific code is generated by tablegen in the file
11 // ARMGenFastISel.inc, which is #included here.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARM.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
25 #include "Utils/ARMBaseInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/CodeGen/FastISel.h"
49 #include "llvm/IR/Argument.h"
50 #include "llvm/IR/Attributes.h"
51 #include "llvm/IR/CallSite.h"
52 #include "llvm/IR/CallingConv.h"
53 #include "llvm/IR/Constant.h"
54 #include "llvm/IR/Constants.h"
55 #include "llvm/IR/DataLayout.h"
56 #include "llvm/IR/DerivedTypes.h"
57 #include "llvm/IR/Function.h"
59 #include "llvm/IR/GlobalValue.h"
60 #include "llvm/IR/GlobalVariable.h"
61 #include "llvm/IR/InstrTypes.h"
62 #include "llvm/IR/Instruction.h"
63 #include "llvm/IR/Instructions.h"
64 #include "llvm/IR/IntrinsicInst.h"
65 #include "llvm/IR/Intrinsics.h"
66 #include "llvm/IR/Module.h"
67 #include "llvm/IR/Operator.h"
68 #include "llvm/IR/Type.h"
69 #include "llvm/IR/User.h"
70 #include "llvm/IR/Value.h"
71 #include "llvm/MC/MCInstrDesc.h"
72 #include "llvm/MC/MCRegisterInfo.h"
73 #include "llvm/Support/Casting.h"
74 #include "llvm/Support/Compiler.h"
80 #include <cassert>
81 #include <cstdint>
82 #include <utility>
83 
84 using namespace llvm;
85 
86 namespace {
87 
88  // All possible address modes, plus some.
89  struct Address {
90  enum {
91  RegBase,
92  FrameIndexBase
93  } BaseType = RegBase;
94 
95  union {
96  unsigned Reg;
97  int FI;
98  } Base;
99 
100  int Offset = 0;
101 
102  // Innocuous defaults for our address.
103  Address() {
104  Base.Reg = 0;
105  }
106  };
107 
108 class ARMFastISel final : public FastISel {
109  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
110  /// make the right decision when generating code for different targets.
111  const ARMSubtarget *Subtarget;
112  Module &M;
113  const TargetMachine &TM;
114  const TargetInstrInfo &TII;
115  const TargetLowering &TLI;
116  ARMFunctionInfo *AFI;
117 
118  // Convenience variables to avoid some queries.
119  bool isThumb2;
121 
122  public:
123  explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
124  const TargetLibraryInfo *libInfo)
125  : FastISel(funcInfo, libInfo),
126  Subtarget(
127  &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
128  M(const_cast<Module &>(*funcInfo.Fn->getParent())),
129  TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
130  TLI(*Subtarget->getTargetLowering()) {
131  AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
132  isThumb2 = AFI->isThumbFunction();
133  Context = &funcInfo.Fn->getContext();
134  }
135 
136  private:
137  // Code from FastISel.cpp.
138 
139  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
140  const TargetRegisterClass *RC,
141  unsigned Op0, bool Op0IsKill);
142  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
143  const TargetRegisterClass *RC,
144  unsigned Op0, bool Op0IsKill,
145  unsigned Op1, bool Op1IsKill);
146  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
147  const TargetRegisterClass *RC,
148  unsigned Op0, bool Op0IsKill,
149  uint64_t Imm);
150  unsigned fastEmitInst_i(unsigned MachineInstOpcode,
151  const TargetRegisterClass *RC,
152  uint64_t Imm);
153 
154  // Backend specific FastISel code.
155 
156  bool fastSelectInstruction(const Instruction *I) override;
157  unsigned fastMaterializeConstant(const Constant *C) override;
158  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
159  bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
160  const LoadInst *LI) override;
161  bool fastLowerArguments() override;
162 
163  #include "ARMGenFastISel.inc"
164 
165  // Instruction selection routines.
166 
167  bool SelectLoad(const Instruction *I);
168  bool SelectStore(const Instruction *I);
169  bool SelectBranch(const Instruction *I);
170  bool SelectIndirectBr(const Instruction *I);
171  bool SelectCmp(const Instruction *I);
172  bool SelectFPExt(const Instruction *I);
173  bool SelectFPTrunc(const Instruction *I);
174  bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
175  bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
176  bool SelectIToFP(const Instruction *I, bool isSigned);
177  bool SelectFPToI(const Instruction *I, bool isSigned);
178  bool SelectDiv(const Instruction *I, bool isSigned);
179  bool SelectRem(const Instruction *I, bool isSigned);
180  bool SelectCall(const Instruction *I, const char *IntrMemName);
181  bool SelectIntrinsicCall(const IntrinsicInst &I);
182  bool SelectSelect(const Instruction *I);
183  bool SelectRet(const Instruction *I);
184  bool SelectTrunc(const Instruction *I);
185  bool SelectIntExt(const Instruction *I);
186  bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
187 
188  // Utility routines.
189 
190  bool isPositionIndependent() const;
191  bool isTypeLegal(Type *Ty, MVT &VT);
192  bool isLoadTypeLegal(Type *Ty, MVT &VT);
193  bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
194  bool isZExt, bool isEquality);
195  bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
196  unsigned Alignment = 0, bool isZExt = true,
197  bool allocReg = true);
198  bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
199  unsigned Alignment = 0);
200  bool ARMComputeAddress(const Value *Obj, Address &Addr);
201  void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
202  bool ARMIsMemCpySmall(uint64_t Len);
203  bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
204  unsigned Alignment);
205  unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
206  unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
207  unsigned ARMMaterializeInt(const Constant *C, MVT VT);
208  unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
209  unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
210  unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
211  unsigned ARMSelectCallOp(bool UseReg);
212  unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
213 
214  const TargetLowering *getTargetLowering() { return &TLI; }
215 
216  // Call handling routines.
217 
218  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
219  bool Return,
220  bool isVarArg);
221  bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
222  SmallVectorImpl<unsigned> &ArgRegs,
223  SmallVectorImpl<MVT> &ArgVTs,
225  SmallVectorImpl<unsigned> &RegArgs,
226  CallingConv::ID CC,
227  unsigned &NumBytes,
228  bool isVarArg);
229  unsigned getLibcallReg(const Twine &Name);
230  bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
231  const Instruction *I, CallingConv::ID CC,
232  unsigned &NumBytes, bool isVarArg);
233  bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
234 
235  // OptionalDef handling routines.
236 
237  bool isARMNEONPred(const MachineInstr *MI);
238  bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
239  const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
240  void AddLoadStoreOperands(MVT VT, Address &Addr,
241  const MachineInstrBuilder &MIB,
242  MachineMemOperand::Flags Flags, bool useAM3);
243 };
244 
245 } // end anonymous namespace
246 
247 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
248 // we don't care about implicit defs here, just places we'll need to add a
249 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
250 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
251  if (!MI->hasOptionalDef())
252  return false;
253 
254  // Look to see if our OptionalDef is defining CPSR or CCR.
255  for (const MachineOperand &MO : MI->operands()) {
256  if (!MO.isReg() || !MO.isDef()) continue;
257  if (MO.getReg() == ARM::CPSR)
258  *CPSR = true;
259  }
260  return true;
261 }
262 
263 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
264  const MCInstrDesc &MCID = MI->getDesc();
265 
266  // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
267  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
268  AFI->isThumb2Function())
269  return MI->isPredicable();
270 
271  for (const MCOperandInfo &opInfo : MCID.operands())
272  if (opInfo.isPredicate())
273  return true;
274 
275  return false;
276 }
277 
278 // If the machine is predicable go ahead and add the predicate operands, if
279 // it needs default CC operands add those.
280 // TODO: If we want to support thumb1 then we'll need to deal with optional
281 // CPSR defs that need to be added before the remaining operands. See s_cc_out
282 // for descriptions why.
283 const MachineInstrBuilder &
284 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
285  MachineInstr *MI = &*MIB;
286 
287  // Do we use a predicate? or...
288  // Are we NEON in ARM mode and have a predicate operand? If so, I know
289  // we're not predicable but add it anyways.
290  if (isARMNEONPred(MI))
291  MIB.add(predOps(ARMCC::AL));
292 
293  // Do we optionally set a predicate? Preds is size > 0 iff the predicate
294  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
295  bool CPSR = false;
296  if (DefinesOptionalPredicate(MI, &CPSR))
297  MIB.add(CPSR ? t1CondCodeOp() : condCodeOp());
298  return MIB;
299 }
300 
301 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
302  const TargetRegisterClass *RC,
303  unsigned Op0, bool Op0IsKill) {
304  unsigned ResultReg = createResultReg(RC);
305  const MCInstrDesc &II = TII.get(MachineInstOpcode);
306 
307  // Make sure the input operand is sufficiently constrained to be legal
308  // for this instruction.
309  Op0 = constrainOperandRegClass(II, Op0, 1);
310  if (II.getNumDefs() >= 1) {
311  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
312  ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
313  } else {
314  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
315  .addReg(Op0, Op0IsKill * RegState::Kill));
316  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
317  TII.get(TargetOpcode::COPY), ResultReg)
318  .addReg(II.ImplicitDefs[0]));
319  }
320  return ResultReg;
321 }
322 
323 unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
324  const TargetRegisterClass *RC,
325  unsigned Op0, bool Op0IsKill,
326  unsigned Op1, bool Op1IsKill) {
327  unsigned ResultReg = createResultReg(RC);
328  const MCInstrDesc &II = TII.get(MachineInstOpcode);
329 
330  // Make sure the input operands are sufficiently constrained to be legal
331  // for this instruction.
332  Op0 = constrainOperandRegClass(II, Op0, 1);
333  Op1 = constrainOperandRegClass(II, Op1, 2);
334 
335  if (II.getNumDefs() >= 1) {
336  AddOptionalDefs(
337  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
338  .addReg(Op0, Op0IsKill * RegState::Kill)
339  .addReg(Op1, Op1IsKill * RegState::Kill));
340  } else {
341  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
342  .addReg(Op0, Op0IsKill * RegState::Kill)
343  .addReg(Op1, Op1IsKill * RegState::Kill));
344  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
345  TII.get(TargetOpcode::COPY), ResultReg)
346  .addReg(II.ImplicitDefs[0]));
347  }
348  return ResultReg;
349 }
350 
351 unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
352  const TargetRegisterClass *RC,
353  unsigned Op0, bool Op0IsKill,
354  uint64_t Imm) {
355  unsigned ResultReg = createResultReg(RC);
356  const MCInstrDesc &II = TII.get(MachineInstOpcode);
357 
358  // Make sure the input operand is sufficiently constrained to be legal
359  // for this instruction.
360  Op0 = constrainOperandRegClass(II, Op0, 1);
361  if (II.getNumDefs() >= 1) {
362  AddOptionalDefs(
363  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
364  .addReg(Op0, Op0IsKill * RegState::Kill)
365  .addImm(Imm));
366  } else {
367  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
368  .addReg(Op0, Op0IsKill * RegState::Kill)
369  .addImm(Imm));
370  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
371  TII.get(TargetOpcode::COPY), ResultReg)
372  .addReg(II.ImplicitDefs[0]));
373  }
374  return ResultReg;
375 }
376 
377 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
378  const TargetRegisterClass *RC,
379  uint64_t Imm) {
380  unsigned ResultReg = createResultReg(RC);
381  const MCInstrDesc &II = TII.get(MachineInstOpcode);
382 
383  if (II.getNumDefs() >= 1) {
384  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
385  ResultReg).addImm(Imm));
386  } else {
387  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
388  .addImm(Imm));
389  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
390  TII.get(TargetOpcode::COPY), ResultReg)
391  .addReg(II.ImplicitDefs[0]));
392  }
393  return ResultReg;
394 }
395 
396 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
397 // checks from the various callers.
398 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
399  if (VT == MVT::f64) return 0;
400 
401  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
402  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
403  TII.get(ARM::VMOVSR), MoveReg)
404  .addReg(SrcReg));
405  return MoveReg;
406 }
407 
408 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
409  if (VT == MVT::i64) return 0;
410 
411  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
412  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
413  TII.get(ARM::VMOVRS), MoveReg)
414  .addReg(SrcReg));
415  return MoveReg;
416 }
417 
418 // For double width floating point we need to materialize two constants
419 // (the high and the low) into integer registers then use a move to get
420 // the combined constant into an FP reg.
421 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
422  const APFloat Val = CFP->getValueAPF();
423  bool is64bit = VT == MVT::f64;
424 
425  // This checks to see if we can use VFP3 instructions to materialize
426  // a constant, otherwise we have to go through the constant pool.
427  if (TLI.isFPImmLegal(Val, VT)) {
428  int Imm;
429  unsigned Opc;
430  if (is64bit) {
431  Imm = ARM_AM::getFP64Imm(Val);
432  Opc = ARM::FCONSTD;
433  } else {
434  Imm = ARM_AM::getFP32Imm(Val);
435  Opc = ARM::FCONSTS;
436  }
437  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
438  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
439  TII.get(Opc), DestReg).addImm(Imm));
440  return DestReg;
441  }
442 
443  // Require VFP2 for loading fp constants.
444  if (!Subtarget->hasVFP2()) return false;
445 
446  // MachineConstantPool wants an explicit alignment.
447  unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
448  if (Align == 0) {
449  // TODO: Figure out if this is correct.
450  Align = DL.getTypeAllocSize(CFP->getType());
451  }
452  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
453  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
454  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
455 
456  // The extra reg is for addrmode5.
457  AddOptionalDefs(
458  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
459  .addConstantPoolIndex(Idx)
460  .addReg(0));
461  return DestReg;
462 }
463 
464 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
465  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
466  return 0;
467 
468  // If we can do this in a single instruction without a constant pool entry
469  // do so now.
470  const ConstantInt *CI = cast<ConstantInt>(C);
471  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
472  unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
473  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
474  &ARM::GPRRegClass;
475  unsigned ImmReg = createResultReg(RC);
476  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
477  TII.get(Opc), ImmReg)
478  .addImm(CI->getZExtValue()));
479  return ImmReg;
480  }
481 
482  // Use MVN to emit negative constants.
483  if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
484  unsigned Imm = (unsigned)~(CI->getSExtValue());
485  bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
486  (ARM_AM::getSOImmVal(Imm) != -1);
487  if (UseImm) {
488  unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
489  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
490  &ARM::GPRRegClass;
491  unsigned ImmReg = createResultReg(RC);
492  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
493  TII.get(Opc), ImmReg)
494  .addImm(Imm));
495  return ImmReg;
496  }
497  }
498 
499  unsigned ResultReg = 0;
500  if (Subtarget->useMovt())
501  ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
502 
503  if (ResultReg)
504  return ResultReg;
505 
506  // Load from constant pool. For now 32-bit only.
507  if (VT != MVT::i32)
508  return 0;
509 
510  // MachineConstantPool wants an explicit alignment.
511  unsigned Align = DL.getPrefTypeAlignment(C->getType());
512  if (Align == 0) {
513  // TODO: Figure out if this is correct.
514  Align = DL.getTypeAllocSize(C->getType());
515  }
516  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
517  ResultReg = createResultReg(TLI.getRegClassFor(VT));
518  if (isThumb2)
519  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
520  TII.get(ARM::t2LDRpci), ResultReg)
521  .addConstantPoolIndex(Idx));
522  else {
523  // The extra immediate is for addrmode2.
524  ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
525  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
526  TII.get(ARM::LDRcp), ResultReg)
527  .addConstantPoolIndex(Idx)
528  .addImm(0));
529  }
530  return ResultReg;
531 }
532 
533 bool ARMFastISel::isPositionIndependent() const {
534  return TLI.isPositionIndependent();
535 }
536 
537 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
538  // For now 32-bit only.
539  if (VT != MVT::i32 || GV->isThreadLocal()) return 0;
540 
541  // ROPI/RWPI not currently supported.
542  if (Subtarget->isROPI() || Subtarget->isRWPI())
543  return 0;
544 
545  bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
546  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
547  : &ARM::GPRRegClass;
548  unsigned DestReg = createResultReg(RC);
549 
550  // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
551  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
552  bool IsThreadLocal = GVar && GVar->isThreadLocal();
553  if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
554 
555  bool IsPositionIndependent = isPositionIndependent();
556  // Use movw+movt when possible, it avoids constant pool entries.
557  // Non-darwin targets only support static movt relocations in FastISel.
558  if (Subtarget->useMovt() &&
559  (Subtarget->isTargetMachO() || !IsPositionIndependent)) {
560  unsigned Opc;
561  unsigned char TF = 0;
562  if (Subtarget->isTargetMachO())
563  TF = ARMII::MO_NONLAZY;
564 
565  if (IsPositionIndependent)
566  Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
567  else
568  Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
569  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
570  TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
571  } else {
572  // MachineConstantPool wants an explicit alignment.
573  unsigned Align = DL.getPrefTypeAlignment(GV->getType());
574  if (Align == 0) {
575  // TODO: Figure out if this is correct.
576  Align = DL.getTypeAllocSize(GV->getType());
577  }
578 
579  if (Subtarget->isTargetELF() && IsPositionIndependent)
580  return ARMLowerPICELF(GV, Align, VT);
581 
582  // Grab index.
583  unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
584  unsigned Id = AFI->createPICLabelUId();
587  PCAdj);
588  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
589 
590  // Load value.
592  if (isThumb2) {
593  unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci;
594  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
595  DestReg).addConstantPoolIndex(Idx);
596  if (IsPositionIndependent)
597  MIB.addImm(Id);
598  AddOptionalDefs(MIB);
599  } else {
600  // The extra immediate is for addrmode2.
601  DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
602  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
603  TII.get(ARM::LDRcp), DestReg)
604  .addConstantPoolIndex(Idx)
605  .addImm(0);
606  AddOptionalDefs(MIB);
607 
608  if (IsPositionIndependent) {
609  unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
610  unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
611 
612  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
613  DbgLoc, TII.get(Opc), NewDestReg)
614  .addReg(DestReg)
615  .addImm(Id);
616  AddOptionalDefs(MIB);
617  return NewDestReg;
618  }
619  }
620  }
621 
622  if (IsIndirect) {
624  unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
625  if (isThumb2)
626  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
627  TII.get(ARM::t2LDRi12), NewDestReg)
628  .addReg(DestReg)
629  .addImm(0);
630  else
631  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
632  TII.get(ARM::LDRi12), NewDestReg)
633  .addReg(DestReg)
634  .addImm(0);
635  DestReg = NewDestReg;
636  AddOptionalDefs(MIB);
637  }
638 
639  return DestReg;
640 }
641 
642 unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
643  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
644 
645  // Only handle simple types.
646  if (!CEVT.isSimple()) return 0;
647  MVT VT = CEVT.getSimpleVT();
648 
649  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
650  return ARMMaterializeFP(CFP, VT);
651  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
652  return ARMMaterializeGV(GV, VT);
653  else if (isa<ConstantInt>(C))
654  return ARMMaterializeInt(C, VT);
655 
656  return 0;
657 }
658 
659 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
660 
661 unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
662  // Don't handle dynamic allocas.
663  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
664 
665  MVT VT;
666  if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
667 
669  FuncInfo.StaticAllocaMap.find(AI);
670 
671  // This will get lowered later into the correct offsets and registers
672  // via rewriteXFrameIndex.
673  if (SI != FuncInfo.StaticAllocaMap.end()) {
674  unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
675  const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
676  unsigned ResultReg = createResultReg(RC);
677  ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
678 
679  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
680  TII.get(Opc), ResultReg)
681  .addFrameIndex(SI->second)
682  .addImm(0));
683  return ResultReg;
684  }
685 
686  return 0;
687 }
688 
689 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
690  EVT evt = TLI.getValueType(DL, Ty, true);
691 
692  // Only handle simple types.
693  if (evt == MVT::Other || !evt.isSimple()) return false;
694  VT = evt.getSimpleVT();
695 
696  // Handle all legal types, i.e. a register that will directly hold this
697  // value.
698  return TLI.isTypeLegal(VT);
699 }
700 
701 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
702  if (isTypeLegal(Ty, VT)) return true;
703 
704  // If this is a type than can be sign or zero-extended to a basic operation
705  // go ahead and accept it now.
706  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
707  return true;
708 
709  return false;
710 }
711 
712 // Computes the address to get to an object.
713 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
714  // Some boilerplate from the X86 FastISel.
715  const User *U = nullptr;
716  unsigned Opcode = Instruction::UserOp1;
717  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
718  // Don't walk into other basic blocks unless the object is an alloca from
719  // another block, otherwise it may not have a virtual register assigned.
720  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
721  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
722  Opcode = I->getOpcode();
723  U = I;
724  }
725  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
726  Opcode = C->getOpcode();
727  U = C;
728  }
729 
730  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
731  if (Ty->getAddressSpace() > 255)
732  // Fast instruction selection doesn't support the special
733  // address spaces.
734  return false;
735 
736  switch (Opcode) {
737  default:
738  break;
739  case Instruction::BitCast:
740  // Look through bitcasts.
741  return ARMComputeAddress(U->getOperand(0), Addr);
742  case Instruction::IntToPtr:
743  // Look past no-op inttoptrs.
744  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
745  TLI.getPointerTy(DL))
746  return ARMComputeAddress(U->getOperand(0), Addr);
747  break;
748  case Instruction::PtrToInt:
749  // Look past no-op ptrtoints.
750  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
751  return ARMComputeAddress(U->getOperand(0), Addr);
752  break;
753  case Instruction::GetElementPtr: {
754  Address SavedAddr = Addr;
755  int TmpOffset = Addr.Offset;
756 
757  // Iterate through the GEP folding the constants into offsets where
758  // we can.
760  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
761  i != e; ++i, ++GTI) {
762  const Value *Op = *i;
763  if (StructType *STy = GTI.getStructTypeOrNull()) {
764  const StructLayout *SL = DL.getStructLayout(STy);
765  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
766  TmpOffset += SL->getElementOffset(Idx);
767  } else {
768  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
769  while (true) {
770  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
771  // Constant-offset addressing.
772  TmpOffset += CI->getSExtValue() * S;
773  break;
774  }
775  if (canFoldAddIntoGEP(U, Op)) {
776  // A compatible add with a constant operand. Fold the constant.
777  ConstantInt *CI =
778  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
779  TmpOffset += CI->getSExtValue() * S;
780  // Iterate on the other operand.
781  Op = cast<AddOperator>(Op)->getOperand(0);
782  continue;
783  }
784  // Unsupported
785  goto unsupported_gep;
786  }
787  }
788  }
789 
790  // Try to grab the base operand now.
791  Addr.Offset = TmpOffset;
792  if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
793 
794  // We failed, restore everything and try the other options.
795  Addr = SavedAddr;
796 
797  unsupported_gep:
798  break;
799  }
800  case Instruction::Alloca: {
801  const AllocaInst *AI = cast<AllocaInst>(Obj);
803  FuncInfo.StaticAllocaMap.find(AI);
804  if (SI != FuncInfo.StaticAllocaMap.end()) {
805  Addr.BaseType = Address::FrameIndexBase;
806  Addr.Base.FI = SI->second;
807  return true;
808  }
809  break;
810  }
811  }
812 
813  // Try to get this in a register if nothing else has worked.
814  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
815  return Addr.Base.Reg != 0;
816 }
817 
818 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
819  bool needsLowering = false;
820  switch (VT.SimpleTy) {
821  default: llvm_unreachable("Unhandled load/store type!");
822  case MVT::i1:
823  case MVT::i8:
824  case MVT::i16:
825  case MVT::i32:
826  if (!useAM3) {
827  // Integer loads/stores handle 12-bit offsets.
828  needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
829  // Handle negative offsets.
830  if (needsLowering && isThumb2)
831  needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
832  Addr.Offset > -256);
833  } else {
834  // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
835  needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
836  }
837  break;
838  case MVT::f32:
839  case MVT::f64:
840  // Floating point operands handle 8-bit offsets.
841  needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
842  break;
843  }
844 
845  // If this is a stack pointer and the offset needs to be simplified then
846  // put the alloca address into a register, set the base type back to
847  // register and continue. This should almost never happen.
848  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
849  const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
850  : &ARM::GPRRegClass;
851  unsigned ResultReg = createResultReg(RC);
852  unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
853  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
854  TII.get(Opc), ResultReg)
855  .addFrameIndex(Addr.Base.FI)
856  .addImm(0));
857  Addr.Base.Reg = ResultReg;
858  Addr.BaseType = Address::RegBase;
859  }
860 
861  // Since the offset is too large for the load/store instruction
862  // get the reg+offset into a register.
863  if (needsLowering) {
864  Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
865  /*Op0IsKill*/false, Addr.Offset, MVT::i32);
866  Addr.Offset = 0;
867  }
868 }
869 
870 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
871  const MachineInstrBuilder &MIB,
873  bool useAM3) {
874  // addrmode5 output depends on the selection dag addressing dividing the
875  // offset by 4 that it then later multiplies. Do this here as well.
876  if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
877  Addr.Offset /= 4;
878 
879  // Frame base works a bit differently. Handle it separately.
880  if (Addr.BaseType == Address::FrameIndexBase) {
881  int FI = Addr.Base.FI;
882  int Offset = Addr.Offset;
883  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
884  MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
885  MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
886  // Now add the rest of the operands.
887  MIB.addFrameIndex(FI);
888 
889  // ARM halfword load/stores and signed byte loads need an additional
890  // operand.
891  if (useAM3) {
892  int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
893  MIB.addReg(0);
894  MIB.addImm(Imm);
895  } else {
896  MIB.addImm(Addr.Offset);
897  }
898  MIB.addMemOperand(MMO);
899  } else {
900  // Now add the rest of the operands.
901  MIB.addReg(Addr.Base.Reg);
902 
903  // ARM halfword load/stores and signed byte loads need an additional
904  // operand.
905  if (useAM3) {
906  int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
907  MIB.addReg(0);
908  MIB.addImm(Imm);
909  } else {
910  MIB.addImm(Addr.Offset);
911  }
912  }
913  AddOptionalDefs(MIB);
914 }
915 
916 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
917  unsigned Alignment, bool isZExt, bool allocReg) {
918  unsigned Opc;
919  bool useAM3 = false;
920  bool needVMOV = false;
921  const TargetRegisterClass *RC;
922  switch (VT.SimpleTy) {
923  // This is mostly going to be Neon/vector support.
924  default: return false;
925  case MVT::i1:
926  case MVT::i8:
927  if (isThumb2) {
928  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
929  Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
930  else
931  Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
932  } else {
933  if (isZExt) {
934  Opc = ARM::LDRBi12;
935  } else {
936  Opc = ARM::LDRSB;
937  useAM3 = true;
938  }
939  }
940  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
941  break;
942  case MVT::i16:
943  if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
944  return false;
945 
946  if (isThumb2) {
947  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
948  Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
949  else
950  Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
951  } else {
952  Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
953  useAM3 = true;
954  }
955  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
956  break;
957  case MVT::i32:
958  if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
959  return false;
960 
961  if (isThumb2) {
962  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
963  Opc = ARM::t2LDRi8;
964  else
965  Opc = ARM::t2LDRi12;
966  } else {
967  Opc = ARM::LDRi12;
968  }
969  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
970  break;
971  case MVT::f32:
972  if (!Subtarget->hasVFP2()) return false;
973  // Unaligned loads need special handling. Floats require word-alignment.
974  if (Alignment && Alignment < 4) {
975  needVMOV = true;
976  VT = MVT::i32;
977  Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
978  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
979  } else {
980  Opc = ARM::VLDRS;
981  RC = TLI.getRegClassFor(VT);
982  }
983  break;
984  case MVT::f64:
985  if (!Subtarget->hasVFP2()) return false;
986  // FIXME: Unaligned loads need special handling. Doublewords require
987  // word-alignment.
988  if (Alignment && Alignment < 4)
989  return false;
990 
991  Opc = ARM::VLDRD;
992  RC = TLI.getRegClassFor(VT);
993  break;
994  }
995  // Simplify this down to something we can handle.
996  ARMSimplifyAddress(Addr, VT, useAM3);
997 
998  // Create the base instruction, then add the operands.
999  if (allocReg)
1000  ResultReg = createResultReg(RC);
1001  assert(ResultReg > 255 && "Expected an allocated virtual register.");
1002  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1003  TII.get(Opc), ResultReg);
1004  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1005 
1006  // If we had an unaligned load of a float we've converted it to an regular
1007  // load. Now we must move from the GRP to the FP register.
1008  if (needVMOV) {
1009  unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1010  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1011  TII.get(ARM::VMOVSR), MoveReg)
1012  .addReg(ResultReg));
1013  ResultReg = MoveReg;
1014  }
1015  return true;
1016 }
1017 
1018 bool ARMFastISel::SelectLoad(const Instruction *I) {
1019  // Atomic loads need special handling.
1020  if (cast<LoadInst>(I)->isAtomic())
1021  return false;
1022 
1023  const Value *SV = I->getOperand(0);
1024  if (TLI.supportSwiftError()) {
1025  // Swifterror values can come from either a function parameter with
1026  // swifterror attribute or an alloca with swifterror attribute.
1027  if (const Argument *Arg = dyn_cast<Argument>(SV)) {
1028  if (Arg->hasSwiftErrorAttr())
1029  return false;
1030  }
1031 
1032  if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
1033  if (Alloca->isSwiftError())
1034  return false;
1035  }
1036  }
1037 
1038  // Verify we have a legal type before going any further.
1039  MVT VT;
1040  if (!isLoadTypeLegal(I->getType(), VT))
1041  return false;
1042 
1043  // See if we can handle this address.
1044  Address Addr;
1045  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1046 
1047  unsigned ResultReg;
1048  if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1049  return false;
1050  updateValueMap(I, ResultReg);
1051  return true;
1052 }
1053 
1054 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1055  unsigned Alignment) {
1056  unsigned StrOpc;
1057  bool useAM3 = false;
1058  switch (VT.SimpleTy) {
1059  // This is mostly going to be Neon/vector support.
1060  default: return false;
1061  case MVT::i1: {
1062  unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1063  : &ARM::GPRRegClass);
1064  unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1065  SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1066  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1067  TII.get(Opc), Res)
1068  .addReg(SrcReg).addImm(1));
1069  SrcReg = Res;
1071  }
1072  case MVT::i8:
1073  if (isThumb2) {
1074  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1075  StrOpc = ARM::t2STRBi8;
1076  else
1077  StrOpc = ARM::t2STRBi12;
1078  } else {
1079  StrOpc = ARM::STRBi12;
1080  }
1081  break;
1082  case MVT::i16:
1083  if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1084  return false;
1085 
1086  if (isThumb2) {
1087  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1088  StrOpc = ARM::t2STRHi8;
1089  else
1090  StrOpc = ARM::t2STRHi12;
1091  } else {
1092  StrOpc = ARM::STRH;
1093  useAM3 = true;
1094  }
1095  break;
1096  case MVT::i32:
1097  if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1098  return false;
1099 
1100  if (isThumb2) {
1101  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1102  StrOpc = ARM::t2STRi8;
1103  else
1104  StrOpc = ARM::t2STRi12;
1105  } else {
1106  StrOpc = ARM::STRi12;
1107  }
1108  break;
1109  case MVT::f32:
1110  if (!Subtarget->hasVFP2()) return false;
1111  // Unaligned stores need special handling. Floats require word-alignment.
1112  if (Alignment && Alignment < 4) {
1113  unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1114  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1115  TII.get(ARM::VMOVRS), MoveReg)
1116  .addReg(SrcReg));
1117  SrcReg = MoveReg;
1118  VT = MVT::i32;
1119  StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1120  } else {
1121  StrOpc = ARM::VSTRS;
1122  }
1123  break;
1124  case MVT::f64:
1125  if (!Subtarget->hasVFP2()) return false;
1126  // FIXME: Unaligned stores need special handling. Doublewords require
1127  // word-alignment.
1128  if (Alignment && Alignment < 4)
1129  return false;
1130 
1131  StrOpc = ARM::VSTRD;
1132  break;
1133  }
1134  // Simplify this down to something we can handle.
1135  ARMSimplifyAddress(Addr, VT, useAM3);
1136 
1137  // Create the base instruction, then add the operands.
1138  SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1139  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1140  TII.get(StrOpc))
1141  .addReg(SrcReg);
1142  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1143  return true;
1144 }
1145 
1146 bool ARMFastISel::SelectStore(const Instruction *I) {
1147  Value *Op0 = I->getOperand(0);
1148  unsigned SrcReg = 0;
1149 
1150  // Atomic stores need special handling.
1151  if (cast<StoreInst>(I)->isAtomic())
1152  return false;
1153 
1154  const Value *PtrV = I->getOperand(1);
1155  if (TLI.supportSwiftError()) {
1156  // Swifterror values can come from either a function parameter with
1157  // swifterror attribute or an alloca with swifterror attribute.
1158  if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
1159  if (Arg->hasSwiftErrorAttr())
1160  return false;
1161  }
1162 
1163  if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
1164  if (Alloca->isSwiftError())
1165  return false;
1166  }
1167  }
1168 
1169  // Verify we have a legal type before going any further.
1170  MVT VT;
1171  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1172  return false;
1173 
1174  // Get the value to be stored into a register.
1175  SrcReg = getRegForValue(Op0);
1176  if (SrcReg == 0) return false;
1177 
1178  // See if we can handle this address.
1179  Address Addr;
1180  if (!ARMComputeAddress(I->getOperand(1), Addr))
1181  return false;
1182 
1183  if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1184  return false;
1185  return true;
1186 }
1187 
1189  switch (Pred) {
1190  // Needs two compares...
1191  case CmpInst::FCMP_ONE:
1192  case CmpInst::FCMP_UEQ:
1193  default:
1194  // AL is our "false" for now. The other two need more compares.
1195  return ARMCC::AL;
1196  case CmpInst::ICMP_EQ:
1197  case CmpInst::FCMP_OEQ:
1198  return ARMCC::EQ;
1199  case CmpInst::ICMP_SGT:
1200  case CmpInst::FCMP_OGT:
1201  return ARMCC::GT;
1202  case CmpInst::ICMP_SGE:
1203  case CmpInst::FCMP_OGE:
1204  return ARMCC::GE;
1205  case CmpInst::ICMP_UGT:
1206  case CmpInst::FCMP_UGT:
1207  return ARMCC::HI;
1208  case CmpInst::FCMP_OLT:
1209  return ARMCC::MI;
1210  case CmpInst::ICMP_ULE:
1211  case CmpInst::FCMP_OLE:
1212  return ARMCC::LS;
1213  case CmpInst::FCMP_ORD:
1214  return ARMCC::VC;
1215  case CmpInst::FCMP_UNO:
1216  return ARMCC::VS;
1217  case CmpInst::FCMP_UGE:
1218  return ARMCC::PL;
1219  case CmpInst::ICMP_SLT:
1220  case CmpInst::FCMP_ULT:
1221  return ARMCC::LT;
1222  case CmpInst::ICMP_SLE:
1223  case CmpInst::FCMP_ULE:
1224  return ARMCC::LE;
1225  case CmpInst::FCMP_UNE:
1226  case CmpInst::ICMP_NE:
1227  return ARMCC::NE;
1228  case CmpInst::ICMP_UGE:
1229  return ARMCC::HS;
1230  case CmpInst::ICMP_ULT:
1231  return ARMCC::LO;
1232  }
1233 }
1234 
1235 bool ARMFastISel::SelectBranch(const Instruction *I) {
1236  const BranchInst *BI = cast<BranchInst>(I);
1237  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1238  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1239 
1240  // Simple branch support.
1241 
1242  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1243  // behavior.
1244  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1245  if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1246  // Get the compare predicate.
1247  // Try to take advantage of fallthrough opportunities.
1248  CmpInst::Predicate Predicate = CI->getPredicate();
1249  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1250  std::swap(TBB, FBB);
1251  Predicate = CmpInst::getInversePredicate(Predicate);
1252  }
1253 
1254  ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1255 
1256  // We may not handle every CC for now.
1257  if (ARMPred == ARMCC::AL) return false;
1258 
1259  // Emit the compare.
1260  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
1261  CI->isEquality()))
1262  return false;
1263 
1264  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1265  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1266  .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1267  finishCondBranch(BI->getParent(), TBB, FBB);
1268  return true;
1269  }
1270  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1271  MVT SourceVT;
1272  if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1273  (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1274  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1275  unsigned OpReg = getRegForValue(TI->getOperand(0));
1276  OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1277  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1278  TII.get(TstOpc))
1279  .addReg(OpReg).addImm(1));
1280 
1281  unsigned CCMode = ARMCC::NE;
1282  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1283  std::swap(TBB, FBB);
1284  CCMode = ARMCC::EQ;
1285  }
1286 
1287  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1288  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1289  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1290 
1291  finishCondBranch(BI->getParent(), TBB, FBB);
1292  return true;
1293  }
1294  } else if (const ConstantInt *CI =
1295  dyn_cast<ConstantInt>(BI->getCondition())) {
1296  uint64_t Imm = CI->getZExtValue();
1297  MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1298  fastEmitBranch(Target, DbgLoc);
1299  return true;
1300  }
1301 
1302  unsigned CmpReg = getRegForValue(BI->getCondition());
1303  if (CmpReg == 0) return false;
1304 
1305  // We've been divorced from our compare! Our block was split, and
1306  // now our compare lives in a predecessor block. We musn't
1307  // re-compare here, as the children of the compare aren't guaranteed
1308  // live across the block boundary (we *could* check for this).
1309  // Regardless, the compare has been done in the predecessor block,
1310  // and it left a value for us in a virtual register. Ergo, we test
1311  // the one-bit value left in the virtual register.
1312  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1313  CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1314  AddOptionalDefs(
1315  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1316  .addReg(CmpReg)
1317  .addImm(1));
1318 
1319  unsigned CCMode = ARMCC::NE;
1320  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1321  std::swap(TBB, FBB);
1322  CCMode = ARMCC::EQ;
1323  }
1324 
1325  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1326  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1327  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1328  finishCondBranch(BI->getParent(), TBB, FBB);
1329  return true;
1330 }
1331 
1332 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1333  unsigned AddrReg = getRegForValue(I->getOperand(0));
1334  if (AddrReg == 0) return false;
1335 
1336  unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1337  assert(isThumb2 || Subtarget->hasV4TOps());
1338 
1339  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1340  TII.get(Opc)).addReg(AddrReg));
1341 
1342  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1343  for (const BasicBlock *SuccBB : IB->successors())
1344  FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1345 
1346  return true;
1347 }
1348 
1349 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1350  bool isZExt, bool isEquality) {
1351  Type *Ty = Src1Value->getType();
1352  EVT SrcEVT = TLI.getValueType(DL, Ty, true);
1353  if (!SrcEVT.isSimple()) return false;
1354  MVT SrcVT = SrcEVT.getSimpleVT();
1355 
1356  if (Ty->isFloatTy() && !Subtarget->hasVFP2())
1357  return false;
1358 
1359  if (Ty->isDoubleTy() && (!Subtarget->hasVFP2() || Subtarget->isFPOnlySP()))
1360  return false;
1361 
1362  // Check to see if the 2nd operand is a constant that we can encode directly
1363  // in the compare.
1364  int Imm = 0;
1365  bool UseImm = false;
1366  bool isNegativeImm = false;
1367  // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1368  // Thus, Src1Value may be a ConstantInt, but we're missing it.
1369  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1370  if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1371  SrcVT == MVT::i1) {
1372  const APInt &CIVal = ConstInt->getValue();
1373  Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1374  // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1375  // then a cmn, because there is no way to represent 2147483648 as a
1376  // signed 32-bit int.
1377  if (Imm < 0 && Imm != (int)0x80000000) {
1378  isNegativeImm = true;
1379  Imm = -Imm;
1380  }
1381  UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1382  (ARM_AM::getSOImmVal(Imm) != -1);
1383  }
1384  } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1385  if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1386  if (ConstFP->isZero() && !ConstFP->isNegative())
1387  UseImm = true;
1388  }
1389 
1390  unsigned CmpOpc;
1391  bool isICmp = true;
1392  bool needsExt = false;
1393  switch (SrcVT.SimpleTy) {
1394  default: return false;
1395  // TODO: Verify compares.
1396  case MVT::f32:
1397  isICmp = false;
1398  // Equality comparisons shouldn't raise Invalid on uordered inputs.
1399  if (isEquality)
1400  CmpOpc = UseImm ? ARM::VCMPZS : ARM::VCMPS;
1401  else
1402  CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1403  break;
1404  case MVT::f64:
1405  isICmp = false;
1406  // Equality comparisons shouldn't raise Invalid on uordered inputs.
1407  if (isEquality)
1408  CmpOpc = UseImm ? ARM::VCMPZD : ARM::VCMPD;
1409  else
1410  CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1411  break;
1412  case MVT::i1:
1413  case MVT::i8:
1414  case MVT::i16:
1415  needsExt = true;
1417  case MVT::i32:
1418  if (isThumb2) {
1419  if (!UseImm)
1420  CmpOpc = ARM::t2CMPrr;
1421  else
1422  CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1423  } else {
1424  if (!UseImm)
1425  CmpOpc = ARM::CMPrr;
1426  else
1427  CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1428  }
1429  break;
1430  }
1431 
1432  unsigned SrcReg1 = getRegForValue(Src1Value);
1433  if (SrcReg1 == 0) return false;
1434 
1435  unsigned SrcReg2 = 0;
1436  if (!UseImm) {
1437  SrcReg2 = getRegForValue(Src2Value);
1438  if (SrcReg2 == 0) return false;
1439  }
1440 
1441  // We have i1, i8, or i16, we need to either zero extend or sign extend.
1442  if (needsExt) {
1443  SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1444  if (SrcReg1 == 0) return false;
1445  if (!UseImm) {
1446  SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1447  if (SrcReg2 == 0) return false;
1448  }
1449  }
1450 
1451  const MCInstrDesc &II = TII.get(CmpOpc);
1452  SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1453  if (!UseImm) {
1454  SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1455  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1456  .addReg(SrcReg1).addReg(SrcReg2));
1457  } else {
1458  MachineInstrBuilder MIB;
1459  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1460  .addReg(SrcReg1);
1461 
1462  // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1463  if (isICmp)
1464  MIB.addImm(Imm);
1465  AddOptionalDefs(MIB);
1466  }
1467 
1468  // For floating point we need to move the result to a comparison register
1469  // that we can then use for branches.
1470  if (Ty->isFloatTy() || Ty->isDoubleTy())
1471  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1472  TII.get(ARM::FMSTAT)));
1473  return true;
1474 }
1475 
1476 bool ARMFastISel::SelectCmp(const Instruction *I) {
1477  const CmpInst *CI = cast<CmpInst>(I);
1478 
1479  // Get the compare predicate.
1480  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1481 
1482  // We may not handle every CC for now.
1483  if (ARMPred == ARMCC::AL) return false;
1484 
1485  // Emit the compare.
1486  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
1487  CI->isEquality()))
1488  return false;
1489 
1490  // Now set a register based on the comparison. Explicitly set the predicates
1491  // here.
1492  unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1493  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1494  : &ARM::GPRRegClass;
1495  unsigned DestReg = createResultReg(RC);
1496  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1497  unsigned ZeroReg = fastMaterializeConstant(Zero);
1498  // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1499  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1500  .addReg(ZeroReg).addImm(1)
1501  .addImm(ARMPred).addReg(ARM::CPSR);
1502 
1503  updateValueMap(I, DestReg);
1504  return true;
1505 }
1506 
1507 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1508  // Make sure we have VFP and that we're extending float to double.
1509  if (!Subtarget->hasVFP2() || Subtarget->isFPOnlySP()) return false;
1510 
1511  Value *V = I->getOperand(0);
1512  if (!I->getType()->isDoubleTy() ||
1513  !V->getType()->isFloatTy()) return false;
1514 
1515  unsigned Op = getRegForValue(V);
1516  if (Op == 0) return false;
1517 
1518  unsigned Result = createResultReg(&ARM::DPRRegClass);
1519  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1520  TII.get(ARM::VCVTDS), Result)
1521  .addReg(Op));
1522  updateValueMap(I, Result);
1523  return true;
1524 }
1525 
1526 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1527  // Make sure we have VFP and that we're truncating double to float.
1528  if (!Subtarget->hasVFP2() || Subtarget->isFPOnlySP()) return false;
1529 
1530  Value *V = I->getOperand(0);
1531  if (!(I->getType()->isFloatTy() &&
1532  V->getType()->isDoubleTy())) return false;
1533 
1534  unsigned Op = getRegForValue(V);
1535  if (Op == 0) return false;
1536 
1537  unsigned Result = createResultReg(&ARM::SPRRegClass);
1538  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1539  TII.get(ARM::VCVTSD), Result)
1540  .addReg(Op));
1541  updateValueMap(I, Result);
1542  return true;
1543 }
1544 
1545 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1546  // Make sure we have VFP.
1547  if (!Subtarget->hasVFP2()) return false;
1548 
1549  MVT DstVT;
1550  Type *Ty = I->getType();
1551  if (!isTypeLegal(Ty, DstVT))
1552  return false;
1553 
1554  Value *Src = I->getOperand(0);
1555  EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1556  if (!SrcEVT.isSimple())
1557  return false;
1558  MVT SrcVT = SrcEVT.getSimpleVT();
1559  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1560  return false;
1561 
1562  unsigned SrcReg = getRegForValue(Src);
1563  if (SrcReg == 0) return false;
1564 
1565  // Handle sign-extension.
1566  if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1567  SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1568  /*isZExt*/!isSigned);
1569  if (SrcReg == 0) return false;
1570  }
1571 
1572  // The conversion routine works on fp-reg to fp-reg and the operand above
1573  // was an integer, move it to the fp registers if possible.
1574  unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1575  if (FP == 0) return false;
1576 
1577  unsigned Opc;
1578  if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1579  else if (Ty->isDoubleTy() && !Subtarget->isFPOnlySP())
1580  Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1581  else return false;
1582 
1583  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1584  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1585  TII.get(Opc), ResultReg).addReg(FP));
1586  updateValueMap(I, ResultReg);
1587  return true;
1588 }
1589 
1590 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1591  // Make sure we have VFP.
1592  if (!Subtarget->hasVFP2()) return false;
1593 
1594  MVT DstVT;
1595  Type *RetTy = I->getType();
1596  if (!isTypeLegal(RetTy, DstVT))
1597  return false;
1598 
1599  unsigned Op = getRegForValue(I->getOperand(0));
1600  if (Op == 0) return false;
1601 
1602  unsigned Opc;
1603  Type *OpTy = I->getOperand(0)->getType();
1604  if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1605  else if (OpTy->isDoubleTy() && !Subtarget->isFPOnlySP())
1606  Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1607  else return false;
1608 
1609  // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1610  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1611  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1612  TII.get(Opc), ResultReg).addReg(Op));
1613 
1614  // This result needs to be in an integer register, but the conversion only
1615  // takes place in fp-regs.
1616  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1617  if (IntReg == 0) return false;
1618 
1619  updateValueMap(I, IntReg);
1620  return true;
1621 }
1622 
1623 bool ARMFastISel::SelectSelect(const Instruction *I) {
1624  MVT VT;
1625  if (!isTypeLegal(I->getType(), VT))
1626  return false;
1627 
1628  // Things need to be register sized for register moves.
1629  if (VT != MVT::i32) return false;
1630 
1631  unsigned CondReg = getRegForValue(I->getOperand(0));
1632  if (CondReg == 0) return false;
1633  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1634  if (Op1Reg == 0) return false;
1635 
1636  // Check to see if we can use an immediate in the conditional move.
1637  int Imm = 0;
1638  bool UseImm = false;
1639  bool isNegativeImm = false;
1640  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1641  assert(VT == MVT::i32 && "Expecting an i32.");
1642  Imm = (int)ConstInt->getValue().getZExtValue();
1643  if (Imm < 0) {
1644  isNegativeImm = true;
1645  Imm = ~Imm;
1646  }
1647  UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1648  (ARM_AM::getSOImmVal(Imm) != -1);
1649  }
1650 
1651  unsigned Op2Reg = 0;
1652  if (!UseImm) {
1653  Op2Reg = getRegForValue(I->getOperand(2));
1654  if (Op2Reg == 0) return false;
1655  }
1656 
1657  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1658  CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1659  AddOptionalDefs(
1660  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1661  .addReg(CondReg)
1662  .addImm(1));
1663 
1664  unsigned MovCCOpc;
1665  const TargetRegisterClass *RC;
1666  if (!UseImm) {
1667  RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1668  MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1669  } else {
1670  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1671  if (!isNegativeImm)
1672  MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1673  else
1674  MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1675  }
1676  unsigned ResultReg = createResultReg(RC);
1677  if (!UseImm) {
1678  Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1679  Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1680  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1681  ResultReg)
1682  .addReg(Op2Reg)
1683  .addReg(Op1Reg)
1684  .addImm(ARMCC::NE)
1685  .addReg(ARM::CPSR);
1686  } else {
1687  Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1688  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1689  ResultReg)
1690  .addReg(Op1Reg)
1691  .addImm(Imm)
1692  .addImm(ARMCC::EQ)
1693  .addReg(ARM::CPSR);
1694  }
1695  updateValueMap(I, ResultReg);
1696  return true;
1697 }
1698 
1699 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1700  MVT VT;
1701  Type *Ty = I->getType();
1702  if (!isTypeLegal(Ty, VT))
1703  return false;
1704 
1705  // If we have integer div support we should have selected this automagically.
1706  // In case we have a real miss go ahead and return false and we'll pick
1707  // it up later.
1708  if (Subtarget->hasDivideInThumbMode())
1709  return false;
1710 
1711  // Otherwise emit a libcall.
1712  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1713  if (VT == MVT::i8)
1714  LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1715  else if (VT == MVT::i16)
1716  LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1717  else if (VT == MVT::i32)
1718  LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1719  else if (VT == MVT::i64)
1720  LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1721  else if (VT == MVT::i128)
1722  LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1723  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1724 
1725  return ARMEmitLibcall(I, LC);
1726 }
1727 
1728 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1729  MVT VT;
1730  Type *Ty = I->getType();
1731  if (!isTypeLegal(Ty, VT))
1732  return false;
1733 
1734  // Many ABIs do not provide a libcall for standalone remainder, so we need to
1735  // use divrem (see the RTABI 4.3.1). Since FastISel can't handle non-double
1736  // multi-reg returns, we'll have to bail out.
1737  if (!TLI.hasStandaloneRem(VT)) {
1738  return false;
1739  }
1740 
1741  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1742  if (VT == MVT::i8)
1743  LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1744  else if (VT == MVT::i16)
1745  LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1746  else if (VT == MVT::i32)
1747  LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1748  else if (VT == MVT::i64)
1749  LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1750  else if (VT == MVT::i128)
1751  LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1752  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1753 
1754  return ARMEmitLibcall(I, LC);
1755 }
1756 
1757 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1758  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1759 
1760  // We can get here in the case when we have a binary operation on a non-legal
1761  // type and the target independent selector doesn't know how to handle it.
1762  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1763  return false;
1764 
1765  unsigned Opc;
1766  switch (ISDOpcode) {
1767  default: return false;
1768  case ISD::ADD:
1769  Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1770  break;
1771  case ISD::OR:
1772  Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1773  break;
1774  case ISD::SUB:
1775  Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1776  break;
1777  }
1778 
1779  unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1780  if (SrcReg1 == 0) return false;
1781 
1782  // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1783  // in the instruction, rather then materializing the value in a register.
1784  unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1785  if (SrcReg2 == 0) return false;
1786 
1787  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1788  SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1789  SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1790  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1791  TII.get(Opc), ResultReg)
1792  .addReg(SrcReg1).addReg(SrcReg2));
1793  updateValueMap(I, ResultReg);
1794  return true;
1795 }
1796 
1797 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1798  EVT FPVT = TLI.getValueType(DL, I->getType(), true);
1799  if (!FPVT.isSimple()) return false;
1800  MVT VT = FPVT.getSimpleVT();
1801 
1802  // FIXME: Support vector types where possible.
1803  if (VT.isVector())
1804  return false;
1805 
1806  // We can get here in the case when we want to use NEON for our fp
1807  // operations, but can't figure out how to. Just use the vfp instructions
1808  // if we have them.
1809  // FIXME: It'd be nice to use NEON instructions.
1810  Type *Ty = I->getType();
1811  if (Ty->isFloatTy() && !Subtarget->hasVFP2())
1812  return false;
1813  if (Ty->isDoubleTy() && (!Subtarget->hasVFP2() || Subtarget->isFPOnlySP()))
1814  return false;
1815 
1816  unsigned Opc;
1817  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1818  switch (ISDOpcode) {
1819  default: return false;
1820  case ISD::FADD:
1821  Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1822  break;
1823  case ISD::FSUB:
1824  Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1825  break;
1826  case ISD::FMUL:
1827  Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1828  break;
1829  }
1830  unsigned Op1 = getRegForValue(I->getOperand(0));
1831  if (Op1 == 0) return false;
1832 
1833  unsigned Op2 = getRegForValue(I->getOperand(1));
1834  if (Op2 == 0) return false;
1835 
1836  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1837  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1838  TII.get(Opc), ResultReg)
1839  .addReg(Op1).addReg(Op2));
1840  updateValueMap(I, ResultReg);
1841  return true;
1842 }
1843 
1844 // Call Handling Code
1845 
1846 // This is largely taken directly from CCAssignFnForNode
1847 // TODO: We may not support all of this.
1848 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1849  bool Return,
1850  bool isVarArg) {
1851  switch (CC) {
1852  default:
1853  report_fatal_error("Unsupported calling convention");
1854  case CallingConv::Fast:
1855  if (Subtarget->hasVFP2() && !isVarArg) {
1856  if (!Subtarget->isAAPCS_ABI())
1857  return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1858  // For AAPCS ABI targets, just use VFP variant of the calling convention.
1859  return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1860  }
1862  case CallingConv::C:
1864  // Use target triple & subtarget features to do actual dispatch.
1865  if (Subtarget->isAAPCS_ABI()) {
1866  if (Subtarget->hasVFP2() &&
1867  TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1868  return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1869  else
1870  return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1871  } else {
1872  return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1873  }
1875  case CallingConv::Swift:
1876  if (!isVarArg)
1877  return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1878  // Fall through to soft float variant, variadic functions don't
1879  // use hard floating point ABI.
1882  return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1883  case CallingConv::ARM_APCS:
1884  return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1885  case CallingConv::GHC:
1886  if (Return)
1887  report_fatal_error("Can't return in GHC call convention");
1888  else
1889  return CC_ARM_APCS_GHC;
1890  }
1891 }
1892 
1893 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1894  SmallVectorImpl<unsigned> &ArgRegs,
1895  SmallVectorImpl<MVT> &ArgVTs,
1897  SmallVectorImpl<unsigned> &RegArgs,
1898  CallingConv::ID CC,
1899  unsigned &NumBytes,
1900  bool isVarArg) {
1902  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1903  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1904  CCAssignFnForCall(CC, false, isVarArg));
1905 
1906  // Check that we can handle all of the arguments. If we can't, then bail out
1907  // now before we add code to the MBB.
1908  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1909  CCValAssign &VA = ArgLocs[i];
1910  MVT ArgVT = ArgVTs[VA.getValNo()];
1911 
1912  // We don't handle NEON/vector parameters yet.
1913  if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1914  return false;
1915 
1916  // Now copy/store arg to correct locations.
1917  if (VA.isRegLoc() && !VA.needsCustom()) {
1918  continue;
1919  } else if (VA.needsCustom()) {
1920  // TODO: We need custom lowering for vector (v2f64) args.
1921  if (VA.getLocVT() != MVT::f64 ||
1922  // TODO: Only handle register args for now.
1923  !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1924  return false;
1925  } else {
1926  switch (ArgVT.SimpleTy) {
1927  default:
1928  return false;
1929  case MVT::i1:
1930  case MVT::i8:
1931  case MVT::i16:
1932  case MVT::i32:
1933  break;
1934  case MVT::f32:
1935  if (!Subtarget->hasVFP2())
1936  return false;
1937  break;
1938  case MVT::f64:
1939  if (!Subtarget->hasVFP2())
1940  return false;
1941  break;
1942  }
1943  }
1944  }
1945 
1946  // At the point, we are able to handle the call's arguments in fast isel.
1947 
1948  // Get a count of how many bytes are to be pushed on the stack.
1949  NumBytes = CCInfo.getNextStackOffset();
1950 
1951  // Issue CALLSEQ_START
1952  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1953  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1954  TII.get(AdjStackDown))
1955  .addImm(NumBytes).addImm(0));
1956 
1957  // Process the args.
1958  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1959  CCValAssign &VA = ArgLocs[i];
1960  const Value *ArgVal = Args[VA.getValNo()];
1961  unsigned Arg = ArgRegs[VA.getValNo()];
1962  MVT ArgVT = ArgVTs[VA.getValNo()];
1963 
1964  assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1965  "We don't handle NEON/vector parameters yet.");
1966 
1967  // Handle arg promotion, etc.
1968  switch (VA.getLocInfo()) {
1969  case CCValAssign::Full: break;
1970  case CCValAssign::SExt: {
1971  MVT DestVT = VA.getLocVT();
1972  Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1973  assert(Arg != 0 && "Failed to emit a sext");
1974  ArgVT = DestVT;
1975  break;
1976  }
1977  case CCValAssign::AExt:
1978  // Intentional fall-through. Handle AExt and ZExt.
1979  case CCValAssign::ZExt: {
1980  MVT DestVT = VA.getLocVT();
1981  Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1982  assert(Arg != 0 && "Failed to emit a zext");
1983  ArgVT = DestVT;
1984  break;
1985  }
1986  case CCValAssign::BCvt: {
1987  unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1988  /*TODO: Kill=*/false);
1989  assert(BC != 0 && "Failed to emit a bitcast!");
1990  Arg = BC;
1991  ArgVT = VA.getLocVT();
1992  break;
1993  }
1994  default: llvm_unreachable("Unknown arg promotion!");
1995  }
1996 
1997  // Now copy/store arg to correct locations.
1998  if (VA.isRegLoc() && !VA.needsCustom()) {
1999  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2000  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
2001  RegArgs.push_back(VA.getLocReg());
2002  } else if (VA.needsCustom()) {
2003  // TODO: We need custom lowering for vector (v2f64) args.
2004  assert(VA.getLocVT() == MVT::f64 &&
2005  "Custom lowering for v2f64 args not available");
2006 
2007  // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
2008  CCValAssign &NextVA = ArgLocs[++i];
2009 
2010  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2011  "We only handle register args!");
2012 
2013  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2014  TII.get(ARM::VMOVRRD), VA.getLocReg())
2015  .addReg(NextVA.getLocReg(), RegState::Define)
2016  .addReg(Arg));
2017  RegArgs.push_back(VA.getLocReg());
2018  RegArgs.push_back(NextVA.getLocReg());
2019  } else {
2020  assert(VA.isMemLoc());
2021  // Need to store on the stack.
2022 
2023  // Don't emit stores for undef values.
2024  if (isa<UndefValue>(ArgVal))
2025  continue;
2026 
2027  Address Addr;
2028  Addr.BaseType = Address::RegBase;
2029  Addr.Base.Reg = ARM::SP;
2030  Addr.Offset = VA.getLocMemOffset();
2031 
2032  bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2033  assert(EmitRet && "Could not emit a store for argument!");
2034  }
2035  }
2036 
2037  return true;
2038 }
2039 
2040 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2041  const Instruction *I, CallingConv::ID CC,
2042  unsigned &NumBytes, bool isVarArg) {
2043  // Issue CALLSEQ_END
2044  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2045  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2046  TII.get(AdjStackUp))
2047  .addImm(NumBytes).addImm(0));
2048 
2049  // Now the return value.
2050  if (RetVT != MVT::isVoid) {
2052  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2053  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2054 
2055  // Copy all of the result registers out of their specified physreg.
2056  if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2057  // For this move we copy into two registers and then move into the
2058  // double fp reg we want.
2059  MVT DestVT = RVLocs[0].getValVT();
2060  const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2061  unsigned ResultReg = createResultReg(DstRC);
2062  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2063  TII.get(ARM::VMOVDRR), ResultReg)
2064  .addReg(RVLocs[0].getLocReg())
2065  .addReg(RVLocs[1].getLocReg()));
2066 
2067  UsedRegs.push_back(RVLocs[0].getLocReg());
2068  UsedRegs.push_back(RVLocs[1].getLocReg());
2069 
2070  // Finally update the result.
2071  updateValueMap(I, ResultReg);
2072  } else {
2073  assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2074  MVT CopyVT = RVLocs[0].getValVT();
2075 
2076  // Special handling for extended integers.
2077  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2078  CopyVT = MVT::i32;
2079 
2080  const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2081 
2082  unsigned ResultReg = createResultReg(DstRC);
2083  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2084  TII.get(TargetOpcode::COPY),
2085  ResultReg).addReg(RVLocs[0].getLocReg());
2086  UsedRegs.push_back(RVLocs[0].getLocReg());
2087 
2088  // Finally update the result.
2089  updateValueMap(I, ResultReg);
2090  }
2091  }
2092 
2093  return true;
2094 }
2095 
2096 bool ARMFastISel::SelectRet(const Instruction *I) {
2097  const ReturnInst *Ret = cast<ReturnInst>(I);
2098  const Function &F = *I->getParent()->getParent();
2099 
2100  if (!FuncInfo.CanLowerReturn)
2101  return false;
2102 
2103  if (TLI.supportSwiftError() &&
2104  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError))
2105  return false;
2106 
2107  if (TLI.supportSplitCSR(FuncInfo.MF))
2108  return false;
2109 
2110  // Build a list of return value registers.
2111  SmallVector<unsigned, 4> RetRegs;
2112 
2113  CallingConv::ID CC = F.getCallingConv();
2114  if (Ret->getNumOperands() > 0) {
2116  GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2117 
2118  // Analyze operands of the call, assigning locations to each operand.
2120  CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2121  CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2122  F.isVarArg()));
2123 
2124  const Value *RV = Ret->getOperand(0);
2125  unsigned Reg = getRegForValue(RV);
2126  if (Reg == 0)
2127  return false;
2128 
2129  // Only handle a single return value for now.
2130  if (ValLocs.size() != 1)
2131  return false;
2132 
2133  CCValAssign &VA = ValLocs[0];
2134 
2135  // Don't bother handling odd stuff for now.
2136  if (VA.getLocInfo() != CCValAssign::Full)
2137  return false;
2138  // Only handle register returns for now.
2139  if (!VA.isRegLoc())
2140  return false;
2141 
2142  unsigned SrcReg = Reg + VA.getValNo();
2143  EVT RVEVT = TLI.getValueType(DL, RV->getType());
2144  if (!RVEVT.isSimple()) return false;
2145  MVT RVVT = RVEVT.getSimpleVT();
2146  MVT DestVT = VA.getValVT();
2147  // Special handling for extended integers.
2148  if (RVVT != DestVT) {
2149  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2150  return false;
2151 
2152  assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2153 
2154  // Perform extension if flagged as either zext or sext. Otherwise, do
2155  // nothing.
2156  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2157  SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2158  if (SrcReg == 0) return false;
2159  }
2160  }
2161 
2162  // Make the copy.
2163  unsigned DstReg = VA.getLocReg();
2164  const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2165  // Avoid a cross-class copy. This is very unlikely.
2166  if (!SrcRC->contains(DstReg))
2167  return false;
2168  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2169  TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2170 
2171  // Add register to return instruction.
2172  RetRegs.push_back(VA.getLocReg());
2173  }
2174 
2175  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2176  TII.get(Subtarget->getReturnOpcode()));
2177  AddOptionalDefs(MIB);
2178  for (unsigned R : RetRegs)
2179  MIB.addReg(R, RegState::Implicit);
2180  return true;
2181 }
2182 
2183 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2184  if (UseReg)
2185  return isThumb2 ? ARM::tBLXr : ARM::BLX;
2186  else
2187  return isThumb2 ? ARM::tBL : ARM::BL;
2188 }
2189 
2190 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2191  // Manually compute the global's type to avoid building it when unnecessary.
2192  Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2193  EVT LCREVT = TLI.getValueType(DL, GVTy);
2194  if (!LCREVT.isSimple()) return 0;
2195 
2196  GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2198  Name);
2199  assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2200  return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2201 }
2202 
2203 // A quick function that will emit a call for a named libcall in F with the
2204 // vector of passed arguments for the Instruction in I. We can assume that we
2205 // can emit a call for any libcall we can produce. This is an abridged version
2206 // of the full call infrastructure since we won't need to worry about things
2207 // like computed function pointers or strange arguments at call sites.
2208 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2209 // with X86.
2210 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2211  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2212 
2213  // Handle *simple* calls for now.
2214  Type *RetTy = I->getType();
2215  MVT RetVT;
2216  if (RetTy->isVoidTy())
2217  RetVT = MVT::isVoid;
2218  else if (!isTypeLegal(RetTy, RetVT))
2219  return false;
2220 
2221  // Can't handle non-double multi-reg retvals.
2222  if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2224  CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2225  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2226  if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2227  return false;
2228  }
2229 
2230  // Set up the argument vectors.
2232  SmallVector<unsigned, 8> ArgRegs;
2233  SmallVector<MVT, 8> ArgVTs;
2235  Args.reserve(I->getNumOperands());
2236  ArgRegs.reserve(I->getNumOperands());
2237  ArgVTs.reserve(I->getNumOperands());
2238  ArgFlags.reserve(I->getNumOperands());
2239  for (Value *Op : I->operands()) {
2240  unsigned Arg = getRegForValue(Op);
2241  if (Arg == 0) return false;
2242 
2243  Type *ArgTy = Op->getType();
2244  MVT ArgVT;
2245  if (!isTypeLegal(ArgTy, ArgVT)) return false;
2246 
2247  ISD::ArgFlagsTy Flags;
2248  unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2249  Flags.setOrigAlign(OriginalAlignment);
2250 
2251  Args.push_back(Op);
2252  ArgRegs.push_back(Arg);
2253  ArgVTs.push_back(ArgVT);
2254  ArgFlags.push_back(Flags);
2255  }
2256 
2257  // Handle the arguments now that we've gotten them.
2258  SmallVector<unsigned, 4> RegArgs;
2259  unsigned NumBytes;
2260  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2261  RegArgs, CC, NumBytes, false))
2262  return false;
2263 
2264  unsigned CalleeReg = 0;
2265  if (Subtarget->genLongCalls()) {
2266  CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2267  if (CalleeReg == 0) return false;
2268  }
2269 
2270  // Issue the call.
2271  unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
2272  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2273  DbgLoc, TII.get(CallOpc));
2274  // BL / BLX don't take a predicate, but tBL / tBLX do.
2275  if (isThumb2)
2276  MIB.add(predOps(ARMCC::AL));
2277  if (Subtarget->genLongCalls())
2278  MIB.addReg(CalleeReg);
2279  else
2280  MIB.addExternalSymbol(TLI.getLibcallName(Call));
2281 
2282  // Add implicit physical register uses to the call.
2283  for (unsigned R : RegArgs)
2284  MIB.addReg(R, RegState::Implicit);
2285 
2286  // Add a register mask with the call-preserved registers.
2287  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2288  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2289 
2290  // Finish off the call including any return values.
2291  SmallVector<unsigned, 4> UsedRegs;
2292  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2293 
2294  // Set all unused physreg defs as dead.
2295  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2296 
2297  return true;
2298 }
2299 
2300 bool ARMFastISel::SelectCall(const Instruction *I,
2301  const char *IntrMemName = nullptr) {
2302  const CallInst *CI = cast<CallInst>(I);
2303  const Value *Callee = CI->getCalledValue();
2304 
2305  // Can't handle inline asm.
2306  if (isa<InlineAsm>(Callee)) return false;
2307 
2308  // Allow SelectionDAG isel to handle tail calls.
2309  if (CI->isTailCall()) return false;
2310 
2311  // Check the calling convention.
2312  ImmutableCallSite CS(CI);
2313  CallingConv::ID CC = CS.getCallingConv();
2314 
2315  // TODO: Avoid some calling conventions?
2316 
2317  FunctionType *FTy = CS.getFunctionType();
2318  bool isVarArg = FTy->isVarArg();
2319 
2320  // Handle *simple* calls for now.
2321  Type *RetTy = I->getType();
2322  MVT RetVT;
2323  if (RetTy->isVoidTy())
2324  RetVT = MVT::isVoid;
2325  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2326  RetVT != MVT::i8 && RetVT != MVT::i1)
2327  return false;
2328 
2329  // Can't handle non-double multi-reg retvals.
2330  if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2331  RetVT != MVT::i16 && RetVT != MVT::i32) {
2333  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2334  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2335  if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2336  return false;
2337  }
2338 
2339  // Set up the argument vectors.
2341  SmallVector<unsigned, 8> ArgRegs;
2342  SmallVector<MVT, 8> ArgVTs;
2344  unsigned arg_size = CS.arg_size();
2345  Args.reserve(arg_size);
2346  ArgRegs.reserve(arg_size);
2347  ArgVTs.reserve(arg_size);
2348  ArgFlags.reserve(arg_size);
2349  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2350  i != e; ++i) {
2351  // If we're lowering a memory intrinsic instead of a regular call, skip the
2352  // last argument, which shouldn't be passed to the underlying function.
2353  if (IntrMemName && e - i <= 1)
2354  break;
2355 
2356  ISD::ArgFlagsTy Flags;
2357  unsigned ArgIdx = i - CS.arg_begin();
2358  if (CS.paramHasAttr(ArgIdx, Attribute::SExt))
2359  Flags.setSExt();
2360  if (CS.paramHasAttr(ArgIdx, Attribute::ZExt))
2361  Flags.setZExt();
2362 
2363  // FIXME: Only handle *easy* calls for now.
2364  if (CS.paramHasAttr(ArgIdx, Attribute::InReg) ||
2365  CS.paramHasAttr(ArgIdx, Attribute::StructRet) ||
2366  CS.paramHasAttr(ArgIdx, Attribute::SwiftSelf) ||
2367  CS.paramHasAttr(ArgIdx, Attribute::SwiftError) ||
2368  CS.paramHasAttr(ArgIdx, Attribute::Nest) ||
2369  CS.paramHasAttr(ArgIdx, Attribute::ByVal))
2370  return false;
2371 
2372  Type *ArgTy = (*i)->getType();
2373  MVT ArgVT;
2374  if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2375  ArgVT != MVT::i1)
2376  return false;
2377 
2378  unsigned Arg = getRegForValue(*i);
2379  if (Arg == 0)
2380  return false;
2381 
2382  unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2383  Flags.setOrigAlign(OriginalAlignment);
2384 
2385  Args.push_back(*i);
2386  ArgRegs.push_back(Arg);
2387  ArgVTs.push_back(ArgVT);
2388  ArgFlags.push_back(Flags);
2389  }
2390 
2391  // Handle the arguments now that we've gotten them.
2392  SmallVector<unsigned, 4> RegArgs;
2393  unsigned NumBytes;
2394  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2395  RegArgs, CC, NumBytes, isVarArg))
2396  return false;
2397 
2398  bool UseReg = false;
2399  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2400  if (!GV || Subtarget->genLongCalls()) UseReg = true;
2401 
2402  unsigned CalleeReg = 0;
2403  if (UseReg) {
2404  if (IntrMemName)
2405  CalleeReg = getLibcallReg(IntrMemName);
2406  else
2407  CalleeReg = getRegForValue(Callee);
2408 
2409  if (CalleeReg == 0) return false;
2410  }
2411 
2412  // Issue the call.
2413  unsigned CallOpc = ARMSelectCallOp(UseReg);
2414  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2415  DbgLoc, TII.get(CallOpc));
2416 
2417  // ARM calls don't take a predicate, but tBL / tBLX do.
2418  if(isThumb2)
2419  MIB.add(predOps(ARMCC::AL));
2420  if (UseReg)
2421  MIB.addReg(CalleeReg);
2422  else if (!IntrMemName)
2423  MIB.addGlobalAddress(GV, 0, 0);
2424  else
2425  MIB.addExternalSymbol(IntrMemName, 0);
2426 
2427  // Add implicit physical register uses to the call.
2428  for (unsigned R : RegArgs)
2429  MIB.addReg(R, RegState::Implicit);
2430 
2431  // Add a register mask with the call-preserved registers.
2432  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2433  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2434 
2435  // Finish off the call including any return values.
2436  SmallVector<unsigned, 4> UsedRegs;
2437  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2438  return false;
2439 
2440  // Set all unused physreg defs as dead.
2441  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2442 
2443  return true;
2444 }
2445 
2446 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2447  return Len <= 16;
2448 }
2449 
2450 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2451  uint64_t Len, unsigned Alignment) {
2452  // Make sure we don't bloat code by inlining very large memcpy's.
2453  if (!ARMIsMemCpySmall(Len))
2454  return false;
2455 
2456  while (Len) {
2457  MVT VT;
2458  if (!Alignment || Alignment >= 4) {
2459  if (Len >= 4)
2460  VT = MVT::i32;
2461  else if (Len >= 2)
2462  VT = MVT::i16;
2463  else {
2464  assert(Len == 1 && "Expected a length of 1!");
2465  VT = MVT::i8;
2466  }
2467  } else {
2468  // Bound based on alignment.
2469  if (Len >= 2 && Alignment == 2)
2470  VT = MVT::i16;
2471  else {
2472  VT = MVT::i8;
2473  }
2474  }
2475 
2476  bool RV;
2477  unsigned ResultReg;
2478  RV = ARMEmitLoad(VT, ResultReg, Src);
2479  assert(RV && "Should be able to handle this load.");
2480  RV = ARMEmitStore(VT, ResultReg, Dest);
2481  assert(RV && "Should be able to handle this store.");
2482  (void)RV;
2483 
2484  unsigned Size = VT.getSizeInBits()/8;
2485  Len -= Size;
2486  Dest.Offset += Size;
2487  Src.Offset += Size;
2488  }
2489 
2490  return true;
2491 }
2492 
2493 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2494  // FIXME: Handle more intrinsics.
2495  switch (I.getIntrinsicID()) {
2496  default: return false;
2497  case Intrinsic::frameaddress: {
2498  MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
2499  MFI.setFrameAddressIsTaken(true);
2500 
2501  unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2502  const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2503  : &ARM::GPRRegClass;
2504 
2505  const ARMBaseRegisterInfo *RegInfo =
2506  static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2507  unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2508  unsigned SrcReg = FramePtr;
2509 
2510  // Recursively load frame address
2511  // ldr r0 [fp]
2512  // ldr r0 [r0]
2513  // ldr r0 [r0]
2514  // ...
2515  unsigned DestReg;
2516  unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2517  while (Depth--) {
2518  DestReg = createResultReg(RC);
2519  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2520  TII.get(LdrOpc), DestReg)
2521  .addReg(SrcReg).addImm(0));
2522  SrcReg = DestReg;
2523  }
2524  updateValueMap(&I, SrcReg);
2525  return true;
2526  }
2527  case Intrinsic::memcpy:
2528  case Intrinsic::memmove: {
2529  const MemTransferInst &MTI = cast<MemTransferInst>(I);
2530  // Don't handle volatile.
2531  if (MTI.isVolatile())
2532  return false;
2533 
2534  // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2535  // we would emit dead code because we don't currently handle memmoves.
2536  bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2537  if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2538  // Small memcpy's are common enough that we want to do them without a call
2539  // if possible.
2540  uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2541  if (ARMIsMemCpySmall(Len)) {
2542  Address Dest, Src;
2543  if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2544  !ARMComputeAddress(MTI.getRawSource(), Src))
2545  return false;
2546  unsigned Alignment = MinAlign(MTI.getDestAlignment(),
2547  MTI.getSourceAlignment());
2548  if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2549  return true;
2550  }
2551  }
2552 
2553  if (!MTI.getLength()->getType()->isIntegerTy(32))
2554  return false;
2555 
2556  if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2557  return false;
2558 
2559  const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2560  return SelectCall(&I, IntrMemName);
2561  }
2562  case Intrinsic::memset: {
2563  const MemSetInst &MSI = cast<MemSetInst>(I);
2564  // Don't handle volatile.
2565  if (MSI.isVolatile())
2566  return false;
2567 
2568  if (!MSI.getLength()->getType()->isIntegerTy(32))
2569  return false;
2570 
2571  if (MSI.getDestAddressSpace() > 255)
2572  return false;
2573 
2574  return SelectCall(&I, "memset");
2575  }
2576  case Intrinsic::trap: {
2577  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2578  Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2579  return true;
2580  }
2581  }
2582 }
2583 
2584 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2585  // The high bits for a type smaller than the register size are assumed to be
2586  // undefined.
2587  Value *Op = I->getOperand(0);
2588 
2589  EVT SrcVT, DestVT;
2590  SrcVT = TLI.getValueType(DL, Op->getType(), true);
2591  DestVT = TLI.getValueType(DL, I->getType(), true);
2592 
2593  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2594  return false;
2595  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2596  return false;
2597 
2598  unsigned SrcReg = getRegForValue(Op);
2599  if (!SrcReg) return false;
2600 
2601  // Because the high bits are undefined, a truncate doesn't generate
2602  // any code.
2603  updateValueMap(I, SrcReg);
2604  return true;
2605 }
2606 
2607 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2608  bool isZExt) {
2609  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2610  return 0;
2611  if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2612  return 0;
2613 
2614  // Table of which combinations can be emitted as a single instruction,
2615  // and which will require two.
2616  static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2617  // ARM Thumb
2618  // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2619  // ext: s z s z s z s z
2620  /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2621  /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2622  /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2623  };
2624 
2625  // Target registers for:
2626  // - For ARM can never be PC.
2627  // - For 16-bit Thumb are restricted to lower 8 registers.
2628  // - For 32-bit Thumb are restricted to non-SP and non-PC.
2629  static const TargetRegisterClass *RCTbl[2][2] = {
2630  // Instructions: Two Single
2631  /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2632  /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2633  };
2634 
2635  // Table governing the instruction(s) to be emitted.
2636  static const struct InstructionTable {
2637  uint32_t Opc : 16;
2638  uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2639  uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2640  uint32_t Imm : 8; // All instructions have either a shift or a mask.
2641  } IT[2][2][3][2] = {
2642  { // Two instructions (first is left shift, second is in this table).
2643  { // ARM Opc S Shift Imm
2644  /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2645  /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2646  /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2647  /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2648  /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2649  /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2650  },
2651  { // Thumb Opc S Shift Imm
2652  /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2653  /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2654  /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2655  /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2656  /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2657  /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2658  }
2659  },
2660  { // Single instruction.
2661  { // ARM Opc S Shift Imm
2662  /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2663  /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2664  /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2665  /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2666  /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2667  /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2668  },
2669  { // Thumb Opc S Shift Imm
2670  /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2671  /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2672  /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2673  /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2674  /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2675  /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2676  }
2677  }
2678  };
2679 
2680  unsigned SrcBits = SrcVT.getSizeInBits();
2681  unsigned DestBits = DestVT.getSizeInBits();
2682  (void) DestBits;
2683  assert((SrcBits < DestBits) && "can only extend to larger types");
2684  assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2685  "other sizes unimplemented");
2686  assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2687  "other sizes unimplemented");
2688 
2689  bool hasV6Ops = Subtarget->hasV6Ops();
2690  unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2691  assert((Bitness < 3) && "sanity-check table bounds");
2692 
2693  bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2694  const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2695  const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2696  unsigned Opc = ITP->Opc;
2697  assert(ARM::KILL != Opc && "Invalid table entry");
2698  unsigned hasS = ITP->hasS;
2699  ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2700  assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2701  "only MOVsi has shift operand addressing mode");
2702  unsigned Imm = ITP->Imm;
2703 
2704  // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2705  bool setsCPSR = &ARM::tGPRRegClass == RC;
2706  unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2707  unsigned ResultReg;
2708  // MOVsi encodes shift and immediate in shift operand addressing mode.
2709  // The following condition has the same value when emitting two
2710  // instruction sequences: both are shifts.
2711  bool ImmIsSO = (Shift != ARM_AM::no_shift);
2712 
2713  // Either one or two instructions are emitted.
2714  // They're always of the form:
2715  // dst = in OP imm
2716  // CPSR is set only by 16-bit Thumb instructions.
2717  // Predicate, if any, is AL.
2718  // S bit, if available, is always 0.
2719  // When two are emitted the first's result will feed as the second's input,
2720  // that value is then dead.
2721  unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2722  for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2723  ResultReg = createResultReg(RC);
2724  bool isLsl = (0 == Instr) && !isSingleInstr;
2725  unsigned Opcode = isLsl ? LSLOpc : Opc;
2726  ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2727  unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2728  bool isKill = 1 == Instr;
2730  *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2731  if (setsCPSR)
2732  MIB.addReg(ARM::CPSR, RegState::Define);
2733  SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2734  MIB.addReg(SrcReg, isKill * RegState::Kill)
2735  .addImm(ImmEnc)
2736  .add(predOps(ARMCC::AL));
2737  if (hasS)
2738  MIB.add(condCodeOp());
2739  // Second instruction consumes the first's result.
2740  SrcReg = ResultReg;
2741  }
2742 
2743  return ResultReg;
2744 }
2745 
2746 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2747  // On ARM, in general, integer casts don't involve legal types; this code
2748  // handles promotable integers.
2749  Type *DestTy = I->getType();
2750  Value *Src = I->getOperand(0);
2751  Type *SrcTy = Src->getType();
2752 
2753  bool isZExt = isa<ZExtInst>(I);
2754  unsigned SrcReg = getRegForValue(Src);
2755  if (!SrcReg) return false;
2756 
2757  EVT SrcEVT, DestEVT;
2758  SrcEVT = TLI.getValueType(DL, SrcTy, true);
2759  DestEVT = TLI.getValueType(DL, DestTy, true);
2760  if (!SrcEVT.isSimple()) return false;
2761  if (!DestEVT.isSimple()) return false;
2762 
2763  MVT SrcVT = SrcEVT.getSimpleVT();
2764  MVT DestVT = DestEVT.getSimpleVT();
2765  unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2766  if (ResultReg == 0) return false;
2767  updateValueMap(I, ResultReg);
2768  return true;
2769 }
2770 
2771 bool ARMFastISel::SelectShift(const Instruction *I,
2772  ARM_AM::ShiftOpc ShiftTy) {
2773  // We handle thumb2 mode by target independent selector
2774  // or SelectionDAG ISel.
2775  if (isThumb2)
2776  return false;
2777 
2778  // Only handle i32 now.
2779  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
2780  if (DestVT != MVT::i32)
2781  return false;
2782 
2783  unsigned Opc = ARM::MOVsr;
2784  unsigned ShiftImm;
2785  Value *Src2Value = I->getOperand(1);
2786  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2787  ShiftImm = CI->getZExtValue();
2788 
2789  // Fall back to selection DAG isel if the shift amount
2790  // is zero or greater than the width of the value type.
2791  if (ShiftImm == 0 || ShiftImm >=32)
2792  return false;
2793 
2794  Opc = ARM::MOVsi;
2795  }
2796 
2797  Value *Src1Value = I->getOperand(0);
2798  unsigned Reg1 = getRegForValue(Src1Value);
2799  if (Reg1 == 0) return false;
2800 
2801  unsigned Reg2 = 0;
2802  if (Opc == ARM::MOVsr) {
2803  Reg2 = getRegForValue(Src2Value);
2804  if (Reg2 == 0) return false;
2805  }
2806 
2807  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2808  if(ResultReg == 0) return false;
2809 
2810  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2811  TII.get(Opc), ResultReg)
2812  .addReg(Reg1);
2813 
2814  if (Opc == ARM::MOVsi)
2815  MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2816  else if (Opc == ARM::MOVsr) {
2817  MIB.addReg(Reg2);
2818  MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2819  }
2820 
2821  AddOptionalDefs(MIB);
2822  updateValueMap(I, ResultReg);
2823  return true;
2824 }
2825 
2826 // TODO: SoftFP support.
2827 bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2828  switch (I->getOpcode()) {
2829  case Instruction::Load:
2830  return SelectLoad(I);
2831  case Instruction::Store:
2832  return SelectStore(I);
2833  case Instruction::Br:
2834  return SelectBranch(I);
2835  case Instruction::IndirectBr:
2836  return SelectIndirectBr(I);
2837  case Instruction::ICmp:
2838  case Instruction::FCmp:
2839  return SelectCmp(I);
2840  case Instruction::FPExt:
2841  return SelectFPExt(I);
2842  case Instruction::FPTrunc:
2843  return SelectFPTrunc(I);
2844  case Instruction::SIToFP:
2845  return SelectIToFP(I, /*isSigned*/ true);
2846  case Instruction::UIToFP:
2847  return SelectIToFP(I, /*isSigned*/ false);
2848  case Instruction::FPToSI:
2849  return SelectFPToI(I, /*isSigned*/ true);
2850  case Instruction::FPToUI:
2851  return SelectFPToI(I, /*isSigned*/ false);
2852  case Instruction::Add:
2853  return SelectBinaryIntOp(I, ISD::ADD);
2854  case Instruction::Or:
2855  return SelectBinaryIntOp(I, ISD::OR);
2856  case Instruction::Sub:
2857  return SelectBinaryIntOp(I, ISD::SUB);
2858  case Instruction::FAdd:
2859  return SelectBinaryFPOp(I, ISD::FADD);
2860  case Instruction::FSub:
2861  return SelectBinaryFPOp(I, ISD::FSUB);
2862  case Instruction::FMul:
2863  return SelectBinaryFPOp(I, ISD::FMUL);
2864  case Instruction::SDiv:
2865  return SelectDiv(I, /*isSigned*/ true);
2866  case Instruction::UDiv:
2867  return SelectDiv(I, /*isSigned*/ false);
2868  case Instruction::SRem:
2869  return SelectRem(I, /*isSigned*/ true);
2870  case Instruction::URem:
2871  return SelectRem(I, /*isSigned*/ false);
2872  case Instruction::Call:
2873  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2874  return SelectIntrinsicCall(*II);
2875  return SelectCall(I);
2876  case Instruction::Select:
2877  return SelectSelect(I);
2878  case Instruction::Ret:
2879  return SelectRet(I);
2880  case Instruction::Trunc:
2881  return SelectTrunc(I);
2882  case Instruction::ZExt:
2883  case Instruction::SExt:
2884  return SelectIntExt(I);
2885  case Instruction::Shl:
2886  return SelectShift(I, ARM_AM::lsl);
2887  case Instruction::LShr:
2888  return SelectShift(I, ARM_AM::lsr);
2889  case Instruction::AShr:
2890  return SelectShift(I, ARM_AM::asr);
2891  default: break;
2892  }
2893  return false;
2894 }
2895 
2896 // This table describes sign- and zero-extend instructions which can be
2897 // folded into a preceding load. All of these extends have an immediate
2898 // (sometimes a mask and sometimes a shift) that's applied after
2899 // extension.
2900 static const struct FoldableLoadExtendsStruct {
2901  uint16_t Opc[2]; // ARM, Thumb.
2902  uint8_t ExpectedImm;
2903  uint8_t isZExt : 1;
2904  uint8_t ExpectedVT : 7;
2905 } FoldableLoadExtends[] = {
2906  { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2907  { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2908  { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2909  { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2910  { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2911 };
2912 
2913 /// The specified machine instr operand is a vreg, and that
2914 /// vreg is being provided by the specified load instruction. If possible,
2915 /// try to fold the load as an operand to the instruction, returning true if
2916 /// successful.
2917 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2918  const LoadInst *LI) {
2919  // Verify we have a legal type before going any further.
2920  MVT VT;
2921  if (!isLoadTypeLegal(LI->getType(), VT))
2922  return false;
2923 
2924  // Combine load followed by zero- or sign-extend.
2925  // ldrb r1, [r0] ldrb r1, [r0]
2926  // uxtb r2, r1 =>
2927  // mov r3, r2 mov r3, r1
2928  if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2929  return false;
2930  const uint64_t Imm = MI->getOperand(2).getImm();
2931 
2932  bool Found = false;
2933  bool isZExt;
2934  for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) {
2935  if (FLE.Opc[isThumb2] == MI->getOpcode() &&
2936  (uint64_t)FLE.ExpectedImm == Imm &&
2937  MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) {
2938  Found = true;
2939  isZExt = FLE.isZExt;
2940  }
2941  }
2942  if (!Found) return false;
2943 
2944  // See if we can handle this address.
2945  Address Addr;
2946  if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2947 
2948  unsigned ResultReg = MI->getOperand(0).getReg();
2949  if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2950  return false;
2952  removeDeadCode(I, std::next(I));
2953  return true;
2954 }
2955 
2956 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2957  unsigned Align, MVT VT) {
2958  bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
2959 
2960  LLVMContext *Context = &MF->getFunction().getContext();
2961  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2962  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2964  GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
2965  UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
2966  /*AddCurrentAddress=*/UseGOT_PREL);
2967 
2968  unsigned ConstAlign =
2969  MF->getDataLayout().getPrefTypeAlignment(Type::getInt32PtrTy(*Context));
2970  unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(CPV, ConstAlign);
2971  MachineMemOperand *CPMMO =
2972  MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
2974 
2975  unsigned TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
2976  unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
2977  MachineInstrBuilder MIB =
2978  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
2979  .addConstantPoolIndex(Idx)
2980  .addMemOperand(CPMMO);
2981  if (Opc == ARM::LDRcp)
2982  MIB.addImm(0);
2983  MIB.add(predOps(ARMCC::AL));
2984 
2985  // Fix the address by adding pc.
2986  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
2987  Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
2988  : ARM::PICADD;
2989  DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
2990  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2991  .addReg(TempReg)
2992  .addImm(ARMPCLabelIndex);
2993 
2994  if (!Subtarget->isThumb())
2995  MIB.add(predOps(ARMCC::AL));
2996 
2997  if (UseGOT_PREL && Subtarget->isThumb()) {
2998  unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
2999  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3000  TII.get(ARM::t2LDRi12), NewDestReg)
3001  .addReg(DestReg)
3002  .addImm(0);
3003  DestReg = NewDestReg;
3004  AddOptionalDefs(MIB);
3005  }
3006  return DestReg;
3007 }
3008 
3009 bool ARMFastISel::fastLowerArguments() {
3010  if (!FuncInfo.CanLowerReturn)
3011  return false;
3012 
3013  const Function *F = FuncInfo.Fn;
3014  if (F->isVarArg())
3015  return false;
3016 
3017  CallingConv::ID CC = F->getCallingConv();
3018  switch (CC) {
3019  default:
3020  return false;
3021  case CallingConv::Fast:
3022  case CallingConv::C:
3025  case CallingConv::ARM_APCS:
3026  case CallingConv::Swift:
3027  break;
3028  }
3029 
3030  // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3031  // which are passed in r0 - r3.
3032  for (const Argument &Arg : F->args()) {
3033  if (Arg.getArgNo() >= 4)
3034  return false;
3035 
3036  if (Arg.hasAttribute(Attribute::InReg) ||
3037  Arg.hasAttribute(Attribute::StructRet) ||
3038  Arg.hasAttribute(Attribute::SwiftSelf) ||
3039  Arg.hasAttribute(Attribute::SwiftError) ||
3040  Arg.hasAttribute(Attribute::ByVal))
3041  return false;
3042 
3043  Type *ArgTy = Arg.getType();
3044  if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3045  return false;
3046 
3047  EVT ArgVT = TLI.getValueType(DL, ArgTy);
3048  if (!ArgVT.isSimple()) return false;
3049  switch (ArgVT.getSimpleVT().SimpleTy) {
3050  case MVT::i8:
3051  case MVT::i16:
3052  case MVT::i32:
3053  break;
3054  default:
3055  return false;
3056  }
3057  }
3058 
3059  static const MCPhysReg GPRArgRegs[] = {
3060  ARM::R0, ARM::R1, ARM::R2, ARM::R3
3061  };
3062 
3063  const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3064  for (const Argument &Arg : F->args()) {
3065  unsigned ArgNo = Arg.getArgNo();
3066  unsigned SrcReg = GPRArgRegs[ArgNo];
3067  unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3068  // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3069  // Without this, EmitLiveInCopies may eliminate the livein if its only
3070  // use is a bitcast (which isn't turned into an instruction).
3071  unsigned ResultReg = createResultReg(RC);
3072  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3073  TII.get(TargetOpcode::COPY),
3074  ResultReg).addReg(DstReg, getKillRegState(true));
3075  updateValueMap(&Arg, ResultReg);
3076  }
3077 
3078  return true;
3079 }
3080 
3081 namespace llvm {
3082 
3084  const TargetLibraryInfo *libInfo) {
3085  if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3086  return new ARMFastISel(funcInfo, libInfo);
3087 
3088  return nullptr;
3089  }
3090 
3091 } // end namespace llvm
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
IterTy arg_end() const
Definition: CallSite.h:583
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
Return a value (possibly void), from a function.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
const MachineInstrBuilder & add(const MachineOperand &MO) const
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:636
bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
LLVMContext & Context
bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
IterTy arg_begin() const
Definition: CallSite.h:579
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
bool isVector() const
Return true if this is a vector value type.
bool useFastISel() const
True if fast-isel is used.
void push_back(const T &Elt)
Definition: SmallVector.h:211
ARMConstantPoolValue - ARM specific constantpool value.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
static PointerType * getInt32PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:227
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
unsigned getSourceAlignment() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:686
unsigned less or equal
Definition: InstrTypes.h:672
unsigned less than
Definition: InstrTypes.h:671
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:652
unsigned getSourceAddressSpace() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
Externally visible function.
Definition: GlobalValue.h:48
unsigned getValNo() const
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:709
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:662
int getFP64Imm(const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
This class wraps the llvm.memset intrinsic.
BasicBlock * getSuccessor(unsigned i) const
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
F(f)
unsigned getCallFrameDestroyOpcode() const
An instruction for reading from memory.
Definition: Instructions.h:167
#define R2(n)
Value * getCondition() const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
void reserve(size_type N)
Definition: SmallVector.h:369
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:458
Value * getLength() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
op_iterator op_begin()
Definition: User.h:229
FunctionType * getFunctionType() const
Definition: CallSite.h:328
bool isMemLoc() const
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:320
bool needsCustom() const
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:657
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:554
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:656
A description of a memory reference used in the backend.
Predicate getInversePredicate() const
For example, EQ -> NE, UGT -> ULE, SLT -> SGE, OEQ -> UNE, UGT -> OLE, OLT -> UGE, etc.
Definition: InstrTypes.h:745
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
const HexagonInstrInfo * TII
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:96
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
Class to represent struct types.
Definition: DerivedTypes.h:232
static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred)
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isUnsigned() const
Definition: InstrTypes.h:822
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:653
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
unsigned getDestAlignment() const
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getSizeInBits() const
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Class to represent function types.
Definition: DerivedTypes.h:102
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:888
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool isVarArg() const
Definition: DerivedTypes.h:122
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Return true if the call or the callee has the given attribute.
Definition: CallSite.h:385
static const MCPhysReg GPRArgRegs[]
void setOrigAlign(unsigned A)
static const struct FoldableLoadExtendsStruct FoldableLoadExtends[]
This class represents a truncation of integer types.
Value * getOperand(unsigned i) const
Definition: User.h:169
Class to represent pointers.
Definition: DerivedTypes.h:498
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:146
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:102
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
Machine Value Type.
Value * getCalledValue() const
Definition: InstrTypes.h:1194
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Indirect Branch Instruction.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
ARM_AAPCS - ARM Architecture Procedure Calling Standard calling convention (aka EABI).
Definition: CallingConv.h:99
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
op_iterator op_end()
Definition: User.h:231
This file declares a class to represent arbitrary precision floating point values and provide a varie...
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:771
Thread Local Storage (General Dynamic Mode)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
op_range operands()
Definition: User.h:237
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:655
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Extended Value Type.
Definition: ValueTypes.h:33
bool isPositionIndependent() const
size_t size() const
Definition: SmallVector.h:52
static bool isAtomic(Instruction *I)
bool isVolatile() const
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:661
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
signed greater than
Definition: InstrTypes.h:673
bool isNegative() const
Definition: Constants.h:187
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:302
BaseType
A given derived pointer can have multiple base pointers through phi/selects.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:50
bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:650
unsigned getNumOperands() const
Definition: User.h:191
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
CCState - This class holds information needed while lowering arguments and return values...
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:660
Module.h This file contains the declarations for the Module class.
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned arg_size() const
Definition: CallSite.h:226
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:675
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
Value * getRawSource() const
Return the arguments to the instruction.
User::const_op_iterator arg_iterator
The type of iterator to use when looping over actual arguments at this call site. ...
Definition: CallSite.h:220
int64_t getImm() const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
signed less or equal
Definition: InstrTypes.h:676
Target - Wrapper for Target specific information.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
This file defines the FastISel class.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
bool isTailCall() const
Flags
Flags values. These may be or&#39;d together.
The memory access reads data.
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate IT block based on arch"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT, "arm-no-restrict-it", "Allow IT blocks based on ARMv7")))
Representation of each machine instruction.
Definition: MachineInstr.h:63
virtual bool isFPImmLegal(const APFloat &, EVT, bool ForCodeSize=false) const
Returns true if the target can instruction select the specified FP immediate natively.
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:721
This class wraps the llvm.memcpy/memmove intrinsics.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getDestAddressSpace() const
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:576
unsigned getAlignment() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:240
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
unsigned getLocMemOffset() const
unsigned greater or equal
Definition: InstrTypes.h:670
static unsigned UseReg(const MachineOperand &MO)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
TargetOptions Options
Establish a view to a call site for examination.
Definition: CallSite.h:892
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:58
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
ARM_APCS - ARM Procedure Calling Standard calling convention (obsolete, but still used on some target...
Definition: CallingConv.h:95
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:654
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
uint32_t Size
Definition: Profile.cpp:46
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:217
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:658
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:612
bool isRegLoc() const
bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int getFP32Imm(const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
aarch64 promote const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:649
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:72
bool isEquality() const
This is just a convenience that dispatches to the subclasses.
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:659
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
static const Function * getParent(const Value *V)
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:278
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:246
IRTranslator LLVM IR MI
bool hasOneUse() const
Return true if there is exactly one user of this value.
Definition: Value.h:412
unsigned greater than
Definition: InstrTypes.h:669
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:156
unsigned getLocReg() const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:651
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:149
Value * getRawDest() const
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:273
iterator_range< arg_iterator > args()
Definition: Function.h:688
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:217
signed greater or equal
Definition: InstrTypes.h:674
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:220
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:66
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
an instruction to allocate memory on the stack
Definition: Instructions.h:59
gep_type_iterator gep_type_begin(const User *GEP)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...