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ARMFastISel.cpp
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1 //===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the ARM-specific support for the FastISel class. Some
10 // of the target-specific code is generated by tablegen in the file
11 // ARMGenFastISel.inc, which is #included here.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARM.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
25 #include "Utils/ARMBaseInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/CodeGen/FastISel.h"
49 #include "llvm/IR/Argument.h"
50 #include "llvm/IR/Attributes.h"
51 #include "llvm/IR/CallSite.h"
52 #include "llvm/IR/CallingConv.h"
53 #include "llvm/IR/Constant.h"
54 #include "llvm/IR/Constants.h"
55 #include "llvm/IR/DataLayout.h"
56 #include "llvm/IR/DerivedTypes.h"
57 #include "llvm/IR/Function.h"
59 #include "llvm/IR/GlobalValue.h"
60 #include "llvm/IR/GlobalVariable.h"
61 #include "llvm/IR/InstrTypes.h"
62 #include "llvm/IR/Instruction.h"
63 #include "llvm/IR/Instructions.h"
64 #include "llvm/IR/IntrinsicInst.h"
65 #include "llvm/IR/Intrinsics.h"
66 #include "llvm/IR/Module.h"
67 #include "llvm/IR/Operator.h"
68 #include "llvm/IR/Type.h"
69 #include "llvm/IR/User.h"
70 #include "llvm/IR/Value.h"
71 #include "llvm/MC/MCInstrDesc.h"
72 #include "llvm/MC/MCRegisterInfo.h"
73 #include "llvm/Support/Casting.h"
74 #include "llvm/Support/Compiler.h"
80 #include <cassert>
81 #include <cstdint>
82 #include <utility>
83 
84 using namespace llvm;
85 
86 namespace {
87 
88  // All possible address modes, plus some.
89  struct Address {
90  enum {
91  RegBase,
92  FrameIndexBase
93  } BaseType = RegBase;
94 
95  union {
96  unsigned Reg;
97  int FI;
98  } Base;
99 
100  int Offset = 0;
101 
102  // Innocuous defaults for our address.
103  Address() {
104  Base.Reg = 0;
105  }
106  };
107 
108 class ARMFastISel final : public FastISel {
109  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
110  /// make the right decision when generating code for different targets.
111  const ARMSubtarget *Subtarget;
112  Module &M;
113  const TargetMachine &TM;
114  const TargetInstrInfo &TII;
115  const TargetLowering &TLI;
116  ARMFunctionInfo *AFI;
117 
118  // Convenience variables to avoid some queries.
119  bool isThumb2;
121 
122  public:
123  explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
124  const TargetLibraryInfo *libInfo)
125  : FastISel(funcInfo, libInfo),
126  Subtarget(
127  &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
128  M(const_cast<Module &>(*funcInfo.Fn->getParent())),
129  TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
130  TLI(*Subtarget->getTargetLowering()) {
131  AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
132  isThumb2 = AFI->isThumbFunction();
133  Context = &funcInfo.Fn->getContext();
134  }
135 
136  private:
137  // Code from FastISel.cpp.
138 
139  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
140  const TargetRegisterClass *RC,
141  unsigned Op0, bool Op0IsKill);
142  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
143  const TargetRegisterClass *RC,
144  unsigned Op0, bool Op0IsKill,
145  unsigned Op1, bool Op1IsKill);
146  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
147  const TargetRegisterClass *RC,
148  unsigned Op0, bool Op0IsKill,
149  uint64_t Imm);
150  unsigned fastEmitInst_i(unsigned MachineInstOpcode,
151  const TargetRegisterClass *RC,
152  uint64_t Imm);
153 
154  // Backend specific FastISel code.
155 
156  bool fastSelectInstruction(const Instruction *I) override;
157  unsigned fastMaterializeConstant(const Constant *C) override;
158  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
159  bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
160  const LoadInst *LI) override;
161  bool fastLowerArguments() override;
162 
163  #include "ARMGenFastISel.inc"
164 
165  // Instruction selection routines.
166 
167  bool SelectLoad(const Instruction *I);
168  bool SelectStore(const Instruction *I);
169  bool SelectBranch(const Instruction *I);
170  bool SelectIndirectBr(const Instruction *I);
171  bool SelectCmp(const Instruction *I);
172  bool SelectFPExt(const Instruction *I);
173  bool SelectFPTrunc(const Instruction *I);
174  bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
175  bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
176  bool SelectIToFP(const Instruction *I, bool isSigned);
177  bool SelectFPToI(const Instruction *I, bool isSigned);
178  bool SelectDiv(const Instruction *I, bool isSigned);
179  bool SelectRem(const Instruction *I, bool isSigned);
180  bool SelectCall(const Instruction *I, const char *IntrMemName);
181  bool SelectIntrinsicCall(const IntrinsicInst &I);
182  bool SelectSelect(const Instruction *I);
183  bool SelectRet(const Instruction *I);
184  bool SelectTrunc(const Instruction *I);
185  bool SelectIntExt(const Instruction *I);
186  bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
187 
188  // Utility routines.
189 
190  bool isPositionIndependent() const;
191  bool isTypeLegal(Type *Ty, MVT &VT);
192  bool isLoadTypeLegal(Type *Ty, MVT &VT);
193  bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
194  bool isZExt, bool isEquality);
195  bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
196  unsigned Alignment = 0, bool isZExt = true,
197  bool allocReg = true);
198  bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
199  unsigned Alignment = 0);
200  bool ARMComputeAddress(const Value *Obj, Address &Addr);
201  void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
202  bool ARMIsMemCpySmall(uint64_t Len);
203  bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
204  unsigned Alignment);
205  unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
206  unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
207  unsigned ARMMaterializeInt(const Constant *C, MVT VT);
208  unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
209  unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
210  unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
211  unsigned ARMSelectCallOp(bool UseReg);
212  unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
213 
214  const TargetLowering *getTargetLowering() { return &TLI; }
215 
216  // Call handling routines.
217 
218  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
219  bool Return,
220  bool isVarArg);
221  bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
222  SmallVectorImpl<unsigned> &ArgRegs,
223  SmallVectorImpl<MVT> &ArgVTs,
225  SmallVectorImpl<unsigned> &RegArgs,
226  CallingConv::ID CC,
227  unsigned &NumBytes,
228  bool isVarArg);
229  unsigned getLibcallReg(const Twine &Name);
230  bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
231  const Instruction *I, CallingConv::ID CC,
232  unsigned &NumBytes, bool isVarArg);
233  bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
234 
235  // OptionalDef handling routines.
236 
237  bool isARMNEONPred(const MachineInstr *MI);
238  bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
239  const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
240  void AddLoadStoreOperands(MVT VT, Address &Addr,
241  const MachineInstrBuilder &MIB,
242  MachineMemOperand::Flags Flags, bool useAM3);
243 };
244 
245 } // end anonymous namespace
246 
247 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
248 // we don't care about implicit defs here, just places we'll need to add a
249 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
250 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
251  if (!MI->hasOptionalDef())
252  return false;
253 
254  // Look to see if our OptionalDef is defining CPSR or CCR.
255  for (const MachineOperand &MO : MI->operands()) {
256  if (!MO.isReg() || !MO.isDef()) continue;
257  if (MO.getReg() == ARM::CPSR)
258  *CPSR = true;
259  }
260  return true;
261 }
262 
263 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
264  const MCInstrDesc &MCID = MI->getDesc();
265 
266  // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
267  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
268  AFI->isThumb2Function())
269  return MI->isPredicable();
270 
271  for (const MCOperandInfo &opInfo : MCID.operands())
272  if (opInfo.isPredicate())
273  return true;
274 
275  return false;
276 }
277 
278 // If the machine is predicable go ahead and add the predicate operands, if
279 // it needs default CC operands add those.
280 // TODO: If we want to support thumb1 then we'll need to deal with optional
281 // CPSR defs that need to be added before the remaining operands. See s_cc_out
282 // for descriptions why.
283 const MachineInstrBuilder &
284 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
285  MachineInstr *MI = &*MIB;
286 
287  // Do we use a predicate? or...
288  // Are we NEON in ARM mode and have a predicate operand? If so, I know
289  // we're not predicable but add it anyways.
290  if (isARMNEONPred(MI))
291  MIB.add(predOps(ARMCC::AL));
292 
293  // Do we optionally set a predicate? Preds is size > 0 iff the predicate
294  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
295  bool CPSR = false;
296  if (DefinesOptionalPredicate(MI, &CPSR))
297  MIB.add(CPSR ? t1CondCodeOp() : condCodeOp());
298  return MIB;
299 }
300 
301 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
302  const TargetRegisterClass *RC,
303  unsigned Op0, bool Op0IsKill) {
304  unsigned ResultReg = createResultReg(RC);
305  const MCInstrDesc &II = TII.get(MachineInstOpcode);
306 
307  // Make sure the input operand is sufficiently constrained to be legal
308  // for this instruction.
309  Op0 = constrainOperandRegClass(II, Op0, 1);
310  if (II.getNumDefs() >= 1) {
311  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
312  ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
313  } else {
314  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
315  .addReg(Op0, Op0IsKill * RegState::Kill));
316  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
317  TII.get(TargetOpcode::COPY), ResultReg)
318  .addReg(II.ImplicitDefs[0]));
319  }
320  return ResultReg;
321 }
322 
323 unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
324  const TargetRegisterClass *RC,
325  unsigned Op0, bool Op0IsKill,
326  unsigned Op1, bool Op1IsKill) {
327  unsigned ResultReg = createResultReg(RC);
328  const MCInstrDesc &II = TII.get(MachineInstOpcode);
329 
330  // Make sure the input operands are sufficiently constrained to be legal
331  // for this instruction.
332  Op0 = constrainOperandRegClass(II, Op0, 1);
333  Op1 = constrainOperandRegClass(II, Op1, 2);
334 
335  if (II.getNumDefs() >= 1) {
336  AddOptionalDefs(
337  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
338  .addReg(Op0, Op0IsKill * RegState::Kill)
339  .addReg(Op1, Op1IsKill * RegState::Kill));
340  } else {
341  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
342  .addReg(Op0, Op0IsKill * RegState::Kill)
343  .addReg(Op1, Op1IsKill * RegState::Kill));
344  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
345  TII.get(TargetOpcode::COPY), ResultReg)
346  .addReg(II.ImplicitDefs[0]));
347  }
348  return ResultReg;
349 }
350 
351 unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
352  const TargetRegisterClass *RC,
353  unsigned Op0, bool Op0IsKill,
354  uint64_t Imm) {
355  unsigned ResultReg = createResultReg(RC);
356  const MCInstrDesc &II = TII.get(MachineInstOpcode);
357 
358  // Make sure the input operand is sufficiently constrained to be legal
359  // for this instruction.
360  Op0 = constrainOperandRegClass(II, Op0, 1);
361  if (II.getNumDefs() >= 1) {
362  AddOptionalDefs(
363  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
364  .addReg(Op0, Op0IsKill * RegState::Kill)
365  .addImm(Imm));
366  } else {
367  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
368  .addReg(Op0, Op0IsKill * RegState::Kill)
369  .addImm(Imm));
370  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
371  TII.get(TargetOpcode::COPY), ResultReg)
372  .addReg(II.ImplicitDefs[0]));
373  }
374  return ResultReg;
375 }
376 
377 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
378  const TargetRegisterClass *RC,
379  uint64_t Imm) {
380  unsigned ResultReg = createResultReg(RC);
381  const MCInstrDesc &II = TII.get(MachineInstOpcode);
382 
383  if (II.getNumDefs() >= 1) {
384  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
385  ResultReg).addImm(Imm));
386  } else {
387  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
388  .addImm(Imm));
389  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
390  TII.get(TargetOpcode::COPY), ResultReg)
391  .addReg(II.ImplicitDefs[0]));
392  }
393  return ResultReg;
394 }
395 
396 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
397 // checks from the various callers.
398 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
399  if (VT == MVT::f64) return 0;
400 
401  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
402  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
403  TII.get(ARM::VMOVSR), MoveReg)
404  .addReg(SrcReg));
405  return MoveReg;
406 }
407 
408 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
409  if (VT == MVT::i64) return 0;
410 
411  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
412  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
413  TII.get(ARM::VMOVRS), MoveReg)
414  .addReg(SrcReg));
415  return MoveReg;
416 }
417 
418 // For double width floating point we need to materialize two constants
419 // (the high and the low) into integer registers then use a move to get
420 // the combined constant into an FP reg.
421 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
422  const APFloat Val = CFP->getValueAPF();
423  bool is64bit = VT == MVT::f64;
424 
425  // This checks to see if we can use VFP3 instructions to materialize
426  // a constant, otherwise we have to go through the constant pool.
427  if (TLI.isFPImmLegal(Val, VT)) {
428  int Imm;
429  unsigned Opc;
430  if (is64bit) {
431  Imm = ARM_AM::getFP64Imm(Val);
432  Opc = ARM::FCONSTD;
433  } else {
434  Imm = ARM_AM::getFP32Imm(Val);
435  Opc = ARM::FCONSTS;
436  }
437  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
438  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
439  TII.get(Opc), DestReg).addImm(Imm));
440  return DestReg;
441  }
442 
443  // Require VFP2 for loading fp constants.
444  if (!Subtarget->hasVFP2Base()) return false;
445 
446  // MachineConstantPool wants an explicit alignment.
447  unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
448  if (Align == 0) {
449  // TODO: Figure out if this is correct.
450  Align = DL.getTypeAllocSize(CFP->getType());
451  }
452  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
453  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
454  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
455 
456  // The extra reg is for addrmode5.
457  AddOptionalDefs(
458  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
459  .addConstantPoolIndex(Idx)
460  .addReg(0));
461  return DestReg;
462 }
463 
464 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
465  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
466  return 0;
467 
468  // If we can do this in a single instruction without a constant pool entry
469  // do so now.
470  const ConstantInt *CI = cast<ConstantInt>(C);
471  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
472  unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
473  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
474  &ARM::GPRRegClass;
475  unsigned ImmReg = createResultReg(RC);
476  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
477  TII.get(Opc), ImmReg)
478  .addImm(CI->getZExtValue()));
479  return ImmReg;
480  }
481 
482  // Use MVN to emit negative constants.
483  if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
484  unsigned Imm = (unsigned)~(CI->getSExtValue());
485  bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
486  (ARM_AM::getSOImmVal(Imm) != -1);
487  if (UseImm) {
488  unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
489  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
490  &ARM::GPRRegClass;
491  unsigned ImmReg = createResultReg(RC);
492  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
493  TII.get(Opc), ImmReg)
494  .addImm(Imm));
495  return ImmReg;
496  }
497  }
498 
499  unsigned ResultReg = 0;
500  if (Subtarget->useMovt())
501  ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
502 
503  if (ResultReg)
504  return ResultReg;
505 
506  // Load from constant pool. For now 32-bit only.
507  if (VT != MVT::i32)
508  return 0;
509 
510  // MachineConstantPool wants an explicit alignment.
511  unsigned Align = DL.getPrefTypeAlignment(C->getType());
512  if (Align == 0) {
513  // TODO: Figure out if this is correct.
514  Align = DL.getTypeAllocSize(C->getType());
515  }
516  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
517  ResultReg = createResultReg(TLI.getRegClassFor(VT));
518  if (isThumb2)
519  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
520  TII.get(ARM::t2LDRpci), ResultReg)
521  .addConstantPoolIndex(Idx));
522  else {
523  // The extra immediate is for addrmode2.
524  ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
525  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
526  TII.get(ARM::LDRcp), ResultReg)
527  .addConstantPoolIndex(Idx)
528  .addImm(0));
529  }
530  return ResultReg;
531 }
532 
533 bool ARMFastISel::isPositionIndependent() const {
534  return TLI.isPositionIndependent();
535 }
536 
537 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
538  // For now 32-bit only.
539  if (VT != MVT::i32 || GV->isThreadLocal()) return 0;
540 
541  // ROPI/RWPI not currently supported.
542  if (Subtarget->isROPI() || Subtarget->isRWPI())
543  return 0;
544 
545  bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
546  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
547  : &ARM::GPRRegClass;
548  unsigned DestReg = createResultReg(RC);
549 
550  // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
551  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
552  bool IsThreadLocal = GVar && GVar->isThreadLocal();
553  if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
554 
555  bool IsPositionIndependent = isPositionIndependent();
556  // Use movw+movt when possible, it avoids constant pool entries.
557  // Non-darwin targets only support static movt relocations in FastISel.
558  if (Subtarget->useMovt() &&
559  (Subtarget->isTargetMachO() || !IsPositionIndependent)) {
560  unsigned Opc;
561  unsigned char TF = 0;
562  if (Subtarget->isTargetMachO())
563  TF = ARMII::MO_NONLAZY;
564 
565  if (IsPositionIndependent)
566  Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
567  else
568  Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
569  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
570  TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
571  } else {
572  // MachineConstantPool wants an explicit alignment.
573  unsigned Align = DL.getPrefTypeAlignment(GV->getType());
574  if (Align == 0) {
575  // TODO: Figure out if this is correct.
576  Align = DL.getTypeAllocSize(GV->getType());
577  }
578 
579  if (Subtarget->isTargetELF() && IsPositionIndependent)
580  return ARMLowerPICELF(GV, Align, VT);
581 
582  // Grab index.
583  unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
584  unsigned Id = AFI->createPICLabelUId();
587  PCAdj);
588  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
589 
590  // Load value.
592  if (isThumb2) {
593  unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci;
594  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
595  DestReg).addConstantPoolIndex(Idx);
596  if (IsPositionIndependent)
597  MIB.addImm(Id);
598  AddOptionalDefs(MIB);
599  } else {
600  // The extra immediate is for addrmode2.
601  DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
602  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
603  TII.get(ARM::LDRcp), DestReg)
604  .addConstantPoolIndex(Idx)
605  .addImm(0);
606  AddOptionalDefs(MIB);
607 
608  if (IsPositionIndependent) {
609  unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
610  unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
611 
612  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
613  DbgLoc, TII.get(Opc), NewDestReg)
614  .addReg(DestReg)
615  .addImm(Id);
616  AddOptionalDefs(MIB);
617  return NewDestReg;
618  }
619  }
620  }
621 
622  if (IsIndirect) {
624  unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
625  if (isThumb2)
626  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
627  TII.get(ARM::t2LDRi12), NewDestReg)
628  .addReg(DestReg)
629  .addImm(0);
630  else
631  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
632  TII.get(ARM::LDRi12), NewDestReg)
633  .addReg(DestReg)
634  .addImm(0);
635  DestReg = NewDestReg;
636  AddOptionalDefs(MIB);
637  }
638 
639  return DestReg;
640 }
641 
642 unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
643  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
644 
645  // Only handle simple types.
646  if (!CEVT.isSimple()) return 0;
647  MVT VT = CEVT.getSimpleVT();
648 
649  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
650  return ARMMaterializeFP(CFP, VT);
651  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
652  return ARMMaterializeGV(GV, VT);
653  else if (isa<ConstantInt>(C))
654  return ARMMaterializeInt(C, VT);
655 
656  return 0;
657 }
658 
659 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
660 
661 unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
662  // Don't handle dynamic allocas.
663  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
664 
665  MVT VT;
666  if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
667 
669  FuncInfo.StaticAllocaMap.find(AI);
670 
671  // This will get lowered later into the correct offsets and registers
672  // via rewriteXFrameIndex.
673  if (SI != FuncInfo.StaticAllocaMap.end()) {
674  unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
675  const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
676  unsigned ResultReg = createResultReg(RC);
677  ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
678 
679  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
680  TII.get(Opc), ResultReg)
681  .addFrameIndex(SI->second)
682  .addImm(0));
683  return ResultReg;
684  }
685 
686  return 0;
687 }
688 
689 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
690  EVT evt = TLI.getValueType(DL, Ty, true);
691 
692  // Only handle simple types.
693  if (evt == MVT::Other || !evt.isSimple()) return false;
694  VT = evt.getSimpleVT();
695 
696  // Handle all legal types, i.e. a register that will directly hold this
697  // value.
698  return TLI.isTypeLegal(VT);
699 }
700 
701 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
702  if (isTypeLegal(Ty, VT)) return true;
703 
704  // If this is a type than can be sign or zero-extended to a basic operation
705  // go ahead and accept it now.
706  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
707  return true;
708 
709  return false;
710 }
711 
712 // Computes the address to get to an object.
713 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
714  // Some boilerplate from the X86 FastISel.
715  const User *U = nullptr;
716  unsigned Opcode = Instruction::UserOp1;
717  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
718  // Don't walk into other basic blocks unless the object is an alloca from
719  // another block, otherwise it may not have a virtual register assigned.
720  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
721  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
722  Opcode = I->getOpcode();
723  U = I;
724  }
725  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
726  Opcode = C->getOpcode();
727  U = C;
728  }
729 
730  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
731  if (Ty->getAddressSpace() > 255)
732  // Fast instruction selection doesn't support the special
733  // address spaces.
734  return false;
735 
736  switch (Opcode) {
737  default:
738  break;
739  case Instruction::BitCast:
740  // Look through bitcasts.
741  return ARMComputeAddress(U->getOperand(0), Addr);
742  case Instruction::IntToPtr:
743  // Look past no-op inttoptrs.
744  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
745  TLI.getPointerTy(DL))
746  return ARMComputeAddress(U->getOperand(0), Addr);
747  break;
748  case Instruction::PtrToInt:
749  // Look past no-op ptrtoints.
750  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
751  return ARMComputeAddress(U->getOperand(0), Addr);
752  break;
753  case Instruction::GetElementPtr: {
754  Address SavedAddr = Addr;
755  int TmpOffset = Addr.Offset;
756 
757  // Iterate through the GEP folding the constants into offsets where
758  // we can.
760  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
761  i != e; ++i, ++GTI) {
762  const Value *Op = *i;
763  if (StructType *STy = GTI.getStructTypeOrNull()) {
764  const StructLayout *SL = DL.getStructLayout(STy);
765  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
766  TmpOffset += SL->getElementOffset(Idx);
767  } else {
768  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
769  while (true) {
770  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
771  // Constant-offset addressing.
772  TmpOffset += CI->getSExtValue() * S;
773  break;
774  }
775  if (canFoldAddIntoGEP(U, Op)) {
776  // A compatible add with a constant operand. Fold the constant.
777  ConstantInt *CI =
778  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
779  TmpOffset += CI->getSExtValue() * S;
780  // Iterate on the other operand.
781  Op = cast<AddOperator>(Op)->getOperand(0);
782  continue;
783  }
784  // Unsupported
785  goto unsupported_gep;
786  }
787  }
788  }
789 
790  // Try to grab the base operand now.
791  Addr.Offset = TmpOffset;
792  if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
793 
794  // We failed, restore everything and try the other options.
795  Addr = SavedAddr;
796 
797  unsupported_gep:
798  break;
799  }
800  case Instruction::Alloca: {
801  const AllocaInst *AI = cast<AllocaInst>(Obj);
803  FuncInfo.StaticAllocaMap.find(AI);
804  if (SI != FuncInfo.StaticAllocaMap.end()) {
805  Addr.BaseType = Address::FrameIndexBase;
806  Addr.Base.FI = SI->second;
807  return true;
808  }
809  break;
810  }
811  }
812 
813  // Try to get this in a register if nothing else has worked.
814  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
815  return Addr.Base.Reg != 0;
816 }
817 
818 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
819  bool needsLowering = false;
820  switch (VT.SimpleTy) {
821  default: llvm_unreachable("Unhandled load/store type!");
822  case MVT::i1:
823  case MVT::i8:
824  case MVT::i16:
825  case MVT::i32:
826  if (!useAM3) {
827  // Integer loads/stores handle 12-bit offsets.
828  needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
829  // Handle negative offsets.
830  if (needsLowering && isThumb2)
831  needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
832  Addr.Offset > -256);
833  } else {
834  // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
835  needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
836  }
837  break;
838  case MVT::f32:
839  case MVT::f64:
840  // Floating point operands handle 8-bit offsets.
841  needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
842  break;
843  }
844 
845  // If this is a stack pointer and the offset needs to be simplified then
846  // put the alloca address into a register, set the base type back to
847  // register and continue. This should almost never happen.
848  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
849  const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
850  : &ARM::GPRRegClass;
851  unsigned ResultReg = createResultReg(RC);
852  unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
853  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
854  TII.get(Opc), ResultReg)
855  .addFrameIndex(Addr.Base.FI)
856  .addImm(0));
857  Addr.Base.Reg = ResultReg;
858  Addr.BaseType = Address::RegBase;
859  }
860 
861  // Since the offset is too large for the load/store instruction
862  // get the reg+offset into a register.
863  if (needsLowering) {
864  Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
865  /*Op0IsKill*/false, Addr.Offset, MVT::i32);
866  Addr.Offset = 0;
867  }
868 }
869 
870 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
871  const MachineInstrBuilder &MIB,
873  bool useAM3) {
874  // addrmode5 output depends on the selection dag addressing dividing the
875  // offset by 4 that it then later multiplies. Do this here as well.
876  if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
877  Addr.Offset /= 4;
878 
879  // Frame base works a bit differently. Handle it separately.
880  if (Addr.BaseType == Address::FrameIndexBase) {
881  int FI = Addr.Base.FI;
882  int Offset = Addr.Offset;
883  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
884  MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
885  MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
886  // Now add the rest of the operands.
887  MIB.addFrameIndex(FI);
888 
889  // ARM halfword load/stores and signed byte loads need an additional
890  // operand.
891  if (useAM3) {
892  int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
893  MIB.addReg(0);
894  MIB.addImm(Imm);
895  } else {
896  MIB.addImm(Addr.Offset);
897  }
898  MIB.addMemOperand(MMO);
899  } else {
900  // Now add the rest of the operands.
901  MIB.addReg(Addr.Base.Reg);
902 
903  // ARM halfword load/stores and signed byte loads need an additional
904  // operand.
905  if (useAM3) {
906  int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
907  MIB.addReg(0);
908  MIB.addImm(Imm);
909  } else {
910  MIB.addImm(Addr.Offset);
911  }
912  }
913  AddOptionalDefs(MIB);
914 }
915 
916 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
917  unsigned Alignment, bool isZExt, bool allocReg) {
918  unsigned Opc;
919  bool useAM3 = false;
920  bool needVMOV = false;
921  const TargetRegisterClass *RC;
922  switch (VT.SimpleTy) {
923  // This is mostly going to be Neon/vector support.
924  default: return false;
925  case MVT::i1:
926  case MVT::i8:
927  if (isThumb2) {
928  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
929  Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
930  else
931  Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
932  } else {
933  if (isZExt) {
934  Opc = ARM::LDRBi12;
935  } else {
936  Opc = ARM::LDRSB;
937  useAM3 = true;
938  }
939  }
940  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
941  break;
942  case MVT::i16:
943  if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
944  return false;
945 
946  if (isThumb2) {
947  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
948  Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
949  else
950  Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
951  } else {
952  Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
953  useAM3 = true;
954  }
955  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
956  break;
957  case MVT::i32:
958  if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
959  return false;
960 
961  if (isThumb2) {
962  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
963  Opc = ARM::t2LDRi8;
964  else
965  Opc = ARM::t2LDRi12;
966  } else {
967  Opc = ARM::LDRi12;
968  }
969  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
970  break;
971  case MVT::f32:
972  if (!Subtarget->hasVFP2Base()) return false;
973  // Unaligned loads need special handling. Floats require word-alignment.
974  if (Alignment && Alignment < 4) {
975  needVMOV = true;
976  VT = MVT::i32;
977  Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
978  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
979  } else {
980  Opc = ARM::VLDRS;
981  RC = TLI.getRegClassFor(VT);
982  }
983  break;
984  case MVT::f64:
985  // Can load and store double precision even without FeatureFP64
986  if (!Subtarget->hasVFP2Base()) return false;
987  // FIXME: Unaligned loads need special handling. Doublewords require
988  // word-alignment.
989  if (Alignment && Alignment < 4)
990  return false;
991 
992  Opc = ARM::VLDRD;
993  RC = TLI.getRegClassFor(VT);
994  break;
995  }
996  // Simplify this down to something we can handle.
997  ARMSimplifyAddress(Addr, VT, useAM3);
998 
999  // Create the base instruction, then add the operands.
1000  if (allocReg)
1001  ResultReg = createResultReg(RC);
1002  assert(ResultReg > 255 && "Expected an allocated virtual register.");
1003  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1004  TII.get(Opc), ResultReg);
1005  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1006 
1007  // If we had an unaligned load of a float we've converted it to an regular
1008  // load. Now we must move from the GRP to the FP register.
1009  if (needVMOV) {
1010  unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1011  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1012  TII.get(ARM::VMOVSR), MoveReg)
1013  .addReg(ResultReg));
1014  ResultReg = MoveReg;
1015  }
1016  return true;
1017 }
1018 
1019 bool ARMFastISel::SelectLoad(const Instruction *I) {
1020  // Atomic loads need special handling.
1021  if (cast<LoadInst>(I)->isAtomic())
1022  return false;
1023 
1024  const Value *SV = I->getOperand(0);
1025  if (TLI.supportSwiftError()) {
1026  // Swifterror values can come from either a function parameter with
1027  // swifterror attribute or an alloca with swifterror attribute.
1028  if (const Argument *Arg = dyn_cast<Argument>(SV)) {
1029  if (Arg->hasSwiftErrorAttr())
1030  return false;
1031  }
1032 
1033  if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
1034  if (Alloca->isSwiftError())
1035  return false;
1036  }
1037  }
1038 
1039  // Verify we have a legal type before going any further.
1040  MVT VT;
1041  if (!isLoadTypeLegal(I->getType(), VT))
1042  return false;
1043 
1044  // See if we can handle this address.
1045  Address Addr;
1046  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1047 
1048  unsigned ResultReg;
1049  if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1050  return false;
1051  updateValueMap(I, ResultReg);
1052  return true;
1053 }
1054 
1055 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1056  unsigned Alignment) {
1057  unsigned StrOpc;
1058  bool useAM3 = false;
1059  switch (VT.SimpleTy) {
1060  // This is mostly going to be Neon/vector support.
1061  default: return false;
1062  case MVT::i1: {
1063  unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1064  : &ARM::GPRRegClass);
1065  unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1066  SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1067  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1068  TII.get(Opc), Res)
1069  .addReg(SrcReg).addImm(1));
1070  SrcReg = Res;
1072  }
1073  case MVT::i8:
1074  if (isThumb2) {
1075  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1076  StrOpc = ARM::t2STRBi8;
1077  else
1078  StrOpc = ARM::t2STRBi12;
1079  } else {
1080  StrOpc = ARM::STRBi12;
1081  }
1082  break;
1083  case MVT::i16:
1084  if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1085  return false;
1086 
1087  if (isThumb2) {
1088  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1089  StrOpc = ARM::t2STRHi8;
1090  else
1091  StrOpc = ARM::t2STRHi12;
1092  } else {
1093  StrOpc = ARM::STRH;
1094  useAM3 = true;
1095  }
1096  break;
1097  case MVT::i32:
1098  if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1099  return false;
1100 
1101  if (isThumb2) {
1102  if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1103  StrOpc = ARM::t2STRi8;
1104  else
1105  StrOpc = ARM::t2STRi12;
1106  } else {
1107  StrOpc = ARM::STRi12;
1108  }
1109  break;
1110  case MVT::f32:
1111  if (!Subtarget->hasVFP2Base()) return false;
1112  // Unaligned stores need special handling. Floats require word-alignment.
1113  if (Alignment && Alignment < 4) {
1114  unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1115  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1116  TII.get(ARM::VMOVRS), MoveReg)
1117  .addReg(SrcReg));
1118  SrcReg = MoveReg;
1119  VT = MVT::i32;
1120  StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1121  } else {
1122  StrOpc = ARM::VSTRS;
1123  }
1124  break;
1125  case MVT::f64:
1126  // Can load and store double precision even without FeatureFP64
1127  if (!Subtarget->hasVFP2Base()) return false;
1128  // FIXME: Unaligned stores need special handling. Doublewords require
1129  // word-alignment.
1130  if (Alignment && Alignment < 4)
1131  return false;
1132 
1133  StrOpc = ARM::VSTRD;
1134  break;
1135  }
1136  // Simplify this down to something we can handle.
1137  ARMSimplifyAddress(Addr, VT, useAM3);
1138 
1139  // Create the base instruction, then add the operands.
1140  SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1141  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1142  TII.get(StrOpc))
1143  .addReg(SrcReg);
1144  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1145  return true;
1146 }
1147 
1148 bool ARMFastISel::SelectStore(const Instruction *I) {
1149  Value *Op0 = I->getOperand(0);
1150  unsigned SrcReg = 0;
1151 
1152  // Atomic stores need special handling.
1153  if (cast<StoreInst>(I)->isAtomic())
1154  return false;
1155 
1156  const Value *PtrV = I->getOperand(1);
1157  if (TLI.supportSwiftError()) {
1158  // Swifterror values can come from either a function parameter with
1159  // swifterror attribute or an alloca with swifterror attribute.
1160  if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
1161  if (Arg->hasSwiftErrorAttr())
1162  return false;
1163  }
1164 
1165  if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
1166  if (Alloca->isSwiftError())
1167  return false;
1168  }
1169  }
1170 
1171  // Verify we have a legal type before going any further.
1172  MVT VT;
1173  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1174  return false;
1175 
1176  // Get the value to be stored into a register.
1177  SrcReg = getRegForValue(Op0);
1178  if (SrcReg == 0) return false;
1179 
1180  // See if we can handle this address.
1181  Address Addr;
1182  if (!ARMComputeAddress(I->getOperand(1), Addr))
1183  return false;
1184 
1185  if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1186  return false;
1187  return true;
1188 }
1189 
1191  switch (Pred) {
1192  // Needs two compares...
1193  case CmpInst::FCMP_ONE:
1194  case CmpInst::FCMP_UEQ:
1195  default:
1196  // AL is our "false" for now. The other two need more compares.
1197  return ARMCC::AL;
1198  case CmpInst::ICMP_EQ:
1199  case CmpInst::FCMP_OEQ:
1200  return ARMCC::EQ;
1201  case CmpInst::ICMP_SGT:
1202  case CmpInst::FCMP_OGT:
1203  return ARMCC::GT;
1204  case CmpInst::ICMP_SGE:
1205  case CmpInst::FCMP_OGE:
1206  return ARMCC::GE;
1207  case CmpInst::ICMP_UGT:
1208  case CmpInst::FCMP_UGT:
1209  return ARMCC::HI;
1210  case CmpInst::FCMP_OLT:
1211  return ARMCC::MI;
1212  case CmpInst::ICMP_ULE:
1213  case CmpInst::FCMP_OLE:
1214  return ARMCC::LS;
1215  case CmpInst::FCMP_ORD:
1216  return ARMCC::VC;
1217  case CmpInst::FCMP_UNO:
1218  return ARMCC::VS;
1219  case CmpInst::FCMP_UGE:
1220  return ARMCC::PL;
1221  case CmpInst::ICMP_SLT:
1222  case CmpInst::FCMP_ULT:
1223  return ARMCC::LT;
1224  case CmpInst::ICMP_SLE:
1225  case CmpInst::FCMP_ULE:
1226  return ARMCC::LE;
1227  case CmpInst::FCMP_UNE:
1228  case CmpInst::ICMP_NE:
1229  return ARMCC::NE;
1230  case CmpInst::ICMP_UGE:
1231  return ARMCC::HS;
1232  case CmpInst::ICMP_ULT:
1233  return ARMCC::LO;
1234  }
1235 }
1236 
1237 bool ARMFastISel::SelectBranch(const Instruction *I) {
1238  const BranchInst *BI = cast<BranchInst>(I);
1239  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1240  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1241 
1242  // Simple branch support.
1243 
1244  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1245  // behavior.
1246  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1247  if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1248  // Get the compare predicate.
1249  // Try to take advantage of fallthrough opportunities.
1250  CmpInst::Predicate Predicate = CI->getPredicate();
1251  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1252  std::swap(TBB, FBB);
1253  Predicate = CmpInst::getInversePredicate(Predicate);
1254  }
1255 
1256  ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1257 
1258  // We may not handle every CC for now.
1259  if (ARMPred == ARMCC::AL) return false;
1260 
1261  // Emit the compare.
1262  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
1263  CI->isEquality()))
1264  return false;
1265 
1266  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1267  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1268  .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1269  finishCondBranch(BI->getParent(), TBB, FBB);
1270  return true;
1271  }
1272  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1273  MVT SourceVT;
1274  if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1275  (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1276  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1277  unsigned OpReg = getRegForValue(TI->getOperand(0));
1278  OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1279  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1280  TII.get(TstOpc))
1281  .addReg(OpReg).addImm(1));
1282 
1283  unsigned CCMode = ARMCC::NE;
1284  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1285  std::swap(TBB, FBB);
1286  CCMode = ARMCC::EQ;
1287  }
1288 
1289  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1290  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1291  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1292 
1293  finishCondBranch(BI->getParent(), TBB, FBB);
1294  return true;
1295  }
1296  } else if (const ConstantInt *CI =
1297  dyn_cast<ConstantInt>(BI->getCondition())) {
1298  uint64_t Imm = CI->getZExtValue();
1299  MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1300  fastEmitBranch(Target, DbgLoc);
1301  return true;
1302  }
1303 
1304  unsigned CmpReg = getRegForValue(BI->getCondition());
1305  if (CmpReg == 0) return false;
1306 
1307  // We've been divorced from our compare! Our block was split, and
1308  // now our compare lives in a predecessor block. We musn't
1309  // re-compare here, as the children of the compare aren't guaranteed
1310  // live across the block boundary (we *could* check for this).
1311  // Regardless, the compare has been done in the predecessor block,
1312  // and it left a value for us in a virtual register. Ergo, we test
1313  // the one-bit value left in the virtual register.
1314  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1315  CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1316  AddOptionalDefs(
1317  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1318  .addReg(CmpReg)
1319  .addImm(1));
1320 
1321  unsigned CCMode = ARMCC::NE;
1322  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1323  std::swap(TBB, FBB);
1324  CCMode = ARMCC::EQ;
1325  }
1326 
1327  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1328  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1329  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1330  finishCondBranch(BI->getParent(), TBB, FBB);
1331  return true;
1332 }
1333 
1334 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1335  unsigned AddrReg = getRegForValue(I->getOperand(0));
1336  if (AddrReg == 0) return false;
1337 
1338  unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1339  assert(isThumb2 || Subtarget->hasV4TOps());
1340 
1341  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1342  TII.get(Opc)).addReg(AddrReg));
1343 
1344  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1345  for (const BasicBlock *SuccBB : IB->successors())
1346  FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1347 
1348  return true;
1349 }
1350 
1351 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1352  bool isZExt, bool isEquality) {
1353  Type *Ty = Src1Value->getType();
1354  EVT SrcEVT = TLI.getValueType(DL, Ty, true);
1355  if (!SrcEVT.isSimple()) return false;
1356  MVT SrcVT = SrcEVT.getSimpleVT();
1357 
1358  if (Ty->isFloatTy() && !Subtarget->hasVFP2Base())
1359  return false;
1360 
1361  if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()))
1362  return false;
1363 
1364  // Check to see if the 2nd operand is a constant that we can encode directly
1365  // in the compare.
1366  int Imm = 0;
1367  bool UseImm = false;
1368  bool isNegativeImm = false;
1369  // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1370  // Thus, Src1Value may be a ConstantInt, but we're missing it.
1371  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1372  if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1373  SrcVT == MVT::i1) {
1374  const APInt &CIVal = ConstInt->getValue();
1375  Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1376  // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1377  // then a cmn, because there is no way to represent 2147483648 as a
1378  // signed 32-bit int.
1379  if (Imm < 0 && Imm != (int)0x80000000) {
1380  isNegativeImm = true;
1381  Imm = -Imm;
1382  }
1383  UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1384  (ARM_AM::getSOImmVal(Imm) != -1);
1385  }
1386  } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1387  if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1388  if (ConstFP->isZero() && !ConstFP->isNegative())
1389  UseImm = true;
1390  }
1391 
1392  unsigned CmpOpc;
1393  bool isICmp = true;
1394  bool needsExt = false;
1395  switch (SrcVT.SimpleTy) {
1396  default: return false;
1397  // TODO: Verify compares.
1398  case MVT::f32:
1399  isICmp = false;
1400  // Equality comparisons shouldn't raise Invalid on uordered inputs.
1401  if (isEquality)
1402  CmpOpc = UseImm ? ARM::VCMPZS : ARM::VCMPS;
1403  else
1404  CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1405  break;
1406  case MVT::f64:
1407  isICmp = false;
1408  // Equality comparisons shouldn't raise Invalid on uordered inputs.
1409  if (isEquality)
1410  CmpOpc = UseImm ? ARM::VCMPZD : ARM::VCMPD;
1411  else
1412  CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1413  break;
1414  case MVT::i1:
1415  case MVT::i8:
1416  case MVT::i16:
1417  needsExt = true;
1419  case MVT::i32:
1420  if (isThumb2) {
1421  if (!UseImm)
1422  CmpOpc = ARM::t2CMPrr;
1423  else
1424  CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1425  } else {
1426  if (!UseImm)
1427  CmpOpc = ARM::CMPrr;
1428  else
1429  CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1430  }
1431  break;
1432  }
1433 
1434  unsigned SrcReg1 = getRegForValue(Src1Value);
1435  if (SrcReg1 == 0) return false;
1436 
1437  unsigned SrcReg2 = 0;
1438  if (!UseImm) {
1439  SrcReg2 = getRegForValue(Src2Value);
1440  if (SrcReg2 == 0) return false;
1441  }
1442 
1443  // We have i1, i8, or i16, we need to either zero extend or sign extend.
1444  if (needsExt) {
1445  SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1446  if (SrcReg1 == 0) return false;
1447  if (!UseImm) {
1448  SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1449  if (SrcReg2 == 0) return false;
1450  }
1451  }
1452 
1453  const MCInstrDesc &II = TII.get(CmpOpc);
1454  SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1455  if (!UseImm) {
1456  SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1457  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1458  .addReg(SrcReg1).addReg(SrcReg2));
1459  } else {
1460  MachineInstrBuilder MIB;
1461  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1462  .addReg(SrcReg1);
1463 
1464  // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1465  if (isICmp)
1466  MIB.addImm(Imm);
1467  AddOptionalDefs(MIB);
1468  }
1469 
1470  // For floating point we need to move the result to a comparison register
1471  // that we can then use for branches.
1472  if (Ty->isFloatTy() || Ty->isDoubleTy())
1473  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1474  TII.get(ARM::FMSTAT)));
1475  return true;
1476 }
1477 
1478 bool ARMFastISel::SelectCmp(const Instruction *I) {
1479  const CmpInst *CI = cast<CmpInst>(I);
1480 
1481  // Get the compare predicate.
1482  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1483 
1484  // We may not handle every CC for now.
1485  if (ARMPred == ARMCC::AL) return false;
1486 
1487  // Emit the compare.
1488  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
1489  CI->isEquality()))
1490  return false;
1491 
1492  // Now set a register based on the comparison. Explicitly set the predicates
1493  // here.
1494  unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1495  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1496  : &ARM::GPRRegClass;
1497  unsigned DestReg = createResultReg(RC);
1498  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1499  unsigned ZeroReg = fastMaterializeConstant(Zero);
1500  // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1501  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1502  .addReg(ZeroReg).addImm(1)
1503  .addImm(ARMPred).addReg(ARM::CPSR);
1504 
1505  updateValueMap(I, DestReg);
1506  return true;
1507 }
1508 
1509 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1510  // Make sure we have VFP and that we're extending float to double.
1511  if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
1512 
1513  Value *V = I->getOperand(0);
1514  if (!I->getType()->isDoubleTy() ||
1515  !V->getType()->isFloatTy()) return false;
1516 
1517  unsigned Op = getRegForValue(V);
1518  if (Op == 0) return false;
1519 
1520  unsigned Result = createResultReg(&ARM::DPRRegClass);
1521  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1522  TII.get(ARM::VCVTDS), Result)
1523  .addReg(Op));
1524  updateValueMap(I, Result);
1525  return true;
1526 }
1527 
1528 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1529  // Make sure we have VFP and that we're truncating double to float.
1530  if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
1531 
1532  Value *V = I->getOperand(0);
1533  if (!(I->getType()->isFloatTy() &&
1534  V->getType()->isDoubleTy())) return false;
1535 
1536  unsigned Op = getRegForValue(V);
1537  if (Op == 0) return false;
1538 
1539  unsigned Result = createResultReg(&ARM::SPRRegClass);
1540  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1541  TII.get(ARM::VCVTSD), Result)
1542  .addReg(Op));
1543  updateValueMap(I, Result);
1544  return true;
1545 }
1546 
1547 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1548  // Make sure we have VFP.
1549  if (!Subtarget->hasVFP2Base()) return false;
1550 
1551  MVT DstVT;
1552  Type *Ty = I->getType();
1553  if (!isTypeLegal(Ty, DstVT))
1554  return false;
1555 
1556  Value *Src = I->getOperand(0);
1557  EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1558  if (!SrcEVT.isSimple())
1559  return false;
1560  MVT SrcVT = SrcEVT.getSimpleVT();
1561  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1562  return false;
1563 
1564  unsigned SrcReg = getRegForValue(Src);
1565  if (SrcReg == 0) return false;
1566 
1567  // Handle sign-extension.
1568  if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1569  SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1570  /*isZExt*/!isSigned);
1571  if (SrcReg == 0) return false;
1572  }
1573 
1574  // The conversion routine works on fp-reg to fp-reg and the operand above
1575  // was an integer, move it to the fp registers if possible.
1576  unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1577  if (FP == 0) return false;
1578 
1579  unsigned Opc;
1580  if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1581  else if (Ty->isDoubleTy() && Subtarget->hasFP64())
1582  Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1583  else return false;
1584 
1585  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1586  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1587  TII.get(Opc), ResultReg).addReg(FP));
1588  updateValueMap(I, ResultReg);
1589  return true;
1590 }
1591 
1592 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1593  // Make sure we have VFP.
1594  if (!Subtarget->hasVFP2Base()) return false;
1595 
1596  MVT DstVT;
1597  Type *RetTy = I->getType();
1598  if (!isTypeLegal(RetTy, DstVT))
1599  return false;
1600 
1601  unsigned Op = getRegForValue(I->getOperand(0));
1602  if (Op == 0) return false;
1603 
1604  unsigned Opc;
1605  Type *OpTy = I->getOperand(0)->getType();
1606  if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1607  else if (OpTy->isDoubleTy() && Subtarget->hasFP64())
1608  Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1609  else return false;
1610 
1611  // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1612  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1613  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1614  TII.get(Opc), ResultReg).addReg(Op));
1615 
1616  // This result needs to be in an integer register, but the conversion only
1617  // takes place in fp-regs.
1618  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1619  if (IntReg == 0) return false;
1620 
1621  updateValueMap(I, IntReg);
1622  return true;
1623 }
1624 
1625 bool ARMFastISel::SelectSelect(const Instruction *I) {
1626  MVT VT;
1627  if (!isTypeLegal(I->getType(), VT))
1628  return false;
1629 
1630  // Things need to be register sized for register moves.
1631  if (VT != MVT::i32) return false;
1632 
1633  unsigned CondReg = getRegForValue(I->getOperand(0));
1634  if (CondReg == 0) return false;
1635  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1636  if (Op1Reg == 0) return false;
1637 
1638  // Check to see if we can use an immediate in the conditional move.
1639  int Imm = 0;
1640  bool UseImm = false;
1641  bool isNegativeImm = false;
1642  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1643  assert(VT == MVT::i32 && "Expecting an i32.");
1644  Imm = (int)ConstInt->getValue().getZExtValue();
1645  if (Imm < 0) {
1646  isNegativeImm = true;
1647  Imm = ~Imm;
1648  }
1649  UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1650  (ARM_AM::getSOImmVal(Imm) != -1);
1651  }
1652 
1653  unsigned Op2Reg = 0;
1654  if (!UseImm) {
1655  Op2Reg = getRegForValue(I->getOperand(2));
1656  if (Op2Reg == 0) return false;
1657  }
1658 
1659  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1660  CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1661  AddOptionalDefs(
1662  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1663  .addReg(CondReg)
1664  .addImm(1));
1665 
1666  unsigned MovCCOpc;
1667  const TargetRegisterClass *RC;
1668  if (!UseImm) {
1669  RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1670  MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1671  } else {
1672  RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1673  if (!isNegativeImm)
1674  MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1675  else
1676  MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1677  }
1678  unsigned ResultReg = createResultReg(RC);
1679  if (!UseImm) {
1680  Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1681  Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1682  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1683  ResultReg)
1684  .addReg(Op2Reg)
1685  .addReg(Op1Reg)
1686  .addImm(ARMCC::NE)
1687  .addReg(ARM::CPSR);
1688  } else {
1689  Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1690  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1691  ResultReg)
1692  .addReg(Op1Reg)
1693  .addImm(Imm)
1694  .addImm(ARMCC::EQ)
1695  .addReg(ARM::CPSR);
1696  }
1697  updateValueMap(I, ResultReg);
1698  return true;
1699 }
1700 
1701 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1702  MVT VT;
1703  Type *Ty = I->getType();
1704  if (!isTypeLegal(Ty, VT))
1705  return false;
1706 
1707  // If we have integer div support we should have selected this automagically.
1708  // In case we have a real miss go ahead and return false and we'll pick
1709  // it up later.
1710  if (Subtarget->hasDivideInThumbMode())
1711  return false;
1712 
1713  // Otherwise emit a libcall.
1714  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1715  if (VT == MVT::i8)
1716  LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1717  else if (VT == MVT::i16)
1718  LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1719  else if (VT == MVT::i32)
1720  LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1721  else if (VT == MVT::i64)
1722  LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1723  else if (VT == MVT::i128)
1724  LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1725  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1726 
1727  return ARMEmitLibcall(I, LC);
1728 }
1729 
1730 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1731  MVT VT;
1732  Type *Ty = I->getType();
1733  if (!isTypeLegal(Ty, VT))
1734  return false;
1735 
1736  // Many ABIs do not provide a libcall for standalone remainder, so we need to
1737  // use divrem (see the RTABI 4.3.1). Since FastISel can't handle non-double
1738  // multi-reg returns, we'll have to bail out.
1739  if (!TLI.hasStandaloneRem(VT)) {
1740  return false;
1741  }
1742 
1743  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1744  if (VT == MVT::i8)
1745  LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1746  else if (VT == MVT::i16)
1747  LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1748  else if (VT == MVT::i32)
1749  LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1750  else if (VT == MVT::i64)
1751  LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1752  else if (VT == MVT::i128)
1753  LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1754  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1755 
1756  return ARMEmitLibcall(I, LC);
1757 }
1758 
1759 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1760  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1761 
1762  // We can get here in the case when we have a binary operation on a non-legal
1763  // type and the target independent selector doesn't know how to handle it.
1764  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1765  return false;
1766 
1767  unsigned Opc;
1768  switch (ISDOpcode) {
1769  default: return false;
1770  case ISD::ADD:
1771  Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1772  break;
1773  case ISD::OR:
1774  Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1775  break;
1776  case ISD::SUB:
1777  Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1778  break;
1779  }
1780 
1781  unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1782  if (SrcReg1 == 0) return false;
1783 
1784  // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1785  // in the instruction, rather then materializing the value in a register.
1786  unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1787  if (SrcReg2 == 0) return false;
1788 
1789  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1790  SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1791  SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1792  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1793  TII.get(Opc), ResultReg)
1794  .addReg(SrcReg1).addReg(SrcReg2));
1795  updateValueMap(I, ResultReg);
1796  return true;
1797 }
1798 
1799 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1800  EVT FPVT = TLI.getValueType(DL, I->getType(), true);
1801  if (!FPVT.isSimple()) return false;
1802  MVT VT = FPVT.getSimpleVT();
1803 
1804  // FIXME: Support vector types where possible.
1805  if (VT.isVector())
1806  return false;
1807 
1808  // We can get here in the case when we want to use NEON for our fp
1809  // operations, but can't figure out how to. Just use the vfp instructions
1810  // if we have them.
1811  // FIXME: It'd be nice to use NEON instructions.
1812  Type *Ty = I->getType();
1813  if (Ty->isFloatTy() && !Subtarget->hasVFP2Base())
1814  return false;
1815  if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()))
1816  return false;
1817 
1818  unsigned Opc;
1819  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1820  switch (ISDOpcode) {
1821  default: return false;
1822  case ISD::FADD:
1823  Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1824  break;
1825  case ISD::FSUB:
1826  Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1827  break;
1828  case ISD::FMUL:
1829  Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1830  break;
1831  }
1832  unsigned Op1 = getRegForValue(I->getOperand(0));
1833  if (Op1 == 0) return false;
1834 
1835  unsigned Op2 = getRegForValue(I->getOperand(1));
1836  if (Op2 == 0) return false;
1837 
1838  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1839  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1840  TII.get(Opc), ResultReg)
1841  .addReg(Op1).addReg(Op2));
1842  updateValueMap(I, ResultReg);
1843  return true;
1844 }
1845 
1846 // Call Handling Code
1847 
1848 // This is largely taken directly from CCAssignFnForNode
1849 // TODO: We may not support all of this.
1850 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1851  bool Return,
1852  bool isVarArg) {
1853  switch (CC) {
1854  default:
1855  report_fatal_error("Unsupported calling convention");
1856  case CallingConv::Fast:
1857  if (Subtarget->hasVFP2Base() && !isVarArg) {
1858  if (!Subtarget->isAAPCS_ABI())
1859  return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1860  // For AAPCS ABI targets, just use VFP variant of the calling convention.
1861  return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1862  }
1864  case CallingConv::C:
1866  // Use target triple & subtarget features to do actual dispatch.
1867  if (Subtarget->isAAPCS_ABI()) {
1868  if (Subtarget->hasVFP2Base() &&
1869  TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1870  return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1871  else
1872  return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1873  } else {
1874  return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1875  }
1877  case CallingConv::Swift:
1878  if (!isVarArg)
1879  return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1880  // Fall through to soft float variant, variadic functions don't
1881  // use hard floating point ABI.
1884  return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1885  case CallingConv::ARM_APCS:
1886  return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1887  case CallingConv::GHC:
1888  if (Return)
1889  report_fatal_error("Can't return in GHC call convention");
1890  else
1891  return CC_ARM_APCS_GHC;
1892  }
1893 }
1894 
1895 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1896  SmallVectorImpl<unsigned> &ArgRegs,
1897  SmallVectorImpl<MVT> &ArgVTs,
1899  SmallVectorImpl<unsigned> &RegArgs,
1900  CallingConv::ID CC,
1901  unsigned &NumBytes,
1902  bool isVarArg) {
1904  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1905  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1906  CCAssignFnForCall(CC, false, isVarArg));
1907 
1908  // Check that we can handle all of the arguments. If we can't, then bail out
1909  // now before we add code to the MBB.
1910  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1911  CCValAssign &VA = ArgLocs[i];
1912  MVT ArgVT = ArgVTs[VA.getValNo()];
1913 
1914  // We don't handle NEON/vector parameters yet.
1915  if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1916  return false;
1917 
1918  // Now copy/store arg to correct locations.
1919  if (VA.isRegLoc() && !VA.needsCustom()) {
1920  continue;
1921  } else if (VA.needsCustom()) {
1922  // TODO: We need custom lowering for vector (v2f64) args.
1923  if (VA.getLocVT() != MVT::f64 ||
1924  // TODO: Only handle register args for now.
1925  !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1926  return false;
1927  } else {
1928  switch (ArgVT.SimpleTy) {
1929  default:
1930  return false;
1931  case MVT::i1:
1932  case MVT::i8:
1933  case MVT::i16:
1934  case MVT::i32:
1935  break;
1936  case MVT::f32:
1937  if (!Subtarget->hasVFP2Base())
1938  return false;
1939  break;
1940  case MVT::f64:
1941  if (!Subtarget->hasVFP2Base())
1942  return false;
1943  break;
1944  }
1945  }
1946  }
1947 
1948  // At the point, we are able to handle the call's arguments in fast isel.
1949 
1950  // Get a count of how many bytes are to be pushed on the stack.
1951  NumBytes = CCInfo.getNextStackOffset();
1952 
1953  // Issue CALLSEQ_START
1954  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1955  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1956  TII.get(AdjStackDown))
1957  .addImm(NumBytes).addImm(0));
1958 
1959  // Process the args.
1960  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1961  CCValAssign &VA = ArgLocs[i];
1962  const Value *ArgVal = Args[VA.getValNo()];
1963  unsigned Arg = ArgRegs[VA.getValNo()];
1964  MVT ArgVT = ArgVTs[VA.getValNo()];
1965 
1966  assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1967  "We don't handle NEON/vector parameters yet.");
1968 
1969  // Handle arg promotion, etc.
1970  switch (VA.getLocInfo()) {
1971  case CCValAssign::Full: break;
1972  case CCValAssign::SExt: {
1973  MVT DestVT = VA.getLocVT();
1974  Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1975  assert(Arg != 0 && "Failed to emit a sext");
1976  ArgVT = DestVT;
1977  break;
1978  }
1979  case CCValAssign::AExt:
1980  // Intentional fall-through. Handle AExt and ZExt.
1981  case CCValAssign::ZExt: {
1982  MVT DestVT = VA.getLocVT();
1983  Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1984  assert(Arg != 0 && "Failed to emit a zext");
1985  ArgVT = DestVT;
1986  break;
1987  }
1988  case CCValAssign::BCvt: {
1989  unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1990  /*TODO: Kill=*/false);
1991  assert(BC != 0 && "Failed to emit a bitcast!");
1992  Arg = BC;
1993  ArgVT = VA.getLocVT();
1994  break;
1995  }
1996  default: llvm_unreachable("Unknown arg promotion!");
1997  }
1998 
1999  // Now copy/store arg to correct locations.
2000  if (VA.isRegLoc() && !VA.needsCustom()) {
2001  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2002  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
2003  RegArgs.push_back(VA.getLocReg());
2004  } else if (VA.needsCustom()) {
2005  // TODO: We need custom lowering for vector (v2f64) args.
2006  assert(VA.getLocVT() == MVT::f64 &&
2007  "Custom lowering for v2f64 args not available");
2008 
2009  // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
2010  CCValAssign &NextVA = ArgLocs[++i];
2011 
2012  assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2013  "We only handle register args!");
2014 
2015  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2016  TII.get(ARM::VMOVRRD), VA.getLocReg())
2017  .addReg(NextVA.getLocReg(), RegState::Define)
2018  .addReg(Arg));
2019  RegArgs.push_back(VA.getLocReg());
2020  RegArgs.push_back(NextVA.getLocReg());
2021  } else {
2022  assert(VA.isMemLoc());
2023  // Need to store on the stack.
2024 
2025  // Don't emit stores for undef values.
2026  if (isa<UndefValue>(ArgVal))
2027  continue;
2028 
2029  Address Addr;
2030  Addr.BaseType = Address::RegBase;
2031  Addr.Base.Reg = ARM::SP;
2032  Addr.Offset = VA.getLocMemOffset();
2033 
2034  bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2035  assert(EmitRet && "Could not emit a store for argument!");
2036  }
2037  }
2038 
2039  return true;
2040 }
2041 
2042 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2043  const Instruction *I, CallingConv::ID CC,
2044  unsigned &NumBytes, bool isVarArg) {
2045  // Issue CALLSEQ_END
2046  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2047  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2048  TII.get(AdjStackUp))
2049  .addImm(NumBytes).addImm(0));
2050 
2051  // Now the return value.
2052  if (RetVT != MVT::isVoid) {
2054  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2055  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2056 
2057  // Copy all of the result registers out of their specified physreg.
2058  if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2059  // For this move we copy into two registers and then move into the
2060  // double fp reg we want.
2061  MVT DestVT = RVLocs[0].getValVT();
2062  const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2063  unsigned ResultReg = createResultReg(DstRC);
2064  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2065  TII.get(ARM::VMOVDRR), ResultReg)
2066  .addReg(RVLocs[0].getLocReg())
2067  .addReg(RVLocs[1].getLocReg()));
2068 
2069  UsedRegs.push_back(RVLocs[0].getLocReg());
2070  UsedRegs.push_back(RVLocs[1].getLocReg());
2071 
2072  // Finally update the result.
2073  updateValueMap(I, ResultReg);
2074  } else {
2075  assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2076  MVT CopyVT = RVLocs[0].getValVT();
2077 
2078  // Special handling for extended integers.
2079  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2080  CopyVT = MVT::i32;
2081 
2082  const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2083 
2084  unsigned ResultReg = createResultReg(DstRC);
2085  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2086  TII.get(TargetOpcode::COPY),
2087  ResultReg).addReg(RVLocs[0].getLocReg());
2088  UsedRegs.push_back(RVLocs[0].getLocReg());
2089 
2090  // Finally update the result.
2091  updateValueMap(I, ResultReg);
2092  }
2093  }
2094 
2095  return true;
2096 }
2097 
2098 bool ARMFastISel::SelectRet(const Instruction *I) {
2099  const ReturnInst *Ret = cast<ReturnInst>(I);
2100  const Function &F = *I->getParent()->getParent();
2101 
2102  if (!FuncInfo.CanLowerReturn)
2103  return false;
2104 
2105  if (TLI.supportSwiftError() &&
2106  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError))
2107  return false;
2108 
2109  if (TLI.supportSplitCSR(FuncInfo.MF))
2110  return false;
2111 
2112  // Build a list of return value registers.
2113  SmallVector<unsigned, 4> RetRegs;
2114 
2115  CallingConv::ID CC = F.getCallingConv();
2116  if (Ret->getNumOperands() > 0) {
2118  GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2119 
2120  // Analyze operands of the call, assigning locations to each operand.
2122  CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2123  CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2124  F.isVarArg()));
2125 
2126  const Value *RV = Ret->getOperand(0);
2127  unsigned Reg = getRegForValue(RV);
2128  if (Reg == 0)
2129  return false;
2130 
2131  // Only handle a single return value for now.
2132  if (ValLocs.size() != 1)
2133  return false;
2134 
2135  CCValAssign &VA = ValLocs[0];
2136 
2137  // Don't bother handling odd stuff for now.
2138  if (VA.getLocInfo() != CCValAssign::Full)
2139  return false;
2140  // Only handle register returns for now.
2141  if (!VA.isRegLoc())
2142  return false;
2143 
2144  unsigned SrcReg = Reg + VA.getValNo();
2145  EVT RVEVT = TLI.getValueType(DL, RV->getType());
2146  if (!RVEVT.isSimple()) return false;
2147  MVT RVVT = RVEVT.getSimpleVT();
2148  MVT DestVT = VA.getValVT();
2149  // Special handling for extended integers.
2150  if (RVVT != DestVT) {
2151  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2152  return false;
2153 
2154  assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2155 
2156  // Perform extension if flagged as either zext or sext. Otherwise, do
2157  // nothing.
2158  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2159  SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2160  if (SrcReg == 0) return false;
2161  }
2162  }
2163 
2164  // Make the copy.
2165  unsigned DstReg = VA.getLocReg();
2166  const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2167  // Avoid a cross-class copy. This is very unlikely.
2168  if (!SrcRC->contains(DstReg))
2169  return false;
2170  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2171  TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2172 
2173  // Add register to return instruction.
2174  RetRegs.push_back(VA.getLocReg());
2175  }
2176 
2177  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2178  TII.get(Subtarget->getReturnOpcode()));
2179  AddOptionalDefs(MIB);
2180  for (unsigned R : RetRegs)
2181  MIB.addReg(R, RegState::Implicit);
2182  return true;
2183 }
2184 
2185 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2186  if (UseReg)
2187  return isThumb2 ? ARM::tBLXr : ARM::BLX;
2188  else
2189  return isThumb2 ? ARM::tBL : ARM::BL;
2190 }
2191 
2192 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2193  // Manually compute the global's type to avoid building it when unnecessary.
2194  Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2195  EVT LCREVT = TLI.getValueType(DL, GVTy);
2196  if (!LCREVT.isSimple()) return 0;
2197 
2198  GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2200  Name);
2201  assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2202  return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2203 }
2204 
2205 // A quick function that will emit a call for a named libcall in F with the
2206 // vector of passed arguments for the Instruction in I. We can assume that we
2207 // can emit a call for any libcall we can produce. This is an abridged version
2208 // of the full call infrastructure since we won't need to worry about things
2209 // like computed function pointers or strange arguments at call sites.
2210 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2211 // with X86.
2212 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2213  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2214 
2215  // Handle *simple* calls for now.
2216  Type *RetTy = I->getType();
2217  MVT RetVT;
2218  if (RetTy->isVoidTy())
2219  RetVT = MVT::isVoid;
2220  else if (!isTypeLegal(RetTy, RetVT))
2221  return false;
2222 
2223  // Can't handle non-double multi-reg retvals.
2224  if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2226  CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2227  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2228  if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2229  return false;
2230  }
2231 
2232  // Set up the argument vectors.
2234  SmallVector<unsigned, 8> ArgRegs;
2235  SmallVector<MVT, 8> ArgVTs;
2237  Args.reserve(I->getNumOperands());
2238  ArgRegs.reserve(I->getNumOperands());
2239  ArgVTs.reserve(I->getNumOperands());
2240  ArgFlags.reserve(I->getNumOperands());
2241  for (Value *Op : I->operands()) {
2242  unsigned Arg = getRegForValue(Op);
2243  if (Arg == 0) return false;
2244 
2245  Type *ArgTy = Op->getType();
2246  MVT ArgVT;
2247  if (!isTypeLegal(ArgTy, ArgVT)) return false;
2248 
2249  ISD::ArgFlagsTy Flags;
2250  unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2251  Flags.setOrigAlign(OriginalAlignment);
2252 
2253  Args.push_back(Op);
2254  ArgRegs.push_back(Arg);
2255  ArgVTs.push_back(ArgVT);
2256  ArgFlags.push_back(Flags);
2257  }
2258 
2259  // Handle the arguments now that we've gotten them.
2260  SmallVector<unsigned, 4> RegArgs;
2261  unsigned NumBytes;
2262  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2263  RegArgs, CC, NumBytes, false))
2264  return false;
2265 
2266  unsigned CalleeReg = 0;
2267  if (Subtarget->genLongCalls()) {
2268  CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2269  if (CalleeReg == 0) return false;
2270  }
2271 
2272  // Issue the call.
2273  unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
2274  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2275  DbgLoc, TII.get(CallOpc));
2276  // BL / BLX don't take a predicate, but tBL / tBLX do.
2277  if (isThumb2)
2278  MIB.add(predOps(ARMCC::AL));
2279  if (Subtarget->genLongCalls())
2280  MIB.addReg(CalleeReg);
2281  else
2282  MIB.addExternalSymbol(TLI.getLibcallName(Call));
2283 
2284  // Add implicit physical register uses to the call.
2285  for (unsigned R : RegArgs)
2286  MIB.addReg(R, RegState::Implicit);
2287 
2288  // Add a register mask with the call-preserved registers.
2289  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2290  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2291 
2292  // Finish off the call including any return values.
2293  SmallVector<unsigned, 4> UsedRegs;
2294  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2295 
2296  // Set all unused physreg defs as dead.
2297  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2298 
2299  return true;
2300 }
2301 
2302 bool ARMFastISel::SelectCall(const Instruction *I,
2303  const char *IntrMemName = nullptr) {
2304  const CallInst *CI = cast<CallInst>(I);
2305  const Value *Callee = CI->getCalledValue();
2306 
2307  // Can't handle inline asm.
2308  if (isa<InlineAsm>(Callee)) return false;
2309 
2310  // Allow SelectionDAG isel to handle tail calls.
2311  if (CI->isTailCall()) return false;
2312 
2313  // Check the calling convention.
2314  ImmutableCallSite CS(CI);
2315  CallingConv::ID CC = CS.getCallingConv();
2316 
2317  // TODO: Avoid some calling conventions?
2318 
2319  FunctionType *FTy = CS.getFunctionType();
2320  bool isVarArg = FTy->isVarArg();
2321 
2322  // Handle *simple* calls for now.
2323  Type *RetTy = I->getType();
2324  MVT RetVT;
2325  if (RetTy->isVoidTy())
2326  RetVT = MVT::isVoid;
2327  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2328  RetVT != MVT::i8 && RetVT != MVT::i1)
2329  return false;
2330 
2331  // Can't handle non-double multi-reg retvals.
2332  if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2333  RetVT != MVT::i16 && RetVT != MVT::i32) {
2335  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2336  CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2337  if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2338  return false;
2339  }
2340 
2341  // Set up the argument vectors.
2343  SmallVector<unsigned, 8> ArgRegs;
2344  SmallVector<MVT, 8> ArgVTs;
2346  unsigned arg_size = CS.arg_size();
2347  Args.reserve(arg_size);
2348  ArgRegs.reserve(arg_size);
2349  ArgVTs.reserve(arg_size);
2350  ArgFlags.reserve(arg_size);
2351  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2352  i != e; ++i) {
2353  // If we're lowering a memory intrinsic instead of a regular call, skip the
2354  // last argument, which shouldn't be passed to the underlying function.
2355  if (IntrMemName && e - i <= 1)
2356  break;
2357 
2358  ISD::ArgFlagsTy Flags;
2359  unsigned ArgIdx = i - CS.arg_begin();
2360  if (CS.paramHasAttr(ArgIdx, Attribute::SExt))
2361  Flags.setSExt();
2362  if (CS.paramHasAttr(ArgIdx, Attribute::ZExt))
2363  Flags.setZExt();
2364 
2365  // FIXME: Only handle *easy* calls for now.
2366  if (CS.paramHasAttr(ArgIdx, Attribute::InReg) ||
2367  CS.paramHasAttr(ArgIdx, Attribute::StructRet) ||
2368  CS.paramHasAttr(ArgIdx, Attribute::SwiftSelf) ||
2369  CS.paramHasAttr(ArgIdx, Attribute::SwiftError) ||
2370  CS.paramHasAttr(ArgIdx, Attribute::Nest) ||
2371  CS.paramHasAttr(ArgIdx, Attribute::ByVal))
2372  return false;
2373 
2374  Type *ArgTy = (*i)->getType();
2375  MVT ArgVT;
2376  if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2377  ArgVT != MVT::i1)
2378  return false;
2379 
2380  unsigned Arg = getRegForValue(*i);
2381  if (Arg == 0)
2382  return false;
2383 
2384  unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2385  Flags.setOrigAlign(OriginalAlignment);
2386 
2387  Args.push_back(*i);
2388  ArgRegs.push_back(Arg);
2389  ArgVTs.push_back(ArgVT);
2390  ArgFlags.push_back(Flags);
2391  }
2392 
2393  // Handle the arguments now that we've gotten them.
2394  SmallVector<unsigned, 4> RegArgs;
2395  unsigned NumBytes;
2396  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2397  RegArgs, CC, NumBytes, isVarArg))
2398  return false;
2399 
2400  bool UseReg = false;
2401  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2402  if (!GV || Subtarget->genLongCalls()) UseReg = true;
2403 
2404  unsigned CalleeReg = 0;
2405  if (UseReg) {
2406  if (IntrMemName)
2407  CalleeReg = getLibcallReg(IntrMemName);
2408  else
2409  CalleeReg = getRegForValue(Callee);
2410 
2411  if (CalleeReg == 0) return false;
2412  }
2413 
2414  // Issue the call.
2415  unsigned CallOpc = ARMSelectCallOp(UseReg);
2416  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2417  DbgLoc, TII.get(CallOpc));
2418 
2419  // ARM calls don't take a predicate, but tBL / tBLX do.
2420  if(isThumb2)
2421  MIB.add(predOps(ARMCC::AL));
2422  if (UseReg)
2423  MIB.addReg(CalleeReg);
2424  else if (!IntrMemName)
2425  MIB.addGlobalAddress(GV, 0, 0);
2426  else
2427  MIB.addExternalSymbol(IntrMemName, 0);
2428 
2429  // Add implicit physical register uses to the call.
2430  for (unsigned R : RegArgs)
2431  MIB.addReg(R, RegState::Implicit);
2432 
2433  // Add a register mask with the call-preserved registers.
2434  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2435  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2436 
2437  // Finish off the call including any return values.
2438  SmallVector<unsigned, 4> UsedRegs;
2439  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2440  return false;
2441 
2442  // Set all unused physreg defs as dead.
2443  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2444 
2445  return true;
2446 }
2447 
2448 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2449  return Len <= 16;
2450 }
2451 
2452 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2453  uint64_t Len, unsigned Alignment) {
2454  // Make sure we don't bloat code by inlining very large memcpy's.
2455  if (!ARMIsMemCpySmall(Len))
2456  return false;
2457 
2458  while (Len) {
2459  MVT VT;
2460  if (!Alignment || Alignment >= 4) {
2461  if (Len >= 4)
2462  VT = MVT::i32;
2463  else if (Len >= 2)
2464  VT = MVT::i16;
2465  else {
2466  assert(Len == 1 && "Expected a length of 1!");
2467  VT = MVT::i8;
2468  }
2469  } else {
2470  // Bound based on alignment.
2471  if (Len >= 2 && Alignment == 2)
2472  VT = MVT::i16;
2473  else {
2474  VT = MVT::i8;
2475  }
2476  }
2477 
2478  bool RV;
2479  unsigned ResultReg;
2480  RV = ARMEmitLoad(VT, ResultReg, Src);
2481  assert(RV && "Should be able to handle this load.");
2482  RV = ARMEmitStore(VT, ResultReg, Dest);
2483  assert(RV && "Should be able to handle this store.");
2484  (void)RV;
2485 
2486  unsigned Size = VT.getSizeInBits()/8;
2487  Len -= Size;
2488  Dest.Offset += Size;
2489  Src.Offset += Size;
2490  }
2491 
2492  return true;
2493 }
2494 
2495 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2496  // FIXME: Handle more intrinsics.
2497  switch (I.getIntrinsicID()) {
2498  default: return false;
2499  case Intrinsic::frameaddress: {
2500  MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
2501  MFI.setFrameAddressIsTaken(true);
2502 
2503  unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2504  const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2505  : &ARM::GPRRegClass;
2506 
2507  const ARMBaseRegisterInfo *RegInfo =
2508  static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2509  unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2510  unsigned SrcReg = FramePtr;
2511 
2512  // Recursively load frame address
2513  // ldr r0 [fp]
2514  // ldr r0 [r0]
2515  // ldr r0 [r0]
2516  // ...
2517  unsigned DestReg;
2518  unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2519  while (Depth--) {
2520  DestReg = createResultReg(RC);
2521  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2522  TII.get(LdrOpc), DestReg)
2523  .addReg(SrcReg).addImm(0));
2524  SrcReg = DestReg;
2525  }
2526  updateValueMap(&I, SrcReg);
2527  return true;
2528  }
2529  case Intrinsic::memcpy:
2530  case Intrinsic::memmove: {
2531  const MemTransferInst &MTI = cast<MemTransferInst>(I);
2532  // Don't handle volatile.
2533  if (MTI.isVolatile())
2534  return false;
2535 
2536  // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2537  // we would emit dead code because we don't currently handle memmoves.
2538  bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2539  if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2540  // Small memcpy's are common enough that we want to do them without a call
2541  // if possible.
2542  uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2543  if (ARMIsMemCpySmall(Len)) {
2544  Address Dest, Src;
2545  if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2546  !ARMComputeAddress(MTI.getRawSource(), Src))
2547  return false;
2548  unsigned Alignment = MinAlign(MTI.getDestAlignment(),
2549  MTI.getSourceAlignment());
2550  if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2551  return true;
2552  }
2553  }
2554 
2555  if (!MTI.getLength()->getType()->isIntegerTy(32))
2556  return false;
2557 
2558  if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2559  return false;
2560 
2561  const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2562  return SelectCall(&I, IntrMemName);
2563  }
2564  case Intrinsic::memset: {
2565  const MemSetInst &MSI = cast<MemSetInst>(I);
2566  // Don't handle volatile.
2567  if (MSI.isVolatile())
2568  return false;
2569 
2570  if (!MSI.getLength()->getType()->isIntegerTy(32))
2571  return false;
2572 
2573  if (MSI.getDestAddressSpace() > 255)
2574  return false;
2575 
2576  return SelectCall(&I, "memset");
2577  }
2578  case Intrinsic::trap: {
2579  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2580  Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2581  return true;
2582  }
2583  }
2584 }
2585 
2586 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2587  // The high bits for a type smaller than the register size are assumed to be
2588  // undefined.
2589  Value *Op = I->getOperand(0);
2590 
2591  EVT SrcVT, DestVT;
2592  SrcVT = TLI.getValueType(DL, Op->getType(), true);
2593  DestVT = TLI.getValueType(DL, I->getType(), true);
2594 
2595  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2596  return false;
2597  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2598  return false;
2599 
2600  unsigned SrcReg = getRegForValue(Op);
2601  if (!SrcReg) return false;
2602 
2603  // Because the high bits are undefined, a truncate doesn't generate
2604  // any code.
2605  updateValueMap(I, SrcReg);
2606  return true;
2607 }
2608 
2609 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2610  bool isZExt) {
2611  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2612  return 0;
2613  if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2614  return 0;
2615 
2616  // Table of which combinations can be emitted as a single instruction,
2617  // and which will require two.
2618  static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2619  // ARM Thumb
2620  // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2621  // ext: s z s z s z s z
2622  /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2623  /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2624  /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2625  };
2626 
2627  // Target registers for:
2628  // - For ARM can never be PC.
2629  // - For 16-bit Thumb are restricted to lower 8 registers.
2630  // - For 32-bit Thumb are restricted to non-SP and non-PC.
2631  static const TargetRegisterClass *RCTbl[2][2] = {
2632  // Instructions: Two Single
2633  /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2634  /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2635  };
2636 
2637  // Table governing the instruction(s) to be emitted.
2638  static const struct InstructionTable {
2639  uint32_t Opc : 16;
2640  uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2641  uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2642  uint32_t Imm : 8; // All instructions have either a shift or a mask.
2643  } IT[2][2][3][2] = {
2644  { // Two instructions (first is left shift, second is in this table).
2645  { // ARM Opc S Shift Imm
2646  /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2647  /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2648  /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2649  /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2650  /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2651  /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2652  },
2653  { // Thumb Opc S Shift Imm
2654  /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2655  /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2656  /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2657  /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2658  /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2659  /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2660  }
2661  },
2662  { // Single instruction.
2663  { // ARM Opc S Shift Imm
2664  /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2665  /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2666  /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2667  /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2668  /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2669  /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2670  },
2671  { // Thumb Opc S Shift Imm
2672  /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2673  /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2674  /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2675  /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2676  /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2677  /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2678  }
2679  }
2680  };
2681 
2682  unsigned SrcBits = SrcVT.getSizeInBits();
2683  unsigned DestBits = DestVT.getSizeInBits();
2684  (void) DestBits;
2685  assert((SrcBits < DestBits) && "can only extend to larger types");
2686  assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2687  "other sizes unimplemented");
2688  assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2689  "other sizes unimplemented");
2690 
2691  bool hasV6Ops = Subtarget->hasV6Ops();
2692  unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2693  assert((Bitness < 3) && "sanity-check table bounds");
2694 
2695  bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2696  const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2697  const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2698  unsigned Opc = ITP->Opc;
2699  assert(ARM::KILL != Opc && "Invalid table entry");
2700  unsigned hasS = ITP->hasS;
2701  ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2702  assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2703  "only MOVsi has shift operand addressing mode");
2704  unsigned Imm = ITP->Imm;
2705 
2706  // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2707  bool setsCPSR = &ARM::tGPRRegClass == RC;
2708  unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2709  unsigned ResultReg;
2710  // MOVsi encodes shift and immediate in shift operand addressing mode.
2711  // The following condition has the same value when emitting two
2712  // instruction sequences: both are shifts.
2713  bool ImmIsSO = (Shift != ARM_AM::no_shift);
2714 
2715  // Either one or two instructions are emitted.
2716  // They're always of the form:
2717  // dst = in OP imm
2718  // CPSR is set only by 16-bit Thumb instructions.
2719  // Predicate, if any, is AL.
2720  // S bit, if available, is always 0.
2721  // When two are emitted the first's result will feed as the second's input,
2722  // that value is then dead.
2723  unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2724  for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2725  ResultReg = createResultReg(RC);
2726  bool isLsl = (0 == Instr) && !isSingleInstr;
2727  unsigned Opcode = isLsl ? LSLOpc : Opc;
2728  ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2729  unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2730  bool isKill = 1 == Instr;
2732  *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2733  if (setsCPSR)
2734  MIB.addReg(ARM::CPSR, RegState::Define);
2735  SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2736  MIB.addReg(SrcReg, isKill * RegState::Kill)
2737  .addImm(ImmEnc)
2738  .add(predOps(ARMCC::AL));
2739  if (hasS)
2740  MIB.add(condCodeOp());
2741  // Second instruction consumes the first's result.
2742  SrcReg = ResultReg;
2743  }
2744 
2745  return ResultReg;
2746 }
2747 
2748 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2749  // On ARM, in general, integer casts don't involve legal types; this code
2750  // handles promotable integers.
2751  Type *DestTy = I->getType();
2752  Value *Src = I->getOperand(0);
2753  Type *SrcTy = Src->getType();
2754 
2755  bool isZExt = isa<ZExtInst>(I);
2756  unsigned SrcReg = getRegForValue(Src);
2757  if (!SrcReg) return false;
2758 
2759  EVT SrcEVT, DestEVT;
2760  SrcEVT = TLI.getValueType(DL, SrcTy, true);
2761  DestEVT = TLI.getValueType(DL, DestTy, true);
2762  if (!SrcEVT.isSimple()) return false;
2763  if (!DestEVT.isSimple()) return false;
2764 
2765  MVT SrcVT = SrcEVT.getSimpleVT();
2766  MVT DestVT = DestEVT.getSimpleVT();
2767  unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2768  if (ResultReg == 0) return false;
2769  updateValueMap(I, ResultReg);
2770  return true;
2771 }
2772 
2773 bool ARMFastISel::SelectShift(const Instruction *I,
2774  ARM_AM::ShiftOpc ShiftTy) {
2775  // We handle thumb2 mode by target independent selector
2776  // or SelectionDAG ISel.
2777  if (isThumb2)
2778  return false;
2779 
2780  // Only handle i32 now.
2781  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
2782  if (DestVT != MVT::i32)
2783  return false;
2784 
2785  unsigned Opc = ARM::MOVsr;
2786  unsigned ShiftImm;
2787  Value *Src2Value = I->getOperand(1);
2788  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2789  ShiftImm = CI->getZExtValue();
2790 
2791  // Fall back to selection DAG isel if the shift amount
2792  // is zero or greater than the width of the value type.
2793  if (ShiftImm == 0 || ShiftImm >=32)
2794  return false;
2795 
2796  Opc = ARM::MOVsi;
2797  }
2798 
2799  Value *Src1Value = I->getOperand(0);
2800  unsigned Reg1 = getRegForValue(Src1Value);
2801  if (Reg1 == 0) return false;
2802 
2803  unsigned Reg2 = 0;
2804  if (Opc == ARM::MOVsr) {
2805  Reg2 = getRegForValue(Src2Value);
2806  if (Reg2 == 0) return false;
2807  }
2808 
2809  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2810  if(ResultReg == 0) return false;
2811 
2812  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2813  TII.get(Opc), ResultReg)
2814  .addReg(Reg1);
2815 
2816  if (Opc == ARM::MOVsi)
2817  MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2818  else if (Opc == ARM::MOVsr) {
2819  MIB.addReg(Reg2);
2820  MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2821  }
2822 
2823  AddOptionalDefs(MIB);
2824  updateValueMap(I, ResultReg);
2825  return true;
2826 }
2827 
2828 // TODO: SoftFP support.
2829 bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2830  switch (I->getOpcode()) {
2831  case Instruction::Load:
2832  return SelectLoad(I);
2833  case Instruction::Store:
2834  return SelectStore(I);
2835  case Instruction::Br:
2836  return SelectBranch(I);
2837  case Instruction::IndirectBr:
2838  return SelectIndirectBr(I);
2839  case Instruction::ICmp:
2840  case Instruction::FCmp:
2841  return SelectCmp(I);
2842  case Instruction::FPExt:
2843  return SelectFPExt(I);
2844  case Instruction::FPTrunc:
2845  return SelectFPTrunc(I);
2846  case Instruction::SIToFP:
2847  return SelectIToFP(I, /*isSigned*/ true);
2848  case Instruction::UIToFP:
2849  return SelectIToFP(I, /*isSigned*/ false);
2850  case Instruction::FPToSI:
2851  return SelectFPToI(I, /*isSigned*/ true);
2852  case Instruction::FPToUI:
2853  return SelectFPToI(I, /*isSigned*/ false);
2854  case Instruction::Add:
2855  return SelectBinaryIntOp(I, ISD::ADD);
2856  case Instruction::Or:
2857  return SelectBinaryIntOp(I, ISD::OR);
2858  case Instruction::Sub:
2859  return SelectBinaryIntOp(I, ISD::SUB);
2860  case Instruction::FAdd:
2861  return SelectBinaryFPOp(I, ISD::FADD);
2862  case Instruction::FSub:
2863  return SelectBinaryFPOp(I, ISD::FSUB);
2864  case Instruction::FMul:
2865  return SelectBinaryFPOp(I, ISD::FMUL);
2866  case Instruction::SDiv:
2867  return SelectDiv(I, /*isSigned*/ true);
2868  case Instruction::UDiv:
2869  return SelectDiv(I, /*isSigned*/ false);
2870  case Instruction::SRem:
2871  return SelectRem(I, /*isSigned*/ true);
2872  case Instruction::URem:
2873  return SelectRem(I, /*isSigned*/ false);
2874  case Instruction::Call:
2875  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2876  return SelectIntrinsicCall(*II);
2877  return SelectCall(I);
2878  case Instruction::Select:
2879  return SelectSelect(I);
2880  case Instruction::Ret:
2881  return SelectRet(I);
2882  case Instruction::Trunc:
2883  return SelectTrunc(I);
2884  case Instruction::ZExt:
2885  case Instruction::SExt:
2886  return SelectIntExt(I);
2887  case Instruction::Shl:
2888  return SelectShift(I, ARM_AM::lsl);
2889  case Instruction::LShr:
2890  return SelectShift(I, ARM_AM::lsr);
2891  case Instruction::AShr:
2892  return SelectShift(I, ARM_AM::asr);
2893  default: break;
2894  }
2895  return false;
2896 }
2897 
2898 // This table describes sign- and zero-extend instructions which can be
2899 // folded into a preceding load. All of these extends have an immediate
2900 // (sometimes a mask and sometimes a shift) that's applied after
2901 // extension.
2902 static const struct FoldableLoadExtendsStruct {
2903  uint16_t Opc[2]; // ARM, Thumb.
2904  uint8_t ExpectedImm;
2905  uint8_t isZExt : 1;
2906  uint8_t ExpectedVT : 7;
2907 } FoldableLoadExtends[] = {
2908  { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2909  { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2910  { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2911  { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2912  { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2913 };
2914 
2915 /// The specified machine instr operand is a vreg, and that
2916 /// vreg is being provided by the specified load instruction. If possible,
2917 /// try to fold the load as an operand to the instruction, returning true if
2918 /// successful.
2919 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2920  const LoadInst *LI) {
2921  // Verify we have a legal type before going any further.
2922  MVT VT;
2923  if (!isLoadTypeLegal(LI->getType(), VT))
2924  return false;
2925 
2926  // Combine load followed by zero- or sign-extend.
2927  // ldrb r1, [r0] ldrb r1, [r0]
2928  // uxtb r2, r1 =>
2929  // mov r3, r2 mov r3, r1
2930  if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2931  return false;
2932  const uint64_t Imm = MI->getOperand(2).getImm();
2933 
2934  bool Found = false;
2935  bool isZExt;
2936  for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) {
2937  if (FLE.Opc[isThumb2] == MI->getOpcode() &&
2938  (uint64_t)FLE.ExpectedImm == Imm &&
2939  MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) {
2940  Found = true;
2941  isZExt = FLE.isZExt;
2942  }
2943  }
2944  if (!Found) return false;
2945 
2946  // See if we can handle this address.
2947  Address Addr;
2948  if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2949 
2950  unsigned ResultReg = MI->getOperand(0).getReg();
2951  if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2952  return false;
2954  removeDeadCode(I, std::next(I));
2955  return true;
2956 }
2957 
2958 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2959  unsigned Align, MVT VT) {
2960  bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
2961 
2962  LLVMContext *Context = &MF->getFunction().getContext();
2963  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2964  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2966  GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
2967  UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
2968  /*AddCurrentAddress=*/UseGOT_PREL);
2969 
2970  unsigned ConstAlign =
2971  MF->getDataLayout().getPrefTypeAlignment(Type::getInt32PtrTy(*Context));
2972  unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(CPV, ConstAlign);
2973  MachineMemOperand *CPMMO =
2974  MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
2976 
2977  unsigned TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
2978  unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
2979  MachineInstrBuilder MIB =
2980  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
2981  .addConstantPoolIndex(Idx)
2982  .addMemOperand(CPMMO);
2983  if (Opc == ARM::LDRcp)
2984  MIB.addImm(0);
2985  MIB.add(predOps(ARMCC::AL));
2986 
2987  // Fix the address by adding pc.
2988  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
2989  Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
2990  : ARM::PICADD;
2991  DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
2992  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2993  .addReg(TempReg)
2994  .addImm(ARMPCLabelIndex);
2995 
2996  if (!Subtarget->isThumb())
2997  MIB.add(predOps(ARMCC::AL));
2998 
2999  if (UseGOT_PREL && Subtarget->isThumb()) {
3000  unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
3001  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3002  TII.get(ARM::t2LDRi12), NewDestReg)
3003  .addReg(DestReg)
3004  .addImm(0);
3005  DestReg = NewDestReg;
3006  AddOptionalDefs(MIB);
3007  }
3008  return DestReg;
3009 }
3010 
3011 bool ARMFastISel::fastLowerArguments() {
3012  if (!FuncInfo.CanLowerReturn)
3013  return false;
3014 
3015  const Function *F = FuncInfo.Fn;
3016  if (F->isVarArg())
3017  return false;
3018 
3019  CallingConv::ID CC = F->getCallingConv();
3020  switch (CC) {
3021  default:
3022  return false;
3023  case CallingConv::Fast:
3024  case CallingConv::C:
3027  case CallingConv::ARM_APCS:
3028  case CallingConv::Swift:
3029  break;
3030  }
3031 
3032  // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3033  // which are passed in r0 - r3.
3034  for (const Argument &Arg : F->args()) {
3035  if (Arg.getArgNo() >= 4)
3036  return false;
3037 
3038  if (Arg.hasAttribute(Attribute::InReg) ||
3039  Arg.hasAttribute(Attribute::StructRet) ||
3040  Arg.hasAttribute(Attribute::SwiftSelf) ||
3041  Arg.hasAttribute(Attribute::SwiftError) ||
3042  Arg.hasAttribute(Attribute::ByVal))
3043  return false;
3044 
3045  Type *ArgTy = Arg.getType();
3046  if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3047  return false;
3048 
3049  EVT ArgVT = TLI.getValueType(DL, ArgTy);
3050  if (!ArgVT.isSimple()) return false;
3051  switch (ArgVT.getSimpleVT().SimpleTy) {
3052  case MVT::i8:
3053  case MVT::i16:
3054  case MVT::i32:
3055  break;
3056  default:
3057  return false;
3058  }
3059  }
3060 
3061  static const MCPhysReg GPRArgRegs[] = {
3062  ARM::R0, ARM::R1, ARM::R2, ARM::R3
3063  };
3064 
3065  const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3066  for (const Argument &Arg : F->args()) {
3067  unsigned ArgNo = Arg.getArgNo();
3068  unsigned SrcReg = GPRArgRegs[ArgNo];
3069  unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3070  // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3071  // Without this, EmitLiveInCopies may eliminate the livein if its only
3072  // use is a bitcast (which isn't turned into an instruction).
3073  unsigned ResultReg = createResultReg(RC);
3074  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3075  TII.get(TargetOpcode::COPY),
3076  ResultReg).addReg(DstReg, getKillRegState(true));
3077  updateValueMap(&Arg, ResultReg);
3078  }
3079 
3080  return true;
3081 }
3082 
3083 namespace llvm {
3084 
3086  const TargetLibraryInfo *libInfo) {
3087  if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3088  return new ARMFastISel(funcInfo, libInfo);
3089 
3090  return nullptr;
3091  }
3092 
3093 } // end namespace llvm
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
IterTy arg_end() const
Definition: CallSite.h:588
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
Return a value (possibly void), from a function.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
const MachineInstrBuilder & add(const MachineOperand &MO) const
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
LLVMContext & Context
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
IterTy arg_begin() const
Definition: CallSite.h:584
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
bool isVector() const
Return true if this is a vector value type.
bool useFastISel() const
True if fast-isel is used.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
void push_back(const T &Elt)
Definition: SmallVector.h:211
ARMConstantPoolValue - ARM specific constantpool value.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
static PointerType * getInt32PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:227
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
unsigned getSourceAlignment() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:688
unsigned less or equal
Definition: InstrTypes.h:758
unsigned less than
Definition: InstrTypes.h:757
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:738
unsigned getSourceAddressSpace() const
Externally visible function.
Definition: GlobalValue.h:48
unsigned getValNo() const
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:720
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:748
int getFP64Imm(const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
This class wraps the llvm.memset intrinsic.
BasicBlock * getSuccessor(unsigned i) const
unsigned const TargetRegisterInfo * TRI
F(f)
unsigned getCallFrameDestroyOpcode() const
An instruction for reading from memory.
Definition: Instructions.h:167
#define R2(n)
Value * getCondition() const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
void reserve(size_type N)
Definition: SmallVector.h:369
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:460
Value * getLength() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
op_iterator op_begin()
Definition: User.h:229
FunctionType * getFunctionType() const
Definition: CallSite.h:328
bool isMemLoc() const
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:320
bool needsCustom() const
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:743
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:562
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:742
A description of a memory reference used in the backend.
Predicate getInversePredicate() const
For example, EQ -> NE, UGT -> ULE, SLT -> SGE, OEQ -> UNE, UGT -> OLE, OLT -> UGE, etc.
Definition: InstrTypes.h:831
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
const HexagonInstrInfo * TII
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:96
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
Class to represent struct types.
Definition: DerivedTypes.h:233
static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred)
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isUnsigned() const
Definition: InstrTypes.h:908
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:739
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
unsigned getDestAlignment() const
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getSizeInBits() const
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Class to represent function types.
Definition: DerivedTypes.h:103
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:888
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool isVarArg() const
Definition: DerivedTypes.h:123
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Return true if the call or the callee has the given attribute.
Definition: CallSite.h:385
static const MCPhysReg GPRArgRegs[]
void setOrigAlign(unsigned A)
static const struct FoldableLoadExtendsStruct FoldableLoadExtends[]
This class represents a truncation of integer types.
Value * getOperand(unsigned i) const
Definition: User.h:169
Class to represent pointers.
Definition: DerivedTypes.h:544
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:146
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
unsigned const MachineRegisterInfo * MRI
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
Machine Value Type.
Value * getCalledValue() const
Definition: InstrTypes.h:1280
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Indirect Branch Instruction.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:174
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
op_iterator op_end()
Definition: User.h:231
This file declares a class to represent arbitrary precision floating point values and provide a varie...
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:798
Thread Local Storage (General Dynamic Mode)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
op_range operands()
Definition: User.h:237
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:741
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Extended Value Type.
Definition: ValueTypes.h:33
bool isPositionIndependent() const
size_t size() const
Definition: SmallVector.h:52
static bool isAtomic(Instruction *I)
bool isVolatile() const
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:747
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
signed greater than
Definition: InstrTypes.h:759
bool isNegative() const
Definition: Constants.h:187
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:302
BaseType
A given derived pointer can have multiple base pointers through phi/selects.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:50
bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:736
unsigned getNumOperands() const
Definition: User.h:191
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
CCState - This class holds information needed while lowering arguments and return values...
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:746
Module.h This file contains the declarations for the Module class.
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned arg_size() const
Definition: CallSite.h:226
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:761
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:226
Value * getRawSource() const
Return the arguments to the instruction.
User::const_op_iterator arg_iterator
The type of iterator to use when looping over actual arguments at this call site. ...
Definition: CallSite.h:220
int64_t getImm() const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
signed less or equal
Definition: InstrTypes.h:762
Target - Wrapper for Target specific information.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Class for arbitrary precision integers.
Definition: APInt.h:69
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:102
amdgpu Simplify well known AMD library false FunctionCallee Callee
This file defines the FastISel class.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
bool isTailCall() const
Flags
Flags values. These may be or&#39;d together.
The memory access reads data.
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate IT block based on arch"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT, "arm-no-restrict-it", "Allow IT blocks based on ARMv7")))
Representation of each machine instruction.
Definition: MachineInstr.h:63
virtual bool isFPImmLegal(const APFloat &, EVT, bool ForCodeSize=false) const
Returns true if the target can instruction select the specified FP immediate natively.
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:807
This class wraps the llvm.memcpy/memmove intrinsics.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getDestAddressSpace() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:584
unsigned getAlignment() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:240
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
unsigned getLocMemOffset() const
unsigned greater or equal
Definition: InstrTypes.h:756
static unsigned UseReg(const MachineOperand &MO)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
TargetOptions Options
Establish a view to a call site for examination.
Definition: CallSite.h:897
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
ARM_AAPCS - ARM Architecture Procedure Calling Standard calling convention (aka EABI).
Definition: CallingConv.h:99
#define I(x, y, z)
Definition: MD5.cpp:58
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:740
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:218
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:744
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:614
bool isRegLoc() const
bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int getFP32Imm(const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
aarch64 promote const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:735
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
bool isEquality() const
This is just a convenience that dispatches to the subclasses.
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:745
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
static const Function * getParent(const Value *V)
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:280
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:250
IRTranslator LLVM IR MI
bool hasOneUse() const
Return true if there is exactly one user of this value.
Definition: Value.h:412
unsigned greater than
Definition: InstrTypes.h:755
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:156
unsigned getLocReg() const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:737
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:149
Value * getRawDest() const
ARM_APCS - ARM Procedure Calling Standard calling convention (obsolete, but still used on some target...
Definition: CallingConv.h:95
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:277
iterator_range< arg_iterator > args()
Definition: Function.h:705
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:217
signed greater or equal
Definition: InstrTypes.h:760
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:220
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:66
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
an instruction to allocate memory on the stack
Definition: Instructions.h:59
gep_type_iterator gep_type_begin(const User *GEP)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...