LLVM  9.0.0svn
ARMISelLowering.cpp
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1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMISelLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSelectionDAGInfo.h"
24 #include "ARMSubtarget.h"
27 #include "Utils/ARMBaseInfo.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/APInt.h"
30 #include "llvm/ADT/ArrayRef.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/ADT/SmallPtrSet.h"
35 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/StringExtras.h"
38 #include "llvm/ADT/StringRef.h"
39 #include "llvm/ADT/StringSwitch.h"
40 #include "llvm/ADT/Triple.h"
41 #include "llvm/ADT/Twine.h"
65 #include "llvm/IR/Attributes.h"
66 #include "llvm/IR/CallingConv.h"
67 #include "llvm/IR/Constant.h"
68 #include "llvm/IR/Constants.h"
69 #include "llvm/IR/DataLayout.h"
70 #include "llvm/IR/DebugLoc.h"
71 #include "llvm/IR/DerivedTypes.h"
72 #include "llvm/IR/Function.h"
73 #include "llvm/IR/GlobalAlias.h"
74 #include "llvm/IR/GlobalValue.h"
75 #include "llvm/IR/GlobalVariable.h"
76 #include "llvm/IR/IRBuilder.h"
77 #include "llvm/IR/InlineAsm.h"
78 #include "llvm/IR/Instruction.h"
79 #include "llvm/IR/Instructions.h"
80 #include "llvm/IR/IntrinsicInst.h"
81 #include "llvm/IR/Intrinsics.h"
82 #include "llvm/IR/Module.h"
83 #include "llvm/IR/Type.h"
84 #include "llvm/IR/User.h"
85 #include "llvm/IR/Value.h"
86 #include "llvm/MC/MCInstrDesc.h"
88 #include "llvm/MC/MCRegisterInfo.h"
89 #include "llvm/MC/MCSchedule.h"
92 #include "llvm/Support/Casting.h"
93 #include "llvm/Support/CodeGen.h"
95 #include "llvm/Support/Compiler.h"
96 #include "llvm/Support/Debug.h"
98 #include "llvm/Support/KnownBits.h"
100 #include "llvm/Support/MathExtras.h"
104 #include <algorithm>
105 #include <cassert>
106 #include <cstdint>
107 #include <cstdlib>
108 #include <iterator>
109 #include <limits>
110 #include <string>
111 #include <tuple>
112 #include <utility>
113 #include <vector>
114 
115 using namespace llvm;
116 
117 #define DEBUG_TYPE "arm-isel"
118 
119 STATISTIC(NumTailCalls, "Number of tail calls");
120 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
121 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
122 STATISTIC(NumConstpoolPromoted,
123  "Number of constants with their storage promoted into constant pools");
124 
125 static cl::opt<bool>
126 ARMInterworking("arm-interworking", cl::Hidden,
127  cl::desc("Enable / disable ARM interworking (for debugging only)"),
128  cl::init(true));
129 
131  "arm-promote-constant", cl::Hidden,
132  cl::desc("Enable / disable promotion of unnamed_addr constants into "
133  "constant pools"),
134  cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
136  "arm-promote-constant-max-size", cl::Hidden,
137  cl::desc("Maximum size of constant to promote into a constant pool"),
138  cl::init(64));
140  "arm-promote-constant-max-total", cl::Hidden,
141  cl::desc("Maximum size of ALL constants to promote into a constant pool"),
142  cl::init(128));
143 
144 // The APCS parameter registers.
145 static const MCPhysReg GPRArgRegs[] = {
146  ARM::R0, ARM::R1, ARM::R2, ARM::R3
147 };
148 
149 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
150  MVT PromotedBitwiseVT) {
151  if (VT != PromotedLdStVT) {
153  AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
154 
156  AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
157  }
158 
159  MVT ElemTy = VT.getVectorElementType();
160  if (ElemTy != MVT::f64)
164  if (ElemTy == MVT::i32) {
169  } else {
174  }
183  if (VT.isInteger()) {
187  }
188 
189  // Promote all bit-wise operations.
190  if (VT.isInteger() && VT != PromotedBitwiseVT) {
192  AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
194  AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
196  AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
197  }
198 
199  // Neon does not support vector divide/remainder operations.
206 
207  if (!VT.isFloatingPoint() &&
208  VT != MVT::v2i64 && VT != MVT::v1i64)
209  for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210  setOperationAction(Opcode, VT, Legal);
211 }
212 
213 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
214  addRegisterClass(VT, &ARM::DPRRegClass);
215  addTypeForNEON(VT, MVT::f64, MVT::v2i32);
216 }
217 
218 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
219  addRegisterClass(VT, &ARM::DPairRegClass);
220  addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
221 }
222 
224  const ARMSubtarget &STI)
225  : TargetLowering(TM), Subtarget(&STI) {
226  RegInfo = Subtarget->getRegisterInfo();
227  Itins = Subtarget->getInstrItineraryData();
228 
231 
232  if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
233  !Subtarget->isTargetWatchOS()) {
234  bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
235  for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
236  setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
237  IsHFTarget ? CallingConv::ARM_AAPCS_VFP
239  }
240 
241  if (Subtarget->isTargetMachO()) {
242  // Uses VFP for Thumb libfuncs if available.
243  if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
244  Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
245  static const struct {
246  const RTLIB::Libcall Op;
247  const char * const Name;
248  const ISD::CondCode Cond;
249  } LibraryCalls[] = {
250  // Single-precision floating-point arithmetic.
251  { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
252  { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
253  { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
254  { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
255 
256  // Double-precision floating-point arithmetic.
257  { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
258  { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
259  { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
260  { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
261 
262  // Single-precision comparisons.
263  { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
264  { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
265  { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
266  { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
267  { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
268  { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
269  { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
270  { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
271 
272  // Double-precision comparisons.
273  { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
274  { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
275  { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
276  { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
277  { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
278  { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
279  { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
280  { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
281 
282  // Floating-point to integer conversions.
283  // i64 conversions are done via library routines even when generating VFP
284  // instructions, so use the same ones.
285  { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
286  { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
287  { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
288  { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
289 
290  // Conversions between floating types.
291  { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
292  { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
293 
294  // Integer to floating-point conversions.
295  // i64 conversions are done via library routines even when generating VFP
296  // instructions, so use the same ones.
297  // FIXME: There appears to be some naming inconsistency in ARM libgcc:
298  // e.g., __floatunsidf vs. __floatunssidfvfp.
299  { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
300  { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
301  { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
302  { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
303  };
304 
305  for (const auto &LC : LibraryCalls) {
306  setLibcallName(LC.Op, LC.Name);
307  if (LC.Cond != ISD::SETCC_INVALID)
308  setCmpLibcallCC(LC.Op, LC.Cond);
309  }
310  }
311  }
312 
313  // These libcalls are not available in 32-bit.
314  setLibcallName(RTLIB::SHL_I128, nullptr);
315  setLibcallName(RTLIB::SRL_I128, nullptr);
316  setLibcallName(RTLIB::SRA_I128, nullptr);
317 
318  // RTLIB
319  if (Subtarget->isAAPCS_ABI() &&
320  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
321  Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
322  static const struct {
323  const RTLIB::Libcall Op;
324  const char * const Name;
325  const CallingConv::ID CC;
326  const ISD::CondCode Cond;
327  } LibraryCalls[] = {
328  // Double-precision floating-point arithmetic helper functions
329  // RTABI chapter 4.1.2, Table 2
330  { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
331  { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332  { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333  { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334 
335  // Double-precision floating-point comparison helper functions
336  // RTABI chapter 4.1.2, Table 3
337  { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
338  { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
339  { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
340  { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
341  { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
342  { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
343  { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
344  { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
345 
346  // Single-precision floating-point arithmetic helper functions
347  // RTABI chapter 4.1.2, Table 4
348  { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
349  { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350  { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
351  { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
352 
353  // Single-precision floating-point comparison helper functions
354  // RTABI chapter 4.1.2, Table 5
355  { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
356  { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
357  { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
358  { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
359  { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
360  { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
361  { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
362  { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
363 
364  // Floating-point to integer conversions.
365  // RTABI chapter 4.1.2, Table 6
366  { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
367  { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
368  { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
369  { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
370  { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
371  { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
372  { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
373  { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
374 
375  // Conversions between floating types.
376  // RTABI chapter 4.1.2, Table 7
377  { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
378  { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
379  { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
380 
381  // Integer to floating-point conversions.
382  // RTABI chapter 4.1.2, Table 8
383  { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
384  { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
385  { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
386  { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
387  { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
388  { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
389  { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
390  { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
391 
392  // Long long helper functions
393  // RTABI chapter 4.2, Table 9
394  { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
395  { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
396  { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
397  { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
398 
399  // Integer division functions
400  // RTABI chapter 4.3.1
401  { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
402  { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
403  { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
404  { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
405  { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
406  { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
407  { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
408  { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
409  };
410 
411  for (const auto &LC : LibraryCalls) {
412  setLibcallName(LC.Op, LC.Name);
413  setLibcallCallingConv(LC.Op, LC.CC);
414  if (LC.Cond != ISD::SETCC_INVALID)
415  setCmpLibcallCC(LC.Op, LC.Cond);
416  }
417 
418  // EABI dependent RTLIB
419  if (TM.Options.EABIVersion == EABI::EABI4 ||
421  static const struct {
422  const RTLIB::Libcall Op;
423  const char *const Name;
424  const CallingConv::ID CC;
425  const ISD::CondCode Cond;
426  } MemOpsLibraryCalls[] = {
427  // Memory operations
428  // RTABI chapter 4.3.4
430  { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
431  { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
432  };
433 
434  for (const auto &LC : MemOpsLibraryCalls) {
435  setLibcallName(LC.Op, LC.Name);
436  setLibcallCallingConv(LC.Op, LC.CC);
437  if (LC.Cond != ISD::SETCC_INVALID)
438  setCmpLibcallCC(LC.Op, LC.Cond);
439  }
440  }
441  }
442 
443  if (Subtarget->isTargetWindows()) {
444  static const struct {
445  const RTLIB::Libcall Op;
446  const char * const Name;
447  const CallingConv::ID CC;
448  } LibraryCalls[] = {
449  { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
450  { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
451  { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
452  { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
453  { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
454  { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
455  { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
456  { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
457  };
458 
459  for (const auto &LC : LibraryCalls) {
460  setLibcallName(LC.Op, LC.Name);
461  setLibcallCallingConv(LC.Op, LC.CC);
462  }
463  }
464 
465  // Use divmod compiler-rt calls for iOS 5.0 and later.
466  if (Subtarget->isTargetMachO() &&
467  !(Subtarget->isTargetIOS() &&
468  Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
469  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
470  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
471  }
472 
473  // The half <-> float conversion functions are always soft-float on
474  // non-watchos platforms, but are needed for some targets which use a
475  // hard-float calling convention by default.
476  if (!Subtarget->isTargetWatchABI()) {
477  if (Subtarget->isAAPCS_ABI()) {
478  setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
479  setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
480  setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
481  } else {
482  setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
483  setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
484  setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
485  }
486  }
487 
488  // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
489  // a __gnu_ prefix (which is the default).
490  if (Subtarget->isTargetAEABI()) {
491  static const struct {
492  const RTLIB::Libcall Op;
493  const char * const Name;
494  const CallingConv::ID CC;
495  } LibraryCalls[] = {
496  { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
497  { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
498  { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
499  };
500 
501  for (const auto &LC : LibraryCalls) {
502  setLibcallName(LC.Op, LC.Name);
503  setLibcallCallingConv(LC.Op, LC.CC);
504  }
505  }
506 
507  if (Subtarget->isThumb1Only())
508  addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
509  else
510  addRegisterClass(MVT::i32, &ARM::GPRRegClass);
511 
512  if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
513  !Subtarget->isThumb1Only()) {
514  addRegisterClass(MVT::f32, &ARM::SPRRegClass);
515  addRegisterClass(MVT::f64, &ARM::DPRRegClass);
516  }
517 
518  if (Subtarget->hasFullFP16()) {
519  addRegisterClass(MVT::f16, &ARM::HPRRegClass);
523 
526  }
527 
528  for (MVT VT : MVT::vector_valuetypes()) {
529  for (MVT InnerVT : MVT::vector_valuetypes()) {
530  setTruncStoreAction(VT, InnerVT, Expand);
531  setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
532  setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
533  setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
534  }
535 
540 
542  }
543 
546 
549 
550  if (Subtarget->hasNEON()) {
551  addDRTypeForNEON(MVT::v2f32);
552  addDRTypeForNEON(MVT::v8i8);
553  addDRTypeForNEON(MVT::v4i16);
554  addDRTypeForNEON(MVT::v2i32);
555  addDRTypeForNEON(MVT::v1i64);
556 
557  addQRTypeForNEON(MVT::v4f32);
558  addQRTypeForNEON(MVT::v2f64);
559  addQRTypeForNEON(MVT::v16i8);
560  addQRTypeForNEON(MVT::v8i16);
561  addQRTypeForNEON(MVT::v4i32);
562  addQRTypeForNEON(MVT::v2i64);
563 
564  if (Subtarget->hasFullFP16()) {
565  addQRTypeForNEON(MVT::v8f16);
566  addDRTypeForNEON(MVT::v4f16);
567  }
568 
569  // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
570  // neither Neon nor VFP support any arithmetic operations on it.
571  // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
572  // supported for v4f32.
576  // FIXME: Code duplication: FDIV and FREM are expanded always, see
577  // ARMTargetLowering::addTypeForNEON method for details.
580  // FIXME: Create unittest.
581  // In another words, find a way when "copysign" appears in DAG with vector
582  // operands.
584  // FIXME: Code duplication: SETCC has custom operation action, see
585  // ARMTargetLowering::addTypeForNEON method for details.
587  // FIXME: Create unittest for FNEG and for FABS.
599  // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
606 
621 
622  // Mark v2f32 intrinsics.
637 
638  // Neon does not support some operations on v1i64 and v2i64 types.
640  // Custom handling for some quad-vector types to detect VMULL.
644  // Custom handling for some vector types to avoid expensive expansions
649  // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
650  // a destination type that is wider than the source, and nor does
651  // it have a FP_TO_[SU]INT instruction with a narrower destination than
652  // source.
661 
664 
665  // NEON does not have single instruction CTPOP for vectors with element
666  // types wider than 8-bits. However, custom lowering can leverage the
667  // v8i8/v16i8 vcnt instruction.
674 
677 
678  // NEON does not have single instruction CTTZ for vectors.
683 
688 
693 
698 
699  // NEON only has FMA instructions as of VFP4.
700  if (!Subtarget->hasVFP4()) {
703  }
704 
722 
723  // It is legal to extload from v4i8 to v4i16 or v4i32.
725  MVT::v2i32}) {
726  for (MVT VT : MVT::integer_vector_valuetypes()) {
730  }
731  }
732  }
733 
734  if (Subtarget->isFPOnlySP()) {
735  // When targeting a floating-point unit with only single-precision
736  // operations, f64 is legal for the few double-precision instructions which
737  // are present However, no double-precision operations other than moves,
738  // loads and stores are provided by the hardware.
771  }
772 
774 
775  // ARM does not have floating-point extending loads.
776  for (MVT VT : MVT::fp_valuetypes()) {
779  }
780 
781  // ... or truncating stores
785 
786  // ARM does not have i1 sign extending load.
787  for (MVT VT : MVT::integer_valuetypes())
789 
790  // ARM supports all 4 flavors of integer indexed load / store.
791  if (!Subtarget->isThumb1Only()) {
792  for (unsigned im = (unsigned)ISD::PRE_INC;
802  }
803  } else {
804  // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
807  }
808 
813 
816 
817  // i64 operation support.
820  if (Subtarget->isThumb1Only()) {
823  }
824  if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
825  || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
827 
834 
835  // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
836  if (Subtarget->isThumb1Only()) {
840  }
841 
842  if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
844 
845  // ARM does not have ROTL.
847  for (MVT VT : MVT::vector_valuetypes()) {
850  }
853  if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
856  }
857 
858  // @llvm.readcyclecounter requires the Performance Monitors extension.
859  // Default to the 0 expansion on unsupported platforms.
860  // FIXME: Technically there are older ARM CPUs that have
861  // implementation-specific ways of obtaining this information.
862  if (Subtarget->hasPerfMon())
864 
865  // Only ARMv6 has BSWAP.
866  if (!Subtarget->hasV6Ops())
868 
869  bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
870  : Subtarget->hasDivideInARMMode();
871  if (!hasDivide) {
872  // These are expanded into libcalls if the cpu doesn't have HW divider.
875  }
876 
877  if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
880 
883  }
884 
887 
888  // Register based DivRem for AEABI (RTABI 4.2)
889  if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
890  Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
891  Subtarget->isTargetWindows()) {
894  HasStandaloneRem = false;
895 
896  if (Subtarget->isTargetWindows()) {
897  const struct {
898  const RTLIB::Libcall Op;
899  const char * const Name;
900  const CallingConv::ID CC;
901  } LibraryCalls[] = {
902  { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
903  { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
904  { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
905  { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
906 
907  { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
908  { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
909  { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
910  { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
911  };
912 
913  for (const auto &LC : LibraryCalls) {
914  setLibcallName(LC.Op, LC.Name);
915  setLibcallCallingConv(LC.Op, LC.CC);
916  }
917  } else {
918  const struct {
919  const RTLIB::Libcall Op;
920  const char * const Name;
921  const CallingConv::ID CC;
922  } LibraryCalls[] = {
923  { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
924  { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
925  { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
926  { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
927 
928  { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
929  { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
930  { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
931  { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
932  };
933 
934  for (const auto &LC : LibraryCalls) {
935  setLibcallName(LC.Op, LC.Name);
936  setLibcallCallingConv(LC.Op, LC.CC);
937  }
938  }
939 
944  } else {
947  }
948 
949  if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
950  for (auto &VT : {MVT::f32, MVT::f64})
952 
957 
960 
961  // Use the default implementation.
968 
969  if (Subtarget->isTargetWindows())
971  else
973 
974  // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
975  // the default expansion.
976  InsertFencesForAtomic = false;
977  if (Subtarget->hasAnyDataBarrier() &&
978  (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
979  // ATOMIC_FENCE needs custom lowering; the others should have been expanded
980  // to ldrex/strex loops already.
982  if (!Subtarget->isThumb() || !Subtarget->isMClass())
984 
985  // On v8, we have particularly efficient implementations of atomic fences
986  // if they can be combined with nearby atomic loads and stores.
987  if (!Subtarget->hasAcquireRelease() ||
988  getTargetMachine().getOptLevel() == 0) {
989  // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
990  InsertFencesForAtomic = true;
991  }
992  } else {
993  // If there's anything we can use as a barrier, go through custom lowering
994  // for ATOMIC_FENCE.
995  // If target has DMB in thumb, Fences can be inserted.
996  if (Subtarget->hasDataBarrier())
997  InsertFencesForAtomic = true;
998 
1000  Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1001 
1002  // Set them all for expansion, which will force libcalls.
1015  // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1016  // Unordered/Monotonic case.
1017  if (!InsertFencesForAtomic) {
1020  }
1021  }
1022 
1024 
1025  // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1026  if (!Subtarget->hasV6Ops()) {
1029  }
1031 
1032  if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1033  !Subtarget->isThumb1Only()) {
1034  // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1035  // iff target supports vfp2.
1038  }
1039 
1040  // We want to custom lower some of our intrinsics.
1045  if (Subtarget->useSjLjEH())
1046  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1047 
1057  if (Subtarget->hasFullFP16()) {
1061  }
1062 
1064 
1067  if (Subtarget->hasFullFP16())
1072 
1073  // We don't support sin/cos/fmod/copysign/pow
1082  if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1083  !Subtarget->isThumb1Only()) {
1086  }
1089 
1090  if (!Subtarget->hasVFP4()) {
1093  }
1094 
1095  // Various VFP goodness
1096  if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1097  // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1098  if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
1101  }
1102 
1103  // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1104  if (!Subtarget->hasFP16()) {
1107  }
1108  }
1109 
1110  // Use __sincos_stret if available.
1111  if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1112  getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1115  }
1116 
1117  // FP-ARMv8 implements a lot of rounding-like FP operations.
1118  if (Subtarget->hasFPARMv8()) {
1131 
1132  if (!Subtarget->isFPOnlySP()) {
1141  }
1142  }
1143 
1144  if (Subtarget->hasNEON()) {
1145  // vmin and vmax aren't available in a scalar form, so we use
1146  // a NEON instruction with an undef lane instead.
1155 
1156  if (Subtarget->hasFullFP16()) {
1161 
1166  }
1167  }
1168 
1169  // We have target-specific dag combine patterns for the following nodes:
1170  // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1177 
1178  if (Subtarget->hasV6Ops())
1180 
1182 
1183  if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1184  !Subtarget->hasVFP2())
1186  else
1188 
1189  //// temporary - rewrite interface to use type
1190  MaxStoresPerMemset = 8;
1192  MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1194  MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1196 
1197  // On ARM arguments smaller than 4 bytes are extended, so all arguments
1198  // are at least 4 bytes aligned.
1200 
1201  // Prefer likely predicted branches to selects on out-of-order cores.
1202  PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1203 
1205 
1206  setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1207 }
1208 
1210  return Subtarget->useSoftFloat();
1211 }
1212 
1213 // FIXME: It might make sense to define the representative register class as the
1214 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1215 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1216 // SPR's representative would be DPR_VFP2. This should work well if register
1217 // pressure tracking were modified such that a register use would increment the
1218 // pressure of the register class's representative and all of it's super
1219 // classes' representatives transitively. We have not implemented this because
1220 // of the difficulty prior to coalescing of modeling operand register classes
1221 // due to the common occurrence of cross class copies and subregister insertions
1222 // and extractions.
1223 std::pair<const TargetRegisterClass *, uint8_t>
1225  MVT VT) const {
1226  const TargetRegisterClass *RRC = nullptr;
1227  uint8_t Cost = 1;
1228  switch (VT.SimpleTy) {
1229  default:
1231  // Use DPR as representative register class for all floating point
1232  // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1233  // the cost is 1 for both f32 and f64.
1234  case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1235  case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1236  RRC = &ARM::DPRRegClass;
1237  // When NEON is used for SP, only half of the register file is available
1238  // because operations that define both SP and DP results will be constrained
1239  // to the VFP2 class (D0-D15). We currently model this constraint prior to
1240  // coalescing by double-counting the SP regs. See the FIXME above.
1241  if (Subtarget->useNEONForSinglePrecisionFP())
1242  Cost = 2;
1243  break;
1244  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1245  case MVT::v4f32: case MVT::v2f64:
1246  RRC = &ARM::DPRRegClass;
1247  Cost = 2;
1248  break;
1249  case MVT::v4i64:
1250  RRC = &ARM::DPRRegClass;
1251  Cost = 4;
1252  break;
1253  case MVT::v8i64:
1254  RRC = &ARM::DPRRegClass;
1255  Cost = 8;
1256  break;
1257  }
1258  return std::make_pair(RRC, Cost);
1259 }
1260 
1261 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1262  switch ((ARMISD::NodeType)Opcode) {
1263  case ARMISD::FIRST_NUMBER: break;
1264  case ARMISD::Wrapper: return "ARMISD::Wrapper";
1265  case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1266  case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1267  case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1268  case ARMISD::CALL: return "ARMISD::CALL";
1269  case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1270  case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1271  case ARMISD::BRCOND: return "ARMISD::BRCOND";
1272  case ARMISD::BR_JT: return "ARMISD::BR_JT";
1273  case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1274  case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1275  case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1276  case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1277  case ARMISD::CMP: return "ARMISD::CMP";
1278  case ARMISD::CMN: return "ARMISD::CMN";
1279  case ARMISD::CMPZ: return "ARMISD::CMPZ";
1280  case ARMISD::CMPFP: return "ARMISD::CMPFP";
1281  case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1282  case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1283  case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1284 
1285  case ARMISD::CMOV: return "ARMISD::CMOV";
1286  case ARMISD::SUBS: return "ARMISD::SUBS";
1287 
1288  case ARMISD::SSAT: return "ARMISD::SSAT";
1289  case ARMISD::USAT: return "ARMISD::USAT";
1290 
1291  case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1292  case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1293  case ARMISD::RRX: return "ARMISD::RRX";
1294 
1295  case ARMISD::ADDC: return "ARMISD::ADDC";
1296  case ARMISD::ADDE: return "ARMISD::ADDE";
1297  case ARMISD::SUBC: return "ARMISD::SUBC";
1298  case ARMISD::SUBE: return "ARMISD::SUBE";
1299 
1300  case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1301  case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1302  case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1303  case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1304  case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1305 
1306  case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1307  case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1308  case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1309 
1310  case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1311 
1312  case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1313 
1314  case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1315 
1316  case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1317 
1318  case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1319 
1320  case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1321  case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1322 
1323  case ARMISD::VCEQ: return "ARMISD::VCEQ";
1324  case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1325  case ARMISD::VCGE: return "ARMISD::VCGE";
1326  case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1327  case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1328  case ARMISD::VCGEU: return "ARMISD::VCGEU";
1329  case ARMISD::VCGT: return "ARMISD::VCGT";
1330  case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1331  case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1332  case ARMISD::VCGTU: return "ARMISD::VCGTU";
1333  case ARMISD::VTST: return "ARMISD::VTST";
1334 
1335  case ARMISD::VSHL: return "ARMISD::VSHL";
1336  case ARMISD::VSHRs: return "ARMISD::VSHRs";
1337  case ARMISD::VSHRu: return "ARMISD::VSHRu";
1338  case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1339  case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1340  case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1341  case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1342  case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1343  case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1344  case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1345  case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1346  case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1347  case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1348  case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1349  case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1350  case ARMISD::VSLI: return "ARMISD::VSLI";
1351  case ARMISD::VSRI: return "ARMISD::VSRI";
1352  case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1353  case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1354  case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1355  case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1356  case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1357  case ARMISD::VDUP: return "ARMISD::VDUP";
1358  case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1359  case ARMISD::VEXT: return "ARMISD::VEXT";
1360  case ARMISD::VREV64: return "ARMISD::VREV64";
1361  case ARMISD::VREV32: return "ARMISD::VREV32";
1362  case ARMISD::VREV16: return "ARMISD::VREV16";
1363  case ARMISD::VZIP: return "ARMISD::VZIP";
1364  case ARMISD::VUZP: return "ARMISD::VUZP";
1365  case ARMISD::VTRN: return "ARMISD::VTRN";
1366  case ARMISD::VTBL1: return "ARMISD::VTBL1";
1367  case ARMISD::VTBL2: return "ARMISD::VTBL2";
1368  case ARMISD::VMULLs: return "ARMISD::VMULLs";
1369  case ARMISD::VMULLu: return "ARMISD::VMULLu";
1370  case ARMISD::UMAAL: return "ARMISD::UMAAL";
1371  case ARMISD::UMLAL: return "ARMISD::UMLAL";
1372  case ARMISD::SMLAL: return "ARMISD::SMLAL";
1373  case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1374  case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1375  case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1376  case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1377  case ARMISD::SMULWB: return "ARMISD::SMULWB";
1378  case ARMISD::SMULWT: return "ARMISD::SMULWT";
1379  case ARMISD::SMLALD: return "ARMISD::SMLALD";
1380  case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1381  case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1382  case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1383  case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1384  case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1385  case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1386  case ARMISD::BFI: return "ARMISD::BFI";
1387  case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1388  case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1389  case ARMISD::VBSL: return "ARMISD::VBSL";
1390  case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1391  case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1392  case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1393  case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1394  case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1395  case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1396  case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1397  case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1398  case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1399  case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1400  case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1401  case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1402  case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1403  case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1404  case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1405  case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1406  case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1407  case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1408  case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1409  case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1410  case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1411  case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1412  case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1413  }
1414  return nullptr;
1415 }
1416 
1418  EVT VT) const {
1419  if (!VT.isVector())
1420  return getPointerTy(DL);
1422 }
1423 
1424 /// getRegClassFor - Return the register class that should be used for the
1425 /// specified value type.
1427  // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1428  // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1429  // load / store 4 to 8 consecutive D registers.
1430  if (Subtarget->hasNEON()) {
1431  if (VT == MVT::v4i64)
1432  return &ARM::QQPRRegClass;
1433  if (VT == MVT::v8i64)
1434  return &ARM::QQQQPRRegClass;
1435  }
1436  return TargetLowering::getRegClassFor(VT);
1437 }
1438 
1439 // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1440 // source/dest is aligned and the copy size is large enough. We therefore want
1441 // to align such objects passed to memory intrinsics.
1443  unsigned &PrefAlign) const {
1444  if (!isa<MemIntrinsic>(CI))
1445  return false;
1446  MinSize = 8;
1447  // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1448  // cycle faster than 4-byte aligned LDM.
1449  PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1450  return true;
1451 }
1452 
1453 // Create a fast isel object.
1454 FastISel *
1456  const TargetLibraryInfo *libInfo) const {
1457  return ARM::createFastISel(funcInfo, libInfo);
1458 }
1459 
1461  unsigned NumVals = N->getNumValues();
1462  if (!NumVals)
1463  return Sched::RegPressure;
1464 
1465  for (unsigned i = 0; i != NumVals; ++i) {
1466  EVT VT = N->getValueType(i);
1467  if (VT == MVT::Glue || VT == MVT::Other)
1468  continue;
1469  if (VT.isFloatingPoint() || VT.isVector())
1470  return Sched::ILP;
1471  }
1472 
1473  if (!N->isMachineOpcode())
1474  return Sched::RegPressure;
1475 
1476  // Load are scheduled for latency even if there instruction itinerary
1477  // is not available.
1478  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1479  const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1480 
1481  if (MCID.getNumDefs() == 0)
1482  return Sched::RegPressure;
1483  if (!Itins->isEmpty() &&
1484  Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1485  return Sched::ILP;
1486 
1487  return Sched::RegPressure;
1488 }
1489 
1490 //===----------------------------------------------------------------------===//
1491 // Lowering Code
1492 //===----------------------------------------------------------------------===//
1493 
1494 static bool isSRL16(const SDValue &Op) {
1495  if (Op.getOpcode() != ISD::SRL)
1496  return false;
1497  if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1498  return Const->getZExtValue() == 16;
1499  return false;
1500 }
1501 
1502 static bool isSRA16(const SDValue &Op) {
1503  if (Op.getOpcode() != ISD::SRA)
1504  return false;
1505  if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1506  return Const->getZExtValue() == 16;
1507  return false;
1508 }
1509 
1510 static bool isSHL16(const SDValue &Op) {
1511  if (Op.getOpcode() != ISD::SHL)
1512  return false;
1513  if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1514  return Const->getZExtValue() == 16;
1515  return false;
1516 }
1517 
1518 // Check for a signed 16-bit value. We special case SRA because it makes it
1519 // more simple when also looking for SRAs that aren't sign extending a
1520 // smaller value. Without the check, we'd need to take extra care with
1521 // checking order for some operations.
1522 static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1523  if (isSRA16(Op))
1524  return isSHL16(Op.getOperand(0));
1525  return DAG.ComputeNumSignBits(Op) == 17;
1526 }
1527 
1528 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1530  switch (CC) {
1531  default: llvm_unreachable("Unknown condition code!");
1532  case ISD::SETNE: return ARMCC::NE;
1533  case ISD::SETEQ: return ARMCC::EQ;
1534  case ISD::SETGT: return ARMCC::GT;
1535  case ISD::SETGE: return ARMCC::GE;
1536  case ISD::SETLT: return ARMCC::LT;
1537  case ISD::SETLE: return ARMCC::LE;
1538  case ISD::SETUGT: return ARMCC::HI;
1539  case ISD::SETUGE: return ARMCC::HS;
1540  case ISD::SETULT: return ARMCC::LO;
1541  case ISD::SETULE: return ARMCC::LS;
1542  }
1543 }
1544 
1545 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1547  ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
1548  CondCode2 = ARMCC::AL;
1549  InvalidOnQNaN = true;
1550  switch (CC) {
1551  default: llvm_unreachable("Unknown FP condition!");
1552  case ISD::SETEQ:
1553  case ISD::SETOEQ:
1554  CondCode = ARMCC::EQ;
1555  InvalidOnQNaN = false;
1556  break;
1557  case ISD::SETGT:
1558  case ISD::SETOGT: CondCode = ARMCC::GT; break;
1559  case ISD::SETGE:
1560  case ISD::SETOGE: CondCode = ARMCC::GE; break;
1561  case ISD::SETOLT: CondCode = ARMCC::MI; break;
1562  case ISD::SETOLE: CondCode = ARMCC::LS; break;
1563  case ISD::SETONE:
1564  CondCode = ARMCC::MI;
1565  CondCode2 = ARMCC::GT;
1566  InvalidOnQNaN = false;
1567  break;
1568  case ISD::SETO: CondCode = ARMCC::VC; break;
1569  case ISD::SETUO: CondCode = ARMCC::VS; break;
1570  case ISD::SETUEQ:
1571  CondCode = ARMCC::EQ;
1572  CondCode2 = ARMCC::VS;
1573  InvalidOnQNaN = false;
1574  break;
1575  case ISD::SETUGT: CondCode = ARMCC::HI; break;
1576  case ISD::SETUGE: CondCode = ARMCC::PL; break;
1577  case ISD::SETLT:
1578  case ISD::SETULT: CondCode = ARMCC::LT; break;
1579  case ISD::SETLE:
1580  case ISD::SETULE: CondCode = ARMCC::LE; break;
1581  case ISD::SETNE:
1582  case ISD::SETUNE:
1583  CondCode = ARMCC::NE;
1584  InvalidOnQNaN = false;
1585  break;
1586  }
1587 }
1588 
1589 //===----------------------------------------------------------------------===//
1590 // Calling Convention Implementation
1591 //===----------------------------------------------------------------------===//
1592 
1593 #include "ARMGenCallingConv.inc"
1594 
1595 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1596 /// account presence of floating point hardware and calling convention
1597 /// limitations, such as support for variadic functions.
1599 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1600  bool isVarArg) const {
1601  switch (CC) {
1602  default:
1603  report_fatal_error("Unsupported calling convention");
1605  case CallingConv::ARM_APCS:
1606  case CallingConv::GHC:
1607  return CC;
1611  case CallingConv::Swift:
1613  case CallingConv::C:
1614  if (!Subtarget->isAAPCS_ABI())
1615  return CallingConv::ARM_APCS;
1616  else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1618  !isVarArg)
1620  else
1621  return CallingConv::ARM_AAPCS;
1622  case CallingConv::Fast:
1624  if (!Subtarget->isAAPCS_ABI()) {
1625  if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1626  return CallingConv::Fast;
1627  return CallingConv::ARM_APCS;
1628  } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1630  else
1631  return CallingConv::ARM_AAPCS;
1632  }
1633 }
1634 
1636  bool isVarArg) const {
1637  return CCAssignFnForNode(CC, false, isVarArg);
1638 }
1639 
1641  bool isVarArg) const {
1642  return CCAssignFnForNode(CC, true, isVarArg);
1643 }
1644 
1645 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1646 /// CallingConvention.
1647 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1648  bool Return,
1649  bool isVarArg) const {
1650  switch (getEffectiveCallingConv(CC, isVarArg)) {
1651  default:
1652  report_fatal_error("Unsupported calling convention");
1653  case CallingConv::ARM_APCS:
1654  return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1656  return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1658  return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1659  case CallingConv::Fast:
1660  return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1661  case CallingConv::GHC:
1662  return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1664  return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1665  }
1666 }
1667 
1668 /// LowerCallResult - Lower the result values of a call into the
1669 /// appropriate copies out of appropriate physical registers.
1670 SDValue ARMTargetLowering::LowerCallResult(
1671  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1672  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1673  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1674  SDValue ThisVal) const {
1675  // Assign locations to each value returned by this call.
1677  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1678  *DAG.getContext());
1679  CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1680 
1681  // Copy all of the result registers out of their specified physreg.
1682  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1683  CCValAssign VA = RVLocs[i];
1684 
1685  // Pass 'this' value directly from the argument to return value, to avoid
1686  // reg unit interference
1687  if (i == 0 && isThisReturn) {
1688  assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1689  "unexpected return calling convention register assignment");
1690  InVals.push_back(ThisVal);
1691  continue;
1692  }
1693 
1694  SDValue Val;
1695  if (VA.needsCustom()) {
1696  // Handle f64 or half of a v2f64.
1697  SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1698  InFlag);
1699  Chain = Lo.getValue(1);
1700  InFlag = Lo.getValue(2);
1701  VA = RVLocs[++i]; // skip ahead to next loc
1702  SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1703  InFlag);
1704  Chain = Hi.getValue(1);
1705  InFlag = Hi.getValue(2);
1706  if (!Subtarget->isLittle())
1707  std::swap (Lo, Hi);
1708  Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1709 
1710  if (VA.getLocVT() == MVT::v2f64) {
1711  SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1712  Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1713  DAG.getConstant(0, dl, MVT::i32));
1714 
1715  VA = RVLocs[++i]; // skip ahead to next loc
1716  Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1717  Chain = Lo.getValue(1);
1718  InFlag = Lo.getValue(2);
1719  VA = RVLocs[++i]; // skip ahead to next loc
1720  Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1721  Chain = Hi.getValue(1);
1722  InFlag = Hi.getValue(2);
1723  if (!Subtarget->isLittle())
1724  std::swap (Lo, Hi);
1725  Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1726  Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1727  DAG.getConstant(1, dl, MVT::i32));
1728  }
1729  } else {
1730  Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1731  InFlag);
1732  Chain = Val.getValue(1);
1733  InFlag = Val.getValue(2);
1734  }
1735 
1736  switch (VA.getLocInfo()) {
1737  default: llvm_unreachable("Unknown loc info!");
1738  case CCValAssign::Full: break;
1739  case CCValAssign::BCvt:
1740  Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1741  break;
1742  }
1743 
1744  InVals.push_back(Val);
1745  }
1746 
1747  return Chain;
1748 }
1749 
1750 /// LowerMemOpCallTo - Store the argument to the stack.
1751 SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1752  SDValue Arg, const SDLoc &dl,
1753  SelectionDAG &DAG,
1754  const CCValAssign &VA,
1755  ISD::ArgFlagsTy Flags) const {
1756  unsigned LocMemOffset = VA.getLocMemOffset();
1757  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1758  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1759  StackPtr, PtrOff);
1760  return DAG.getStore(
1761  Chain, dl, Arg, PtrOff,
1762  MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
1763 }
1764 
1765 void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
1766  SDValue Chain, SDValue &Arg,
1767  RegsToPassVector &RegsToPass,
1768  CCValAssign &VA, CCValAssign &NextVA,
1769  SDValue &StackPtr,
1770  SmallVectorImpl<SDValue> &MemOpChains,
1771  ISD::ArgFlagsTy Flags) const {
1772  SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1773  DAG.getVTList(MVT::i32, MVT::i32), Arg);
1774  unsigned id = Subtarget->isLittle() ? 0 : 1;
1775  RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1776 
1777  if (NextVA.isRegLoc())
1778  RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1779  else {
1780  assert(NextVA.isMemLoc());
1781  if (!StackPtr.getNode())
1782  StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1783  getPointerTy(DAG.getDataLayout()));
1784 
1785  MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1786  dl, DAG, NextVA,
1787  Flags));
1788  }
1789 }
1790 
1791 /// LowerCall - Lowering a call into a callseq_start <-
1792 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1793 /// nodes.
1794 SDValue
1795 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1796  SmallVectorImpl<SDValue> &InVals) const {
1797  SelectionDAG &DAG = CLI.DAG;
1798  SDLoc &dl = CLI.DL;
1800  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1802  SDValue Chain = CLI.Chain;
1803  SDValue Callee = CLI.Callee;
1804  bool &isTailCall = CLI.IsTailCall;
1805  CallingConv::ID CallConv = CLI.CallConv;
1806  bool doesNotRet = CLI.DoesNotReturn;
1807  bool isVarArg = CLI.IsVarArg;
1808 
1809  MachineFunction &MF = DAG.getMachineFunction();
1810  bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1811  bool isThisReturn = false;
1812  bool isSibCall = false;
1813  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
1814 
1815  // Disable tail calls if they're not supported.
1816  if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1817  isTailCall = false;
1818 
1819  if (isTailCall) {
1820  // Check if it's really possible to do a tail call.
1821  isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1822  isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(),
1823  Outs, OutVals, Ins, DAG);
1824  if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
1825  report_fatal_error("failed to perform tail call elimination on a call "
1826  "site marked musttail");
1827  // We don't support GuaranteedTailCallOpt for ARM, only automatically
1828  // detected sibcalls.
1829  if (isTailCall) {
1830  ++NumTailCalls;
1831  isSibCall = true;
1832  }
1833  }
1834 
1835  // Analyze operands of the call, assigning locations to each operand.
1837  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1838  *DAG.getContext());
1839  CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
1840 
1841  // Get a count of how many bytes are to be pushed on the stack.
1842  unsigned NumBytes = CCInfo.getNextStackOffset();
1843 
1844  // For tail calls, memory operands are available in our caller's stack.
1845  if (isSibCall)
1846  NumBytes = 0;
1847 
1848  // Adjust the stack pointer for the new arguments...
1849  // These operations are automatically eliminated by the prolog/epilog pass
1850  if (!isSibCall)
1851  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1852 
1853  SDValue StackPtr =
1854  DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1855 
1856  RegsToPassVector RegsToPass;
1857  SmallVector<SDValue, 8> MemOpChains;
1858 
1859  // Walk the register/memloc assignments, inserting copies/loads. In the case
1860  // of tail call optimization, arguments are handled later.
1861  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1862  i != e;
1863  ++i, ++realArgIdx) {
1864  CCValAssign &VA = ArgLocs[i];
1865  SDValue Arg = OutVals[realArgIdx];
1866  ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1867  bool isByVal = Flags.isByVal();
1868 
1869  // Promote the value if needed.
1870  switch (VA.getLocInfo()) {
1871  default: llvm_unreachable("Unknown loc info!");
1872  case CCValAssign::Full: break;
1873  case CCValAssign::SExt:
1874  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1875  break;
1876  case CCValAssign::ZExt:
1877  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1878  break;
1879  case CCValAssign::AExt:
1880  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1881  break;
1882  case CCValAssign::BCvt:
1883  Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1884  break;
1885  }
1886 
1887  // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1888  if (VA.needsCustom()) {
1889  if (VA.getLocVT() == MVT::v2f64) {
1890  SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1891  DAG.getConstant(0, dl, MVT::i32));
1892  SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1893  DAG.getConstant(1, dl, MVT::i32));
1894 
1895  PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1896  VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1897 
1898  VA = ArgLocs[++i]; // skip ahead to next loc
1899  if (VA.isRegLoc()) {
1900  PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1901  VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1902  } else {
1903  assert(VA.isMemLoc());
1904 
1905  MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1906  dl, DAG, VA, Flags));
1907  }
1908  } else {
1909  PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1910  StackPtr, MemOpChains, Flags);
1911  }
1912  } else if (VA.isRegLoc()) {
1913  if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
1914  Outs[0].VT == MVT::i32) {
1915  assert(VA.getLocVT() == MVT::i32 &&
1916  "unexpected calling convention register assignment");
1917  assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1918  "unexpected use of 'returned'");
1919  isThisReturn = true;
1920  }
1921  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1922  } else if (isByVal) {
1923  assert(VA.isMemLoc());
1924  unsigned offset = 0;
1925 
1926  // True if this byval aggregate will be split between registers
1927  // and memory.
1928  unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1929  unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1930 
1931  if (CurByValIdx < ByValArgsCount) {
1932 
1933  unsigned RegBegin, RegEnd;
1934  CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1935 
1936  EVT PtrVT =
1938  unsigned int i, j;
1939  for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1940  SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1941  SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1942  SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1944  DAG.InferPtrAlignment(AddArg));
1945  MemOpChains.push_back(Load.getValue(1));
1946  RegsToPass.push_back(std::make_pair(j, Load));
1947  }
1948 
1949  // If parameter size outsides register area, "offset" value
1950  // helps us to calculate stack slot for remained part properly.
1951  offset = RegEnd - RegBegin;
1952 
1953  CCInfo.nextInRegsParam();
1954  }
1955 
1956  if (Flags.getByValSize() > 4*offset) {
1957  auto PtrVT = getPointerTy(DAG.getDataLayout());
1958  unsigned LocMemOffset = VA.getLocMemOffset();
1959  SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1960  SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1961  SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1962  SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1963  SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1964  MVT::i32);
1965  SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1966  MVT::i32);
1967 
1968  SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1969  SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1970  MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1971  Ops));
1972  }
1973  } else if (!isSibCall) {
1974  assert(VA.isMemLoc());
1975 
1976  MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1977  dl, DAG, VA, Flags));
1978  }
1979  }
1980 
1981  if (!MemOpChains.empty())
1982  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1983 
1984  // Build a sequence of copy-to-reg nodes chained together with token chain
1985  // and flag operands which copy the outgoing args into the appropriate regs.
1986  SDValue InFlag;
1987  // Tail call byval lowering might overwrite argument registers so in case of
1988  // tail call optimization the copies to registers are lowered later.
1989  if (!isTailCall)
1990  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1991  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1992  RegsToPass[i].second, InFlag);
1993  InFlag = Chain.getValue(1);
1994  }
1995 
1996  // For tail calls lower the arguments to the 'real' stack slot.
1997  if (isTailCall) {
1998  // Force all the incoming stack arguments to be loaded from the stack
1999  // before any new outgoing arguments are stored to the stack, because the
2000  // outgoing stack slots may alias the incoming argument stack slots, and
2001  // the alias isn't otherwise explicit. This is slightly more conservative
2002  // than necessary, because it means that each store effectively depends
2003  // on every argument instead of just those arguments it would clobber.
2004 
2005  // Do not flag preceding copytoreg stuff together with the following stuff.
2006  InFlag = SDValue();
2007  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2008  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2009  RegsToPass[i].second, InFlag);
2010  InFlag = Chain.getValue(1);
2011  }
2012  InFlag = SDValue();
2013  }
2014 
2015  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2016  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2017  // node so that legalize doesn't hack it.
2018  bool isDirect = false;
2019 
2020  const TargetMachine &TM = getTargetMachine();
2021  const Module *Mod = MF.getFunction().getParent();
2022  const GlobalValue *GV = nullptr;
2023  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2024  GV = G->getGlobal();
2025  bool isStub =
2026  !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2027 
2028  bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2029  bool isLocalARMFunc = false;
2031  auto PtrVt = getPointerTy(DAG.getDataLayout());
2032 
2033  if (Subtarget->genLongCalls()) {
2034  assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&
2035  "long-calls codegen is not position independent!");
2036  // Handle a global address or an external symbol. If it's not one of
2037  // those, the target's already in a register, so we don't need to do
2038  // anything extra.
2039  if (isa<GlobalAddressSDNode>(Callee)) {
2040  // Create a constant pool entry for the callee address
2041  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2042  ARMConstantPoolValue *CPV =
2043  ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2044 
2045  // Get the address of the callee into a register
2046  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2047  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2048  Callee = DAG.getLoad(
2049  PtrVt, dl, DAG.getEntryNode(), CPAddr,
2051  } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2052  const char *Sym = S->getSymbol();
2053 
2054  // Create a constant pool entry for the callee address
2055  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2056  ARMConstantPoolValue *CPV =
2058  ARMPCLabelIndex, 0);
2059  // Get the address of the callee into a register
2060  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2061  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2062  Callee = DAG.getLoad(
2063  PtrVt, dl, DAG.getEntryNode(), CPAddr,
2065  }
2066  } else if (isa<GlobalAddressSDNode>(Callee)) {
2067  // If we're optimizing for minimum size and the function is called three or
2068  // more times in this block, we can improve codesize by calling indirectly
2069  // as BLXr has a 16-bit encoding.
2070  auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2071  auto *BB = CLI.CS.getParent();
2072  bool PreferIndirect =
2073  Subtarget->isThumb() && MF.getFunction().optForMinSize() &&
2074  count_if(GV->users(), [&BB](const User *U) {
2075  return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
2076  }) > 2;
2077 
2078  if (!PreferIndirect) {
2079  isDirect = true;
2080  bool isDef = GV->isStrongDefinitionForLinker();
2081 
2082  // ARM call to a local ARM function is predicable.
2083  isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2084  // tBX takes a register source operand.
2085  if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2086  assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
2087  Callee = DAG.getNode(
2088  ARMISD::WrapperPIC, dl, PtrVt,
2089  DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2090  Callee = DAG.getLoad(
2091  PtrVt, dl, DAG.getEntryNode(), Callee,
2093  /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2095  } else if (Subtarget->isTargetCOFF()) {
2096  assert(Subtarget->isTargetWindows() &&
2097  "Windows is the only supported COFF target");
2098  unsigned TargetFlags = GV->hasDLLImportStorageClass()
2101  Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
2102  TargetFlags);
2103  if (GV->hasDLLImportStorageClass())
2104  Callee =
2105  DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2106  DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2108  } else {
2109  Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2110  }
2111  }
2112  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2113  isDirect = true;
2114  // tBX takes a register source operand.
2115  const char *Sym = S->getSymbol();
2116  if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2117  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2118  ARMConstantPoolValue *CPV =
2120  ARMPCLabelIndex, 4);
2121  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2122  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2123  Callee = DAG.getLoad(
2124  PtrVt, dl, DAG.getEntryNode(), CPAddr,
2126  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2127  Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2128  } else {
2129  Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2130  }
2131  }
2132 
2133  // FIXME: handle tail calls differently.
2134  unsigned CallOpc;
2135  if (Subtarget->isThumb()) {
2136  if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2137  CallOpc = ARMISD::CALL_NOLINK;
2138  else
2139  CallOpc = ARMISD::CALL;
2140  } else {
2141  if (!isDirect && !Subtarget->hasV5TOps())
2142  CallOpc = ARMISD::CALL_NOLINK;
2143  else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2144  // Emit regular call when code size is the priority
2145  !MF.getFunction().optForMinSize())
2146  // "mov lr, pc; b _foo" to avoid confusing the RSP
2147  CallOpc = ARMISD::CALL_NOLINK;
2148  else
2149  CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2150  }
2151 
2152  std::vector<SDValue> Ops;
2153  Ops.push_back(Chain);
2154  Ops.push_back(Callee);
2155 
2156  // Add argument registers to the end of the list so that they are known live
2157  // into the call.
2158  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2159  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2160  RegsToPass[i].second.getValueType()));
2161 
2162  // Add a register mask operand representing the call-preserved registers.
2163  if (!isTailCall) {
2164  const uint32_t *Mask;
2165  const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2166  if (isThisReturn) {
2167  // For 'this' returns, use the R0-preserving mask if applicable
2168  Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2169  if (!Mask) {
2170  // Set isThisReturn to false if the calling convention is not one that
2171  // allows 'returned' to be modeled in this way, so LowerCallResult does
2172  // not try to pass 'this' straight through
2173  isThisReturn = false;
2174  Mask = ARI->getCallPreservedMask(MF, CallConv);
2175  }
2176  } else
2177  Mask = ARI->getCallPreservedMask(MF, CallConv);
2178 
2179  assert(Mask && "Missing call preserved mask for calling convention");
2180  Ops.push_back(DAG.getRegisterMask(Mask));
2181  }
2182 
2183  if (InFlag.getNode())
2184  Ops.push_back(InFlag);
2185 
2186  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2187  if (isTailCall) {
2189  return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2190  }
2191 
2192  // Returns a chain and a flag for retval copy to use.
2193  Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2194  InFlag = Chain.getValue(1);
2195 
2196  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2197  DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2198  if (!Ins.empty())
2199  InFlag = Chain.getValue(1);
2200 
2201  // Handle result values, copying them out of physregs into vregs that we
2202  // return.
2203  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2204  InVals, isThisReturn,
2205  isThisReturn ? OutVals[0] : SDValue());
2206 }
2207 
2208 /// HandleByVal - Every parameter *after* a byval parameter is passed
2209 /// on the stack. Remember the next parameter register to allocate,
2210 /// and then confiscate the rest of the parameter registers to insure
2211 /// this.
2212 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2213  unsigned Align) const {
2214  // Byval (as with any stack) slots are always at least 4 byte aligned.
2215  Align = std::max(Align, 4U);
2216 
2217  unsigned Reg = State->AllocateReg(GPRArgRegs);
2218  if (!Reg)
2219  return;
2220 
2221  unsigned AlignInRegs = Align / 4;
2222  unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2223  for (unsigned i = 0; i < Waste; ++i)
2224  Reg = State->AllocateReg(GPRArgRegs);
2225 
2226  if (!Reg)
2227  return;
2228 
2229  unsigned Excess = 4 * (ARM::R4 - Reg);
2230 
2231  // Special case when NSAA != SP and parameter size greater than size of
2232  // all remained GPR regs. In that case we can't split parameter, we must
2233  // send it to stack. We also must set NCRN to R4, so waste all
2234  // remained registers.
2235  const unsigned NSAAOffset = State->getNextStackOffset();
2236  if (NSAAOffset != 0 && Size > Excess) {
2237  while (State->AllocateReg(GPRArgRegs))
2238  ;
2239  return;
2240  }
2241 
2242  // First register for byval parameter is the first register that wasn't
2243  // allocated before this method call, so it would be "reg".
2244  // If parameter is small enough to be saved in range [reg, r4), then
2245  // the end (first after last) register would be reg + param-size-in-regs,
2246  // else parameter would be splitted between registers and stack,
2247  // end register would be r4 in this case.
2248  unsigned ByValRegBegin = Reg;
2249  unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2250  State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2251  // Note, first register is allocated in the beginning of function already,
2252  // allocate remained amount of registers we need.
2253  for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2254  State->AllocateReg(GPRArgRegs);
2255  // A byval parameter that is split between registers and memory needs its
2256  // size truncated here.
2257  // In the case where the entire structure fits in registers, we set the
2258  // size in memory to zero.
2259  Size = std::max<int>(Size - Excess, 0);
2260 }
2261 
2262 /// MatchingStackOffset - Return true if the given stack call argument is
2263 /// already available in the same position (relatively) of the caller's
2264 /// incoming argument stack.
2265 static
2268  const TargetInstrInfo *TII) {
2269  unsigned Bytes = Arg.getValueSizeInBits() / 8;
2270  int FI = std::numeric_limits<int>::max();
2271  if (Arg.getOpcode() == ISD::CopyFromReg) {
2272  unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2274  return false;
2275  MachineInstr *Def = MRI->getVRegDef(VR);
2276  if (!Def)
2277  return false;
2278  if (!Flags.isByVal()) {
2279  if (!TII->isLoadFromStackSlot(*Def, FI))
2280  return false;
2281  } else {
2282  return false;
2283  }
2284  } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2285  if (Flags.isByVal())
2286  // ByVal argument is passed in as a pointer but it's now being
2287  // dereferenced. e.g.
2288  // define @foo(%struct.X* %A) {
2289  // tail call @bar(%struct.X* byval %A)
2290  // }
2291  return false;
2292  SDValue Ptr = Ld->getBasePtr();
2293  FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2294  if (!FINode)
2295  return false;
2296  FI = FINode->getIndex();
2297  } else
2298  return false;
2299 
2301  if (!MFI.isFixedObjectIndex(FI))
2302  return false;
2303  return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2304 }
2305 
2306 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2307 /// for tail call optimization. Targets which want to do tail call
2308 /// optimization should implement this function.
2309 bool
2310 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2311  CallingConv::ID CalleeCC,
2312  bool isVarArg,
2313  bool isCalleeStructRet,
2314  bool isCallerStructRet,
2315  const SmallVectorImpl<ISD::OutputArg> &Outs,
2316  const SmallVectorImpl<SDValue> &OutVals,
2317  const SmallVectorImpl<ISD::InputArg> &Ins,
2318  SelectionDAG& DAG) const {
2319  MachineFunction &MF = DAG.getMachineFunction();
2320  const Function &CallerF = MF.getFunction();
2321  CallingConv::ID CallerCC = CallerF.getCallingConv();
2322 
2323  assert(Subtarget->supportsTailCall());
2324 
2325  // Tail calls to function pointers cannot be optimized for Thumb1 if the args
2326  // to the call take up r0-r3. The reason is that there are no legal registers
2327  // left to hold the pointer to the function to be called.
2328  if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2329  !isa<GlobalAddressSDNode>(Callee.getNode()))
2330  return false;
2331 
2332  // Look for obvious safe cases to perform tail call optimization that do not
2333  // require ABI changes. This is what gcc calls sibcall.
2334 
2335  // Exception-handling functions need a special set of instructions to indicate
2336  // a return to the hardware. Tail-calling another function would probably
2337  // break this.
2338  if (CallerF.hasFnAttribute("interrupt"))
2339  return false;
2340 
2341  // Also avoid sibcall optimization if either caller or callee uses struct
2342  // return semantics.
2343  if (isCalleeStructRet || isCallerStructRet)
2344  return false;
2345 
2346  // Externally-defined functions with weak linkage should not be
2347  // tail-called on ARM when the OS does not support dynamic
2348  // pre-emption of symbols, as the AAELF spec requires normal calls
2349  // to undefined weak functions to be replaced with a NOP or jump to the
2350  // next instruction. The behaviour of branch instructions in this
2351  // situation (as used for tail calls) is implementation-defined, so we
2352  // cannot rely on the linker replacing the tail call with a return.
2353  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2354  const GlobalValue *GV = G->getGlobal();
2355  const Triple &TT = getTargetMachine().getTargetTriple();
2356  if (GV->hasExternalWeakLinkage() &&
2357  (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2358  return false;
2359  }
2360 
2361  // Check that the call results are passed in the same way.
2362  LLVMContext &C = *DAG.getContext();
2363  if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2364  CCAssignFnForReturn(CalleeCC, isVarArg),
2365  CCAssignFnForReturn(CallerCC, isVarArg)))
2366  return false;
2367  // The callee has to preserve all registers the caller needs to preserve.
2368  const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2369  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2370  if (CalleeCC != CallerCC) {
2371  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2372  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2373  return false;
2374  }
2375 
2376  // If Caller's vararg or byval argument has been split between registers and
2377  // stack, do not perform tail call, since part of the argument is in caller's
2378  // local frame.
2379  const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2380  if (AFI_Caller->getArgRegsSaveSize())
2381  return false;
2382 
2383  // If the callee takes no arguments then go on to check the results of the
2384  // call.
2385  if (!Outs.empty()) {
2386  // Check if stack adjustment is needed. For now, do not do this if any
2387  // argument is passed on the stack.
2389  CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2390  CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2391  if (CCInfo.getNextStackOffset()) {
2392  // Check if the arguments are already laid out in the right way as
2393  // the caller's fixed stack objects.
2394  MachineFrameInfo &MFI = MF.getFrameInfo();
2395  const MachineRegisterInfo *MRI = &MF.getRegInfo();
2396  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2397  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2398  i != e;
2399  ++i, ++realArgIdx) {
2400  CCValAssign &VA = ArgLocs[i];
2401  EVT RegVT = VA.getLocVT();
2402  SDValue Arg = OutVals[realArgIdx];
2403  ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2404  if (VA.getLocInfo() == CCValAssign::Indirect)
2405  return false;
2406  if (VA.needsCustom()) {
2407  // f64 and vector types are split into multiple registers or
2408  // register/stack-slot combinations. The types will not match
2409  // the registers; give up on memory f64 refs until we figure
2410  // out what to do about this.
2411  if (!VA.isRegLoc())
2412  return false;
2413  if (!ArgLocs[++i].isRegLoc())
2414  return false;
2415  if (RegVT == MVT::v2f64) {
2416  if (!ArgLocs[++i].isRegLoc())
2417  return false;
2418  if (!ArgLocs[++i].isRegLoc())
2419  return false;
2420  }
2421  } else if (!VA.isRegLoc()) {
2422  if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2423  MFI, MRI, TII))
2424  return false;
2425  }
2426  }
2427  }
2428 
2429  const MachineRegisterInfo &MRI = MF.getRegInfo();
2430  if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2431  return false;
2432  }
2433 
2434  return true;
2435 }
2436 
2437 bool
2438 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2439  MachineFunction &MF, bool isVarArg,
2440  const SmallVectorImpl<ISD::OutputArg> &Outs,
2441  LLVMContext &Context) const {
2443  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2444  return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2445 }
2446 
2448  const SDLoc &DL, SelectionDAG &DAG) {
2449  const MachineFunction &MF = DAG.getMachineFunction();
2450  const Function &F = MF.getFunction();
2451 
2452  StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2453 
2454  // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2455  // version of the "preferred return address". These offsets affect the return
2456  // instruction if this is a return from PL1 without hypervisor extensions.
2457  // IRQ/FIQ: +4 "subs pc, lr, #4"
2458  // SWI: 0 "subs pc, lr, #0"
2459  // ABORT: +4 "subs pc, lr, #4"
2460  // UNDEF: +4/+2 "subs pc, lr, #0"
2461  // UNDEF varies depending on where the exception came from ARM or Thumb
2462  // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2463 
2464  int64_t LROffset;
2465  if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2466  IntKind == "ABORT")
2467  LROffset = 4;
2468  else if (IntKind == "SWI" || IntKind == "UNDEF")
2469  LROffset = 0;
2470  else
2471  report_fatal_error("Unsupported interrupt attribute. If present, value "
2472  "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2473 
2474  RetOps.insert(RetOps.begin() + 1,
2475  DAG.getConstant(LROffset, DL, MVT::i32, false));
2476 
2477  return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2478 }
2479 
2480 SDValue
2481 ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2482  bool isVarArg,
2483  const SmallVectorImpl<ISD::OutputArg> &Outs,
2484  const SmallVectorImpl<SDValue> &OutVals,
2485  const SDLoc &dl, SelectionDAG &DAG) const {
2486  // CCValAssign - represent the assignment of the return value to a location.
2488 
2489  // CCState - Info about the registers and stack slots.
2490  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2491  *DAG.getContext());
2492 
2493  // Analyze outgoing return values.
2494  CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2495 
2496  SDValue Flag;
2497  SmallVector<SDValue, 4> RetOps;
2498  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2499  bool isLittleEndian = Subtarget->isLittle();
2500 
2501  MachineFunction &MF = DAG.getMachineFunction();
2503  AFI->setReturnRegsCount(RVLocs.size());
2504 
2505  // Copy the result values into the output registers.
2506  for (unsigned i = 0, realRVLocIdx = 0;
2507  i != RVLocs.size();
2508  ++i, ++realRVLocIdx) {
2509  CCValAssign &VA = RVLocs[i];
2510  assert(VA.isRegLoc() && "Can only return in registers!");
2511 
2512  SDValue Arg = OutVals[realRVLocIdx];
2513  bool ReturnF16 = false;
2514 
2515  if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2516  // Half-precision return values can be returned like this:
2517  //
2518  // t11 f16 = fadd ...
2519  // t12: i16 = bitcast t11
2520  // t13: i32 = zero_extend t12
2521  // t14: f32 = bitcast t13 <~~~~~~~ Arg
2522  //
2523  // to avoid code generation for bitcasts, we simply set Arg to the node
2524  // that produces the f16 value, t11 in this case.
2525  //
2526  if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2527  SDValue ZE = Arg.getOperand(0);
2528  if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2529  SDValue BC = ZE.getOperand(0);
2530  if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2531  Arg = BC.getOperand(0);
2532  ReturnF16 = true;
2533  }
2534  }
2535  }
2536  }
2537 
2538  switch (VA.getLocInfo()) {
2539  default: llvm_unreachable("Unknown loc info!");
2540  case CCValAssign::Full: break;
2541  case CCValAssign::BCvt:
2542  if (!ReturnF16)
2543  Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2544  break;
2545  }
2546 
2547  if (VA.needsCustom()) {
2548  if (VA.getLocVT() == MVT::v2f64) {
2549  // Extract the first half and return it in two registers.
2550  SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2551  DAG.getConstant(0, dl, MVT::i32));
2552  SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2553  DAG.getVTList(MVT::i32, MVT::i32), Half);
2554 
2555  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2556  HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2557  Flag);
2558  Flag = Chain.getValue(1);
2559  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2560  VA = RVLocs[++i]; // skip ahead to next loc
2561  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2562  HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2563  Flag);
2564  Flag = Chain.getValue(1);
2565  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2566  VA = RVLocs[++i]; // skip ahead to next loc
2567 
2568  // Extract the 2nd half and fall through to handle it as an f64 value.
2569  Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2570  DAG.getConstant(1, dl, MVT::i32));
2571  }
2572  // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2573  // available.
2574  SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2575  DAG.getVTList(MVT::i32, MVT::i32), Arg);
2576  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2577  fmrrd.getValue(isLittleEndian ? 0 : 1),
2578  Flag);
2579  Flag = Chain.getValue(1);
2580  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2581  VA = RVLocs[++i]; // skip ahead to next loc
2582  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2583  fmrrd.getValue(isLittleEndian ? 1 : 0),
2584  Flag);
2585  } else
2586  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2587 
2588  // Guarantee that all emitted copies are
2589  // stuck together, avoiding something bad.
2590  Flag = Chain.getValue(1);
2591  RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2592  ReturnF16 ? MVT::f16 : VA.getLocVT()));
2593  }
2594  const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2595  const MCPhysReg *I =
2597  if (I) {
2598  for (; *I; ++I) {
2599  if (ARM::GPRRegClass.contains(*I))
2600  RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2601  else if (ARM::DPRRegClass.contains(*I))
2602  RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2603  else
2604  llvm_unreachable("Unexpected register class in CSRsViaCopy!");
2605  }
2606  }
2607 
2608  // Update chain and glue.
2609  RetOps[0] = Chain;
2610  if (Flag.getNode())
2611  RetOps.push_back(Flag);
2612 
2613  // CPUs which aren't M-class use a special sequence to return from
2614  // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2615  // though we use "subs pc, lr, #N").
2616  //
2617  // M-class CPUs actually use a normal return sequence with a special
2618  // (hardware-provided) value in LR, so the normal code path works.
2619  if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2620  !Subtarget->isMClass()) {
2621  if (Subtarget->isThumb1Only())
2622  report_fatal_error("interrupt attribute is not supported in Thumb1");
2623  return LowerInterruptReturn(RetOps, dl, DAG);
2624  }
2625 
2626  return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2627 }
2628 
2629 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2630  if (N->getNumValues() != 1)
2631  return false;
2632  if (!N->hasNUsesOfValue(1, 0))
2633  return false;
2634 
2635  SDValue TCChain = Chain;
2636  SDNode *Copy = *N->use_begin();
2637  if (Copy->getOpcode() == ISD::CopyToReg) {
2638  // If the copy has a glue operand, we conservatively assume it isn't safe to
2639  // perform a tail call.
2640  if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2641  return false;
2642  TCChain = Copy->getOperand(0);
2643  } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2644  SDNode *VMov = Copy;
2645  // f64 returned in a pair of GPRs.
2647  for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2648  UI != UE; ++UI) {
2649  if (UI->getOpcode() != ISD::CopyToReg)
2650  return false;
2651  Copies.insert(*UI);
2652  }
2653  if (Copies.size() > 2)
2654  return false;
2655 
2656  for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2657  UI != UE; ++UI) {
2658  SDValue UseChain = UI->getOperand(0);
2659  if (Copies.count(UseChain.getNode()))
2660  // Second CopyToReg
2661  Copy = *UI;
2662  else {
2663  // We are at the top of this chain.
2664  // If the copy has a glue operand, we conservatively assume it
2665  // isn't safe to perform a tail call.
2666  if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2667  return false;
2668  // First CopyToReg
2669  TCChain = UseChain;
2670  }
2671  }
2672  } else if (Copy->getOpcode() == ISD::BITCAST) {
2673  // f32 returned in a single GPR.
2674  if (!Copy->hasOneUse())
2675  return false;
2676  Copy = *Copy->use_begin();
2677  if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2678  return false;
2679  // If the copy has a glue operand, we conservatively assume it isn't safe to
2680  // perform a tail call.
2681  if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2682  return false;
2683  TCChain = Copy->getOperand(0);
2684  } else {
2685  return false;
2686  }
2687 
2688  bool HasRet = false;
2689  for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2690  UI != UE; ++UI) {
2691  if (UI->getOpcode() != ARMISD::RET_FLAG &&
2692  UI->getOpcode() != ARMISD::INTRET_FLAG)
2693  return false;
2694  HasRet = true;
2695  }
2696 
2697  if (!HasRet)
2698  return false;
2699 
2700  Chain = TCChain;
2701  return true;
2702 }
2703 
2704 bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2705  if (!Subtarget->supportsTailCall())
2706  return false;
2707 
2708  auto Attr =
2709  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2710  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2711  return false;
2712 
2713  return true;
2714 }
2715 
2716 // Trying to write a 64 bit value so need to split into two 32 bit values first,
2717 // and pass the lower and high parts through.
2719  SDLoc DL(Op);
2720  SDValue WriteValue = Op->getOperand(2);
2721 
2722  // This function is only supposed to be called for i64 type argument.
2723  assert(WriteValue.getValueType() == MVT::i64
2724  && "LowerWRITE_REGISTER called for non-i64 type argument.");
2725 
2726  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2727  DAG.getConstant(0, DL, MVT::i32));
2728  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2729  DAG.getConstant(1, DL, MVT::i32));
2730  SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2731  return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2732 }
2733 
2734 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2735 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2736 // one of the above mentioned nodes. It has to be wrapped because otherwise
2737 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2738 // be used to form addressing mode. These wrapped nodes will be selected
2739 // into MOVi.
2740 SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2741  SelectionDAG &DAG) const {
2742  EVT PtrVT = Op.getValueType();
2743  // FIXME there is no actual debug info here
2744  SDLoc dl(Op);
2745  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2746  SDValue Res;
2747 
2748  // When generating execute-only code Constant Pools must be promoted to the
2749  // global data section. It's a bit ugly that we can't share them across basic
2750  // blocks, but this way we guarantee that execute-only behaves correct with
2751  // position-independent addressing modes.
2752  if (Subtarget->genExecuteOnly()) {
2753  auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2754  auto T = const_cast<Type*>(CP->getType());
2755  auto C = const_cast<Constant*>(CP->getConstVal());
2756  auto M = const_cast<Module*>(DAG.getMachineFunction().
2757  getFunction().getParent());
2758  auto GV = new GlobalVariable(
2759  *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
2760  Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
2761  Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
2762  Twine(AFI->createPICLabelUId())
2763  );
2764  SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
2765  dl, PtrVT);
2766  return LowerGlobalAddress(GA, DAG);
2767  }
2768 
2769  if (CP->isMachineConstantPoolEntry())
2770  Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2771  CP->getAlignment());
2772  else
2773  Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2774  CP->getAlignment());
2775  return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2776 }
2777 
2780 }
2781 
2782 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2783  SelectionDAG &DAG) const {
2784  MachineFunction &MF = DAG.getMachineFunction();
2786  unsigned ARMPCLabelIndex = 0;
2787  SDLoc DL(Op);
2788  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2789  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2790  SDValue CPAddr;
2791  bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
2792  if (!IsPositionIndependent) {
2793  CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2794  } else {
2795  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2796  ARMPCLabelIndex = AFI->createPICLabelUId();
2797  ARMConstantPoolValue *CPV =
2798  ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2799  ARMCP::CPBlockAddress, PCAdj);
2800  CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2801  }
2802  CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2803  SDValue Result = DAG.getLoad(
2804  PtrVT, DL, DAG.getEntryNode(), CPAddr,
2806  if (!IsPositionIndependent)
2807  return Result;
2808  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2809  return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2810 }
2811 
2812 /// Convert a TLS address reference into the correct sequence of loads
2813 /// and calls to compute the variable's address for Darwin, and return an
2814 /// SDValue containing the final node.
2815 
2816 /// Darwin only has one TLS scheme which must be capable of dealing with the
2817 /// fully general situation, in the worst case. This means:
2818 /// + "extern __thread" declaration.
2819 /// + Defined in a possibly unknown dynamic library.
2820 ///
2821 /// The general system is that each __thread variable has a [3 x i32] descriptor
2822 /// which contains information used by the runtime to calculate the address. The
2823 /// only part of this the compiler needs to know about is the first word, which
2824 /// contains a function pointer that must be called with the address of the
2825 /// entire descriptor in "r0".
2826 ///
2827 /// Since this descriptor may be in a different unit, in general access must
2828 /// proceed along the usual ARM rules. A common sequence to produce is:
2829 ///
2830 /// movw rT1, :lower16:_var$non_lazy_ptr
2831 /// movt rT1, :upper16:_var$non_lazy_ptr
2832 /// ldr r0, [rT1]
2833 /// ldr rT2, [r0]
2834 /// blx rT2
2835 /// [...address now in r0...]
2836 SDValue
2837 ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2838  SelectionDAG &DAG) const {
2839  assert(Subtarget->isTargetDarwin() &&
2840  "This function expects a Darwin target");
2841  SDLoc DL(Op);
2842 
2843  // First step is to get the address of the actua global symbol. This is where
2844  // the TLS descriptor lives.
2845  SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2846 
2847  // The first entry in the descriptor is a function pointer that we must call
2848  // to obtain the address of the variable.
2849  SDValue Chain = DAG.getEntryNode();
2850  SDValue FuncTLVGet = DAG.getLoad(
2851  MVT::i32, DL, Chain, DescAddr,
2853  /* Alignment = */ 4,
2856  Chain = FuncTLVGet.getValue(1);
2857 
2859  MachineFrameInfo &MFI = F.getFrameInfo();
2860  MFI.setAdjustsStack(true);
2861 
2862  // TLS calls preserve all registers except those that absolutely must be
2863  // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2864  // silly).
2865  auto TRI =
2866  getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
2867  auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2868  const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2869 
2870  // Finally, we can make the call. This is just a degenerate version of a
2871  // normal AArch64 call node: r0 takes the address of the descriptor, and
2872  // returns the address of the variable in this thread.
2873  Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2874  Chain =
2876  Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2877  DAG.getRegisterMask(Mask), Chain.getValue(1));
2878  return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2879 }
2880 
2881 SDValue
2882 ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2883  SelectionDAG &DAG) const {
2884  assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering");
2885 
2886  SDValue Chain = DAG.getEntryNode();
2887  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2888  SDLoc DL(Op);
2889 
2890  // Load the current TEB (thread environment block)
2891  SDValue Ops[] = {Chain,
2892  DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
2893  DAG.getConstant(15, DL, MVT::i32),
2894  DAG.getConstant(0, DL, MVT::i32),
2895  DAG.getConstant(13, DL, MVT::i32),
2896  DAG.getConstant(0, DL, MVT::i32),
2897  DAG.getConstant(2, DL, MVT::i32)};
2898  SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
2899  DAG.getVTList(MVT::i32, MVT::Other), Ops);
2900 
2901  SDValue TEB = CurrentTEB.getValue(0);
2902  Chain = CurrentTEB.getValue(1);
2903 
2904  // Load the ThreadLocalStoragePointer from the TEB
2905  // A pointer to the TLS array is located at offset 0x2c from the TEB.
2906  SDValue TLSArray =
2907  DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2908  TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
2909 
2910  // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
2911  // offset into the TLSArray.
2912 
2913  // Load the TLS index from the C runtime
2914  SDValue TLSIndex =
2915  DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
2916  TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2917  TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
2918 
2919  SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
2920  DAG.getConstant(2, DL, MVT::i32));
2921  SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
2922  DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2923  MachinePointerInfo());
2924 
2925  // Get the offset of the start of the .tls section (section base)
2926  const auto *GA = cast<GlobalAddressSDNode>(Op);
2927  auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
2928  SDValue Offset = DAG.getLoad(
2929  PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2930  DAG.getTargetConstantPool(CPV, PtrVT, 4)),
2932 
2933  return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2934 }
2935 
2936 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2937 SDValue
2938 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2939  SelectionDAG &DAG) const {
2940  SDLoc dl(GA);
2941  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2942  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2943  MachineFunction &MF = DAG.getMachineFunction();
2945  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2946  ARMConstantPoolValue *CPV =
2947  ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2948  ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2949  SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2950  Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2951  Argument = DAG.getLoad(
2952  PtrVT, dl, DAG.getEntryNode(), Argument,
2954  SDValue Chain = Argument.getValue(1);
2955 
2956  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2957  Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2958 
2959  // call __tls_get_addr.
2960  ArgListTy Args;
2961  ArgListEntry Entry;
2962  Entry.Node = Argument;
2963  Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2964  Args.push_back(Entry);
2965 
2966  // FIXME: is there useful debug info available here?
2968  CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2970  DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
2971 
2972  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2973  return CallResult.first;
2974 }
2975 
2976 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2977 // "local exec" model.
2978 SDValue
2979 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2980  SelectionDAG &DAG,
2981  TLSModel::Model model) const {
2982  const GlobalValue *GV = GA->getGlobal();
2983  SDLoc dl(GA);
2984  SDValue Offset;
2985  SDValue Chain = DAG.getEntryNode();
2986  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2987  // Get the Thread Pointer
2989 
2990  if (model == TLSModel::InitialExec) {
2991  MachineFunction &MF = DAG.getMachineFunction();
2993  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2994  // Initial exec model.
2995  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2996  ARMConstantPoolValue *CPV =
2997  ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2999  true);
3000  Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3001  Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3002  Offset = DAG.getLoad(
3003  PtrVT, dl, Chain, Offset,
3005  Chain = Offset.getValue(1);
3006 
3007  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3008  Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3009 
3010  Offset = DAG.getLoad(
3011  PtrVT, dl, Chain, Offset,
3013  } else {
3014  // local exec model
3015  assert(model == TLSModel::LocalExec);
3016  ARMConstantPoolValue *CPV =
3018  Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3019  Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3020  Offset = DAG.getLoad(
3021  PtrVT, dl, Chain, Offset,
3023  }
3024 
3025  // The address of the thread local variable is the add of the thread
3026  // pointer with the offset of the variable.
3027  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3028 }
3029 
3030 SDValue
3031 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3032  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3033  if (DAG.getTarget().useEmulatedTLS())
3034  return LowerToTLSEmulatedModel(GA, DAG);
3035 
3036  if (Subtarget->isTargetDarwin())
3037  return LowerGlobalTLSAddressDarwin(Op, DAG);
3038 
3039  if (Subtarget->isTargetWindows())
3040  return LowerGlobalTLSAddressWindows(Op, DAG);
3041 
3042  // TODO: implement the "local dynamic" model
3043  assert(Subtarget->isTargetELF() && "Only ELF implemented here");
3045 
3046  switch (model) {
3049  return LowerToTLSGeneralDynamicModel(GA, DAG);
3050  case TLSModel::InitialExec:
3051  case TLSModel::LocalExec:
3052  return LowerToTLSExecModels(GA, DAG, model);
3053  }
3054  llvm_unreachable("bogus TLS model");
3055 }
3056 
3057 /// Return true if all users of V are within function F, looking through
3058 /// ConstantExprs.
3059 static bool allUsersAreInFunction(const Value *V, const Function *F) {
3060  SmallVector<const User*,4> Worklist;
3061  for (auto *U : V->users())
3062  Worklist.push_back(U);
3063  while (!Worklist.empty()) {
3064  auto *U = Worklist.pop_back_val();
3065  if (isa<ConstantExpr>(U)) {
3066  for (auto *UU : U->users())
3067  Worklist.push_back(UU);
3068  continue;
3069  }
3070 
3071  auto *I = dyn_cast<Instruction>(U);
3072  if (!I || I->getParent()->getParent() != F)
3073  return false;
3074  }
3075  return true;
3076 }
3077 
3079  const GlobalValue *GV, SelectionDAG &DAG,
3080  EVT PtrVT, const SDLoc &dl) {
3081  // If we're creating a pool entry for a constant global with unnamed address,
3082  // and the global is small enough, we can emit it inline into the constant pool
3083  // to save ourselves an indirection.
3084  //
3085  // This is a win if the constant is only used in one function (so it doesn't
3086  // need to be duplicated) or duplicating the constant wouldn't increase code
3087  // size (implying the constant is no larger than 4 bytes).
3088  const Function &F = DAG.getMachineFunction().getFunction();
3089 
3090  // We rely on this decision to inline being idemopotent and unrelated to the
3091  // use-site. We know that if we inline a variable at one use site, we'll
3092  // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3093  // doesn't know about this optimization, so bail out if it's enabled else
3094  // we could decide to inline here (and thus never emit the GV) but require
3095  // the GV from fast-isel generated code.
3096  if (!EnableConstpoolPromotion ||
3098  return SDValue();
3099 
3100  auto *GVar = dyn_cast<GlobalVariable>(GV);
3101  if (!GVar || !GVar->hasInitializer() ||
3102  !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3103  !GVar->hasLocalLinkage())
3104  return SDValue();
3105 
3106  // If we inline a value that contains relocations, we move the relocations
3107  // from .data to .text. This is not allowed in position-independent code.
3108  auto *Init = GVar->getInitializer();
3109  if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3110  Init->needsRelocation())
3111  return SDValue();
3112 
3113  // The constant islands pass can only really deal with alignment requests
3114  // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3115  // any type wanting greater alignment requirements than 4 bytes. We also
3116  // can only promote constants that are multiples of 4 bytes in size or
3117  // are paddable to a multiple of 4. Currently we only try and pad constants
3118  // that are strings for simplicity.
3119  auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3120  unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3121  unsigned Align = DAG.getDataLayout().getPreferredAlignment(GVar);
3122  unsigned RequiredPadding = 4 - (Size % 4);
3123  bool PaddingPossible =
3124  RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3125  if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3126  Size == 0)
3127  return SDValue();
3128 
3129  unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3130  MachineFunction &MF = DAG.getMachineFunction();
3132 
3133  // We can't bloat the constant pool too much, else the ConstantIslands pass
3134  // may fail to converge. If we haven't promoted this global yet (it may have
3135  // multiple uses), and promoting it would increase the constant pool size (Sz
3136  // > 4), ensure we have space to do so up to MaxTotal.
3137  if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3138  if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3140  return SDValue();
3141 
3142  // This is only valid if all users are in a single function; we can't clone
3143  // the constant in general. The LLVM IR unnamed_addr allows merging
3144  // constants, but not cloning them.
3145  //
3146  // We could potentially allow cloning if we could prove all uses of the
3147  // constant in the current function don't care about the address, like
3148  // printf format strings. But that isn't implemented for now.
3149  if (!allUsersAreInFunction(GVar, &F))
3150  return SDValue();
3151 
3152  // We're going to inline this global. Pad it out if needed.
3153  if (RequiredPadding != 4) {
3154  StringRef S = CDAInit->getAsString();
3155 
3157  std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3158  while (RequiredPadding--)
3159  V.push_back(0);
3160  Init = ConstantDataArray::get(*DAG.getContext(), V);
3161  }
3162 
3163  auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3164  SDValue CPAddr =
3165  DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3166  if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3169  PaddedSize - 4);
3170  }
3171  ++NumConstpoolPromoted;
3172  return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3173 }
3174 
3176  if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3177  if (!(GV = GA->getBaseObject()))
3178  return false;
3179  if (const auto *V = dyn_cast<GlobalVariable>(GV))
3180  return V->isConstant();
3181  return isa<Function>(GV);
3182 }
3183 
3184 SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3185  SelectionDAG &DAG) const {
3186  switch (Subtarget->getTargetTriple().getObjectFormat()) {
3187  default: llvm_unreachable("unknown object format");
3188  case Triple::COFF:
3189  return LowerGlobalAddressWindows(Op, DAG);
3190  case Triple::ELF:
3191  return LowerGlobalAddressELF(Op, DAG);
3192  case Triple::MachO:
3193  return LowerGlobalAddressDarwin(Op, DAG);
3194  }
3195 }
3196 
3197 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3198  SelectionDAG &DAG) const {
3199  EVT PtrVT = getPointerTy(DAG.getDataLayout());
3200  SDLoc dl(Op);
3201  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3202  const TargetMachine &TM = getTargetMachine();
3203  bool IsRO = isReadOnly(GV);
3204 
3205  // promoteToConstantPool only if not generating XO text section
3206  if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3207  if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3208  return V;
3209 
3210  if (isPositionIndependent()) {
3211  bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3212  SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3213  UseGOT_PREL ? ARMII::MO_GOT : 0);
3214  SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3215  if (UseGOT_PREL)
3216  Result =
3217  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3219  return Result;
3220  } else if (Subtarget->isROPI() && IsRO) {
3221  // PC-relative.
3222  SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3223  SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3224  return Result;
3225  } else if (Subtarget->isRWPI() && !IsRO) {
3226  // SB-relative.
3227  SDValue RelAddr;
3228  if (Subtarget->useMovt(DAG.getMachineFunction())) {
3229  ++NumMovwMovt;
3230  SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3231  RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3232  } else { // use literal pool for address constant
3233  ARMConstantPoolValue *CPV =
3235  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3236  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3237  RelAddr = DAG.getLoad(
3238  PtrVT, dl, DAG.getEntryNode(), CPAddr,
3240  }
3241  SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3242  SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3243  return Result;
3244  }
3245 
3246  // If we have T2 ops, we can materialize the address directly via movt/movw
3247  // pair. This is always cheaper.
3248  if (Subtarget->useMovt(DAG.getMachineFunction())) {
3249  ++NumMovwMovt;
3250  // FIXME: Once remat is capable of dealing with instructions with register
3251  // operands, expand this into two nodes.
3252  return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3253  DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3254  } else {
3255  SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3256  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3257  return DAG.getLoad(
3258  PtrVT, dl, DAG.getEntryNode(), CPAddr,
3260  }
3261 }
3262 
3263 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3264  SelectionDAG &DAG) const {
3265  assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&
3266  "ROPI/RWPI not currently supported for Darwin");
3267  EVT PtrVT = getPointerTy(DAG.getDataLayout());
3268  SDLoc dl(Op);
3269  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3270 
3271  if (Subtarget->useMovt(DAG.getMachineFunction()))
3272  ++NumMovwMovt;
3273 
3274  // FIXME: Once remat is capable of dealing with instructions with register
3275  // operands, expand this into multiple nodes
3276  unsigned Wrapper =
3278 
3279  SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3280  SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3281 
3282  if (Subtarget->isGVIndirectSymbol(GV))
3283  Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3285  return Result;
3286 }
3287 
3288 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3289  SelectionDAG &DAG) const {
3290  assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
3291  assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
3292  "Windows on ARM expects to use movw/movt");
3293  assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&
3294  "ROPI/RWPI not currently supported for Windows");
3295 
3296  const TargetMachine &TM = getTargetMachine();
3297  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3299  if (GV->hasDLLImportStorageClass())
3300  TargetFlags = ARMII::MO_DLLIMPORT;
3301  else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3302  TargetFlags = ARMII::MO_COFFSTUB;
3303  EVT PtrVT = getPointerTy(DAG.getDataLayout());
3304  SDValue Result;
3305  SDLoc DL(Op);
3306 
3307  ++NumMovwMovt;
3308 
3309  // FIXME: Once remat is capable of dealing with instructions with register
3310  // operands, expand this into two nodes.
3311  Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3312  DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
3313  TargetFlags));
3314  if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3315  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3317  return Result;
3318 }
3319 
3320 SDValue
3321 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3322  SDLoc dl(Op);
3323  SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3324  return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3325  DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3326  Op.getOperand(1), Val);
3327 }
3328 
3329 SDValue
3330 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3331  SDLoc dl(Op);
3332  return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3333  Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3334 }
3335 
3336 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3337  SelectionDAG &DAG) const {
3338  SDLoc dl(Op);
3340  Op.getOperand(0));
3341 }
3342 
3343 SDValue
3344 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3345  const ARMSubtarget *Subtarget) const {
3346  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3347  SDLoc dl(Op);
3348  switch (IntNo) {
3349  default: return SDValue(); // Don't custom lower most intrinsics.
3350  case Intrinsic::thread_pointer: {
3351  EVT PtrVT = getPointerTy(DAG.getDataLayout());
3352  return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3353  }
3354  case Intrinsic::eh_sjlj_lsda: {
3355  MachineFunction &MF = DAG.getMachineFunction();
3357  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3358  EVT PtrVT = getPointerTy(DAG.getDataLayout());
3359  SDValue CPAddr;
3360  bool IsPositionIndependent = isPositionIndependent();
3361  unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3362  ARMConstantPoolValue *CPV =
3363  ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3364  ARMCP::CPLSDA, PCAdj);
3365  CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3366  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3367  SDValue Result = DAG.getLoad(
3368  PtrVT, dl, DAG.getEntryNode(), CPAddr,
3370 
3371  if (IsPositionIndependent) {
3372  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3373  Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3374  }
3375  return Result;
3376  }
3377  case Intrinsic::arm_neon_vabs:
3378  return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3379  Op.getOperand(1));
3380  case Intrinsic::arm_neon_vmulls:
3381  case Intrinsic::arm_neon_vmullu: {
3382  unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3384  return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3385  Op.getOperand(1), Op.getOperand(2));
3386  }
3387  case Intrinsic::arm_neon_vminnm:
3388  case Intrinsic::arm_neon_vmaxnm: {
3389  unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3391  return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3392  Op.getOperand(1), Op.getOperand(2));
3393  }
3394  case Intrinsic::arm_neon_vminu:
3395  case Intrinsic::arm_neon_vmaxu: {
3396  if (Op.getValueType().isFloatingPoint())
3397  return SDValue();
3398  unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3399  ? ISD::UMIN : ISD::UMAX;
3400  return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3401  Op.getOperand(1), Op.getOperand(2));
3402  }
3403  case Intrinsic::arm_neon_vmins:
3404  case Intrinsic::arm_neon_vmaxs: {
3405  // v{min,max}s is overloaded between signed integers and floats.
3406  if (!Op.getValueType().isFloatingPoint()) {
3407  unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3408  ? ISD::SMIN : ISD::SMAX;
3409  return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3410  Op.getOperand(1), Op.getOperand(2));
3411  }
3412  unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3414  return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3415  Op.getOperand(1), Op.getOperand(2));
3416  }
3417  case Intrinsic::arm_neon_vtbl1:
3418  return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3419  Op.getOperand(1), Op.getOperand(2));
3420  case Intrinsic::arm_neon_vtbl2:
3421  return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3422  Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3423  }
3424 }
3425 
3427  const ARMSubtarget *Subtarget) {
3428  SDLoc dl(Op);
3429  ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3430  auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3431  if (SSID == SyncScope::SingleThread)
3432  return Op;
3433 
3434  if (!Subtarget->hasDataBarrier()) {
3435  // Some ARMv6 cpus can support data barriers with an mcr instruction.
3436  // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3437  // here.
3438  assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
3439  "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
3440  return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3441  DAG.getConstant(0, dl, MVT::i32));
3442  }
3443 
3444  ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3445  AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3446  ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3447  if (Subtarget->isMClass()) {
3448  // Only a full system barrier exists in the M-class architectures.
3449  Domain = ARM_MB::SY;
3450  } else if (Subtarget->preferISHSTBarriers() &&
3451  Ord == AtomicOrdering::Release) {
3452  // Swift happens to implement ISHST barriers in a way that's compatible with
3453  // Release semantics but weaker than ISH so we'd be fools not to use
3454  // it. Beware: other processors probably don't!
3455  Domain = ARM_MB::ISHST;
3456  }
3457 
3458  return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3459  DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3460  DAG.getConstant(Domain, dl, MVT::i32));
3461 }
3462 
3464  const ARMSubtarget *Subtarget) {
3465  // ARM pre v5TE and Thumb1 does not have preload instructions.
3466  if (!(Subtarget->isThumb2() ||
3467  (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3468  // Just preserve the chain.
3469  return Op.getOperand(0);
3470 
3471  SDLoc dl(Op);
3472  unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3473  if (!isRead &&
3474  (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3475  // ARMv7 with MP extension has PLDW.
3476  return Op.getOperand(0);
3477 
3478  unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3479  if (Subtarget->isThumb()) {
3480  // Invert the bits.
3481  isRead = ~isRead & 1;
3482  isData = ~isData & 1;
3483  }
3484 
3485  return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3486  Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3487  DAG.getConstant(isData, dl, MVT::i32));
3488 }
3489 
3491  MachineFunction &MF = DAG.getMachineFunction();
3492  ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3493 
3494  // vastart just stores the address of the VarArgsFrameIndex slot into the
3495  // memory location argument.
3496  SDLoc dl(Op);
3497  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3498  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3499  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3500  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3501  MachinePointerInfo(SV));
3502 }
3503 
3504 SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3505  CCValAssign &NextVA,
3506  SDValue &Root,
3507  SelectionDAG &DAG,
3508  const SDLoc &dl) const {
3509  MachineFunction &MF = DAG.getMachineFunction();
3511 
3512  const TargetRegisterClass *RC;
3513  if (AFI->isThumb1OnlyFunction())
3514  RC = &ARM::tGPRRegClass;
3515  else
3516  RC = &ARM::GPRRegClass;
3517 
3518  // Transform the arguments stored in physical registers into virtual ones.
3519  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3520  SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3521 
3522  SDValue ArgValue2;
3523  if (NextVA.isMemLoc()) {
3524  MachineFrameInfo &MFI = MF.getFrameInfo();
3525  int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3526 
3527  // Create load node to retrieve arguments from the stack.
3528  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3529  ArgValue2 = DAG.getLoad(
3530  MVT::i32, dl, Root, FIN,
3532  } else {
3533  Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3534  ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3535  }
3536  if (!Subtarget->isLittle())
3537  std::swap (ArgValue, ArgValue2);
3538  return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3539 }
3540 
3541 // The remaining GPRs hold either the beginning of variable-argument
3542 // data, or the beginning of an aggregate passed by value (usually
3543 // byval). Either way, we allocate stack slots adjacent to the data
3544 // provided by our caller, and store the unallocated registers there.
3545 // If this is a variadic function, the va_list pointer will begin with
3546 // these values; otherwise, this reassembles a (byval) structure that
3547 // was split between registers and memory.
3548 // Return: The frame index registers were stored into.
3549 int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3550  const SDLoc &dl, SDValue &Chain,
3551  const Value *OrigArg,
3552  unsigned InRegsParamRecordIdx,
3553  int ArgOffset, unsigned ArgSize) const {
3554  // Currently, two use-cases possible:
3555  // Case #1. Non-var-args function, and we meet first byval parameter.
3556  // Setup first unallocated register as first byval register;
3557  // eat all remained registers
3558  // (these two actions are performed by HandleByVal method).
3559  // Then, here, we initialize stack frame with
3560  // "store-reg" instructions.
3561  // Case #2. Var-args function, that doesn't contain byval parameters.
3562  // The same: eat all remained unallocated registers,
3563  // initialize stack frame.
3564 
3565  MachineFunction &MF = DAG.getMachineFunction();
3566  MachineFrameInfo &MFI = MF.getFrameInfo();
3568  unsigned RBegin, REnd;
3569  if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3570  CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3571  } else {
3572  unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3573  RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3574  REnd = ARM::R4;
3575  }
3576 
3577  if (REnd != RBegin)
3578  ArgOffset = -4 * (ARM::R4 - RBegin);
3579 
3580  auto PtrVT = getPointerTy(DAG.getDataLayout());
3581  int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3582  SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3583 
3584  SmallVector<SDValue, 4> MemOps;
3585  const TargetRegisterClass *RC =
3586  AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3587 
3588  for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3589  unsigned VReg = MF.addLiveIn(Reg, RC);
3590  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3591  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3592  MachinePointerInfo(OrigArg, 4 * i));
3593  MemOps.push_back(Store);
3594  FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3595  }
3596 
3597  if (!MemOps.empty())
3598  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3599  return FrameIndex;
3600 }
3601 
3602 // Setup stack frame, the va_list pointer will start from.
3603 void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3604  const SDLoc &dl, SDValue &Chain,
3605  unsigned ArgOffset,
3606  unsigned TotalArgRegsSaveSize,
3607  bool ForceMutable) const {
3608  MachineFunction &MF = DAG.getMachineFunction();
3610 
3611  // Try to store any remaining integer argument regs
3612  // to their spots on the stack so that they may be loaded by dereferencing
3613  // the result of va_next.
3614  // If there is no regs to be stored, just point address after last
3615  // argument passed via stack.
3616  int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3617  CCInfo.getInRegsParamsCount(),
3618  CCInfo.getNextStackOffset(), 4);
3619  AFI->setVarArgsFrameIndex(FrameIndex);
3620 }
3621 
3622 SDValue ARMTargetLowering::LowerFormalArguments(
3623  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3624  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3625  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3626  MachineFunction &MF = DAG.getMachineFunction();
3627  MachineFrameInfo &MFI = MF.getFrameInfo();
3628 
3630 
3631  // Assign locations to all of the incoming arguments.
3633  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3634  *DAG.getContext());
3635  CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3636 
3637  SmallVector<SDValue, 16> ArgValues;
3638  SDValue ArgValue;
3640  unsigned CurArgIdx = 0;
3641 
3642  // Initially ArgRegsSaveSize is zero.
3643  // Then we increase this value each time we meet byval parameter.
3644  // We also increase this value in case of varargs function.
3645  AFI->setArgRegsSaveSize(0);
3646 
3647  // Calculate the amount of stack space that we need to allocate to store
3648  // byval and variadic arguments that are passed in registers.
3649  // We need to know this before we allocate the first byval or variadic
3650  // argument, as they will be allocated a stack slot below the CFA (Canonical
3651  // Frame Address, the stack pointer at entry to the function).
3652  unsigned ArgRegBegin = ARM::R4;
3653  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3654  if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3655  break;
3656 
3657  CCValAssign &VA = ArgLocs[i];
3658  unsigned Index = VA.getValNo();
3659  ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3660  if (!Flags.isByVal())
3661  continue;
3662 
3663  assert(VA.isMemLoc() && "unexpected byval pointer in reg");
3664  unsigned RBegin, REnd;
3665  CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3666  ArgRegBegin = std::min(ArgRegBegin, RBegin);
3667 
3668  CCInfo.nextInRegsParam();
3669  }
3670  CCInfo.rewindByValRegsInfo();
3671 
3672  int lastInsIndex = -1;
3673  if (isVarArg && MFI.hasVAStart()) {
3674  unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3675  if (RegIdx != array_lengthof(GPRArgRegs))
3676  ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3677  }
3678 
3679  unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3680  AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3681  auto PtrVT = getPointerTy(DAG.getDataLayout());
3682 
3683  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3684  CCValAssign &VA = ArgLocs[i];
3685  if (Ins[VA.getValNo()].isOrigArg()) {
3686  std::advance(CurOrigArg,
3687  Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3688  CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3689  }
3690  // Arguments stored in registers.
3691  if (VA.isRegLoc()) {
3692  EVT RegVT = VA.getLocVT();
3693 
3694  if (VA.needsCustom()) {
3695  // f64 and vector types are split up into multiple registers or
3696  // combinations of registers and stack slots.
3697  if (VA.getLocVT() == MVT::v2f64) {
3698  SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3699  Chain, DAG, dl);
3700  VA = ArgLocs[++i]; // skip ahead to next loc
3701  SDValue ArgValue2;
3702  if (VA.isMemLoc()) {
3703  int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
3704  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3705  ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3707  DAG.getMachineFunction(), FI));
3708  } else {
3709  ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3710  Chain, DAG, dl);
3711  }
3712  ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3713  ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3714  ArgValue, ArgValue1,
3715  DAG.getIntPtrConstant(0, dl));
3716  ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3717  ArgValue, ArgValue2,
3718  DAG.getIntPtrConstant(1, dl));
3719  } else
3720  ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3721  } else {
3722  const TargetRegisterClass *RC;
3723 
3724 
3725  if (RegVT == MVT::f16)
3726  RC = &ARM::HPRRegClass;
3727  else if (RegVT == MVT::f32)
3728  RC = &ARM::SPRRegClass;
3729  else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
3730  RC = &ARM::DPRRegClass;
3731  else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
3732  RC = &ARM::QPRRegClass;
3733  else if (RegVT == MVT::i32)
3734  RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3735  : &ARM::GPRRegClass;
3736  else
3737  llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3738 
3739  // Transform the arguments in physical registers into virtual ones.
3740  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3741  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3742  }
3743 
3744  // If this is an 8 or 16-bit value, it is really passed promoted
3745  // to 32 bits. Insert an assert[sz]ext to capture this, then
3746  // truncate to the right size.
3747  switch (VA.getLocInfo()) {
3748  default: llvm_unreachable("Unknown loc info!");
3749  case CCValAssign::Full: break;
3750  case CCValAssign::BCvt:
3751  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3752  break;
3753  case CCValAssign::SExt:
3754  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3755  DAG.getValueType(VA.getValVT()));
3756  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3757  break;
3758  case CCValAssign::ZExt:
3759  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3760  DAG.getValueType(VA.getValVT()));
3761  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3762  break;
3763  }
3764 
3765  InVals.push_back(ArgValue);
3766  } else { // VA.isRegLoc()
3767  // sanity check
3768  assert(VA.isMemLoc());
3769  assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3770 
3771  int index = VA.getValNo();
3772 
3773  // Some Ins[] entries become multiple ArgLoc[] entries.
3774  // Process them only once.
3775  if (index != lastInsIndex)
3776  {
3777  ISD::ArgFlagsTy Flags = Ins[index].Flags;
3778  // FIXME: For now, all byval parameter objects are marked mutable.
3779  // This can be changed with more analysis.
3780  // In case of tail call optimization mark all arguments mutable.
3781  // Since they could be overwritten by lowering of arguments in case of
3782  // a tail call.
3783  if (Flags.isByVal()) {
3784  assert(Ins[index].isOrigArg() &&
3785  "Byval arguments cannot be implicit");
3786  unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3787 
3788  int FrameIndex = StoreByValRegs(
3789  CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3790  VA.getLocMemOffset(), Flags.getByValSize());
3791  InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3792  CCInfo.nextInRegsParam();
3793  } else {
3794  unsigned FIOffset = VA.getLocMemOffset();
3795  int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3796  FIOffset, true);
3797 
3798  // Create load nodes to retrieve arguments from the stack.
3799  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3800  InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3802  DAG.getMachineFunction(), FI)));
3803  }
3804  lastInsIndex = index;
3805  }
3806  }
3807  }
3808 
3809  // varargs
3810  if (isVarArg && MFI.hasVAStart())
3811  VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3812  CCInfo.getNextStackOffset(),
3813  TotalArgRegsSaveSize);
3814 
3816 
3817  return Chain;
3818 }
3819 
3820 /// isFloatingPointZero - Return true if this is +0.0.
3821 static bool isFloatingPointZero(SDValue Op) {
3822  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3823  return CFP->getValueAPF().isPosZero();
3824  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3825  // Maybe this has already been legalized into the constant pool?
3826  if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3827  SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3828  if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3829  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3830  return CFP->getValueAPF().isPosZero();
3831  }
3832  } else if (Op->getOpcode() == ISD::BITCAST &&
3833  Op->getValueType(0) == MVT::f64) {
3834  // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3835  // created by LowerConstantFP().
3836  SDValue BitcastOp = Op->getOperand(0);
3837  if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3838  isNullConstant(BitcastOp->getOperand(0)))
3839  return true;
3840  }
3841  return false;
3842 }
3843 
3844 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3845 /// the given operands.
3846 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3847  SDValue &ARMcc, SelectionDAG &DAG,
3848  const SDLoc &dl) const {
3849  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3850  unsigned C = RHSC->getZExtValue();
3851  if (!isLegalICmpImmediate((int32_t)C)) {
3852  // Constant does not fit, try adjusting it by one.
3853  switch (CC) {
3854  default: break;
3855  case ISD::SETLT:
3856  case ISD::SETGE:
3857  if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3858  CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3859  RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3860  }
3861  break;
3862  case ISD::SETULT:
3863  case ISD::SETUGE:
3864  if (C != 0 && isLegalICmpImmediate(C-1)) {
3865  CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3866  RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3867  }
3868  break;
3869  case ISD::SETLE:
3870  case ISD::SETGT:
3871  if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3872  CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3873  RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3874  }
3875  break;
3876  case ISD::SETULE:
3877  case ISD::SETUGT:
3878  if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3879  CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3880  RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3881  }
3882  break;
3883  }
3884  }
3885  } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
3887  // In ARM and Thumb-2, the compare instructions can shift their second
3888  // operand.
3890  std::swap(LHS, RHS);
3891  }
3892 
3894  ARMISD::NodeType CompareType;
3895  switch (CondCode) {
3896  default:
3897  CompareType = ARMISD::CMP;
3898  break;
3899  case ARMCC::EQ:
3900  case ARMCC::NE:
3901  // Uses only Z Flag
3902  CompareType = ARMISD::CMPZ;
3903  break;
3904  }
3905  ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3906  return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3907 }
3908 
3909 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3910 SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
3911  SelectionDAG &DAG, const SDLoc &dl,
3912  bool InvalidOnQNaN) const {
3913  assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3914  SDValue Cmp;
3915  SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
3916  if (!isFloatingPointZero(RHS))
3917  Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
3918  else
3919  Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
3920  return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3921 }
3922 
3923 /// duplicateCmp - Glue values can have only one use, so this function
3924 /// duplicates a comparison node.
3925 SDValue
3926 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3927  unsigned Opc = Cmp.getOpcode();
3928  SDLoc DL(Cmp);
3929  if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3930  return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3931 
3932  assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3933  Cmp = Cmp.getOperand(0);
3934  Opc = Cmp.getOpcode();
3935  if (Opc == ARMISD::CMPFP)
3936  Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3937  Cmp.getOperand(1), Cmp.getOperand(2));
3938  else {
3939  assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3940  Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3941  Cmp.getOperand(1));
3942  }
3943  return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3944 }
3945 
3946 // This function returns three things: the arithmetic computation itself
3947 // (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
3948 // comparison and the condition code define the case in which the arithmetic
3949 // computation *does not* overflow.
3950 std::pair<SDValue, SDValue>
3951 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3952  SDValue &ARMcc) const {
3953  assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3954 
3955  SDValue Value, OverflowCmp;
3956  SDValue LHS = Op.getOperand(0);
3957  SDValue RHS = Op.getOperand(1);
3958  SDLoc dl(Op);
3959 
3960  // FIXME: We are currently always generating CMPs because we don't support
3961  // generating CMN through the backend. This is not as good as the natural
3962  // CMP case because it causes a register dependency and cannot be folded
3963  // later.
3964 
3965  switch (Op.getOpcode()) {
3966  default:
3967  llvm_unreachable("Unknown overflow instruction!");
3968  case ISD::SADDO:
3969  ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3970  Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3971  OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3972  break;
3973  case ISD::UADDO:
3974  ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3975  // We use ADDC here to correspond to its use in LowerUnsignedALUO.
3976  // We do not use it in the USUBO case as Value may not be used.
3977  Value = DAG.getNode(ARMISD::ADDC, dl,
3978  DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
3979  .getValue(0);
3980  OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3981  break;
3982  case ISD::SSUBO:
3983  ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3984  Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3985  OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3986  break;
3987  case ISD::USUBO:
3988  ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3989  Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3990  OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3991  break;
3992  case ISD::UMULO:
3993  // We generate a UMUL_LOHI and then check if the high word is 0.
3994  ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
3995  Value = DAG.getNode(ISD::UMUL_LOHI, dl,
3996  DAG.getVTList(Op.getValueType(), Op.getValueType()),
3997  LHS, RHS);
3998  OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
3999  DAG.getConstant(0, dl, MVT::i32));
4000  Value = Value.getValue(0); // We only want the low 32 bits for the result.
4001  break;
4002  case ISD::SMULO:
4003  // We generate a SMUL_LOHI and then check if all the bits of the high word
4004  // are the same as the sign bit of the low word.
4005  ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4006  Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4007  DAG.getVTList(Op.getValueType(), Op.getValueType()),
4008  LHS, RHS);
4009  OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4010  DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4011  Value.getValue(0),
4012  DAG.getConstant(31, dl, MVT::i32)));
4013  Value = Value.getValue(0); // We only want the low 32 bits for the result.
4014  break;
4015  } // switch (...)
4016 
4017  return std::make_pair(Value, OverflowCmp);
4018 }
4019 
4020 SDValue
4021 ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4022  // Let legalize expand this if it isn't a legal type yet.
4024  return SDValue();
4025 
4026  SDValue Value, OverflowCmp;
4027  SDValue ARMcc;
4028  std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4029  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4030  SDLoc dl(Op);
4031  // We use 0 and 1 as false and true values.
4032  SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4033  SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4034  EVT VT = Op.getValueType();
4035 
4036  SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4037  ARMcc, CCR, OverflowCmp);
4038 
4039  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4040  retu