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ARMLowOverheadLoops.cpp File Reference

Finalize v8.1-m low-overhead loops by converting the associated pseudo instructions into machine operations. More...

#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMBasicBlockInfo.h"
#include "ARMSubtarget.h"
#include "Thumb2InstrInfo.h"
#include "llvm/ADT/SetOperations.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineLoopUtils.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/ReachingDefAnalysis.h"
#include "llvm/MC/MCInstrDesc.h"
Include dependency graph for ARMLowOverheadLoops.cpp:

Go to the source code of this file.


#define DEBUG_TYPE   "arm-low-overhead-loops"
#define ARM_LOW_OVERHEAD_LOOPS_NAME   "ARM Low Overhead Loops pass"


 INITIALIZE_PASS (ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME, false, false) MachineInstr *LowOverheadLoop
static bool isVectorPredicated (MachineInstr *MI)
static bool isRegInClass (const MachineOperand &MO, const TargetRegisterClass *Class)
static bool retainsPreviousHalfElement (const MachineInstr &MI)
static bool producesDoubleWidthResult (const MachineInstr &MI)
static bool isHorizontalReduction (const MachineInstr &MI)
static bool canGenerateNonZeros (const MachineInstr &MI)
static bool producesFalseLanesZero (MachineInstr &MI, const TargetRegisterClass *QPRs, const ReachingDefAnalysis &RDA, InstSet &FalseLanesZero)

Detailed Description

Finalize v8.1-m low-overhead loops by converting the associated pseudo instructions into machine operations.

The expectation is that the loop contains three pseudo instructions:

In addition to this, we also look for the presence of the VCTP instruction, which determines whether we can generated the tail-predicated low-overhead loop form.

Assumptions and Dependencies: Low-overhead loops are constructed and executed using a setup instruction: DLS, WLS, DLSTP or WLSTP and an instruction that loops back: LE or LETP. WLS(TP) and LE(TP) are branching instructions with a (large) limited range but fixed polarity: WLS can only branch forwards and LE can only branch backwards. These restrictions mean that this pass is dependent upon block layout and block sizes, which is why it's the last pass to run. The same is true for ConstantIslands, but this pass does not increase the size of the basic blocks, nor does it change the CFG. Instructions are mainly removed during the transform and pseudo instructions are replaced by real ones. In some cases, when we have to revert to a 'normal' loop, we have to introduce multiple instructions for a single pseudo (see RevertWhile and RevertLoopEnd). To handle this situation, t2WhileLoopStart and t2LoopEnd are defined to be as large as this maximum sequence of replacement instructions.

A note on VPR.P0 (the lane mask): VPT, VCMP, VPNOT and VCTP won't overwrite VPR.P0 when they update it in a "VPT Active" context (which includes low-overhead loops and vpt blocks). They will simply "and" the result of their calculation with the current value of VPR.P0. You can think of it like this:

/// if VPT active:    ; Between a DLSTP/LETP, or for predicated instrs
///   VPR.P0 &= Value
/// else
///   VPR.P0 = Value

When we're inside the low-overhead loop (between DLSTP and LETP), we always fall in the "VPT active" case, so we can consider that all VPR writes by one of those instruction is actually a "and".

Definition in file ARMLowOverheadLoops.cpp.

Macro Definition Documentation


#define ARM_LOW_OVERHEAD_LOOPS_NAME   "ARM Low Overhead Loops pass"

Definition at line 74 of file ARMLowOverheadLoops.cpp.


#define DEBUG_TYPE   "arm-low-overhead-loops"

Definition at line 73 of file ARMLowOverheadLoops.cpp.

Function Documentation

◆ canGenerateNonZeros()

static bool canGenerateNonZeros ( const MachineInstr MI)


INITIALIZE_PASS ( ARMLowOverheadLoops  ,
false  ,

Definition at line 379 of file ARMLowOverheadLoops.cpp.

◆ isHorizontalReduction()

static bool isHorizontalReduction ( const MachineInstr MI)

◆ isRegInClass()

static bool isRegInClass ( const MachineOperand MO,
const TargetRegisterClass Class 

◆ isVectorPredicated()

static bool isVectorPredicated ( MachineInstr MI)

◆ producesDoubleWidthResult()

static bool producesDoubleWidthResult ( const MachineInstr MI)

◆ producesFalseLanesZero()

static bool producesFalseLanesZero ( MachineInstr MI,
const TargetRegisterClass QPRs,
const ReachingDefAnalysis RDA,
InstSet &  FalseLanesZero 

◆ retainsPreviousHalfElement()

static bool retainsPreviousHalfElement ( const MachineInstr MI)