LLVM  10.0.0svn
ARMRegisterBankInfo.h
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1 //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the RegisterBankInfo class for ARM.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
15 
17 
18 #define GET_REGBANK_DECLARATIONS
19 #include "ARMGenRegisterBank.inc"
20 
21 namespace llvm {
22 
23 class TargetRegisterInfo;
24 
26 #define GET_TARGET_REGBANK_CLASS
27 #include "ARMGenRegisterBank.inc"
28 };
29 
30 /// This class provides the information for the target register banks.
32 public:
34 
35  const RegisterBank &
36  getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
37 
38  const InstructionMapping &
39  getInstrMapping(const MachineInstr &MI) const override;
40 };
41 } // End llvm namespace.
42 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned const TargetRegisterInfo * TRI
Holds all the information related to register banks.
This class provides the information for the target register banks.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements the register bank concept.
Definition: RegisterBank.h:28
Representation of each machine instruction.
Definition: MachineInstr.h:63
IRTranslator LLVM IR MI
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.