LLVM  10.0.0svn
ARMSubtarget.cpp
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1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARM.h"
14 
15 #include "ARMCallLowering.h"
16 #include "ARMLegalizerInfo.h"
17 #include "ARMRegisterBankInfo.h"
18 #include "ARMSubtarget.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/ADT/Twine.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/Support/CodeGen.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "arm-subtarget"
44 
45 #define GET_SUBTARGETINFO_TARGET_DESC
46 #define GET_SUBTARGETINFO_CTOR
47 #include "ARMGenSubtargetInfo.inc"
48 
49 static cl::opt<bool>
50 UseFusedMulOps("arm-use-mulops",
51  cl::init(true), cl::Hidden);
52 
53 enum ITMode {
57 };
58 
59 static cl::opt<ITMode>
60 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
62  cl::values(clEnumValN(DefaultIT, "arm-default-it",
63  "Generate IT block based on arch"),
64  clEnumValN(RestrictedIT, "arm-restrict-it",
65  "Disallow deprecated IT based on ARMv8"),
66  clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
67  "Allow IT blocks based on ARMv7")));
68 
69 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
70 /// currently supported (for testing only).
71 static cl::opt<bool>
72 ForceFastISel("arm-force-fast-isel",
73  cl::init(false), cl::Hidden);
74 
75 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
76 /// so that we can use initializer lists for subtarget initialization.
78  StringRef FS) {
79  initializeEnvironment();
80  initSubtargetFeatures(CPU, FS);
81  return *this;
82 }
83 
84 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
85  StringRef FS) {
87  if (STI.isThumb1Only())
88  return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
89 
90  return new ARMFrameLowering(STI);
91 }
92 
93 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
94  const std::string &FS,
95  const ARMBaseTargetMachine &TM, bool IsLittle,
96  bool MinSize)
98  CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle),
99  TargetTriple(TT), Options(TM.Options), TM(TM),
100  FrameLowering(initializeFrameLowering(CPU, FS)),
101  // At this point initializeSubtargetDependencies has been called so
102  // we can query directly.
103  InstrInfo(isThumb1Only()
104  ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
105  : !isThumb()
106  ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
107  : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
108  TLInfo(TM, *this) {
109 
110  CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
111  Legalizer.reset(new ARMLegalizerInfo(*this));
112 
113  auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
114 
115  // FIXME: At this point, we can't rely on Subtarget having RBI.
116  // It's awkward to mix passing RBI and the Subtarget; should we pass
117  // TII/TRI as well?
118  InstSelector.reset(createARMInstructionSelector(
119  *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
120 
121  RegBankInfo.reset(RBI);
122 }
123 
125  return CallLoweringInfo.get();
126 }
127 
129  return InstSelector.get();
130 }
131 
133  return Legalizer.get();
134 }
135 
137  return RegBankInfo.get();
138 }
139 
141  // We don't currently suppport Thumb, but Windows requires Thumb.
142  return hasV6Ops() && hasARMOps() && !isTargetWindows();
143 }
144 
145 void ARMSubtarget::initializeEnvironment() {
146  // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
147  // directly from it, but we can try to make sure they're consistent when both
148  // available.
152  assert((!TM.getMCAsmInfo() ||
155  "inconsistent sjlj choice between CodeGen and MC");
156 }
157 
158 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
159  if (CPUString.empty()) {
160  CPUString = "generic";
161 
162  if (isTargetDarwin()) {
163  StringRef ArchName = TargetTriple.getArchName();
164  ARM::ArchKind AK = ARM::parseArch(ArchName);
165  if (AK == ARM::ArchKind::ARMV7S)
166  // Default to the Swift CPU when targeting armv7s/thumbv7s.
167  CPUString = "swift";
168  else if (AK == ARM::ArchKind::ARMV7K)
169  // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
170  // ARMv7k does not use SjLj exception handling.
171  CPUString = "cortex-a7";
172  }
173  }
174 
175  // Insert the architecture feature derived from the target triple into the
176  // feature string. This is important for setting features that are implied
177  // based on the architecture version.
178  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
179  if (!FS.empty()) {
180  if (!ArchFS.empty())
181  ArchFS = (Twine(ArchFS) + "," + FS).str();
182  else
183  ArchFS = FS;
184  }
186 
187  // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
188  // Assert this for now to make the change obvious.
189  assert(hasV6T2Ops() || !hasThumb2());
190 
191  // Execute only support requires movt support
192  if (genExecuteOnly()) {
193  NoMovt = false;
194  assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
195  }
196 
197  // Keep a pointer to static instruction cost data for the specified CPU.
198  SchedModel = getSchedModelForCPU(CPUString);
199 
200  // Initialize scheduling itinerary for the specified CPU.
201  InstrItins = getInstrItineraryForCPU(CPUString);
202 
203  // FIXME: this is invalid for WindowsCE
204  if (isTargetWindows())
205  NoARM = true;
206 
207  if (isAAPCS_ABI())
208  stackAlignment = 8;
209  if (isTargetNaCl() || isAAPCS16_ABI())
210  stackAlignment = 16;
211 
212  // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
213  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
214  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
215  // support in the assembler and linker to be used. This would need to be
216  // fixed to fully support tail calls in Thumb1.
217  //
218  // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
219  // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
220  // means if we need to reload LR, it takes extra instructions, which outweighs
221  // the value of the tail call; but here we don't know yet whether LR is going
222  // to be used. We take the optimistic approach of generating the tail call and
223  // perhaps taking a hit if we need to restore the LR.
224 
225  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
226  // but we need to make sure there are enough registers; the only valid
227  // registers are the 4 used for parameters. We don't currently do this
228  // case.
229 
231 
232  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
233  SupportsTailCall = false;
234 
235  switch (IT) {
236  case DefaultIT:
237  RestrictIT = hasV8Ops();
238  break;
239  case RestrictedIT:
240  RestrictIT = true;
241  break;
242  case NoRestrictedIT:
243  RestrictIT = false;
244  break;
245  }
246 
247  // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
248  const FeatureBitset &Bits = getFeatureBits();
249  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
252 
253  if (isRWPI())
254  ReserveR9 = true;
255 
256  // FIXME: Teach TableGen to deal with these instead of doing it manually here.
257  switch (ARMProcFamily) {
258  case Others:
259  case CortexA5:
260  break;
261  case CortexA7:
263  break;
264  case CortexA8:
266  break;
267  case CortexA9:
270  break;
271  case CortexA12:
272  break;
273  case CortexA15:
277  break;
278  case CortexA17:
279  case CortexA32:
280  case CortexA35:
281  case CortexA53:
282  case CortexA55:
283  case CortexA57:
284  case CortexA72:
285  case CortexA73:
286  case CortexA75:
287  case CortexA76:
288  case CortexR4:
289  case CortexR4F:
290  case CortexR5:
291  case CortexR7:
292  case CortexM3:
293  case CortexR52:
294  break;
295  case Exynos:
298  if (!isThumb())
299  PrefLoopAlignment = 3;
300  break;
301  case Kryo:
302  break;
303  case Krait:
305  break;
306  case Swift:
311  break;
312  }
313 }
314 
316 
320 }
325 }
329 }
330 
331 bool ARMSubtarget::isROPI() const {
332  return TM.getRelocationModel() == Reloc::ROPI ||
334 }
335 bool ARMSubtarget::isRWPI() const {
336  return TM.getRelocationModel() == Reloc::RWPI ||
338 }
339 
341  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
342  return true;
343 
344  // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
345  // the section that is being relocated. This means we have to use o load even
346  // for GVs that are known to be local to the dso.
348  (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
349  return true;
350 
351  return false;
352 }
353 
354 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
355  return isTargetELF() && TM.isPositionIndependent() &&
356  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
357 }
358 
361 }
362 
364  // The MachineScheduler can increase register usage, so we use more high
365  // registers and end up with more T2 instructions that cannot be converted to
366  // T1 instructions. At least until we do better at converting to thumb1
367  // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
368  // Machine scheduler, relying on the DAG register pressure scheduler instead.
369  if (isMClass() && hasMinSize())
370  return false;
371  // Enable the MachineScheduler before register allocation for subtargets
372  // with the use-misched feature.
373  return useMachineScheduler();
374 }
375 
376 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
379  return false;
380  // Don't reschedule potential IT blocks.
381  return !isThumb1Only();
382 }
383 
385 
387  // For general targets, the prologue can grow when VFPs are allocated with
388  // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
389  // format which it's more important to get right.
390  return isTargetWatchABI() ||
392 }
393 
394 bool ARMSubtarget::useMovt() const {
395  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
396  // immediates as it is inherently position independent, and may be out of
397  // range otherwise.
398  return !NoMovt && hasV8MBaselineOps() &&
400 }
401 
403  // Enable fast-isel for any target, for testing only.
404  if (ForceFastISel)
405  return true;
406 
407  // Limit fast-isel to the targets that are or have been tested.
408  if (!hasV6Ops())
409  return false;
410 
411  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
412  return TM.Options.EnableFastISel &&
413  ((isTargetMachO() && !isThumb1Only()) ||
414  (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
415 }
416 
418  // The GPR register class has multiple possible allocation orders, with
419  // tradeoffs preferred by different sub-architectures and optimisation goals.
420  // The allocation orders are:
421  // 0: (the default tablegen order, not used)
422  // 1: r14, r0-r13
423  // 2: r0-r7
424  // 3: r0-r7, r12, lr, r8-r11
425  // Note that the register allocator will change this order so that
426  // callee-saved registers are used later, as they require extra work in the
427  // prologue/epilogue (though we sometimes override that).
428 
429  // For thumb1-only targets, only the low registers are allocatable.
430  if (isThumb1Only())
431  return 2;
432 
433  // Allocate low registers first, so we can select more 16-bit instructions.
434  // We also (in ignoreCSRForAllocationOrder) override the default behaviour
435  // with regards to callee-saved registers, because pushing extra registers is
436  // much cheaper (in terms of code size) than using high registers. After
437  // that, we allocate r12 (doesn't need to be saved), lr (saving it means we
438  // can return with the pop, don't need an extra "bx lr") and then the rest of
439  // the high registers.
440  if (isThumb2() && MF.getFunction().hasMinSize())
441  return 3;
442 
443  // Otherwise, allocate in the default order, using LR first because saving it
444  // allows a shorter epilogue sequence.
445  return 1;
446 }
447 
449  unsigned PhysReg) const {
450  // To minimize code size in Thumb2, we prefer the usage of low regs (lower
451  // cost per use) so we can use narrow encoding. By default, caller-saved
452  // registers (e.g. lr, r12) are always allocated first, regardless of
453  // their cost per use. When optForMinSize, we prefer the low regs even if
454  // they are CSR because usually push/pop can be folded into existing ones.
455  return isThumb2() && MF.getFunction().hasMinSize() &&
456  ARM::GPRRegClass.contains(PhysReg);
457 }
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:241
bool isDeclarationForLinker() const
Definition: GlobalValue.h:533
bool useMovt() const
unsigned MispredictPenalty
Definition: MCSchedule.h:297
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:453
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:482
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isThumb() const
Definition: ARMSubtarget.h:749
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
bool useFastISel() const
True if fast-isel is used.
setjmp/longjmp based exceptions
bool isTargetNaCl() const
Definition: ARMSubtarget.h:689
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:525
This class provides the information for the target register banks.
bool OptMinSize
OptMinSize - True if we&#39;re optimising for minimum code size, equal to the function attribute...
Definition: ARMSubtarget.h:476
bool hasV6Ops() const
Definition: ARMSubtarget.h:566
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
bool isThumb1Only() const
Definition: ARMSubtarget.h:751
const LegalizerInfo * getLegalizerInfo() const override
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:493
bool isTargetHardFloat() const
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:246
bool genExecuteOnly() const
Definition: ARMSubtarget.h:670
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:201
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:577
bool isTargetELF() const
Definition: ARMSubtarget.h:694
Holds all the information related to register banks.
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
bool hasARMOps() const
Definition: ARMSubtarget.h:601
bool hasV8Ops() const
Definition: ARMSubtarget.h:571
ExceptionHandling ExceptionModel
What exception model to use.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
bool hasCommonLinkage() const
Definition: GlobalValue.h:449
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:479
bool enableAtomicExpand() const override
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:124
bool isXRaySupported() const override
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:234
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:569
This class provides the information for the target register banks.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:684
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:469
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:687
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Container class for subtarget features.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:134
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:423
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
This file declares the targeting of the RegisterBankInfo class for ARM.
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
bool isMClass() const
Definition: ARMSubtarget.h:754
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:652
This file declares the targeting of the Machinelegalizer class for ARM.
bool useMachineScheduler() const
Definition: ARMSubtarget.h:746
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
unsigned getMispredictionPenalty() const
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
bool isAPCS_ABI() const
const CallLowering * getCallLowering() const override
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:651
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:989
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
ArchKind parseArch(StringRef Arch)
bool isTargetLinux() const
Definition: ARMSubtarget.h:688
const InstructionSelector * getInstructionSelector() const override
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
unsigned PrefLoopAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:472
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:485
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:747
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:491
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool useStride4VFPs() const
bool isROPI() const
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:627
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate IT block based on arch"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT, "arm-no-restrict-it", "Allow IT blocks based on ARMv7")))
Provides the logic to select generic machine instructions.
bool isThumb2() const
Definition: ARMSubtarget.h:752
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:682
bool isTargetIOS() const
Definition: ARMSubtarget.h:685
bool isPositionIndependent() const
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:237
TargetOptions Options
No exception support.
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:488
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:197
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:533
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:619
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:461
bool hasMinSize() const
Definition: ARMSubtarget.h:750
bool isTargetMachO() const
Definition: ARMSubtarget.h:695
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:465
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:129
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:576
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool isRWPI() const
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:121
bool isTargetWindows() const
Definition: ARMSubtarget.h:691
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:456
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
This file describes how to lower LLVM calls to machine code calls.
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:628
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
ITMode
bool isAAPCS_ABI() const
bool hasThumb2() const
Definition: ARMSubtarget.h:753
const RegisterBankInfo * getRegBankInfo() const override
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:442
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:458