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ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMISelLowering.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "llvm/ADT/Triple.h"
30 #include "llvm/MC/MCSchedule.h"
32 #include <memory>
33 #include <string>
34 
35 #define GET_SUBTARGETINFO_HEADER
36 #include "ARMGenSubtargetInfo.inc"
37 
38 namespace llvm {
39 
40 class ARMBaseTargetMachine;
41 class GlobalValue;
42 class StringRef;
43 
45 protected:
48 
76  };
79 
83  };
84  enum ARMArchEnum {
116  };
117 
118 public:
119  /// What kind of timing do load multiple/store multiple instructions have.
121  /// Can load/store 2 registers/cycle.
123  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
124  /// is not 64-bit aligned.
126  /// Can load/store 1 register/cycle.
128  /// Can load/store 1 register/cycle, but needs an extra cycle for address
129  /// computation and potentially also for register writeback.
131  };
132 
133 protected:
134  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
136 
137  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
139 
140  /// ARMArch - ARM architecture
142 
143  /// HasV4TOps, HasV5TOps, HasV5TEOps,
144  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
145  /// Specify whether target support specific ARM ISA variants.
146  bool HasV4TOps = false;
147  bool HasV5TOps = false;
148  bool HasV5TEOps = false;
149  bool HasV6Ops = false;
150  bool HasV6MOps = false;
151  bool HasV6KOps = false;
152  bool HasV6T2Ops = false;
153  bool HasV7Ops = false;
154  bool HasV8Ops = false;
155  bool HasV8_1aOps = false;
156  bool HasV8_2aOps = false;
157  bool HasV8_3aOps = false;
158  bool HasV8_4aOps = false;
159  bool HasV8_5aOps = false;
160  bool HasV8MBaselineOps = false;
161  bool HasV8MMainlineOps = false;
162  bool HasV8_1MMainlineOps = false;
163  bool HasMVEIntegerOps = false;
164  bool HasMVEFloatOps = false;
165 
166  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
167  /// floating point ISAs are supported.
168  bool HasVFPv2 = false;
169  bool HasVFPv3 = false;
170  bool HasVFPv4 = false;
171  bool HasFPARMv8 = false;
172  bool HasNEON = false;
173  bool HasFPRegs = false;
174  bool HasFPRegs16 = false;
175  bool HasFPRegs64 = false;
176 
177  /// Versions of the VFP flags restricted to single precision, or to
178  /// 16 d-registers, or both.
179  bool HasVFPv2SP = false;
180  bool HasVFPv3SP = false;
181  bool HasVFPv4SP = false;
182  bool HasFPARMv8SP = false;
183  bool HasVFPv2D16 = false;
184  bool HasVFPv3D16 = false;
185  bool HasVFPv4D16 = false;
186  bool HasFPARMv8D16 = false;
187  bool HasVFPv2D16SP = false;
188  bool HasVFPv3D16SP = false;
189  bool HasVFPv4D16SP = false;
190  bool HasFPARMv8D16SP = false;
191 
192  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
193  bool HasDotProd = false;
194 
195  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
196  /// specified. Use the method useNEONForSinglePrecisionFP() to
197  /// determine if NEON should actually be used.
199 
200  /// UseMulOps - True if non-microcoded fused integer multiply-add and
201  /// multiply-subtract instructions should be used.
202  bool UseMulOps = false;
203 
204  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
205  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
206  bool SlowFPVMLx = false;
207 
208  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
209  /// forwarding to allow mul + mla being issued back to back.
210  bool HasVMLxForwarding = false;
211 
212  /// SlowFPBrcc - True if floating point compare + branch is slow.
213  bool SlowFPBrcc = false;
214 
215  /// InThumbMode - True if compiling for Thumb, false for ARM.
216  bool InThumbMode = false;
217 
218  /// UseSoftFloat - True if we're using software floating point features.
219  bool UseSoftFloat = false;
220 
221  /// UseMISched - True if MachineScheduler should be used for this subtarget.
222  bool UseMISched = false;
223 
224  /// DisablePostRAScheduler - False if scheduling should happen again after
225  /// register allocation.
227 
228  /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
229  bool UseAA = false;
230 
231  /// HasThumb2 - True if Thumb2 instructions are supported.
232  bool HasThumb2 = false;
233 
234  /// NoARM - True if subtarget does not support ARM mode execution.
235  bool NoARM = false;
236 
237  /// ReserveR9 - True if R9 is not available as a general purpose register.
238  bool ReserveR9 = false;
239 
240  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
241  /// 32-bit imms (including global addresses).
242  bool NoMovt = false;
243 
244  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
245  /// must be able to synthesize call stubs for interworking between ARM and
246  /// Thumb.
247  bool SupportsTailCall = false;
248 
249  /// HasFP16 - True if subtarget supports half-precision FP conversions
250  bool HasFP16 = false;
251 
252  /// HasFullFP16 - True if subtarget supports half-precision FP operations
253  bool HasFullFP16 = false;
254 
255  /// HasFP16FML - True if subtarget supports half-precision FP fml operations
256  bool HasFP16FML = false;
257 
258  /// HasD32 - True if subtarget has the full 32 double precision
259  /// FP registers for VFPv3.
260  bool HasD32 = false;
261 
262  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
264 
265  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
267 
268  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
269  /// instructions.
270  bool HasDataBarrier = false;
271 
272  /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
273  /// instruction.
274  bool HasFullDataBarrier = false;
275 
276  /// HasV7Clrex - True if the subtarget supports CLREX instructions
277  bool HasV7Clrex = false;
278 
279  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
280  /// instructions
281  bool HasAcquireRelease = false;
282 
283  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
284  /// over 16-bit ones.
285  bool Pref32BitThumb = false;
286 
287  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
288  /// that partially update CPSR and add false dependency on the previous
289  /// CPSR setting instruction.
291 
292  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
293  /// for instructions updating CPSR. Enabled for Cortex-A57.
295 
296  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
297  /// movs with shifter operand (i.e. asr, lsl, lsr).
299 
300  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
301  /// avoid issue "normal" call instructions to callees which do not return.
302  bool HasRetAddrStack = false;
303 
304  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
305  /// a branch predictor or not changes the expected cost of taking a branch
306  /// which affects the choice of whether to use predicated instructions.
307  bool HasBranchPredictor = true;
308 
309  /// HasMPExtension - True if the subtarget supports Multiprocessing
310  /// extension (ARMv7 only).
311  bool HasMPExtension = false;
312 
313  /// HasVirtualization - True if the subtarget supports the Virtualization
314  /// extension.
315  bool HasVirtualization = false;
316 
317  /// HasFP64 - If true, the floating point unit supports double
318  /// precision.
319  bool HasFP64 = false;
320 
321  /// If true, the processor supports the Performance Monitor Extensions. These
322  /// include a generic cycle-counter as well as more fine-grained (often
323  /// implementation-specific) events.
324  bool HasPerfMon = false;
325 
326  /// HasTrustZone - if true, processor supports TrustZone security extensions
327  bool HasTrustZone = false;
328 
329  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
330  bool Has8MSecExt = false;
331 
332  /// HasSHA2 - if true, processor supports SHA1 and SHA256
333  bool HasSHA2 = false;
334 
335  /// HasAES - if true, processor supports AES
336  bool HasAES = false;
337 
338  /// HasCrypto - if true, processor supports Cryptography extensions
339  bool HasCrypto = false;
340 
341  /// HasCRC - if true, processor supports CRC instructions
342  bool HasCRC = false;
343 
344  /// HasRAS - if true, the processor supports RAS extensions
345  bool HasRAS = false;
346 
347  /// HasLOB - if true, the processor supports the Low Overhead Branch extension
348  bool HasLOB = false;
349 
350  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
351  /// particularly effective at zeroing a VFP register.
352  bool HasZeroCycleZeroing = false;
353 
354  /// HasFPAO - if true, processor does positive address offset computation faster
355  bool HasFPAO = false;
356 
357  /// HasFuseAES - if true, processor executes back to back AES instruction
358  /// pairs faster.
359  bool HasFuseAES = false;
360 
361  /// HasFuseLiterals - if true, processor executes back to back
362  /// bottom and top halves of literal generation faster.
363  bool HasFuseLiterals = false;
364 
365  /// If true, if conversion may decide to leave some instructions unpredicated.
367 
368  /// If true, VMOV will be favored over VGETLNi32.
369  bool HasSlowVGETLNi32 = false;
370 
371  /// If true, VMOV will be favored over VDUP.
372  bool HasSlowVDUP32 = false;
373 
374  /// If true, VMOVSR will be favored over VMOVDRR.
375  bool PreferVMOVSR = false;
376 
377  /// If true, ISHST barriers will be used for Release semantics.
378  bool PreferISHST = false;
379 
380  /// If true, a VLDM/VSTM starting with an odd register number is considered to
381  /// take more microops than single VLDRS/VSTRS.
382  bool SlowOddRegister = false;
383 
384  /// If true, loading into a D subregister will be penalized.
385  bool SlowLoadDSubregister = false;
386 
387  /// If true, use a wider stride when allocating VFP registers.
388  bool UseWideStrideVFP = false;
389 
390  /// If true, the AGU and NEON/FPU units are multiplexed.
391  bool HasMuxedUnits = false;
392 
393  /// If true, VMOVS will never be widened to VMOVD.
394  bool DontWidenVMOVS = false;
395 
396  /// If true, splat a register between VFP and NEON instructions.
397  bool SplatVFPToNeon = false;
398 
399  /// If true, run the MLx expansion pass.
400  bool ExpandMLx = false;
401 
402  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
403  bool HasVMLxHazards = false;
404 
405  // If true, read thread pointer from coprocessor register.
406  bool ReadTPHard = false;
407 
408  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
409  bool UseNEONForFPMovs = false;
410 
411  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
412  bool CheckVLDnAlign = false;
413 
414  /// If true, VFP instructions are not pipelined.
415  bool NonpipelinedVFP = false;
416 
417  /// StrictAlign - If true, the subtarget disallows unaligned memory
418  /// accesses for some types. For details, see
419  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
420  bool StrictAlign = false;
421 
422  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
423  /// blocks to conform to ARMv8 rule.
424  bool RestrictIT = false;
425 
426  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
427  /// and such) instructions.
428  bool HasDSP = false;
429 
430  /// NaCl TRAP instruction is generated instead of the regular TRAP.
431  bool UseNaClTrap = false;
432 
433  /// Generate calls via indirect call instructions.
434  bool GenLongCalls = false;
435 
436  /// Generate code that does not contain data access to code sections.
437  bool GenExecuteOnly = false;
438 
439  /// Target machine allowed unsafe FP math (such as use of NEON fp)
440  bool UnsafeFPMath = false;
441 
442  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
443  bool UseSjLjEH = false;
444 
445  /// Has speculation barrier
446  bool HasSB = false;
447 
448  /// Implicitly convert an instruction to a different one if its immediates
449  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
450  bool NegativeImmediates = true;
451 
452  /// stackAlignment - The minimum alignment known to hold of the stack frame on
453  /// entry to the function and which must be maintained by every function.
454  unsigned stackAlignment = 4;
455 
456  /// CPUString - String name of used CPU.
457  std::string CPUString;
458 
459  unsigned MaxInterleaveFactor = 1;
460 
461  /// Clearance before partial register updates (in number of instructions)
463 
464  /// What kind of timing do load multiple/store multiple have (double issue,
465  /// single issue etc).
467 
468  /// The adjustment that we need to apply to get the operand latency from the
469  /// operand cycle returned by the itinerary data for pre-ISel operands.
471 
472  /// What alignment is preferred for loop bodies, in log2(bytes).
473  unsigned PrefLoopAlignment = 0;
474 
475  /// The cost factor for MVE instructions, representing the multiple beats an
476  // instruction can take. The default is 2, (set in initSubtargetFeatures so
477  // that we can use subtarget features less than 2).
478  unsigned MVEVectorCostFactor = 0;
479 
480  /// OptMinSize - True if we're optimising for minimum code size, equal to
481  /// the function attribute.
482  bool OptMinSize = false;
483 
484  /// IsLittle - The target is Little Endian
485  bool IsLittle;
486 
487  /// TargetTriple - What processor and OS we're targeting.
489 
490  /// SchedModel - Processor specific instruction costs.
492 
493  /// Selected instruction itineraries (one entry per itinerary class.)
495 
496  /// Options passed via command line that could influence the target
498 
500 
501 public:
502  /// This constructor initializes the data members to match that
503  /// of the specified triple.
504  ///
505  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
506  const ARMBaseTargetMachine &TM, bool IsLittle,
507  bool MinSize = false);
508 
509  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
510  /// that still makes it profitable to inline the call.
511  unsigned getMaxInlineSizeThreshold() const {
512  return 64;
513  }
514 
515  /// ParseSubtargetFeatures - Parses features string setting specified
516  /// subtarget options. Definition of function is auto generated by tblgen.
518 
519  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
520  /// so that we can use initializer lists for subtarget initialization.
522 
523  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
524  return &TSInfo;
525  }
526 
527  const ARMBaseInstrInfo *getInstrInfo() const override {
528  return InstrInfo.get();
529  }
530 
531  const ARMTargetLowering *getTargetLowering() const override {
532  return &TLInfo;
533  }
534 
535  const ARMFrameLowering *getFrameLowering() const override {
536  return FrameLowering.get();
537  }
538 
539  const ARMBaseRegisterInfo *getRegisterInfo() const override {
540  return &InstrInfo->getRegisterInfo();
541  }
542 
543  const CallLowering *getCallLowering() const override;
545  const LegalizerInfo *getLegalizerInfo() const override;
546  const RegisterBankInfo *getRegBankInfo() const override;
547 
548 private:
549  ARMSelectionDAGInfo TSInfo;
550  // Either Thumb1FrameLowering or ARMFrameLowering.
551  std::unique_ptr<ARMFrameLowering> FrameLowering;
552  // Either Thumb1InstrInfo or Thumb2InstrInfo.
553  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
554  ARMTargetLowering TLInfo;
555 
556  /// GlobalISel related APIs.
557  std::unique_ptr<CallLowering> CallLoweringInfo;
558  std::unique_ptr<InstructionSelector> InstSelector;
559  std::unique_ptr<LegalizerInfo> Legalizer;
560  std::unique_ptr<RegisterBankInfo> RegBankInfo;
561 
562  void initializeEnvironment();
563  void initSubtargetFeatures(StringRef CPU, StringRef FS);
564  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
565 
566 public:
567  void computeIssueWidth();
568 
569  bool hasV4TOps() const { return HasV4TOps; }
570  bool hasV5TOps() const { return HasV5TOps; }
571  bool hasV5TEOps() const { return HasV5TEOps; }
572  bool hasV6Ops() const { return HasV6Ops; }
573  bool hasV6MOps() const { return HasV6MOps; }
574  bool hasV6KOps() const { return HasV6KOps; }
575  bool hasV6T2Ops() const { return HasV6T2Ops; }
576  bool hasV7Ops() const { return HasV7Ops; }
577  bool hasV8Ops() const { return HasV8Ops; }
578  bool hasV8_1aOps() const { return HasV8_1aOps; }
579  bool hasV8_2aOps() const { return HasV8_2aOps; }
580  bool hasV8_3aOps() const { return HasV8_3aOps; }
581  bool hasV8_4aOps() const { return HasV8_4aOps; }
582  bool hasV8_5aOps() const { return HasV8_5aOps; }
583  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
584  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
585  bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
586  bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
587  bool hasMVEFloatOps() const { return HasMVEFloatOps; }
588  bool hasFPRegs() const { return HasFPRegs; }
589  bool hasFPRegs16() const { return HasFPRegs16; }
590  bool hasFPRegs64() const { return HasFPRegs64; }
591 
592  /// @{
593  /// These functions are obsolete, please consider adding subtarget features
594  /// or properties instead of calling them.
595  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
596  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
597  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
598  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
599  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
600  bool isSwift() const { return ARMProcFamily == Swift; }
601  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
602  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
603  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
604  bool isKrait() const { return ARMProcFamily == Krait; }
605  /// @}
606 
607  bool hasARMOps() const { return !NoARM; }
608 
609  bool hasVFP2Base() const { return HasVFPv2D16SP; }
610  bool hasVFP3Base() const { return HasVFPv3D16SP; }
611  bool hasVFP4Base() const { return HasVFPv4D16SP; }
612  bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
613  bool hasNEON() const { return HasNEON; }
614  bool hasSHA2() const { return HasSHA2; }
615  bool hasAES() const { return HasAES; }
616  bool hasCrypto() const { return HasCrypto; }
617  bool hasDotProd() const { return HasDotProd; }
618  bool hasCRC() const { return HasCRC; }
619  bool hasRAS() const { return HasRAS; }
620  bool hasLOB() const { return HasLOB; }
621  bool hasVirtualization() const { return HasVirtualization; }
622 
625  }
626 
629  bool hasDataBarrier() const { return HasDataBarrier; }
630  bool hasFullDataBarrier() const { return HasFullDataBarrier; }
631  bool hasV7Clrex() const { return HasV7Clrex; }
632  bool hasAcquireRelease() const { return HasAcquireRelease; }
633 
634  bool hasAnyDataBarrier() const {
635  return HasDataBarrier || (hasV6Ops() && !isThumb());
636  }
637 
638  bool useMulOps() const { return UseMulOps; }
639  bool useFPVMLx() const { return !SlowFPVMLx; }
640  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
641  bool isFPBrccSlow() const { return SlowFPBrcc; }
642  bool hasFP64() const { return HasFP64; }
643  bool hasPerfMon() const { return HasPerfMon; }
644  bool hasTrustZone() const { return HasTrustZone; }
645  bool has8MSecExt() const { return Has8MSecExt; }
646  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
647  bool hasFPAO() const { return HasFPAO; }
649  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
650  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
651  bool preferVMOVSR() const { return PreferVMOVSR; }
652  bool preferISHSTBarriers() const { return PreferISHST; }
653  bool expandMLx() const { return ExpandMLx; }
654  bool hasVMLxHazards() const { return HasVMLxHazards; }
655  bool hasSlowOddRegister() const { return SlowOddRegister; }
657  bool useWideStrideVFP() const { return UseWideStrideVFP; }
658  bool hasMuxedUnits() const { return HasMuxedUnits; }
659  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
660  bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
661  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
662  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
663  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
664  bool prefers32BitThumb() const { return Pref32BitThumb; }
668  bool hasRetAddrStack() const { return HasRetAddrStack; }
669  bool hasBranchPredictor() const { return HasBranchPredictor; }
670  bool hasMPExtension() const { return HasMPExtension; }
671  bool hasDSP() const { return HasDSP; }
672  bool useNaClTrap() const { return UseNaClTrap; }
673  bool useSjLjEH() const { return UseSjLjEH; }
674  bool hasSB() const { return HasSB; }
675  bool genLongCalls() const { return GenLongCalls; }
676  bool genExecuteOnly() const { return GenExecuteOnly; }
677 
678  bool hasFP16() const { return HasFP16; }
679  bool hasD32() const { return HasD32; }
680  bool hasFullFP16() const { return HasFullFP16; }
681  bool hasFP16FML() const { return HasFP16FML; }
682 
683  bool hasFuseAES() const { return HasFuseAES; }
684  bool hasFuseLiterals() const { return HasFuseLiterals; }
685  /// Return true if the CPU supports any kind of instruction fusion.
686  bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
687 
688  const Triple &getTargetTriple() const { return TargetTriple; }
689 
690  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
691  bool isTargetIOS() const { return TargetTriple.isiOS(); }
692  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
693  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
694  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
695  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
696  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
697  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
698 
699  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
700  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
701  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
702 
703  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
704  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
705  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
706  // even for GNUEABI, so we can make a distinction here and still conform to
707  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
708  // FIXME: The Darwin exception is temporary, while we move users to
709  // "*-*-*-macho" triples as quickly as possible.
710  bool isTargetAEABI() const {
711  return (TargetTriple.getEnvironment() == Triple::EABI ||
712  TargetTriple.getEnvironment() == Triple::EABIHF) &&
714  }
715  bool isTargetGNUAEABI() const {
716  return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
717  TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
719  }
720  bool isTargetMuslAEABI() const {
721  return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
722  TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
724  }
725 
726  // ARM Targets that support EHABI exception handling standard
727  // Darwin uses SjLj. Other targets might need more checks.
728  bool isTargetEHABICompatible() const {
729  return (TargetTriple.getEnvironment() == Triple::EABI ||
730  TargetTriple.getEnvironment() == Triple::GNUEABI ||
731  TargetTriple.getEnvironment() == Triple::MuslEABI ||
732  TargetTriple.getEnvironment() == Triple::EABIHF ||
733  TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
734  TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
735  isTargetAndroid()) &&
737  }
738 
739  bool isTargetHardFloat() const;
740 
741  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
742 
743  bool isXRaySupported() const override;
744 
745  bool isAPCS_ABI() const;
746  bool isAAPCS_ABI() const;
747  bool isAAPCS16_ABI() const;
748 
749  bool isROPI() const;
750  bool isRWPI() const;
751 
752  bool useMachineScheduler() const { return UseMISched; }
754  bool useSoftFloat() const { return UseSoftFloat; }
755  bool isThumb() const { return InThumbMode; }
756  bool hasMinSize() const { return OptMinSize; }
757  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
758  bool isThumb2() const { return InThumbMode && HasThumb2; }
759  bool hasThumb2() const { return HasThumb2; }
760  bool isMClass() const { return ARMProcClass == MClass; }
761  bool isRClass() const { return ARMProcClass == RClass; }
762  bool isAClass() const { return ARMProcClass == AClass; }
763  bool isReadTPHard() const { return ReadTPHard; }
764 
765  bool isR9Reserved() const {
766  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
767  }
768 
769  bool useR7AsFramePointer() const {
770  return isTargetDarwin() || (!isTargetWindows() && isThumb());
771  }
772 
773  /// Returns true if the frame setup is split into two separate pushes (first
774  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
775  /// to lr. This is always required on Thumb1-only targets, as the push and
776  /// pop instructions can't access the high registers.
777  bool splitFramePushPop(const MachineFunction &MF) const {
778  return (useR7AsFramePointer() &&
780  isThumb1Only();
781  }
782 
783  bool useStride4VFPs() const;
784 
785  bool useMovt() const;
786 
787  bool supportsTailCall() const { return SupportsTailCall; }
788 
789  bool allowsUnalignedMem() const { return !StrictAlign; }
790 
791  bool restrictIT() const { return RestrictIT; }
792 
793  const std::string & getCPUString() const { return CPUString; }
794 
795  bool isLittle() const { return IsLittle; }
796 
797  unsigned getMispredictionPenalty() const;
798 
799  /// Returns true if machine scheduler should be enabled.
800  bool enableMachineScheduler() const override;
801 
802  /// True for some subtargets at > -O0.
803  bool enablePostRAScheduler() const override;
804 
805  /// Enable use of alias analysis during code generation (during MI
806  /// scheduling, DAGCombine, etc.).
807  bool useAA() const override { return UseAA; }
808 
809  // enableAtomicExpand- True if we need to expand our atomics.
810  bool enableAtomicExpand() const override;
811 
812  /// getInstrItins - Return the instruction itineraries based on subtarget
813  /// selection.
814  const InstrItineraryData *getInstrItineraryData() const override {
815  return &InstrItins;
816  }
817 
818  /// getStackAlignment - Returns the minimum alignment known to hold of the
819  /// stack frame on entry to the function and which must be maintained by every
820  /// function for this subtarget.
821  unsigned getStackAlignment() const { return stackAlignment; }
822 
823  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
824 
826 
828  return LdStMultipleTiming;
829  }
830 
833  }
834 
835  /// True if the GV will be accessed via an indirect symbol.
836  bool isGVIndirectSymbol(const GlobalValue *GV) const;
837 
838  /// Returns the constant pool modifier needed to access the GV.
839  bool isGVInGOT(const GlobalValue *GV) const;
840 
841  /// True if fast-isel is used.
842  bool useFastISel() const;
843 
844  /// Returns the correct return opcode for the current feature set.
845  /// Use BX if available to allow mixing thumb/arm code, but fall back
846  /// to plain mov pc,lr on ARMv4.
847  unsigned getReturnOpcode() const {
848  if (isThumb())
849  return ARM::tBX_RET;
850  if (hasV4TOps())
851  return ARM::BX_RET;
852  return ARM::MOVPCLR;
853  }
854 
855  /// Allow movt+movw for PIC global address calculation.
856  /// ELF does not have GOT relocations for movt+movw.
857  /// ROPI does not use GOT.
859  return isROPI() || !isTargetELF();
860  }
861 
862  unsigned getPrefLoopAlignment() const {
863  return PrefLoopAlignment;
864  }
865 
866  unsigned getMVEVectorCostFactor() const { return MVEVectorCostFactor; }
867 
869  unsigned PhysReg) const override;
870  unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
871 };
872 
873 } // end namespace llvm
874 
875 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:242
bool hasV5TEOps() const
Definition: ARMSubtarget.h:571
bool useMovt() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
bool hasCRC() const
Definition: ARMSubtarget.h:618
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition: ARMSubtarget.h:409
bool hasD32() const
Definition: ARMSubtarget.h:679
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:715
bool hasV8_2aOps() const
Definition: ARMSubtarget.h:579
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:454
bool ExpandMLx
If true, run the MLx expansion pass.
Definition: ARMSubtarget.h:400
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:488
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:662
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:665
bool HasBranchPredictor
HasBranchPredictor - True if the subtarget has a branch predictor.
Definition: ARMSubtarget.h:307
bool hasRAS() const
Definition: ARMSubtarget.h:619
bool hasSHA2() const
Definition: ARMSubtarget.h:614
bool isThumb() const
Definition: ARMSubtarget.h:755
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:627
bool SplatVFPToNeon
If true, splat a register between VFP and NEON instructions.
Definition: ARMSubtarget.h:397
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:206
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
Definition: ARMSubtarget.h:385
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:523
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
bool hasV4TOps() const
Definition: ARMSubtarget.h:569
bool isLittle() const
Definition: ARMSubtarget.h:795
bool useFastISel() const
True if fast-isel is used.
bool hasBranchPredictor() const
Definition: ARMSubtarget.h:669
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:302
bool isTargetNaCl() const
Definition: ARMSubtarget.h:695
bool hasFuseAES() const
Definition: ARMSubtarget.h:683
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:531
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition: ARMSubtarget.h:253
bool HasHardwareDivideInThumb
HasHardwareDivide - True if subtarget supports [su]div in Thumb mode.
Definition: ARMSubtarget.h:263
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
Definition: ARMSubtarget.h:372
bool preferVMOVSR() const
Definition: ARMSubtarget.h:651
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:581
bool hasV7Ops() const
Definition: ARMSubtarget.h:576
bool hasV8_5aOps() const
Definition: ARMSubtarget.h:582
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:664
bool isCortexA5() const
Definition: ARMSubtarget.h:595
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:472
bool isTargetCOFF() const
Definition: ARMSubtarget.h:699
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
Definition: ARMSubtarget.h:168
bool useNaClTrap() const
Definition: ARMSubtarget.h:672
bool OptMinSize
OptMinSize - True if we&#39;re optimising for minimum code size, equal to the function attribute...
Definition: ARMSubtarget.h:482
bool HasFP64
HasFP64 - If true, the floating point unit supports double precision.
Definition: ARMSubtarget.h:319
bool UseAA
UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
Definition: ARMSubtarget.h:229
bool hasV6Ops() const
Definition: ARMSubtarget.h:572
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:266
bool hasDotProd() const
Definition: ARMSubtarget.h:617
bool isThumb1Only() const
Definition: ARMSubtarget.h:757
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:720
bool hasAcquireRelease() const
Definition: ARMSubtarget.h:632
const LegalizerInfo * getLegalizerInfo() const override
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:667
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:499
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:434
bool isTargetHardFloat() const
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:696
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:247
bool hasSlowVDUP32() const
Definition: ARMSubtarget.h:650
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
Definition: ARMSubtarget.h:391
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
Definition: ARMSubtarget.h:369
bool isRClass() const
Definition: ARMSubtarget.h:761
bool genExecuteOnly() const
Definition: ARMSubtarget.h:676
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:823
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:202
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:527
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:583
bool isTargetELF() const
Definition: ARMSubtarget.h:700
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:127
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition: ARMSubtarget.h:330
Holds all the information related to register banks.
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
Definition: ARMSubtarget.h:345
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
bool hasARMOps() const
Definition: ARMSubtarget.h:607
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
Definition: ARMSubtarget.h:382
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:352
bool hasV8_4aOps() const
Definition: ARMSubtarget.h:581
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types...
Definition: ARMSubtarget.h:420
bool hasV8Ops() const
Definition: ARMSubtarget.h:577
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:232
bool HasFuseAES
HasFuseAES - if true, processor executes back to back AES instruction pairs faster.
Definition: ARMSubtarget.h:359
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:440
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:661
bool hasPerfMon() const
Definition: ARMSubtarget.h:643
bool hasFuseLiterals() const
Definition: ARMSubtarget.h:684
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
Definition: ARMSubtarget.h:394
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
Definition: ARMSubtarget.h:375
bool isReadTPHard() const
Definition: ARMSubtarget.h:763
bool isCortexM3() const
Definition: ARMSubtarget.h:601
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
Definition: ARMSubtarget.h:285
bool isCortexR5() const
Definition: ARMSubtarget.h:603
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:485
bool hasDSP() const
Definition: ARMSubtarget.h:671
bool useFPVMLx() const
Definition: ARMSubtarget.h:639
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:511
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:777
bool hasFullDataBarrier() const
Definition: ARMSubtarget.h:630
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:120
bool enableAtomicExpand() const override
bool hasVirtualization() const
Definition: ARMSubtarget.h:621
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:125
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:658
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isXRaySupported() const override
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:728
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:235
bool HasFuseLiterals
HasFuseLiterals - if true, processor executes back to back bottom and top halves of literal generatio...
Definition: ARMSubtarget.h:363
bool HasSB
Has speculation barrier.
Definition: ARMSubtarget.h:446
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:623
bool hasFPAO() const
Definition: ARMSubtarget.h:647
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:825
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:575
bool isTargetDarwin() const
Definition: ARMSubtarget.h:690
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:470
bool HasAES
HasAES - if true, processor supports AES.
Definition: ARMSubtarget.h:336
bool hasV6MOps() const
Definition: ARMSubtarget.h:573
Itinerary data supplied by a subtarget to be used by a target.
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:462
bool hasV8_1MMainlineOps() const
Definition: ARMSubtarget.h:585
bool NegativeImmediates
Implicitly convert an instruction to a different one if its immediates cannot be encoded.
Definition: ARMSubtarget.h:450
bool isOSNetBSD() const
Definition: Triple.h:493
bool isAClass() const
Definition: ARMSubtarget.h:762
bool hasFP16() const
Definition: ARMSubtarget.h:678
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:769
bool hasSB() const
Definition: ARMSubtarget.h:674
bool isR9Reserved() const
Definition: ARMSubtarget.h:765
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:324
bool hasSlowVGETLNi32() const
Definition: ARMSubtarget.h:649
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:628
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:693
bool HasD32
HasD32 - True if subtarget has the full 32 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:260
bool hasCrypto() const
Definition: ARMSubtarget.h:616
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:298
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:342
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:648
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition: ARMSubtarget.h:428
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition: ARMSubtarget.h:277
bool preferISHSTBarriers() const
Definition: ARMSubtarget.h:652
bool hasV6KOps() const
Definition: ARMSubtarget.h:574
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:315
bool has8MSecExt() const
Definition: ARMSubtarget.h:645
unsigned getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:821
bool restrictIT() const
Definition: ARMSubtarget.h:791
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:135
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:424
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:628
bool isMClass() const
Definition: ARMSubtarget.h:760
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
Definition: ARMSubtarget.h:366
bool isWatchABI() const
Definition: Triple.h:476
bool UseMISched
UseMISched - True if MachineScheduler should be used for this subtarget.
Definition: ARMSubtarget.h:222
bool useMachineScheduler() const
Definition: ARMSubtarget.h:752
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition: ARMSubtarget.h:146
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:210
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:692
bool DisablePostRAScheduler
DisablePostRAScheduler - False if scheduling should happen again after register allocation.
Definition: ARMSubtarget.h:226
bool HasVFPv2SP
Versions of the VFP flags restricted to single precision, or to 16 d-registers, or both...
Definition: ARMSubtarget.h:179
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition: ARMSubtarget.h:403
bool hasFPRegs16() const
Definition: ARMSubtarget.h:589
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:339
bool useMulOps() const
Definition: ARMSubtarget.h:638
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:663
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:656
unsigned getMispredictionPenalty() const
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
bool hasVFP2Base() const
Definition: ARMSubtarget.h:609
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:311
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:789
bool hasTrustZone() const
Definition: ARMSubtarget.h:644
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:535
bool hasSlowOddRegister() const
Definition: ARMSubtarget.h:655
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
bool HasDotProd
HasDotProd - True if the ARMv8.2A dot product instructions are supported.
Definition: ARMSubtarget.h:193
bool isAPCS_ABI() const
bool hasVFP3Base() const
Definition: ARMSubtarget.h:610
const CallLowering * getCallLowering() const override
unsigned getMVEVectorCostFactor() const
Definition: ARMSubtarget.h:866
bool useSjLjEH() const
Definition: ARMSubtarget.h:673
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
Definition: ARMSubtarget.h:415
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:827
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
bool hasV7Clrex() const
Definition: ARMSubtarget.h:631
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:657
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition: ARMSubtarget.h:250
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:327
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:216
bool hasAES() const
Definition: ARMSubtarget.h:615
const std::string & getCPUString() const
Definition: ARMSubtarget.h:793
bool isCortexA9() const
Definition: ARMSubtarget.h:598
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool hasFP64() const
Definition: ARMSubtarget.h:642
bool useSoftFloat() const
Definition: ARMSubtarget.h:754
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:612
bool isTargetAEABI() const
Definition: ARMSubtarget.h:710
bool isTargetLinux() const
Definition: ARMSubtarget.h:694
bool hasVFP4Base() const
Definition: ARMSubtarget.h:611
bool hasMVEFloatOps() const
Definition: ARMSubtarget.h:587
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:814
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:641
bool cheapPredicableCPSRDef() const
Definition: ARMSubtarget.h:666
bool isTargetAndroid() const
Definition: ARMSubtarget.h:741
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:141
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:858
bool hasMPExtension() const
Definition: ARMSubtarget.h:670
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:586
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:138
bool hasNEON() const
Definition: ARMSubtarget.h:613
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:314
bool UseWideStrideVFP
If true, use a wider stride when allocating VFP registers.
Definition: ARMSubtarget.h:388
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
Definition: ARMSubtarget.h:437
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:431
bool CheapPredicableCPSRDef
CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR...
Definition: ARMSubtarget.h:294
unsigned getPrefLoopAlignment() const
Definition: ARMSubtarget.h:862
bool hasFPRegs64() const
Definition: ARMSubtarget.h:590
unsigned PrefLoopAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:473
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:491
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
Definition: ARMSubtarget.h:378
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:753
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:497
bool genLongCalls() const
Definition: ARMSubtarget.h:675
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool useStride4VFPs() const
bool UseSoftFloat
UseSoftFloat - True if we&#39;re using software floating point features.
Definition: ARMSubtarget.h:219
bool isROPI() const
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:847
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:640
bool expandMLx() const
Definition: ARMSubtarget.h:653
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:578
Provides the logic to select generic machine instructions.
bool isThumb2() const
Definition: ARMSubtarget.h:758
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:688
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:646
bool hasRetAddrStack() const
Definition: ARMSubtarget.h:668
bool isTargetIOS() const
Definition: ARMSubtarget.h:691
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:238
TargetOptions Options
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:494
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:198
bool isCortexA7() const
Definition: ARMSubtarget.h:596
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:539
bool hasLOB() const
Definition: ARMSubtarget.h:620
bool hasFPRegs() const
Definition: ARMSubtarget.h:588
bool useSplatVFPToNeon() const
Definition: ARMSubtarget.h:660
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:462
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:831
bool hasV5TOps() const
Definition: ARMSubtarget.h:570
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool HasFP16FML
HasFP16FML - True if subtarget supports half-precision FP fml operations.
Definition: ARMSubtarget.h:256
bool hasVMLxHazards() const
Definition: ARMSubtarget.h:654
bool hasMinSize() const
Definition: ARMSubtarget.h:756
bool isTargetMachO() const
Definition: ARMSubtarget.h:701
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:478
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:213
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:466
bool isKrait() const
Definition: ARMSubtarget.h:604
bool isSwift() const
Definition: ARMSubtarget.h:600
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
bool supportsTailCall() const
Definition: ARMSubtarget.h:787
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:130
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:290
bool isCortexA8() const
Definition: ARMSubtarget.h:597
This file describes how to lower LLVM calls to machine code calls.
InstructionSelector * getInstructionSelector() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:661
bool hasMVEIntegerOps() const
Definition: ARMSubtarget.h:586
bool isRWPI() const
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:584
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:122
bool isTargetWindows() const
Definition: ARMSubtarget.h:697
bool HasFullDataBarrier
HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction. ...
Definition: ARMSubtarget.h:274
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:457
bool isCortexA15() const
Definition: ARMSubtarget.h:599
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition: ARMSubtarget.h:281
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:686
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:634
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
Definition: ARMSubtarget.h:807
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
Definition: ARMSubtarget.h:355
bool HasLOB
HasLOB - if true, the processor supports the Low Overhead Branch extension.
Definition: ARMSubtarget.h:348
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:270
bool isAAPCS_ABI() const
bool hasDataBarrier() const
Definition: ARMSubtarget.h:629
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
bool hasFP16FML() const
Definition: ARMSubtarget.h:681
bool hasThumb2() const
Definition: ARMSubtarget.h:759
bool isLikeA9() const
Definition: ARMSubtarget.h:602
const RegisterBankInfo * getRegBankInfo() const override
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition: ARMSubtarget.h:412
bool HasSHA2
HasSHA2 - if true, processor supports SHA1 and SHA256.
Definition: ARMSubtarget.h:333
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:443
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:659
bool hasFullFP16() const
Definition: ARMSubtarget.h:680
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:459
bool hasV8_3aOps() const
Definition: ARMSubtarget.h:580