LLVM  10.0.0svn
AntiDepBreaker.h
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1 //===- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AntiDepBreaker class, which implements
10 // anti-dependence breaking heuristics for post-register-allocation scheduling.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
15 #define LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
16 
22 #include "llvm/Support/Compiler.h"
23 #include <cassert>
24 #include <utility>
25 #include <vector>
26 
27 namespace llvm {
28 
29 /// This class works in conjunction with the post-RA scheduler to rename
30 /// registers to break register anti-dependencies (WAR hazards).
32 public:
33  using DbgValueVector =
34  std::vector<std::pair<MachineInstr *, MachineInstr *>>;
35 
36  virtual ~AntiDepBreaker();
37 
38  /// Initialize anti-dep breaking for a new basic block.
39  virtual void StartBlock(MachineBasicBlock *BB) = 0;
40 
41  /// Identifiy anti-dependencies within a basic-block region and break them by
42  /// renaming registers. Return the number of anti-dependencies broken.
43  virtual unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
46  unsigned InsertPosIndex,
47  DbgValueVector &DbgValues) = 0;
48 
49  /// Update liveness information to account for the current
50  /// instruction, which will not be scheduled.
51  virtual void Observe(MachineInstr &MI, unsigned Count,
52  unsigned InsertPosIndex) = 0;
53 
54  /// Finish anti-dep breaking for a basic block.
55  virtual void FinishBlock() = 0;
56 
57  /// Update DBG_VALUE if dependency breaker is updating
58  /// other machine instruction to use NewReg.
59  void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
60  assert(MI.isDebugValue() && "MI is not DBG_VALUE!");
61  if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
62  MI.getOperand(0).setReg(NewReg);
63  }
64 
65  /// Update all DBG_VALUE instructions that may be affected by the dependency
66  /// breaker's update of ParentMI to use NewReg.
67  void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
68  unsigned OldReg, unsigned NewReg) {
69  // The following code is dependent on the order in which the DbgValues are
70  // constructed in ScheduleDAGInstrs::buildSchedGraph.
71  MachineInstr *PrevDbgMI = nullptr;
72  for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) {
73  MachineInstr *PrevMI = DV.second;
74  if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) {
75  MachineInstr *DbgMI = DV.first;
76  UpdateDbgValue(*DbgMI, OldReg, NewReg);
77  PrevDbgMI = DbgMI;
78  } else if (PrevDbgMI) {
79  break; // If no match and already found a DBG_VALUE, we're done.
80  }
81  }
82  }
83 };
84 
85 } // end namespace llvm
86 
87 #endif // LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
void setReg(Register Reg)
Change the register this operand corresponds to.
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
Definition: Compiler.h:124
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isDebugValue() const
void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg)
Update DBG_VALUE if dependency breaker is updating other machine instruction to use NewReg...
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI, unsigned OldReg, unsigned NewReg)
Update all DBG_VALUE instructions that may be affected by the dependency breaker&#39;s update of ParentMI...
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416