LLVM  10.0.0svn
BPFAsmBackend.cpp
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1 //===-- BPFAsmBackend.cpp - BPF Assembler Backend -------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/ADT/StringRef.h"
11 #include "llvm/MC/MCAsmBackend.h"
12 #include "llvm/MC/MCAssembler.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCFixup.h"
15 #include "llvm/MC/MCObjectWriter.h"
17 #include <cassert>
18 #include <cstdint>
19 
20 using namespace llvm;
21 
22 namespace {
23 
24 class BPFAsmBackend : public MCAsmBackend {
25 public:
26  BPFAsmBackend(support::endianness Endian) : MCAsmBackend(Endian) {}
27  ~BPFAsmBackend() override = default;
28 
29  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
31  uint64_t Value, bool IsResolved,
32  const MCSubtargetInfo *STI) const override;
33 
34  std::unique_ptr<MCObjectTargetWriter>
35  createObjectTargetWriter() const override;
36 
37  // No instruction requires relaxation
38  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
39  const MCRelaxableFragment *DF,
40  const MCAsmLayout &Layout) const override {
41  return false;
42  }
43 
44  unsigned getNumFixupKinds() const override { return 1; }
45 
46  bool mayNeedRelaxation(const MCInst &Inst,
47  const MCSubtargetInfo &STI) const override {
48  return false;
49  }
50 
51  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
52  MCInst &Res) const override {}
53 
54  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
55 };
56 
57 } // end anonymous namespace
58 
59 bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
60  if ((Count % 8) != 0)
61  return false;
62 
63  for (uint64_t i = 0; i < Count; i += 8)
64  support::endian::write<uint64_t>(OS, 0x15000000, Endian);
65 
66  return true;
67 }
68 
69 void BPFAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
70  const MCValue &Target,
72  bool IsResolved,
73  const MCSubtargetInfo *STI) const {
74  if (Fixup.getKind() == FK_SecRel_4 || Fixup.getKind() == FK_SecRel_8) {
75  // The Value is 0 for global variables, and the in-section offset
76  // for static variables. Write to the immediate field of the inst.
77  assert(Value <= UINT32_MAX);
78  support::endian::write<uint32_t>(&Data[Fixup.getOffset() + 4],
79  static_cast<uint32_t>(Value),
80  Endian);
81  } else if (Fixup.getKind() == FK_Data_4) {
82  support::endian::write<uint32_t>(&Data[Fixup.getOffset()], Value, Endian);
83  } else if (Fixup.getKind() == FK_Data_8) {
84  support::endian::write<uint64_t>(&Data[Fixup.getOffset()], Value, Endian);
85  } else if (Fixup.getKind() == FK_PCRel_4) {
86  Value = (uint32_t)((Value - 8) / 8);
87  if (Endian == support::little) {
88  Data[Fixup.getOffset() + 1] = 0x10;
89  support::endian::write32le(&Data[Fixup.getOffset() + 4], Value);
90  } else {
91  Data[Fixup.getOffset() + 1] = 0x1;
92  support::endian::write32be(&Data[Fixup.getOffset() + 4], Value);
93  }
94  } else {
95  assert(Fixup.getKind() == FK_PCRel_2);
96  Value = (uint16_t)((Value - 8) / 8);
97  support::endian::write<uint16_t>(&Data[Fixup.getOffset() + 2], Value,
98  Endian);
99  }
100 }
101 
102 std::unique_ptr<MCObjectTargetWriter>
103 BPFAsmBackend::createObjectTargetWriter() const {
104  return createBPFELFObjectWriter(0);
105 }
106 
108  const MCSubtargetInfo &STI,
109  const MCRegisterInfo &MRI,
110  const MCTargetOptions &) {
111  return new BPFAsmBackend(support::little);
112 }
113 
115  const MCSubtargetInfo &STI,
116  const MCRegisterInfo &MRI,
117  const MCTargetOptions &) {
118  return new BPFAsmBackend(support::big);
119 }
void write32be(void *P, uint32_t V)
Definition: Endian.h:421
This class represents lattice values for constants.
Definition: AllocatorList.h:23
std::unique_ptr< MCObjectTargetWriter > createBPFELFObjectWriter(uint8_t OSABI)
This represents an "assembler immediate".
Definition: MCValue.h:39
void write32le(void *P, uint32_t V)
Definition: Endian.h:418
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:77
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
A four-byte section relative fixup.
Definition: MCFixup.h:43
A four-byte fixup.
Definition: MCFixup.h:26
MCAsmBackend * createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:272
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
uint32_t getOffset() const
Definition: MCFixup.h:130
A two-byte pc relative fixup.
Definition: MCFixup.h:30
A four-byte pc relative fixup.
Definition: MCFixup.h:31
MCAsmBackend * createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target - Wrapper for Target specific information.
A eight-byte section relative fixup.
Definition: MCFixup.h:44
Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:27
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:74
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
MCFixupKind getKind() const
Definition: MCFixup.h:126