LLVM 19.0.0git
CallLowering.cpp
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1//===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements some simple delegations needed for call lowering.
11///
12//===----------------------------------------------------------------------===//
13
23#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/LLVMContext.h"
26#include "llvm/IR/Module.h"
28
29#define DEBUG_TYPE "call-lowering"
30
31using namespace llvm;
32
33void CallLowering::anchor() {}
34
35/// Helper function which updates \p Flags when \p AttrFn returns true.
36static void
38 const std::function<bool(Attribute::AttrKind)> &AttrFn) {
39 if (AttrFn(Attribute::SExt))
40 Flags.setSExt();
41 if (AttrFn(Attribute::ZExt))
42 Flags.setZExt();
43 if (AttrFn(Attribute::InReg))
44 Flags.setInReg();
45 if (AttrFn(Attribute::StructRet))
46 Flags.setSRet();
47 if (AttrFn(Attribute::Nest))
48 Flags.setNest();
49 if (AttrFn(Attribute::ByVal))
50 Flags.setByVal();
51 if (AttrFn(Attribute::Preallocated))
52 Flags.setPreallocated();
53 if (AttrFn(Attribute::InAlloca))
54 Flags.setInAlloca();
55 if (AttrFn(Attribute::Returned))
56 Flags.setReturned();
57 if (AttrFn(Attribute::SwiftSelf))
58 Flags.setSwiftSelf();
59 if (AttrFn(Attribute::SwiftAsync))
60 Flags.setSwiftAsync();
61 if (AttrFn(Attribute::SwiftError))
62 Flags.setSwiftError();
63}
64
66 unsigned ArgIdx) const {
67 ISD::ArgFlagsTy Flags;
68 addFlagsUsingAttrFn(Flags, [&Call, &ArgIdx](Attribute::AttrKind Attr) {
69 return Call.paramHasAttr(ArgIdx, Attr);
70 });
71 return Flags;
72}
73
76 ISD::ArgFlagsTy Flags;
77 addFlagsUsingAttrFn(Flags, [&Call](Attribute::AttrKind Attr) {
78 return Call.hasRetAttr(Attr);
79 });
80 return Flags;
81}
82
84 const AttributeList &Attrs,
85 unsigned OpIdx) const {
86 addFlagsUsingAttrFn(Flags, [&Attrs, &OpIdx](Attribute::AttrKind Attr) {
87 return Attrs.hasAttributeAtIndex(OpIdx, Attr);
88 });
89}
90
92 ArrayRef<Register> ResRegs,
94 Register SwiftErrorVReg,
95 Register ConvergenceCtrlToken,
96 std::function<unsigned()> GetCalleeReg) const {
98 const DataLayout &DL = MIRBuilder.getDataLayout();
99 MachineFunction &MF = MIRBuilder.getMF();
101 bool CanBeTailCalled = CB.isTailCall() &&
103 (MF.getFunction()
104 .getFnAttribute("disable-tail-calls")
105 .getValueAsString() != "true");
106
107 CallingConv::ID CallConv = CB.getCallingConv();
108 Type *RetTy = CB.getType();
109 bool IsVarArg = CB.getFunctionType()->isVarArg();
110
112 getReturnInfo(CallConv, RetTy, CB.getAttributes(), SplitArgs, DL);
113 Info.CanLowerReturn = canLowerReturn(MF, CallConv, SplitArgs, IsVarArg);
114
115 Info.IsConvergent = CB.isConvergent();
116
117 if (!Info.CanLowerReturn) {
118 // Callee requires sret demotion.
119 insertSRetOutgoingArgument(MIRBuilder, CB, Info);
120
121 // The sret demotion isn't compatible with tail-calls, since the sret
122 // argument points into the caller's stack frame.
123 CanBeTailCalled = false;
124 }
125
126 // First step is to marshall all the function's parameters into the correct
127 // physregs and memory locations. Gather the sequence of argument types that
128 // we'll pass to the assigner function.
129 unsigned i = 0;
130 unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
131 for (const auto &Arg : CB.args()) {
132 ArgInfo OrigArg{ArgRegs[i], *Arg.get(), i, getAttributesForArgIdx(CB, i),
133 i < NumFixedArgs};
135
136 // If we have an explicit sret argument that is an Instruction, (i.e., it
137 // might point to function-local memory), we can't meaningfully tail-call.
138 if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg))
139 CanBeTailCalled = false;
140
141 Info.OrigArgs.push_back(OrigArg);
142 ++i;
143 }
144
145 // Try looking through a bitcast from one function type to another.
146 // Commonly happens with calls to objc_msgSend().
147 const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
148 if (const Function *F = dyn_cast<Function>(CalleeV)) {
149 if (F->hasFnAttribute(Attribute::NonLazyBind)) {
150 LLT Ty = getLLTForType(*F->getType(), DL);
151 Register Reg = MIRBuilder.buildGlobalValue(Ty, F).getReg(0);
152 Info.Callee = MachineOperand::CreateReg(Reg, false);
153 } else {
154 Info.Callee = MachineOperand::CreateGA(F, 0);
155 }
156 } else if (isa<GlobalIFunc>(CalleeV) || isa<GlobalAlias>(CalleeV)) {
157 // IR IFuncs and Aliases can't be forward declared (only defined), so the
158 // callee must be in the same TU and therefore we can direct-call it without
159 // worrying about it being out of range.
160 Info.Callee = MachineOperand::CreateGA(cast<GlobalValue>(CalleeV), 0);
161 } else
162 Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
163
164 Register ReturnHintAlignReg;
165 Align ReturnHintAlign;
166
167 Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, getAttributesForReturn(CB)};
168
169 if (!Info.OrigRet.Ty->isVoidTy()) {
171
172 if (MaybeAlign Alignment = CB.getRetAlign()) {
173 if (*Alignment > Align(1)) {
174 ReturnHintAlignReg = MRI.cloneVirtualRegister(ResRegs[0]);
175 Info.OrigRet.Regs[0] = ReturnHintAlignReg;
176 ReturnHintAlign = *Alignment;
177 }
178 }
179 }
180
181 auto Bundle = CB.getOperandBundle(LLVMContext::OB_kcfi);
182 if (Bundle && CB.isIndirectCall()) {
183 Info.CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
184 assert(Info.CFIType->getType()->isIntegerTy(32) && "Invalid CFI type");
185 }
186
187 Info.CB = &CB;
188 Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees);
189 Info.CallConv = CallConv;
190 Info.SwiftErrorVReg = SwiftErrorVReg;
191 Info.ConvergenceCtrlToken = ConvergenceCtrlToken;
192 Info.IsMustTailCall = CB.isMustTailCall();
193 Info.IsTailCall = CanBeTailCalled;
194 Info.IsVarArg = IsVarArg;
195 if (!lowerCall(MIRBuilder, Info))
196 return false;
197
198 if (ReturnHintAlignReg && !Info.LoweredTailCall) {
199 MIRBuilder.buildAssertAlign(ResRegs[0], ReturnHintAlignReg,
200 ReturnHintAlign);
201 }
202
203 return true;
204}
205
206template <typename FuncInfoTy>
208 const DataLayout &DL,
209 const FuncInfoTy &FuncInfo) const {
210 auto &Flags = Arg.Flags[0];
211 const AttributeList &Attrs = FuncInfo.getAttributes();
212 addArgFlagsFromAttributes(Flags, Attrs, OpIdx);
213
214 PointerType *PtrTy = dyn_cast<PointerType>(Arg.Ty->getScalarType());
215 if (PtrTy) {
216 Flags.setPointer();
217 Flags.setPointerAddrSpace(PtrTy->getPointerAddressSpace());
218 }
219
220 Align MemAlign = DL.getABITypeAlign(Arg.Ty);
221 if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated()) {
223 unsigned ParamIdx = OpIdx - AttributeList::FirstArgIndex;
224
225 Type *ElementTy = FuncInfo.getParamByValType(ParamIdx);
226 if (!ElementTy)
227 ElementTy = FuncInfo.getParamInAllocaType(ParamIdx);
228 if (!ElementTy)
229 ElementTy = FuncInfo.getParamPreallocatedType(ParamIdx);
230 assert(ElementTy && "Must have byval, inalloca or preallocated type");
231 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
232
233 // For ByVal, alignment should be passed from FE. BE will guess if
234 // this info is not there but there are cases it cannot get right.
235 if (auto ParamAlign = FuncInfo.getParamStackAlign(ParamIdx))
236 MemAlign = *ParamAlign;
237 else if ((ParamAlign = FuncInfo.getParamAlign(ParamIdx)))
238 MemAlign = *ParamAlign;
239 else
240 MemAlign = Align(getTLI()->getByValTypeAlignment(ElementTy, DL));
241 } else if (OpIdx >= AttributeList::FirstArgIndex) {
242 if (auto ParamAlign =
243 FuncInfo.getParamStackAlign(OpIdx - AttributeList::FirstArgIndex))
244 MemAlign = *ParamAlign;
245 }
246 Flags.setMemAlign(MemAlign);
247 Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
248
249 // Don't try to use the returned attribute if the argument is marked as
250 // swiftself, since it won't be passed in x0.
251 if (Flags.isSwiftSelf())
252 Flags.setReturned(false);
253}
254
255template void
256CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
257 const DataLayout &DL,
258 const Function &FuncInfo) const;
259
260template void
261CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
262 const DataLayout &DL,
263 const CallBase &FuncInfo) const;
264
266 SmallVectorImpl<ArgInfo> &SplitArgs,
267 const DataLayout &DL,
268 CallingConv::ID CallConv,
269 SmallVectorImpl<uint64_t> *Offsets) const {
270 LLVMContext &Ctx = OrigArg.Ty->getContext();
271
272 SmallVector<EVT, 4> SplitVTs;
273 ComputeValueVTs(*TLI, DL, OrigArg.Ty, SplitVTs, Offsets, 0);
274
275 if (SplitVTs.size() == 0)
276 return;
277
278 if (SplitVTs.size() == 1) {
279 // No splitting to do, but we want to replace the original type (e.g. [1 x
280 // double] -> double).
281 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
282 OrigArg.OrigArgIndex, OrigArg.Flags[0],
283 OrigArg.IsFixed, OrigArg.OrigValue);
284 return;
285 }
286
287 // Create one ArgInfo for each virtual register in the original ArgInfo.
288 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
289
290 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
291 OrigArg.Ty, CallConv, false, DL);
292 for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
293 Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
294 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex,
295 OrigArg.Flags[0], OrigArg.IsFixed);
296 if (NeedsRegBlock)
297 SplitArgs.back().Flags[0].setInConsecutiveRegs();
298 }
299
300 SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
301}
302
303/// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
306 ArrayRef<Register> SrcRegs) {
307 MachineRegisterInfo &MRI = *B.getMRI();
308 LLT LLTy = MRI.getType(DstRegs[0]);
309 LLT PartLLT = MRI.getType(SrcRegs[0]);
310
311 // Deal with v3s16 split into v2s16
312 LLT LCMTy = getCoverTy(LLTy, PartLLT);
313 if (LCMTy == LLTy) {
314 // Common case where no padding is needed.
315 assert(DstRegs.size() == 1);
316 return B.buildConcatVectors(DstRegs[0], SrcRegs);
317 }
318
319 // We need to create an unmerge to the result registers, which may require
320 // widening the original value.
321 Register UnmergeSrcReg;
322 if (LCMTy != PartLLT) {
323 assert(DstRegs.size() == 1);
324 return B.buildDeleteTrailingVectorElements(
325 DstRegs[0], B.buildMergeLikeInstr(LCMTy, SrcRegs));
326 } else {
327 // We don't need to widen anything if we're extracting a scalar which was
328 // promoted to a vector e.g. s8 -> v4s8 -> s8
329 assert(SrcRegs.size() == 1);
330 UnmergeSrcReg = SrcRegs[0];
331 }
332
333 int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
334
335 SmallVector<Register, 8> PadDstRegs(NumDst);
336 std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());
337
338 // Create the excess dead defs for the unmerge.
339 for (int I = DstRegs.size(); I != NumDst; ++I)
340 PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);
341
342 if (PadDstRegs.size() == 1)
343 return B.buildDeleteTrailingVectorElements(DstRegs[0], UnmergeSrcReg);
344 return B.buildUnmerge(PadDstRegs, UnmergeSrcReg);
345}
346
347/// Create a sequence of instructions to combine pieces split into register
348/// typed values to the original IR value. \p OrigRegs contains the destination
349/// value registers of type \p LLTy, and \p Regs contains the legalized pieces
350/// with type \p PartLLT. This is used for incoming values (physregs to vregs).
352 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT,
353 const ISD::ArgFlagsTy Flags) {
354 MachineRegisterInfo &MRI = *B.getMRI();
355
356 if (PartLLT == LLTy) {
357 // We should have avoided introducing a new virtual register, and just
358 // directly assigned here.
359 assert(OrigRegs[0] == Regs[0]);
360 return;
361 }
362
363 if (PartLLT.getSizeInBits() == LLTy.getSizeInBits() && OrigRegs.size() == 1 &&
364 Regs.size() == 1) {
365 B.buildBitcast(OrigRegs[0], Regs[0]);
366 return;
367 }
368
369 // A vector PartLLT needs extending to LLTy's element size.
370 // E.g. <2 x s64> = G_SEXT <2 x s32>.
371 if (PartLLT.isVector() == LLTy.isVector() &&
372 PartLLT.getScalarSizeInBits() > LLTy.getScalarSizeInBits() &&
373 (!PartLLT.isVector() ||
374 PartLLT.getElementCount() == LLTy.getElementCount()) &&
375 OrigRegs.size() == 1 && Regs.size() == 1) {
376 Register SrcReg = Regs[0];
377
378 LLT LocTy = MRI.getType(SrcReg);
379
380 if (Flags.isSExt()) {
381 SrcReg = B.buildAssertSExt(LocTy, SrcReg, LLTy.getScalarSizeInBits())
382 .getReg(0);
383 } else if (Flags.isZExt()) {
384 SrcReg = B.buildAssertZExt(LocTy, SrcReg, LLTy.getScalarSizeInBits())
385 .getReg(0);
386 }
387
388 // Sometimes pointers are passed zero extended.
389 LLT OrigTy = MRI.getType(OrigRegs[0]);
390 if (OrigTy.isPointer()) {
391 LLT IntPtrTy = LLT::scalar(OrigTy.getSizeInBits());
392 B.buildIntToPtr(OrigRegs[0], B.buildTrunc(IntPtrTy, SrcReg));
393 return;
394 }
395
396 B.buildTrunc(OrigRegs[0], SrcReg);
397 return;
398 }
399
400 if (!LLTy.isVector() && !PartLLT.isVector()) {
401 assert(OrigRegs.size() == 1);
402 LLT OrigTy = MRI.getType(OrigRegs[0]);
403
404 unsigned SrcSize = PartLLT.getSizeInBits().getFixedValue() * Regs.size();
405 if (SrcSize == OrigTy.getSizeInBits())
406 B.buildMergeValues(OrigRegs[0], Regs);
407 else {
408 auto Widened = B.buildMergeLikeInstr(LLT::scalar(SrcSize), Regs);
409 B.buildTrunc(OrigRegs[0], Widened);
410 }
411
412 return;
413 }
414
415 if (PartLLT.isVector()) {
416 assert(OrigRegs.size() == 1);
417 SmallVector<Register> CastRegs(Regs.begin(), Regs.end());
418
419 // If PartLLT is a mismatched vector in both number of elements and element
420 // size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
421 // have the same elt type, i.e. v4s32.
422 // TODO: Extend this coersion to element multiples other than just 2.
423 if (TypeSize::isKnownGT(PartLLT.getSizeInBits(), LLTy.getSizeInBits()) &&
424 PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
425 Regs.size() == 1) {
426 LLT NewTy = PartLLT.changeElementType(LLTy.getElementType())
427 .changeElementCount(PartLLT.getElementCount() * 2);
428 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0);
429 PartLLT = NewTy;
430 }
431
432 if (LLTy.getScalarType() == PartLLT.getElementType()) {
433 mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
434 } else {
435 unsigned I = 0;
436 LLT GCDTy = getGCDType(LLTy, PartLLT);
437
438 // We are both splitting a vector, and bitcasting its element types. Cast
439 // the source pieces into the appropriate number of pieces with the result
440 // element type.
441 for (Register SrcReg : CastRegs)
442 CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0);
443 mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
444 }
445
446 return;
447 }
448
449 assert(LLTy.isVector() && !PartLLT.isVector());
450
451 LLT DstEltTy = LLTy.getElementType();
452
453 // Pointer information was discarded. We'll need to coerce some register types
454 // to avoid violating type constraints.
455 LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType();
456
457 assert(DstEltTy.getSizeInBits() == RealDstEltTy.getSizeInBits());
458
459 if (DstEltTy == PartLLT) {
460 // Vector was trivially scalarized.
461
462 if (RealDstEltTy.isPointer()) {
463 for (Register Reg : Regs)
464 MRI.setType(Reg, RealDstEltTy);
465 }
466
467 B.buildBuildVector(OrigRegs[0], Regs);
468 } else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {
469 // Deal with vector with 64-bit elements decomposed to 32-bit
470 // registers. Need to create intermediate 64-bit elements.
471 SmallVector<Register, 8> EltMerges;
472 int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();
473
474 assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
475
476 for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
477 auto Merge =
478 B.buildMergeLikeInstr(RealDstEltTy, Regs.take_front(PartsPerElt));
479 // Fix the type in case this is really a vector of pointers.
480 MRI.setType(Merge.getReg(0), RealDstEltTy);
481 EltMerges.push_back(Merge.getReg(0));
482 Regs = Regs.drop_front(PartsPerElt);
483 }
484
485 B.buildBuildVector(OrigRegs[0], EltMerges);
486 } else {
487 // Vector was split, and elements promoted to a wider type.
488 // FIXME: Should handle floating point promotions.
489 unsigned NumElts = LLTy.getNumElements();
490 LLT BVType = LLT::fixed_vector(NumElts, PartLLT);
491
492 Register BuildVec;
493 if (NumElts == Regs.size())
494 BuildVec = B.buildBuildVector(BVType, Regs).getReg(0);
495 else {
496 // Vector elements are packed in the inputs.
497 // e.g. we have a <4 x s16> but 2 x s32 in regs.
498 assert(NumElts > Regs.size());
499 LLT SrcEltTy = MRI.getType(Regs[0]);
500
501 LLT OriginalEltTy = MRI.getType(OrigRegs[0]).getElementType();
502
503 // Input registers contain packed elements.
504 // Determine how many elements per reg.
505 assert((SrcEltTy.getSizeInBits() % OriginalEltTy.getSizeInBits()) == 0);
506 unsigned EltPerReg =
507 (SrcEltTy.getSizeInBits() / OriginalEltTy.getSizeInBits());
508
510 BVRegs.reserve(Regs.size() * EltPerReg);
511 for (Register R : Regs) {
512 auto Unmerge = B.buildUnmerge(OriginalEltTy, R);
513 for (unsigned K = 0; K < EltPerReg; ++K)
514 BVRegs.push_back(B.buildAnyExt(PartLLT, Unmerge.getReg(K)).getReg(0));
515 }
516
517 // We may have some more elements in BVRegs, e.g. if we have 2 s32 pieces
518 // for a <3 x s16> vector. We should have less than EltPerReg extra items.
519 if (BVRegs.size() > NumElts) {
520 assert((BVRegs.size() - NumElts) < EltPerReg);
521 BVRegs.truncate(NumElts);
522 }
523 BuildVec = B.buildBuildVector(BVType, BVRegs).getReg(0);
524 }
525 B.buildTrunc(OrigRegs[0], BuildVec);
526 }
527}
528
529/// Create a sequence of instructions to expand the value in \p SrcReg (of type
530/// \p SrcTy) to the types in \p DstRegs (of type \p PartTy). \p ExtendOp should
531/// contain the type of scalar value extension if necessary.
532///
533/// This is used for outgoing values (vregs to physregs)
535 Register SrcReg, LLT SrcTy, LLT PartTy,
536 unsigned ExtendOp = TargetOpcode::G_ANYEXT) {
537 // We could just insert a regular copy, but this is unreachable at the moment.
538 assert(SrcTy != PartTy && "identical part types shouldn't reach here");
539
540 const TypeSize PartSize = PartTy.getSizeInBits();
541
542 if (PartTy.isVector() == SrcTy.isVector() &&
543 PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
544 assert(DstRegs.size() == 1);
545 B.buildInstr(ExtendOp, {DstRegs[0]}, {SrcReg});
546 return;
547 }
548
549 if (SrcTy.isVector() && !PartTy.isVector() &&
550 TypeSize::isKnownGT(PartSize, SrcTy.getElementType().getSizeInBits())) {
551 // Vector was scalarized, and the elements extended.
552 auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
553 for (int i = 0, e = DstRegs.size(); i != e; ++i)
554 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
555 return;
556 }
557
558 if (SrcTy.isVector() && PartTy.isVector() &&
559 PartTy.getSizeInBits() == SrcTy.getSizeInBits() &&
561 PartTy.getElementCount())) {
562 // A coercion like: v2f32 -> v4f32 or nxv2f32 -> nxv4f32
563 Register DstReg = DstRegs.front();
564 B.buildPadVectorWithUndefElements(DstReg, SrcReg);
565 return;
566 }
567
568 LLT GCDTy = getGCDType(SrcTy, PartTy);
569 if (GCDTy == PartTy) {
570 // If this already evenly divisible, we can create a simple unmerge.
571 B.buildUnmerge(DstRegs, SrcReg);
572 return;
573 }
574
575 MachineRegisterInfo &MRI = *B.getMRI();
576 LLT DstTy = MRI.getType(DstRegs[0]);
577 LLT LCMTy = getCoverTy(SrcTy, PartTy);
578
579 if (PartTy.isVector() && LCMTy == PartTy) {
580 assert(DstRegs.size() == 1);
581 B.buildPadVectorWithUndefElements(DstRegs[0], SrcReg);
582 return;
583 }
584
585 const unsigned DstSize = DstTy.getSizeInBits();
586 const unsigned SrcSize = SrcTy.getSizeInBits();
587 unsigned CoveringSize = LCMTy.getSizeInBits();
588
589 Register UnmergeSrc = SrcReg;
590
591 if (!LCMTy.isVector() && CoveringSize != SrcSize) {
592 // For scalars, it's common to be able to use a simple extension.
593 if (SrcTy.isScalar() && DstTy.isScalar()) {
594 CoveringSize = alignTo(SrcSize, DstSize);
595 LLT CoverTy = LLT::scalar(CoveringSize);
596 UnmergeSrc = B.buildInstr(ExtendOp, {CoverTy}, {SrcReg}).getReg(0);
597 } else {
598 // Widen to the common type.
599 // FIXME: This should respect the extend type
600 Register Undef = B.buildUndef(SrcTy).getReg(0);
601 SmallVector<Register, 8> MergeParts(1, SrcReg);
602 for (unsigned Size = SrcSize; Size != CoveringSize; Size += SrcSize)
603 MergeParts.push_back(Undef);
604 UnmergeSrc = B.buildMergeLikeInstr(LCMTy, MergeParts).getReg(0);
605 }
606 }
607
608 if (LCMTy.isVector() && CoveringSize != SrcSize)
609 UnmergeSrc = B.buildPadVectorWithUndefElements(LCMTy, SrcReg).getReg(0);
610
611 B.buildUnmerge(DstRegs, UnmergeSrc);
612}
613
615 ValueHandler &Handler, ValueAssigner &Assigner,
617 CallingConv::ID CallConv, bool IsVarArg,
618 ArrayRef<Register> ThisReturnRegs) const {
619 MachineFunction &MF = MIRBuilder.getMF();
620 const Function &F = MF.getFunction();
622
623 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
624 if (!determineAssignments(Assigner, Args, CCInfo))
625 return false;
626
627 return handleAssignments(Handler, Args, CCInfo, ArgLocs, MIRBuilder,
628 ThisReturnRegs);
629}
630
632 if (Flags.isSExt())
633 return TargetOpcode::G_SEXT;
634 if (Flags.isZExt())
635 return TargetOpcode::G_ZEXT;
636 return TargetOpcode::G_ANYEXT;
637}
638
641 CCState &CCInfo) const {
642 LLVMContext &Ctx = CCInfo.getContext();
643 const CallingConv::ID CallConv = CCInfo.getCallingConv();
644
645 unsigned NumArgs = Args.size();
646 for (unsigned i = 0; i != NumArgs; ++i) {
647 EVT CurVT = EVT::getEVT(Args[i].Ty);
648
649 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT);
650
651 // If we need to split the type over multiple regs, check it's a scenario
652 // we currently support.
653 unsigned NumParts =
654 TLI->getNumRegistersForCallingConv(Ctx, CallConv, CurVT);
655
656 if (NumParts == 1) {
657 // Try to use the register type if we couldn't assign the VT.
658 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i],
659 Args[i].Flags[0], CCInfo))
660 return false;
661 continue;
662 }
663
664 // For incoming arguments (physregs to vregs), we could have values in
665 // physregs (or memlocs) which we want to extract and copy to vregs.
666 // During this, we might have to deal with the LLT being split across
667 // multiple regs, so we have to record this information for later.
668 //
669 // If we have outgoing args, then we have the opposite case. We have a
670 // vreg with an LLT which we want to assign to a physical location, and
671 // we might have to record that the value has to be split later.
672
673 // We're handling an incoming arg which is split over multiple regs.
674 // E.g. passing an s128 on AArch64.
675 ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
676 Args[i].Flags.clear();
677
678 for (unsigned Part = 0; Part < NumParts; ++Part) {
679 ISD::ArgFlagsTy Flags = OrigFlags;
680 if (Part == 0) {
681 Flags.setSplit();
682 } else {
683 Flags.setOrigAlign(Align(1));
684 if (Part == NumParts - 1)
685 Flags.setSplitEnd();
686 }
687
688 Args[i].Flags.push_back(Flags);
689 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i],
690 Args[i].Flags[Part], CCInfo)) {
691 // Still couldn't assign this smaller part type for some reason.
692 return false;
693 }
694 }
695 }
696
697 return true;
698}
699
702 CCState &CCInfo,
704 MachineIRBuilder &MIRBuilder,
705 ArrayRef<Register> ThisReturnRegs) const {
706 MachineFunction &MF = MIRBuilder.getMF();
708 const Function &F = MF.getFunction();
709 const DataLayout &DL = F.getParent()->getDataLayout();
710
711 const unsigned NumArgs = Args.size();
712
713 // Stores thunks for outgoing register assignments. This is used so we delay
714 // generating register copies until mem loc assignments are done. We do this
715 // so that if the target is using the delayed stack protector feature, we can
716 // find the split point of the block accurately. E.g. if we have:
717 // G_STORE %val, %memloc
718 // $x0 = COPY %foo
719 // $x1 = COPY %bar
720 // CALL func
721 // ... then the split point for the block will correctly be at, and including,
722 // the copy to $x0. If instead the G_STORE instruction immediately precedes
723 // the CALL, then we'd prematurely choose the CALL as the split point, thus
724 // generating a split block with a CALL that uses undefined physregs.
725 SmallVector<std::function<void()>> DelayedOutgoingRegAssignments;
726
727 for (unsigned i = 0, j = 0; i != NumArgs; ++i, ++j) {
728 assert(j < ArgLocs.size() && "Skipped too many arg locs");
729 CCValAssign &VA = ArgLocs[j];
730 assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
731
732 if (VA.needsCustom()) {
733 std::function<void()> Thunk;
734 unsigned NumArgRegs = Handler.assignCustomValue(
735 Args[i], ArrayRef(ArgLocs).slice(j), &Thunk);
736 if (Thunk)
737 DelayedOutgoingRegAssignments.emplace_back(Thunk);
738 if (!NumArgRegs)
739 return false;
740 j += (NumArgRegs - 1);
741 continue;
742 }
743
744 const MVT ValVT = VA.getValVT();
745 const MVT LocVT = VA.getLocVT();
746
747 const LLT LocTy(LocVT);
748 const LLT ValTy(ValVT);
749 const LLT NewLLT = Handler.isIncomingArgumentHandler() ? LocTy : ValTy;
750 const EVT OrigVT = EVT::getEVT(Args[i].Ty);
751 const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
752
753 // Expected to be multiple regs for a single incoming arg.
754 // There should be Regs.size() ArgLocs per argument.
755 // This should be the same as getNumRegistersForCallingConv
756 const unsigned NumParts = Args[i].Flags.size();
757
758 // Now split the registers into the assigned types.
759 Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end());
760
761 if (NumParts != 1 || NewLLT != OrigTy) {
762 // If we can't directly assign the register, we need one or more
763 // intermediate values.
764 Args[i].Regs.resize(NumParts);
765
766 // For each split register, create and assign a vreg that will store
767 // the incoming component of the larger value. These will later be
768 // merged to form the final vreg.
769 for (unsigned Part = 0; Part < NumParts; ++Part)
770 Args[i].Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);
771 }
772
773 assert((j + (NumParts - 1)) < ArgLocs.size() &&
774 "Too many regs for number of args");
775
776 // Coerce into outgoing value types before register assignment.
777 if (!Handler.isIncomingArgumentHandler() && OrigTy != ValTy) {
778 assert(Args[i].OrigRegs.size() == 1);
779 buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,
780 ValTy, extendOpFromFlags(Args[i].Flags[0]));
781 }
782
783 bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
784 for (unsigned Part = 0; Part < NumParts; ++Part) {
785 Register ArgReg = Args[i].Regs[Part];
786 // There should be Regs.size() ArgLocs per argument.
787 unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
788 CCValAssign &VA = ArgLocs[j + Idx];
789 const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
790
791 if (VA.isMemLoc() && !Flags.isByVal()) {
792 // Individual pieces may have been spilled to the stack and others
793 // passed in registers.
794
795 // TODO: The memory size may be larger than the value we need to
796 // store. We may need to adjust the offset for big endian targets.
797 LLT MemTy = Handler.getStackValueStoreType(DL, VA, Flags);
798
800 Register StackAddr = Handler.getStackAddress(
801 MemTy.getSizeInBytes(), VA.getLocMemOffset(), MPO, Flags);
802
803 Handler.assignValueToAddress(Args[i], Part, StackAddr, MemTy, MPO, VA);
804 continue;
805 }
806
807 if (VA.isMemLoc() && Flags.isByVal()) {
808 assert(Args[i].Regs.size() == 1 &&
809 "didn't expect split byval pointer");
810
811 if (Handler.isIncomingArgumentHandler()) {
812 // We just need to copy the frame index value to the pointer.
814 Register StackAddr = Handler.getStackAddress(
815 Flags.getByValSize(), VA.getLocMemOffset(), MPO, Flags);
816 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);
817 } else {
818 // For outgoing byval arguments, insert the implicit copy byval
819 // implies, such that writes in the callee do not modify the caller's
820 // value.
821 uint64_t MemSize = Flags.getByValSize();
822 int64_t Offset = VA.getLocMemOffset();
823
824 MachinePointerInfo DstMPO;
825 Register StackAddr =
826 Handler.getStackAddress(MemSize, Offset, DstMPO, Flags);
827
828 MachinePointerInfo SrcMPO(Args[i].OrigValue);
829 if (!Args[i].OrigValue) {
830 // We still need to accurately track the stack address space if we
831 // don't know the underlying value.
832 const LLT PtrTy = MRI.getType(StackAddr);
833 SrcMPO = MachinePointerInfo(PtrTy.getAddressSpace());
834 }
835
836 Align DstAlign = std::max(Flags.getNonZeroByValAlign(),
837 inferAlignFromPtrInfo(MF, DstMPO));
838
839 Align SrcAlign = std::max(Flags.getNonZeroByValAlign(),
840 inferAlignFromPtrInfo(MF, SrcMPO));
841
842 Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],
843 DstMPO, DstAlign, SrcMPO, SrcAlign,
844 MemSize, VA);
845 }
846 continue;
847 }
848
849 assert(!VA.needsCustom() && "custom loc should have been handled already");
850
851 if (i == 0 && !ThisReturnRegs.empty() &&
852 Handler.isIncomingArgumentHandler() &&
854 Handler.assignValueToReg(ArgReg, ThisReturnRegs[Part], VA);
855 continue;
856 }
857
858 if (Handler.isIncomingArgumentHandler())
859 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
860 else {
861 DelayedOutgoingRegAssignments.emplace_back([=, &Handler]() {
862 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
863 });
864 }
865 }
866
867 // Now that all pieces have been assigned, re-pack the register typed values
868 // into the original value typed registers.
869 if (Handler.isIncomingArgumentHandler() && OrigVT != LocVT) {
870 // Merge the split registers into the expected larger result vregs of
871 // the original call.
872 buildCopyFromRegs(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,
873 LocTy, Args[i].Flags[0]);
874 }
875
876 j += NumParts - 1;
877 }
878 for (auto &Fn : DelayedOutgoingRegAssignments)
879 Fn();
880
881 return true;
882}
883
885 ArrayRef<Register> VRegs, Register DemoteReg,
886 int FI) const {
887 MachineFunction &MF = MIRBuilder.getMF();
889 const DataLayout &DL = MF.getDataLayout();
890
891 SmallVector<EVT, 4> SplitVTs;
893 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
894
895 assert(VRegs.size() == SplitVTs.size());
896
897 unsigned NumValues = SplitVTs.size();
898 Align BaseAlign = DL.getPrefTypeAlign(RetTy);
899 Type *RetPtrTy =
900 PointerType::get(RetTy->getContext(), DL.getAllocaAddrSpace());
901 LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetPtrTy), DL);
902
904
905 for (unsigned I = 0; I < NumValues; ++I) {
907 MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
908 auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
909 MRI.getType(VRegs[I]),
910 commonAlignment(BaseAlign, Offsets[I]));
911 MIRBuilder.buildLoad(VRegs[I], Addr, *MMO);
912 }
913}
914
916 ArrayRef<Register> VRegs,
917 Register DemoteReg) const {
918 MachineFunction &MF = MIRBuilder.getMF();
920 const DataLayout &DL = MF.getDataLayout();
921
922 SmallVector<EVT, 4> SplitVTs;
924 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
925
926 assert(VRegs.size() == SplitVTs.size());
927
928 unsigned NumValues = SplitVTs.size();
929 Align BaseAlign = DL.getPrefTypeAlign(RetTy);
930 unsigned AS = DL.getAllocaAddrSpace();
931 LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetTy->getPointerTo(AS)), DL);
932
933 MachinePointerInfo PtrInfo(AS);
934
935 for (unsigned I = 0; I < NumValues; ++I) {
937 MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
938 auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
939 MRI.getType(VRegs[I]),
940 commonAlignment(BaseAlign, Offsets[I]));
941 MIRBuilder.buildStore(VRegs[I], Addr, *MMO);
942 }
943}
944
946 const Function &F, SmallVectorImpl<ArgInfo> &SplitArgs, Register &DemoteReg,
947 MachineRegisterInfo &MRI, const DataLayout &DL) const {
948 unsigned AS = DL.getAllocaAddrSpace();
949 DemoteReg = MRI.createGenericVirtualRegister(
950 LLT::pointer(AS, DL.getPointerSizeInBits(AS)));
951
952 Type *PtrTy = PointerType::get(F.getReturnType(), AS);
953
954 SmallVector<EVT, 1> ValueVTs;
955 ComputeValueVTs(*TLI, DL, PtrTy, ValueVTs);
956
957 // NOTE: Assume that a pointer won't get split into more than one VT.
958 assert(ValueVTs.size() == 1);
959
960 ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext()),
963 DemoteArg.Flags[0].setSRet();
964 SplitArgs.insert(SplitArgs.begin(), DemoteArg);
965}
966
968 const CallBase &CB,
969 CallLoweringInfo &Info) const {
970 const DataLayout &DL = MIRBuilder.getDataLayout();
971 Type *RetTy = CB.getType();
972 unsigned AS = DL.getAllocaAddrSpace();
973 LLT FramePtrTy = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
974
975 int FI = MIRBuilder.getMF().getFrameInfo().CreateStackObject(
976 DL.getTypeAllocSize(RetTy), DL.getPrefTypeAlign(RetTy), false);
977
978 Register DemoteReg = MIRBuilder.buildFrameIndex(FramePtrTy, FI).getReg(0);
979 ArgInfo DemoteArg(DemoteReg, PointerType::get(RetTy, AS),
982 DemoteArg.Flags[0].setSRet();
983
984 Info.OrigArgs.insert(Info.OrigArgs.begin(), DemoteArg);
985 Info.DemoteStackIndex = FI;
986 Info.DemoteRegister = DemoteReg;
987}
988
991 CCAssignFn *Fn) const {
992 for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
993 MVT VT = MVT::getVT(Outs[I].Ty);
994 if (Fn(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo))
995 return false;
996 }
997 return true;
998}
999
1001 AttributeList Attrs,
1003 const DataLayout &DL) const {
1004 LLVMContext &Context = RetTy->getContext();
1006
1007 SmallVector<EVT, 4> SplitVTs;
1008 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs);
1010
1011 for (EVT VT : SplitVTs) {
1012 unsigned NumParts =
1013 TLI->getNumRegistersForCallingConv(Context, CallConv, VT);
1014 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT);
1015 Type *PartTy = EVT(RegVT).getTypeForEVT(Context);
1016
1017 for (unsigned I = 0; I < NumParts; ++I) {
1018 Outs.emplace_back(PartTy, Flags);
1019 }
1020 }
1021}
1022
1024 const auto &F = MF.getFunction();
1025 Type *ReturnType = F.getReturnType();
1026 CallingConv::ID CallConv = F.getCallingConv();
1027
1029 getReturnInfo(CallConv, ReturnType, F.getAttributes(), SplitArgs,
1030 MF.getDataLayout());
1031 return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg());
1032}
1033
1035 const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask,
1036 const SmallVectorImpl<CCValAssign> &OutLocs,
1037 const SmallVectorImpl<ArgInfo> &OutArgs) const {
1038 for (unsigned i = 0; i < OutLocs.size(); ++i) {
1039 const auto &ArgLoc = OutLocs[i];
1040 // If it's not a register, it's fine.
1041 if (!ArgLoc.isRegLoc())
1042 continue;
1043
1044 MCRegister PhysReg = ArgLoc.getLocReg();
1045
1046 // Only look at callee-saved registers.
1047 if (MachineOperand::clobbersPhysReg(CallerPreservedMask, PhysReg))
1048 continue;
1049
1050 LLVM_DEBUG(
1051 dbgs()
1052 << "... Call has an argument passed in a callee-saved register.\n");
1053
1054 // Check if it was copied from.
1055 const ArgInfo &OutInfo = OutArgs[i];
1056
1057 if (OutInfo.Regs.size() > 1) {
1058 LLVM_DEBUG(
1059 dbgs() << "... Cannot handle arguments in multiple registers.\n");
1060 return false;
1061 }
1062
1063 // Check if we copy the register, walking through copies from virtual
1064 // registers. Note that getDefIgnoringCopies does not ignore copies from
1065 // physical registers.
1066 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
1067 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
1068 LLVM_DEBUG(
1069 dbgs()
1070 << "... Parameter was not copied into a VReg, cannot tail call.\n");
1071 return false;
1072 }
1073
1074 // Got a copy. Verify that it's the same as the register we want.
1075 Register CopyRHS = RegDef->getOperand(1).getReg();
1076 if (CopyRHS != PhysReg) {
1077 LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
1078 "VReg, cannot tail call.\n");
1079 return false;
1080 }
1081 }
1082
1083 return true;
1084}
1085
1087 MachineFunction &MF,
1089 ValueAssigner &CalleeAssigner,
1090 ValueAssigner &CallerAssigner) const {
1091 const Function &F = MF.getFunction();
1092 CallingConv::ID CalleeCC = Info.CallConv;
1093 CallingConv::ID CallerCC = F.getCallingConv();
1094
1095 if (CallerCC == CalleeCC)
1096 return true;
1097
1099 CCState CCInfo1(CalleeCC, Info.IsVarArg, MF, ArgLocs1, F.getContext());
1100 if (!determineAssignments(CalleeAssigner, InArgs, CCInfo1))
1101 return false;
1102
1104 CCState CCInfo2(CallerCC, F.isVarArg(), MF, ArgLocs2, F.getContext());
1105 if (!determineAssignments(CallerAssigner, InArgs, CCInfo2))
1106 return false;
1107
1108 // We need the argument locations to match up exactly. If there's more in
1109 // one than the other, then we are done.
1110 if (ArgLocs1.size() != ArgLocs2.size())
1111 return false;
1112
1113 // Make sure that each location is passed in exactly the same way.
1114 for (unsigned i = 0, e = ArgLocs1.size(); i < e; ++i) {
1115 const CCValAssign &Loc1 = ArgLocs1[i];
1116 const CCValAssign &Loc2 = ArgLocs2[i];
1117
1118 // We need both of them to be the same. So if one is a register and one
1119 // isn't, we're done.
1120 if (Loc1.isRegLoc() != Loc2.isRegLoc())
1121 return false;
1122
1123 if (Loc1.isRegLoc()) {
1124 // If they don't have the same register location, we're done.
1125 if (Loc1.getLocReg() != Loc2.getLocReg())
1126 return false;
1127
1128 // They matched, so we can move to the next ArgLoc.
1129 continue;
1130 }
1131
1132 // Loc1 wasn't a RegLoc, so they both must be MemLocs. Check if they match.
1133 if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset())
1134 return false;
1135 }
1136
1137 return true;
1138}
1139
1141 const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const {
1142 const MVT ValVT = VA.getValVT();
1143 if (ValVT != MVT::iPTR) {
1144 LLT ValTy(ValVT);
1145
1146 // We lost the pointeriness going through CCValAssign, so try to restore it
1147 // based on the flags.
1148 if (Flags.isPointer()) {
1149 LLT PtrTy = LLT::pointer(Flags.getPointerAddrSpace(),
1150 ValTy.getScalarSizeInBits());
1151 if (ValVT.isVector())
1152 return LLT::vector(ValTy.getElementCount(), PtrTy);
1153 return PtrTy;
1154 }
1155
1156 return ValTy;
1157 }
1158
1159 unsigned AddrSpace = Flags.getPointerAddrSpace();
1160 return LLT::pointer(AddrSpace, DL.getPointerSize(AddrSpace));
1161}
1162
1164 const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
1165 const MachinePointerInfo &DstPtrInfo, Align DstAlign,
1166 const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize,
1167 CCValAssign &VA) const {
1168 MachineFunction &MF = MIRBuilder.getMF();
1170 SrcPtrInfo,
1172 SrcAlign);
1173
1175 DstPtrInfo,
1177 MemSize, DstAlign);
1178
1179 const LLT PtrTy = MRI.getType(DstPtr);
1180 const LLT SizeTy = LLT::scalar(PtrTy.getSizeInBits());
1181
1182 auto SizeConst = MIRBuilder.buildConstant(SizeTy, MemSize);
1183 MIRBuilder.buildMemCpy(DstPtr, SrcPtr, SizeConst, *DstMMO, *SrcMMO);
1184}
1185
1187 const CCValAssign &VA,
1188 unsigned MaxSizeBits) {
1189 LLT LocTy{VA.getLocVT()};
1190 LLT ValTy{VA.getValVT()};
1191
1192 if (LocTy.getSizeInBits() == ValTy.getSizeInBits())
1193 return ValReg;
1194
1195 if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) {
1196 if (MaxSizeBits <= ValTy.getSizeInBits())
1197 return ValReg;
1198 LocTy = LLT::scalar(MaxSizeBits);
1199 }
1200
1201 const LLT ValRegTy = MRI.getType(ValReg);
1202 if (ValRegTy.isPointer()) {
1203 // The x32 ABI wants to zero extend 32-bit pointers to 64-bit registers, so
1204 // we have to cast to do the extension.
1205 LLT IntPtrTy = LLT::scalar(ValRegTy.getSizeInBits());
1206 ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0);
1207 }
1208
1209 switch (VA.getLocInfo()) {
1210 default: break;
1211 case CCValAssign::Full:
1212 case CCValAssign::BCvt:
1213 // FIXME: bitconverting between vector types may or may not be a
1214 // nop in big-endian situations.
1215 return ValReg;
1216 case CCValAssign::AExt: {
1217 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
1218 return MIB.getReg(0);
1219 }
1220 case CCValAssign::SExt: {
1221 Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1222 MIRBuilder.buildSExt(NewReg, ValReg);
1223 return NewReg;
1224 }
1225 case CCValAssign::ZExt: {
1226 Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1227 MIRBuilder.buildZExt(NewReg, ValReg);
1228 return NewReg;
1229 }
1230 }
1231 llvm_unreachable("unable to extend register");
1232}
1233
1234void CallLowering::ValueAssigner::anchor() {}
1235
1237 const CCValAssign &VA, Register SrcReg, LLT NarrowTy) {
1238 switch (VA.getLocInfo()) {
1240 return MIRBuilder
1241 .buildAssertZExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1242 NarrowTy.getScalarSizeInBits())
1243 .getReg(0);
1244 }
1246 return MIRBuilder
1247 .buildAssertSExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1248 NarrowTy.getScalarSizeInBits())
1249 .getReg(0);
1250 break;
1251 }
1252 default:
1253 return SrcReg;
1254 }
1255}
1256
1257/// Check if we can use a basic COPY instruction between the two types.
1258///
1259/// We're currently building on top of the infrastructure using MVT, which loses
1260/// pointer information in the CCValAssign. We accept copies from physical
1261/// registers that have been reported as integers if it's to an equivalent sized
1262/// pointer LLT.
1263static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) {
1264 if (SrcTy == DstTy)
1265 return true;
1266
1267 if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1268 return false;
1269
1270 SrcTy = SrcTy.getScalarType();
1271 DstTy = DstTy.getScalarType();
1272
1273 return (SrcTy.isPointer() && DstTy.isScalar()) ||
1274 (DstTy.isPointer() && SrcTy.isScalar());
1275}
1276
1278 Register ValVReg, Register PhysReg, const CCValAssign &VA) {
1279 const MVT LocVT = VA.getLocVT();
1280 const LLT LocTy(LocVT);
1281 const LLT RegTy = MRI.getType(ValVReg);
1282
1283 if (isCopyCompatibleType(RegTy, LocTy)) {
1284 MIRBuilder.buildCopy(ValVReg, PhysReg);
1285 return;
1286 }
1287
1288 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);
1289 auto Hint = buildExtensionHint(VA, Copy.getReg(0), RegTy);
1290 MIRBuilder.buildTrunc(ValVReg, Hint);
1291}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static void addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags, const std::function< bool(Attribute::AttrKind)> &AttrFn)
Helper function which updates Flags when AttrFn returns true.
static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, Register SrcReg, LLT SrcTy, LLT PartTy, unsigned ExtendOp=TargetOpcode::G_ANYEXT)
Create a sequence of instructions to expand the value in SrcReg (of type SrcTy) to the types in DstRe...
static MachineInstrBuilder mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, ArrayRef< Register > SrcRegs)
Pack values SrcRegs to cover the vector type result DstRegs.
static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef< Register > OrigRegs, ArrayRef< Register > Regs, LLT LLTy, LLT PartLLT, const ISD::ArgFlagsTy Flags)
Create a sequence of instructions to combine pieces split into register typed values to the original ...
static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy)
Check if we can use a basic COPY instruction between the two types.
static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags)
This file describes how to lower LLVM calls to machine code calls.
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Addr
uint64_t Size
static unsigned NumFixedArgs
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineIRBuilder class.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
R600 Clause Merge
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:228
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:204
const T & front() const
front - Get the first element.
Definition: ArrayRef.h:168
iterator end() const
Definition: ArrayRef.h:154
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
iterator begin() const
Definition: ArrayRef.h:153
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:349
AttrKind
This enumeration lists the attributes that can be associated with parameters, function results,...
Definition: Attributes.h:85
CCState - This class holds information needed while lowering arguments and return values.
CallingConv::ID getCallingConv() const
LLVMContext & getContext() const
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
bool needsCustom() const
bool isMemLoc() const
int64_t getLocMemOffset() const
unsigned getValNo() const
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1461
MaybeAlign getRetAlign() const
Extract the alignment of the return value.
Definition: InstrTypes.h:2062
std::optional< OperandBundleUse > getOperandBundle(StringRef Name) const
Return an operand bundle by name, if present.
Definition: InstrTypes.h:2367
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1767
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
bool isIndirectCall() const
Return true if the callsite is an indirect call.
Value * getCalledOperand() const
Definition: InstrTypes.h:1702
bool isConvergent() const
Determine if the invoke is convergent.
Definition: InstrTypes.h:2251
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1567
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Definition: InstrTypes.h:1645
AttributeList getAttributes() const
Return the parameter attributes for this call.
Definition: InstrTypes.h:1786
bool isTailCall() const
Tests if this call site is marked as a tail call.
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Use Handler to insert code to handle the argument/return values represented by Args.
void insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder, const CallBase &CB, CallLoweringInfo &Info) const
For the call-base described by CB, insert the hidden sret ArgInfo to the OrigArgs field of Info.
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
bool checkReturnTypeForCallConv(MachineFunction &MF) const
Toplevel function to check the return type based on the target calling convention.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const
This hook must be implemented to check whether the return values described by Outs can fit into the r...
Definition: CallLowering.h:498
virtual bool isTypeIsValidForThisReturn(EVT Ty) const
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: CallLowering.h:599
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
ISD::ArgFlagsTy getAttributesForArgIdx(const CallBase &Call, unsigned ArgIdx) const
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
void addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags, const AttributeList &Attrs, unsigned OpIdx) const
Adds flags to Flags based off of the attributes in Attrs.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
void getReturnInfo(CallingConv::ID CallConv, Type *RetTy, AttributeList Attrs, SmallVectorImpl< BaseArgInfo > &Outs, const DataLayout &DL) const
Get the type and the ArgFlags for the split components of RetTy as returned by ComputeValueVTs.
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
const TargetLowering * getTLI() const
Getter for generic TargetLowering class.
Definition: CallLowering.h:346
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: CallLowering.h:558
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
ISD::ArgFlagsTy getAttributesForReturn(const CallBase &Call) const
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:142
bool isVarArg() const
Definition: DerivedTypes.h:123
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:703
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:359
constexpr unsigned getScalarSizeInBits() const
Definition: LowLevelType.h:267
constexpr bool isScalar() const
Definition: LowLevelType.h:146
constexpr LLT changeElementType(LLT NewEltTy) const
If this type is a vector, return a vector with the same number of elements but the new element type.
Definition: LowLevelType.h:214
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelType.h:64
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:159
constexpr bool isVector() const
Definition: LowLevelType.h:148
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:57
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:193
constexpr bool isPointer() const
Definition: LowLevelType.h:149
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:290
constexpr ElementCount getElementCount() const
Definition: LowLevelType.h:184
constexpr unsigned getAddressSpace() const
Definition: LowLevelType.h:280
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelType.h:100
constexpr LLT changeElementCount(ElementCount EC) const
Return a vector or scalar with the same element type and the new element count.
Definition: LowLevelType.h:230
constexpr LLT getScalarType() const
Definition: LowLevelType.h:208
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelType.h:203
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
bool isVector() const
Return true if this is a vector value type.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:585
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Helper class to build MachineInstr.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:546
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:556
A description of a memory reference used in the backend.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Class to represent pointers.
Definition: DerivedTypes.h:646
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:950
void reserve(size_type N)
Definition: SmallVector.h:676
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:818
void truncate(size_type N)
Like resize, but requires that N is less than size().
Definition: SmallVector.h:657
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:348
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:693
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:187
static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
Definition: TypeSize.h:203
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
Definition: TypeSize.h:210
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:465
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:1143
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:79
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:535
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:1164
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:865
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
const Value * OrigValue
Optionally track the original IR value for the argument.
Definition: CallLowering.h:73
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:63
unsigned OrigArgIndex
Index original Function's argument.
Definition: CallLowering.h:76
static const unsigned NoArgIndex
Sentinel value for implicit machine-level input arguments.
Definition: CallLowering.h:79
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:51
void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA) override
Provides a default implementation for argument handling.
Register buildExtensionHint(const CCValAssign &VA, Register SrcReg, LLT NarrowTy)
Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on VA, returning the new register ...
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:167
virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Wrap call to (typically tablegenerated CCAssignFn).
Definition: CallLowering.h:191
void copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr, const MachinePointerInfo &DstPtrInfo, Align DstAlign, const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize, CCValAssign &VA) const
Do a memory copy of MemSize bytes from SrcPtr to DstPtr.
virtual Register getStackAddress(uint64_t MemSize, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
bool isIncomingArgumentHandler() const
Returns true if the handler is dealing with incoming arguments, i.e.
Definition: CallLowering.h:248
virtual void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, const CCValAssign &VA)=0
The specified value has been assigned to a stack location.
Register extendRegister(Register ValReg, const CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
virtual unsigned assignCustomValue(ArgInfo &Arg, ArrayRef< CCValAssign > VAs, std::function< void()> *Thunk=nullptr)
Handle custom values, which may be passed into one or more of VAs.
Definition: CallLowering.h:300
virtual void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
Extended Value Type.
Definition: ValueTypes.h:34
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:628
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117