LLVM 19.0.0git
Utils.cpp
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1//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file This file implements the utility functions used by the GlobalISel
9/// pipeline.
10//===----------------------------------------------------------------------===//
11
13#include "llvm/ADT/APFloat.h"
14#include "llvm/ADT/APInt.h"
33#include "llvm/IR/Constants.h"
36#include <numeric>
37#include <optional>
38
39#define DEBUG_TYPE "globalisel-utils"
40
41using namespace llvm;
42using namespace MIPatternMatch;
43
45 const TargetInstrInfo &TII,
46 const RegisterBankInfo &RBI, Register Reg,
47 const TargetRegisterClass &RegClass) {
48 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
49 return MRI.createVirtualRegister(&RegClass);
50
51 return Reg;
52}
53
55 const MachineFunction &MF, const TargetRegisterInfo &TRI,
57 const RegisterBankInfo &RBI, MachineInstr &InsertPt,
58 const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
59 Register Reg = RegMO.getReg();
60 // Assume physical registers are properly constrained.
61 assert(Reg.isVirtual() && "PhysReg not implemented");
62
63 // Save the old register class to check whether
64 // the change notifications will be required.
65 // TODO: A better approach would be to pass
66 // the observers to constrainRegToClass().
67 auto *OldRegClass = MRI.getRegClassOrNull(Reg);
68 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
69 // If we created a new virtual register because the class is not compatible
70 // then create a copy between the new and the old register.
71 if (ConstrainedReg != Reg) {
72 MachineBasicBlock::iterator InsertIt(&InsertPt);
73 MachineBasicBlock &MBB = *InsertPt.getParent();
74 // FIXME: The copy needs to have the classes constrained for its operands.
75 // Use operand's regbank to get the class for old register (Reg).
76 if (RegMO.isUse()) {
77 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
78 TII.get(TargetOpcode::COPY), ConstrainedReg)
79 .addReg(Reg);
80 } else {
81 assert(RegMO.isDef() && "Must be a definition");
82 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
83 TII.get(TargetOpcode::COPY), Reg)
84 .addReg(ConstrainedReg);
85 }
86 if (GISelChangeObserver *Observer = MF.getObserver()) {
87 Observer->changingInstr(*RegMO.getParent());
88 }
89 RegMO.setReg(ConstrainedReg);
90 if (GISelChangeObserver *Observer = MF.getObserver()) {
91 Observer->changedInstr(*RegMO.getParent());
92 }
93 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) {
94 if (GISelChangeObserver *Observer = MF.getObserver()) {
95 if (!RegMO.isDef()) {
96 MachineInstr *RegDef = MRI.getVRegDef(Reg);
97 Observer->changedInstr(*RegDef);
98 }
99 Observer->changingAllUsesOfReg(MRI, Reg);
100 Observer->finishedChangingAllUsesOfReg();
101 }
102 }
103 return ConstrainedReg;
104}
105
107 const MachineFunction &MF, const TargetRegisterInfo &TRI,
109 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
110 MachineOperand &RegMO, unsigned OpIdx) {
111 Register Reg = RegMO.getReg();
112 // Assume physical registers are properly constrained.
113 assert(Reg.isVirtual() && "PhysReg not implemented");
114
115 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF);
116 // Some of the target independent instructions, like COPY, may not impose any
117 // register class constraints on some of their operands: If it's a use, we can
118 // skip constraining as the instruction defining the register would constrain
119 // it.
120
121 if (OpRC) {
122 // Obtain the RC from incoming regbank if it is a proper sub-class. Operands
123 // can have multiple regbanks for a superclass that combine different
124 // register types (E.g., AMDGPU's VGPR and AGPR). The regbank ambiguity
125 // resolved by targets during regbankselect should not be overridden.
126 if (const auto *SubRC = TRI.getCommonSubClass(
127 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI)))
128 OpRC = SubRC;
129
130 OpRC = TRI.getAllocatableClass(OpRC);
131 }
132
133 if (!OpRC) {
134 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
135 "Register class constraint is required unless either the "
136 "instruction is target independent or the operand is a use");
137 // FIXME: Just bailing out like this here could be not enough, unless we
138 // expect the users of this function to do the right thing for PHIs and
139 // COPY:
140 // v1 = COPY v0
141 // v2 = COPY v1
142 // v1 here may end up not being constrained at all. Please notice that to
143 // reproduce the issue we likely need a destination pattern of a selection
144 // rule producing such extra copies, not just an input GMIR with them as
145 // every existing target using selectImpl handles copies before calling it
146 // and they never reach this function.
147 return Reg;
148 }
149 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC,
150 RegMO);
151}
152
154 const TargetInstrInfo &TII,
155 const TargetRegisterInfo &TRI,
156 const RegisterBankInfo &RBI) {
157 assert(!isPreISelGenericOpcode(I.getOpcode()) &&
158 "A selected instruction is expected");
159 MachineBasicBlock &MBB = *I.getParent();
162
163 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
164 MachineOperand &MO = I.getOperand(OpI);
165
166 // There's nothing to be done on non-register operands.
167 if (!MO.isReg())
168 continue;
169
170 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
171 assert(MO.isReg() && "Unsupported non-reg operand");
172
173 Register Reg = MO.getReg();
174 // Physical registers don't need to be constrained.
175 if (Reg.isPhysical())
176 continue;
177
178 // Register operands with a value of 0 (e.g. predicate operands) don't need
179 // to be constrained.
180 if (Reg == 0)
181 continue;
182
183 // If the operand is a vreg, we should constrain its regclass, and only
184 // insert COPYs if that's impossible.
185 // constrainOperandRegClass does that for us.
186 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
187
188 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
189 // done.
190 if (MO.isUse()) {
191 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
192 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
193 I.tieOperands(DefIdx, OpI);
194 }
195 }
196 return true;
197}
198
201 // Give up if either DstReg or SrcReg is a physical register.
202 if (DstReg.isPhysical() || SrcReg.isPhysical())
203 return false;
204 // Give up if the types don't match.
205 if (MRI.getType(DstReg) != MRI.getType(SrcReg))
206 return false;
207 // Replace if either DstReg has no constraints or the register
208 // constraints match.
209 const auto &DstRBC = MRI.getRegClassOrRegBank(DstReg);
210 if (!DstRBC || DstRBC == MRI.getRegClassOrRegBank(SrcReg))
211 return true;
212
213 // Otherwise match if the Src is already a regclass that is covered by the Dst
214 // RegBank.
215 return DstRBC.is<const RegisterBank *>() && MRI.getRegClassOrNull(SrcReg) &&
216 DstRBC.get<const RegisterBank *>()->covers(
217 *MRI.getRegClassOrNull(SrcReg));
218}
219
221 const MachineRegisterInfo &MRI) {
222 // FIXME: This logical is mostly duplicated with
223 // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in
224 // MachineInstr::isLabel?
225
226 // Don't delete frame allocation labels.
227 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
228 return false;
229 // LIFETIME markers should be preserved even if they seem dead.
230 if (MI.getOpcode() == TargetOpcode::LIFETIME_START ||
231 MI.getOpcode() == TargetOpcode::LIFETIME_END)
232 return false;
233
234 // If we can move an instruction, we can remove it. Otherwise, it has
235 // a side-effect of some sort.
236 bool SawStore = false;
237 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
238 return false;
239
240 // Instructions without side-effects are dead iff they only define dead vregs.
241 for (const auto &MO : MI.all_defs()) {
242 Register Reg = MO.getReg();
243 if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
244 return false;
245 }
246 return true;
247}
248
250 MachineFunction &MF,
251 const TargetPassConfig &TPC,
254 bool IsFatal = Severity == DS_Error &&
256 // Print the function name explicitly if we don't have a debug location (which
257 // makes the diagnostic less useful) or if we're going to emit a raw error.
258 if (!R.getLocation().isValid() || IsFatal)
259 R << (" (in function: " + MF.getName() + ")").str();
260
261 if (IsFatal)
262 report_fatal_error(Twine(R.getMsg()));
263 else
264 MORE.emit(R);
265}
266
271}
272
276 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
277 reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R);
278}
279
282 const char *PassName, StringRef Msg,
283 const MachineInstr &MI) {
284 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
285 MI.getDebugLoc(), MI.getParent());
286 R << Msg;
287 // Printing MI is expensive; only do it if expensive remarks are enabled.
288 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
289 R << ": " << ore::MNV("Inst", MI);
290 reportGISelFailure(MF, TPC, MORE, R);
291}
292
293std::optional<APInt> llvm::getIConstantVRegVal(Register VReg,
294 const MachineRegisterInfo &MRI) {
295 std::optional<ValueAndVReg> ValAndVReg = getIConstantVRegValWithLookThrough(
296 VReg, MRI, /*LookThroughInstrs*/ false);
297 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
298 "Value found while looking through instrs");
299 if (!ValAndVReg)
300 return std::nullopt;
301 return ValAndVReg->Value;
302}
303
304std::optional<int64_t>
306 std::optional<APInt> Val = getIConstantVRegVal(VReg, MRI);
307 if (Val && Val->getBitWidth() <= 64)
308 return Val->getSExtValue();
309 return std::nullopt;
310}
311
312namespace {
313
314typedef std::function<bool(const MachineInstr *)> IsOpcodeFn;
315typedef std::function<std::optional<APInt>(const MachineInstr *MI)> GetAPCstFn;
316
317std::optional<ValueAndVReg> getConstantVRegValWithLookThrough(
318 Register VReg, const MachineRegisterInfo &MRI, IsOpcodeFn IsConstantOpcode,
319 GetAPCstFn getAPCstValue, bool LookThroughInstrs = true,
320 bool LookThroughAnyExt = false) {
323
324 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) &&
325 LookThroughInstrs) {
326 switch (MI->getOpcode()) {
327 case TargetOpcode::G_ANYEXT:
328 if (!LookThroughAnyExt)
329 return std::nullopt;
330 [[fallthrough]];
331 case TargetOpcode::G_TRUNC:
332 case TargetOpcode::G_SEXT:
333 case TargetOpcode::G_ZEXT:
334 SeenOpcodes.push_back(std::make_pair(
335 MI->getOpcode(),
336 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
337 VReg = MI->getOperand(1).getReg();
338 break;
339 case TargetOpcode::COPY:
340 VReg = MI->getOperand(1).getReg();
341 if (VReg.isPhysical())
342 return std::nullopt;
343 break;
344 case TargetOpcode::G_INTTOPTR:
345 VReg = MI->getOperand(1).getReg();
346 break;
347 default:
348 return std::nullopt;
349 }
350 }
351 if (!MI || !IsConstantOpcode(MI))
352 return std::nullopt;
353
354 std::optional<APInt> MaybeVal = getAPCstValue(MI);
355 if (!MaybeVal)
356 return std::nullopt;
357 APInt &Val = *MaybeVal;
358 for (auto [Opcode, Size] : reverse(SeenOpcodes)) {
359 switch (Opcode) {
360 case TargetOpcode::G_TRUNC:
361 Val = Val.trunc(Size);
362 break;
363 case TargetOpcode::G_ANYEXT:
364 case TargetOpcode::G_SEXT:
365 Val = Val.sext(Size);
366 break;
367 case TargetOpcode::G_ZEXT:
368 Val = Val.zext(Size);
369 break;
370 }
371 }
372
373 return ValueAndVReg{Val, VReg};
374}
375
376bool isIConstant(const MachineInstr *MI) {
377 if (!MI)
378 return false;
379 return MI->getOpcode() == TargetOpcode::G_CONSTANT;
380}
381
382bool isFConstant(const MachineInstr *MI) {
383 if (!MI)
384 return false;
385 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
386}
387
388bool isAnyConstant(const MachineInstr *MI) {
389 if (!MI)
390 return false;
391 unsigned Opc = MI->getOpcode();
392 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
393}
394
395std::optional<APInt> getCImmAsAPInt(const MachineInstr *MI) {
396 const MachineOperand &CstVal = MI->getOperand(1);
397 if (CstVal.isCImm())
398 return CstVal.getCImm()->getValue();
399 return std::nullopt;
400}
401
402std::optional<APInt> getCImmOrFPImmAsAPInt(const MachineInstr *MI) {
403 const MachineOperand &CstVal = MI->getOperand(1);
404 if (CstVal.isCImm())
405 return CstVal.getCImm()->getValue();
406 if (CstVal.isFPImm())
407 return CstVal.getFPImm()->getValueAPF().bitcastToAPInt();
408 return std::nullopt;
409}
410
411} // end anonymous namespace
412
414 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
415 return getConstantVRegValWithLookThrough(VReg, MRI, isIConstant,
416 getCImmAsAPInt, LookThroughInstrs);
417}
418
420 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
421 bool LookThroughAnyExt) {
422 return getConstantVRegValWithLookThrough(
423 VReg, MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
424 LookThroughAnyExt);
425}
426
427std::optional<FPValueAndVReg> llvm::getFConstantVRegValWithLookThrough(
428 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
429 auto Reg = getConstantVRegValWithLookThrough(
430 VReg, MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
431 if (!Reg)
432 return std::nullopt;
434 Reg->VReg};
435}
436
437const ConstantFP *
439 MachineInstr *MI = MRI.getVRegDef(VReg);
440 if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
441 return nullptr;
442 return MI->getOperand(1).getFPImm();
443}
444
445std::optional<DefinitionAndSourceRegister>
447 Register DefSrcReg = Reg;
448 auto *DefMI = MRI.getVRegDef(Reg);
449 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
450 if (!DstTy.isValid())
451 return std::nullopt;
452 unsigned Opc = DefMI->getOpcode();
453 while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
454 Register SrcReg = DefMI->getOperand(1).getReg();
455 auto SrcTy = MRI.getType(SrcReg);
456 if (!SrcTy.isValid())
457 break;
458 DefMI = MRI.getVRegDef(SrcReg);
459 DefSrcReg = SrcReg;
460 Opc = DefMI->getOpcode();
461 }
462 return DefinitionAndSourceRegister{DefMI, DefSrcReg};
463}
464
466 const MachineRegisterInfo &MRI) {
467 std::optional<DefinitionAndSourceRegister> DefSrcReg =
469 return DefSrcReg ? DefSrcReg->MI : nullptr;
470}
471
473 const MachineRegisterInfo &MRI) {
474 std::optional<DefinitionAndSourceRegister> DefSrcReg =
476 return DefSrcReg ? DefSrcReg->Reg : Register();
477}
478
479void llvm::extractParts(Register Reg, LLT Ty, int NumParts,
481 MachineIRBuilder &MIRBuilder,
483 for (int i = 0; i < NumParts; ++i)
484 VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
485 MIRBuilder.buildUnmerge(VRegs, Reg);
486}
487
488bool llvm::extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
490 SmallVectorImpl<Register> &LeftoverRegs,
491 MachineIRBuilder &MIRBuilder,
493 assert(!LeftoverTy.isValid() && "this is an out argument");
494
495 unsigned RegSize = RegTy.getSizeInBits();
496 unsigned MainSize = MainTy.getSizeInBits();
497 unsigned NumParts = RegSize / MainSize;
498 unsigned LeftoverSize = RegSize - NumParts * MainSize;
499
500 // Use an unmerge when possible.
501 if (LeftoverSize == 0) {
502 for (unsigned I = 0; I < NumParts; ++I)
503 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
504 MIRBuilder.buildUnmerge(VRegs, Reg);
505 return true;
506 }
507
508 // Try to use unmerge for irregular vector split where possible
509 // For example when splitting a <6 x i32> into <4 x i32> with <2 x i32>
510 // leftover, it becomes:
511 // <2 x i32> %2, <2 x i32>%3, <2 x i32> %4 = G_UNMERGE_VALUE <6 x i32> %1
512 // <4 x i32> %5 = G_CONCAT_VECTOR <2 x i32> %2, <2 x i32> %3
513 if (RegTy.isVector() && MainTy.isVector()) {
514 unsigned RegNumElts = RegTy.getNumElements();
515 unsigned MainNumElts = MainTy.getNumElements();
516 unsigned LeftoverNumElts = RegNumElts % MainNumElts;
517 // If can unmerge to LeftoverTy, do it
518 if (MainNumElts % LeftoverNumElts == 0 &&
519 RegNumElts % LeftoverNumElts == 0 &&
520 RegTy.getScalarSizeInBits() == MainTy.getScalarSizeInBits() &&
521 LeftoverNumElts > 1) {
522 LeftoverTy =
523 LLT::fixed_vector(LeftoverNumElts, RegTy.getScalarSizeInBits());
524
525 // Unmerge the SrcReg to LeftoverTy vectors
526 SmallVector<Register, 4> UnmergeValues;
527 extractParts(Reg, LeftoverTy, RegNumElts / LeftoverNumElts, UnmergeValues,
528 MIRBuilder, MRI);
529
530 // Find how many LeftoverTy makes one MainTy
531 unsigned LeftoverPerMain = MainNumElts / LeftoverNumElts;
532 unsigned NumOfLeftoverVal =
533 ((RegNumElts % MainNumElts) / LeftoverNumElts);
534
535 // Create as many MainTy as possible using unmerged value
536 SmallVector<Register, 4> MergeValues;
537 for (unsigned I = 0; I < UnmergeValues.size() - NumOfLeftoverVal; I++) {
538 MergeValues.push_back(UnmergeValues[I]);
539 if (MergeValues.size() == LeftoverPerMain) {
540 VRegs.push_back(
541 MIRBuilder.buildMergeLikeInstr(MainTy, MergeValues).getReg(0));
542 MergeValues.clear();
543 }
544 }
545 // Populate LeftoverRegs with the leftovers
546 for (unsigned I = UnmergeValues.size() - NumOfLeftoverVal;
547 I < UnmergeValues.size(); I++) {
548 LeftoverRegs.push_back(UnmergeValues[I]);
549 }
550 return true;
551 }
552 }
553 // Perform irregular split. Leftover is last element of RegPieces.
554 if (MainTy.isVector()) {
555 SmallVector<Register, 8> RegPieces;
556 extractVectorParts(Reg, MainTy.getNumElements(), RegPieces, MIRBuilder,
557 MRI);
558 for (unsigned i = 0; i < RegPieces.size() - 1; ++i)
559 VRegs.push_back(RegPieces[i]);
560 LeftoverRegs.push_back(RegPieces[RegPieces.size() - 1]);
561 LeftoverTy = MRI.getType(LeftoverRegs[0]);
562 return true;
563 }
564
565 LeftoverTy = LLT::scalar(LeftoverSize);
566 // For irregular sizes, extract the individual parts.
567 for (unsigned I = 0; I != NumParts; ++I) {
568 Register NewReg = MRI.createGenericVirtualRegister(MainTy);
569 VRegs.push_back(NewReg);
570 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
571 }
572
573 for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
574 Offset += LeftoverSize) {
575 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
576 LeftoverRegs.push_back(NewReg);
577 MIRBuilder.buildExtract(NewReg, Reg, Offset);
578 }
579
580 return true;
581}
582
583void llvm::extractVectorParts(Register Reg, unsigned NumElts,
585 MachineIRBuilder &MIRBuilder,
587 LLT RegTy = MRI.getType(Reg);
588 assert(RegTy.isVector() && "Expected a vector type");
589
590 LLT EltTy = RegTy.getElementType();
591 LLT NarrowTy = (NumElts == 1) ? EltTy : LLT::fixed_vector(NumElts, EltTy);
592 unsigned RegNumElts = RegTy.getNumElements();
593 unsigned LeftoverNumElts = RegNumElts % NumElts;
594 unsigned NumNarrowTyPieces = RegNumElts / NumElts;
595
596 // Perfect split without leftover
597 if (LeftoverNumElts == 0)
598 return extractParts(Reg, NarrowTy, NumNarrowTyPieces, VRegs, MIRBuilder,
599 MRI);
600
601 // Irregular split. Provide direct access to all elements for artifact
602 // combiner using unmerge to elements. Then build vectors with NumElts
603 // elements. Remaining element(s) will be (used to build vector) Leftover.
605 extractParts(Reg, EltTy, RegNumElts, Elts, MIRBuilder, MRI);
606
607 unsigned Offset = 0;
608 // Requested sub-vectors of NarrowTy.
609 for (unsigned i = 0; i < NumNarrowTyPieces; ++i, Offset += NumElts) {
610 ArrayRef<Register> Pieces(&Elts[Offset], NumElts);
611 VRegs.push_back(MIRBuilder.buildMergeLikeInstr(NarrowTy, Pieces).getReg(0));
612 }
613
614 // Leftover element(s).
615 if (LeftoverNumElts == 1) {
616 VRegs.push_back(Elts[Offset]);
617 } else {
618 LLT LeftoverTy = LLT::fixed_vector(LeftoverNumElts, EltTy);
619 ArrayRef<Register> Pieces(&Elts[Offset], LeftoverNumElts);
620 VRegs.push_back(
621 MIRBuilder.buildMergeLikeInstr(LeftoverTy, Pieces).getReg(0));
622 }
623}
624
626 const MachineRegisterInfo &MRI) {
628 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
629}
630
631APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
632 if (Size == 32)
633 return APFloat(float(Val));
634 if (Size == 64)
635 return APFloat(Val);
636 if (Size != 16)
637 llvm_unreachable("Unsupported FPConstant size");
638 bool Ignored;
639 APFloat APF(Val);
640 APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
641 return APF;
642}
643
644std::optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode,
645 const Register Op1,
646 const Register Op2,
647 const MachineRegisterInfo &MRI) {
648 auto MaybeOp2Cst = getAnyConstantVRegValWithLookThrough(Op2, MRI, false);
649 if (!MaybeOp2Cst)
650 return std::nullopt;
651
652 auto MaybeOp1Cst = getAnyConstantVRegValWithLookThrough(Op1, MRI, false);
653 if (!MaybeOp1Cst)
654 return std::nullopt;
655
656 const APInt &C1 = MaybeOp1Cst->Value;
657 const APInt &C2 = MaybeOp2Cst->Value;
658 switch (Opcode) {
659 default:
660 break;
661 case TargetOpcode::G_ADD:
662 return C1 + C2;
663 case TargetOpcode::G_PTR_ADD:
664 // Types can be of different width here.
665 // Result needs to be the same width as C1, so trunc or sext C2.
666 return C1 + C2.sextOrTrunc(C1.getBitWidth());
667 case TargetOpcode::G_AND:
668 return C1 & C2;
669 case TargetOpcode::G_ASHR:
670 return C1.ashr(C2);
671 case TargetOpcode::G_LSHR:
672 return C1.lshr(C2);
673 case TargetOpcode::G_MUL:
674 return C1 * C2;
675 case TargetOpcode::G_OR:
676 return C1 | C2;
677 case TargetOpcode::G_SHL:
678 return C1 << C2;
679 case TargetOpcode::G_SUB:
680 return C1 - C2;
681 case TargetOpcode::G_XOR:
682 return C1 ^ C2;
683 case TargetOpcode::G_UDIV:
684 if (!C2.getBoolValue())
685 break;
686 return C1.udiv(C2);
687 case TargetOpcode::G_SDIV:
688 if (!C2.getBoolValue())
689 break;
690 return C1.sdiv(C2);
691 case TargetOpcode::G_UREM:
692 if (!C2.getBoolValue())
693 break;
694 return C1.urem(C2);
695 case TargetOpcode::G_SREM:
696 if (!C2.getBoolValue())
697 break;
698 return C1.srem(C2);
699 case TargetOpcode::G_SMIN:
700 return APIntOps::smin(C1, C2);
701 case TargetOpcode::G_SMAX:
702 return APIntOps::smax(C1, C2);
703 case TargetOpcode::G_UMIN:
704 return APIntOps::umin(C1, C2);
705 case TargetOpcode::G_UMAX:
706 return APIntOps::umax(C1, C2);
707 }
708
709 return std::nullopt;
710}
711
712std::optional<APFloat>
713llvm::ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
714 const Register Op2, const MachineRegisterInfo &MRI) {
715 const ConstantFP *Op2Cst = getConstantFPVRegVal(Op2, MRI);
716 if (!Op2Cst)
717 return std::nullopt;
718
719 const ConstantFP *Op1Cst = getConstantFPVRegVal(Op1, MRI);
720 if (!Op1Cst)
721 return std::nullopt;
722
723 APFloat C1 = Op1Cst->getValueAPF();
724 const APFloat &C2 = Op2Cst->getValueAPF();
725 switch (Opcode) {
726 case TargetOpcode::G_FADD:
727 C1.add(C2, APFloat::rmNearestTiesToEven);
728 return C1;
729 case TargetOpcode::G_FSUB:
730 C1.subtract(C2, APFloat::rmNearestTiesToEven);
731 return C1;
732 case TargetOpcode::G_FMUL:
733 C1.multiply(C2, APFloat::rmNearestTiesToEven);
734 return C1;
735 case TargetOpcode::G_FDIV:
736 C1.divide(C2, APFloat::rmNearestTiesToEven);
737 return C1;
738 case TargetOpcode::G_FREM:
739 C1.mod(C2);
740 return C1;
741 case TargetOpcode::G_FCOPYSIGN:
742 C1.copySign(C2);
743 return C1;
744 case TargetOpcode::G_FMINNUM:
745 return minnum(C1, C2);
746 case TargetOpcode::G_FMAXNUM:
747 return maxnum(C1, C2);
748 case TargetOpcode::G_FMINIMUM:
749 return minimum(C1, C2);
750 case TargetOpcode::G_FMAXIMUM:
751 return maximum(C1, C2);
752 case TargetOpcode::G_FMINNUM_IEEE:
753 case TargetOpcode::G_FMAXNUM_IEEE:
754 // FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
755 // follow the IEEE behavior for signaling nans and follow libm's fmin/fmax,
756 // and currently there isn't a nice wrapper in APFloat for the version with
757 // correct snan handling.
758 break;
759 default:
760 break;
761 }
762
763 return std::nullopt;
764}
765
767llvm::ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
768 const Register Op2,
769 const MachineRegisterInfo &MRI) {
770 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI);
771 if (!SrcVec2)
772 return SmallVector<APInt>();
773
774 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI);
775 if (!SrcVec1)
776 return SmallVector<APInt>();
777
778 SmallVector<APInt> FoldedElements;
779 for (unsigned Idx = 0, E = SrcVec1->getNumSources(); Idx < E; ++Idx) {
780 auto MaybeCst = ConstantFoldBinOp(Opcode, SrcVec1->getSourceReg(Idx),
781 SrcVec2->getSourceReg(Idx), MRI);
782 if (!MaybeCst)
783 return SmallVector<APInt>();
784 FoldedElements.push_back(*MaybeCst);
785 }
786 return FoldedElements;
787}
788
790 bool SNaN) {
791 const MachineInstr *DefMI = MRI.getVRegDef(Val);
792 if (!DefMI)
793 return false;
794
795 const TargetMachine& TM = DefMI->getMF()->getTarget();
796 if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath)
797 return true;
798
799 // If the value is a constant, we can obviously see if it is a NaN or not.
800 if (const ConstantFP *FPVal = getConstantFPVRegVal(Val, MRI)) {
801 return !FPVal->getValueAPF().isNaN() ||
802 (SNaN && !FPVal->getValueAPF().isSignaling());
803 }
804
805 if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
806 for (const auto &Op : DefMI->uses())
807 if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))
808 return false;
809 return true;
810 }
811
812 switch (DefMI->getOpcode()) {
813 default:
814 break;
815 case TargetOpcode::G_FADD:
816 case TargetOpcode::G_FSUB:
817 case TargetOpcode::G_FMUL:
818 case TargetOpcode::G_FDIV:
819 case TargetOpcode::G_FREM:
820 case TargetOpcode::G_FSIN:
821 case TargetOpcode::G_FCOS:
822 case TargetOpcode::G_FMA:
823 case TargetOpcode::G_FMAD:
824 if (SNaN)
825 return true;
826
827 // TODO: Need isKnownNeverInfinity
828 return false;
829 case TargetOpcode::G_FMINNUM_IEEE:
830 case TargetOpcode::G_FMAXNUM_IEEE: {
831 if (SNaN)
832 return true;
833 // This can return a NaN if either operand is an sNaN, or if both operands
834 // are NaN.
835 return (isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI) &&
839 }
840 case TargetOpcode::G_FMINNUM:
841 case TargetOpcode::G_FMAXNUM: {
842 // Only one needs to be known not-nan, since it will be returned if the
843 // other ends up being one.
844 return isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI, SNaN) ||
846 }
847 }
848
849 if (SNaN) {
850 // FP operations quiet. For now, just handle the ones inserted during
851 // legalization.
852 switch (DefMI->getOpcode()) {
853 case TargetOpcode::G_FPEXT:
854 case TargetOpcode::G_FPTRUNC:
855 case TargetOpcode::G_FCANONICALIZE:
856 return true;
857 default:
858 return false;
859 }
860 }
861
862 return false;
863}
864
866 const MachinePointerInfo &MPO) {
867 auto PSV = dyn_cast_if_present<const PseudoSourceValue *>(MPO.V);
868 if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
869 MachineFrameInfo &MFI = MF.getFrameInfo();
870 return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
871 MPO.Offset);
872 }
873
874 if (const Value *V = dyn_cast_if_present<const Value *>(MPO.V)) {
875 const Module *M = MF.getFunction().getParent();
876 return V->getPointerAlignment(M->getDataLayout());
877 }
878
879 return Align(1);
880}
881
883 const TargetInstrInfo &TII,
884 MCRegister PhysReg,
885 const TargetRegisterClass &RC,
886 const DebugLoc &DL, LLT RegTy) {
887 MachineBasicBlock &EntryMBB = MF.front();
889 Register LiveIn = MRI.getLiveInVirtReg(PhysReg);
890 if (LiveIn) {
891 MachineInstr *Def = MRI.getVRegDef(LiveIn);
892 if (Def) {
893 // FIXME: Should the verifier check this is in the entry block?
894 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");
895 return LiveIn;
896 }
897
898 // It's possible the incoming argument register and copy was added during
899 // lowering, but later deleted due to being/becoming dead. If this happens,
900 // re-insert the copy.
901 } else {
902 // The live in register was not present, so add it.
903 LiveIn = MF.addLiveIn(PhysReg, &RC);
904 if (RegTy.isValid())
905 MRI.setType(LiveIn, RegTy);
906 }
907
908 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
909 .addReg(PhysReg);
910 if (!EntryMBB.isLiveIn(PhysReg))
911 EntryMBB.addLiveIn(PhysReg);
912 return LiveIn;
913}
914
915std::optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode,
916 const Register Op1, uint64_t Imm,
917 const MachineRegisterInfo &MRI) {
918 auto MaybeOp1Cst = getIConstantVRegVal(Op1, MRI);
919 if (MaybeOp1Cst) {
920 switch (Opcode) {
921 default:
922 break;
923 case TargetOpcode::G_SEXT_INREG: {
924 LLT Ty = MRI.getType(Op1);
925 return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
926 }
927 }
928 }
929 return std::nullopt;
930}
931
932std::optional<APInt> llvm::ConstantFoldCastOp(unsigned Opcode, LLT DstTy,
933 const Register Op0,
934 const MachineRegisterInfo &MRI) {
935 std::optional<APInt> Val = getIConstantVRegVal(Op0, MRI);
936 if (!Val)
937 return Val;
938
939 const unsigned DstSize = DstTy.getScalarSizeInBits();
940
941 switch (Opcode) {
942 case TargetOpcode::G_SEXT:
943 return Val->sext(DstSize);
944 case TargetOpcode::G_ZEXT:
945 case TargetOpcode::G_ANYEXT:
946 // TODO: DAG considers target preference when constant folding any_extend.
947 return Val->zext(DstSize);
948 default:
949 break;
950 }
951
952 llvm_unreachable("unexpected cast opcode to constant fold");
953}
954
955std::optional<APFloat>
956llvm::ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src,
957 const MachineRegisterInfo &MRI) {
958 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
959 if (auto MaybeSrcVal = getIConstantVRegVal(Src, MRI)) {
960 APFloat DstVal(getFltSemanticForLLT(DstTy));
961 DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,
962 APFloat::rmNearestTiesToEven);
963 return DstVal;
964 }
965 return std::nullopt;
966}
967
968std::optional<SmallVector<unsigned>>
970 std::function<unsigned(APInt)> CB) {
971 LLT Ty = MRI.getType(Src);
972 SmallVector<unsigned> FoldedCTLZs;
973 auto tryFoldScalar = [&](Register R) -> std::optional<unsigned> {
974 auto MaybeCst = getIConstantVRegVal(R, MRI);
975 if (!MaybeCst)
976 return std::nullopt;
977 return CB(*MaybeCst);
978 };
979 if (Ty.isVector()) {
980 // Try to constant fold each element.
981 auto *BV = getOpcodeDef<GBuildVector>(Src, MRI);
982 if (!BV)
983 return std::nullopt;
984 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
985 if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
986 FoldedCTLZs.emplace_back(*MaybeFold);
987 continue;
988 }
989 return std::nullopt;
990 }
991 return FoldedCTLZs;
992 }
993 if (auto MaybeCst = tryFoldScalar(Src)) {
994 FoldedCTLZs.emplace_back(*MaybeCst);
995 return FoldedCTLZs;
996 }
997 return std::nullopt;
998}
999
1001 GISelKnownBits *KB) {
1002 std::optional<DefinitionAndSourceRegister> DefSrcReg =
1004 if (!DefSrcReg)
1005 return false;
1006
1007 const MachineInstr &MI = *DefSrcReg->MI;
1008 const LLT Ty = MRI.getType(Reg);
1009
1010 switch (MI.getOpcode()) {
1011 case TargetOpcode::G_CONSTANT: {
1012 unsigned BitWidth = Ty.getScalarSizeInBits();
1013 const ConstantInt *CI = MI.getOperand(1).getCImm();
1014 return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
1015 }
1016 case TargetOpcode::G_SHL: {
1017 // A left-shift of a constant one will have exactly one bit set because
1018 // shifting the bit off the end is undefined.
1019
1020 // TODO: Constant splat
1021 if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
1022 if (*ConstLHS == 1)
1023 return true;
1024 }
1025
1026 break;
1027 }
1028 case TargetOpcode::G_LSHR: {
1029 if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
1030 if (ConstLHS->isSignMask())
1031 return true;
1032 }
1033
1034 break;
1035 }
1036 case TargetOpcode::G_BUILD_VECTOR: {
1037 // TODO: Probably should have a recursion depth guard since you could have
1038 // bitcasted vector elements.
1039 for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
1040 if (!isKnownToBeAPowerOfTwo(MO.getReg(), MRI, KB))
1041 return false;
1042
1043 return true;
1044 }
1045 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1046 // Only handle constants since we would need to know if number of leading
1047 // zeros is greater than the truncation amount.
1048 const unsigned BitWidth = Ty.getScalarSizeInBits();
1049 for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) {
1050 auto Const = getIConstantVRegVal(MO.getReg(), MRI);
1051 if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())
1052 return false;
1053 }
1054
1055 return true;
1056 }
1057 default:
1058 break;
1059 }
1060
1061 if (!KB)
1062 return false;
1063
1064 // More could be done here, though the above checks are enough
1065 // to handle some common cases.
1066
1067 // Fall back to computeKnownBits to catch other known cases.
1068 KnownBits Known = KB->getKnownBits(Reg);
1069 return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
1070}
1071
1074}
1075
1076LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
1077 if (OrigTy.getSizeInBits() == TargetTy.getSizeInBits())
1078 return OrigTy;
1079
1080 if (OrigTy.isVector() && TargetTy.isVector()) {
1081 LLT OrigElt = OrigTy.getElementType();
1082 LLT TargetElt = TargetTy.getElementType();
1083
1084 // TODO: The docstring for this function says the intention is to use this
1085 // function to build MERGE/UNMERGE instructions. It won't be the case that
1086 // we generate a MERGE/UNMERGE between fixed and scalable vector types. We
1087 // could implement getLCMType between the two in the future if there was a
1088 // need, but it is not worth it now as this function should not be used in
1089 // that way.
1090 assert(((OrigTy.isScalableVector() && !TargetTy.isFixedVector()) ||
1091 (OrigTy.isFixedVector() && !TargetTy.isScalableVector())) &&
1092 "getLCMType not implemented between fixed and scalable vectors.");
1093
1094 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
1095 int GCDMinElts = std::gcd(OrigTy.getElementCount().getKnownMinValue(),
1096 TargetTy.getElementCount().getKnownMinValue());
1097 // Prefer the original element type.
1099 TargetTy.getElementCount().getKnownMinValue());
1100 return LLT::vector(Mul.divideCoefficientBy(GCDMinElts),
1101 OrigTy.getElementType());
1102 }
1103 unsigned LCM = std::lcm(OrigTy.getSizeInBits().getKnownMinValue(),
1104 TargetTy.getSizeInBits().getKnownMinValue());
1105 return LLT::vector(
1106 ElementCount::get(LCM / OrigElt.getSizeInBits(), OrigTy.isScalable()),
1107 OrigElt);
1108 }
1109
1110 // One type is scalar, one type is vector
1111 if (OrigTy.isVector() || TargetTy.isVector()) {
1112 LLT VecTy = OrigTy.isVector() ? OrigTy : TargetTy;
1113 LLT ScalarTy = OrigTy.isVector() ? TargetTy : OrigTy;
1114 LLT EltTy = VecTy.getElementType();
1115 LLT OrigEltTy = OrigTy.isVector() ? OrigTy.getElementType() : OrigTy;
1116
1117 // Prefer scalar type from OrigTy.
1118 if (EltTy.getSizeInBits() == ScalarTy.getSizeInBits())
1119 return LLT::vector(VecTy.getElementCount(), OrigEltTy);
1120
1121 // Different size scalars. Create vector with the same total size.
1122 // LCM will take fixed/scalable from VecTy.
1123 unsigned LCM = std::lcm(EltTy.getSizeInBits().getFixedValue() *
1125 ScalarTy.getSizeInBits().getFixedValue());
1126 // Prefer type from OrigTy
1127 return LLT::vector(ElementCount::get(LCM / OrigEltTy.getSizeInBits(),
1128 VecTy.getElementCount().isScalable()),
1129 OrigEltTy);
1130 }
1131
1132 // At this point, both types are scalars of different size
1133 unsigned LCM = std::lcm(OrigTy.getSizeInBits().getFixedValue(),
1134 TargetTy.getSizeInBits().getFixedValue());
1135 // Preserve pointer types.
1136 if (LCM == OrigTy.getSizeInBits())
1137 return OrigTy;
1138 if (LCM == TargetTy.getSizeInBits())
1139 return TargetTy;
1140 return LLT::scalar(LCM);
1141}
1142
1143LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
1144
1145 if ((OrigTy.isScalableVector() && TargetTy.isFixedVector()) ||
1146 (OrigTy.isFixedVector() && TargetTy.isScalableVector()))
1148 "getCoverTy not implemented between fixed and scalable vectors.");
1149
1150 if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||
1151 (OrigTy.getScalarSizeInBits() != TargetTy.getScalarSizeInBits()))
1152 return getLCMType(OrigTy, TargetTy);
1153
1154 unsigned OrigTyNumElts = OrigTy.getElementCount().getKnownMinValue();
1155 unsigned TargetTyNumElts = TargetTy.getElementCount().getKnownMinValue();
1156 if (OrigTyNumElts % TargetTyNumElts == 0)
1157 return OrigTy;
1158
1159 unsigned NumElts = alignTo(OrigTyNumElts, TargetTyNumElts);
1161 OrigTy.getElementType());
1162}
1163
1164LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
1165 if (OrigTy.getSizeInBits() == TargetTy.getSizeInBits())
1166 return OrigTy;
1167
1168 if (OrigTy.isVector() && TargetTy.isVector()) {
1169 LLT OrigElt = OrigTy.getElementType();
1170
1171 // TODO: The docstring for this function says the intention is to use this
1172 // function to build MERGE/UNMERGE instructions. It won't be the case that
1173 // we generate a MERGE/UNMERGE between fixed and scalable vector types. We
1174 // could implement getGCDType between the two in the future if there was a
1175 // need, but it is not worth it now as this function should not be used in
1176 // that way.
1177 assert(((OrigTy.isScalableVector() && !TargetTy.isFixedVector()) ||
1178 (OrigTy.isFixedVector() && !TargetTy.isScalableVector())) &&
1179 "getGCDType not implemented between fixed and scalable vectors.");
1180
1181 unsigned GCD = std::gcd(OrigTy.getSizeInBits().getKnownMinValue(),
1182 TargetTy.getSizeInBits().getKnownMinValue());
1183 if (GCD == OrigElt.getSizeInBits())
1185 OrigElt);
1186
1187 // Cannot produce original element type, but both have vscale in common.
1188 if (GCD < OrigElt.getSizeInBits())
1190 GCD);
1191
1192 return LLT::vector(
1194 OrigTy.isScalable()),
1195 OrigElt);
1196 }
1197
1198 // If one type is vector and the element size matches the scalar size, then
1199 // the gcd is the scalar type.
1200 if (OrigTy.isVector() &&
1201 OrigTy.getElementType().getSizeInBits() == TargetTy.getSizeInBits())
1202 return OrigTy.getElementType();
1203 if (TargetTy.isVector() &&
1204 TargetTy.getElementType().getSizeInBits() == OrigTy.getSizeInBits())
1205 return OrigTy;
1206
1207 // At this point, both types are either scalars of different type or one is a
1208 // vector and one is a scalar. If both types are scalars, the GCD type is the
1209 // GCD between the two scalar sizes. If one is vector and one is scalar, then
1210 // the GCD type is the GCD between the scalar and the vector element size.
1211 LLT OrigScalar = OrigTy.getScalarType();
1212 LLT TargetScalar = TargetTy.getScalarType();
1213 unsigned GCD = std::gcd(OrigScalar.getSizeInBits().getFixedValue(),
1214 TargetScalar.getSizeInBits().getFixedValue());
1215 return LLT::scalar(GCD);
1216}
1217
1219 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
1220 "Only G_SHUFFLE_VECTOR can have a splat index!");
1221 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
1222 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });
1223
1224 // If all elements are undefined, this shuffle can be considered a splat.
1225 // Return 0 for better potential for callers to simplify.
1226 if (FirstDefinedIdx == Mask.end())
1227 return 0;
1228
1229 // Make sure all remaining elements are either undef or the same
1230 // as the first non-undef value.
1231 int SplatValue = *FirstDefinedIdx;
1232 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),
1233 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1234 return std::nullopt;
1235
1236 return SplatValue;
1237}
1238
1239static bool isBuildVectorOp(unsigned Opcode) {
1240 return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1241 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1242}
1243
1244namespace {
1245
1246std::optional<ValueAndVReg> getAnyConstantSplat(Register VReg,
1247 const MachineRegisterInfo &MRI,
1248 bool AllowUndef) {
1250 if (!MI)
1251 return std::nullopt;
1252
1253 bool isConcatVectorsOp = MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
1254 if (!isBuildVectorOp(MI->getOpcode()) && !isConcatVectorsOp)
1255 return std::nullopt;
1256
1257 std::optional<ValueAndVReg> SplatValAndReg;
1258 for (MachineOperand &Op : MI->uses()) {
1259 Register Element = Op.getReg();
1260 // If we have a G_CONCAT_VECTOR, we recursively look into the
1261 // vectors that we're concatenating to see if they're splats.
1262 auto ElementValAndReg =
1263 isConcatVectorsOp
1264 ? getAnyConstantSplat(Element, MRI, AllowUndef)
1266
1267 // If AllowUndef, treat undef as value that will result in a constant splat.
1268 if (!ElementValAndReg) {
1269 if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element)))
1270 continue;
1271 return std::nullopt;
1272 }
1273
1274 // Record splat value
1275 if (!SplatValAndReg)
1276 SplatValAndReg = ElementValAndReg;
1277
1278 // Different constant than the one already recorded, not a constant splat.
1279 if (SplatValAndReg->Value != ElementValAndReg->Value)
1280 return std::nullopt;
1281 }
1282
1283 return SplatValAndReg;
1284}
1285
1286} // end anonymous namespace
1287
1289 const MachineRegisterInfo &MRI,
1290 int64_t SplatValue, bool AllowUndef) {
1291 if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef))
1292 return mi_match(SplatValAndReg->VReg, MRI, m_SpecificICst(SplatValue));
1293 return false;
1294}
1295
1297 const MachineRegisterInfo &MRI,
1298 int64_t SplatValue, bool AllowUndef) {
1299 return isBuildVectorConstantSplat(MI.getOperand(0).getReg(), MRI, SplatValue,
1300 AllowUndef);
1301}
1302
1303std::optional<APInt>
1305 if (auto SplatValAndReg =
1306 getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false)) {
1307 if (std::optional<ValueAndVReg> ValAndVReg =
1308 getIConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI))
1309 return ValAndVReg->Value;
1310 }
1311
1312 return std::nullopt;
1313}
1314
1315std::optional<APInt>
1317 const MachineRegisterInfo &MRI) {
1318 return getIConstantSplatVal(MI.getOperand(0).getReg(), MRI);
1319}
1320
1321std::optional<int64_t>
1323 const MachineRegisterInfo &MRI) {
1324 if (auto SplatValAndReg =
1325 getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false))
1326 return getIConstantVRegSExtVal(SplatValAndReg->VReg, MRI);
1327 return std::nullopt;
1328}
1329
1330std::optional<int64_t>
1332 const MachineRegisterInfo &MRI) {
1333 return getIConstantSplatSExtVal(MI.getOperand(0).getReg(), MRI);
1334}
1335
1336std::optional<FPValueAndVReg>
1338 bool AllowUndef) {
1339 if (auto SplatValAndReg = getAnyConstantSplat(VReg, MRI, AllowUndef))
1340 return getFConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1341 return std::nullopt;
1342}
1343
1345 const MachineRegisterInfo &MRI,
1346 bool AllowUndef) {
1347 return isBuildVectorConstantSplat(MI, MRI, 0, AllowUndef);
1348}
1349
1351 const MachineRegisterInfo &MRI,
1352 bool AllowUndef) {
1353 return isBuildVectorConstantSplat(MI, MRI, -1, AllowUndef);
1354}
1355
1356std::optional<RegOrConstant>
1358 unsigned Opc = MI.getOpcode();
1359 if (!isBuildVectorOp(Opc))
1360 return std::nullopt;
1361 if (auto Splat = getIConstantSplatSExtVal(MI, MRI))
1362 return RegOrConstant(*Splat);
1363 auto Reg = MI.getOperand(1).getReg();
1364 if (any_of(drop_begin(MI.operands(), 2),
1365 [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
1366 return std::nullopt;
1367 return RegOrConstant(Reg);
1368}
1369
1371 const MachineRegisterInfo &MRI,
1372 bool AllowFP = true,
1373 bool AllowOpaqueConstants = true) {
1374 switch (MI.getOpcode()) {
1375 case TargetOpcode::G_CONSTANT:
1376 case TargetOpcode::G_IMPLICIT_DEF:
1377 return true;
1378 case TargetOpcode::G_FCONSTANT:
1379 return AllowFP;
1380 case TargetOpcode::G_GLOBAL_VALUE:
1381 case TargetOpcode::G_FRAME_INDEX:
1382 case TargetOpcode::G_BLOCK_ADDR:
1383 case TargetOpcode::G_JUMP_TABLE:
1384 return AllowOpaqueConstants;
1385 default:
1386 return false;
1387 }
1388}
1389
1391 const MachineRegisterInfo &MRI) {
1392 Register Def = MI.getOperand(0).getReg();
1393 if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
1394 return true;
1395 GBuildVector *BV = dyn_cast<GBuildVector>(&MI);
1396 if (!BV)
1397 return false;
1398 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1400 getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI))
1401 continue;
1402 return false;
1403 }
1404 return true;
1405}
1406
1408 const MachineRegisterInfo &MRI,
1409 bool AllowFP, bool AllowOpaqueConstants) {
1410 if (isConstantScalar(MI, MRI, AllowFP, AllowOpaqueConstants))
1411 return true;
1412
1413 if (!isBuildVectorOp(MI.getOpcode()))
1414 return false;
1415
1416 const unsigned NumOps = MI.getNumOperands();
1417 for (unsigned I = 1; I != NumOps; ++I) {
1418 const MachineInstr *ElementDef = MRI.getVRegDef(MI.getOperand(I).getReg());
1419 if (!isConstantScalar(*ElementDef, MRI, AllowFP, AllowOpaqueConstants))
1420 return false;
1421 }
1422
1423 return true;
1424}
1425
1426std::optional<APInt>
1428 const MachineRegisterInfo &MRI) {
1429 Register Def = MI.getOperand(0).getReg();
1430 if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
1431 return C->Value;
1432 auto MaybeCst = getIConstantSplatSExtVal(MI, MRI);
1433 if (!MaybeCst)
1434 return std::nullopt;
1435 const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();
1436 return APInt(ScalarSize, *MaybeCst, true);
1437}
1438
1440 const MachineRegisterInfo &MRI, bool AllowUndefs) {
1441 switch (MI.getOpcode()) {
1442 case TargetOpcode::G_IMPLICIT_DEF:
1443 return AllowUndefs;
1444 case TargetOpcode::G_CONSTANT:
1445 return MI.getOperand(1).getCImm()->isNullValue();
1446 case TargetOpcode::G_FCONSTANT: {
1447 const ConstantFP *FPImm = MI.getOperand(1).getFPImm();
1448 return FPImm->isZero() && !FPImm->isNegative();
1449 }
1450 default:
1451 if (!AllowUndefs) // TODO: isBuildVectorAllZeros assumes undef is OK already
1452 return false;
1453 return isBuildVectorAllZeros(MI, MRI);
1454 }
1455}
1456
1458 const MachineRegisterInfo &MRI,
1459 bool AllowUndefs) {
1460 switch (MI.getOpcode()) {
1461 case TargetOpcode::G_IMPLICIT_DEF:
1462 return AllowUndefs;
1463 case TargetOpcode::G_CONSTANT:
1464 return MI.getOperand(1).getCImm()->isAllOnesValue();
1465 default:
1466 if (!AllowUndefs) // TODO: isBuildVectorAllOnes assumes undef is OK already
1467 return false;
1468 return isBuildVectorAllOnes(MI, MRI);
1469 }
1470}
1471
1473 const MachineRegisterInfo &MRI, Register Reg,
1474 std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
1475
1476 const MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
1477 if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1478 return Match(nullptr);
1479
1480 // TODO: Also handle fconstant
1481 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1482 return Match(Def->getOperand(1).getCImm());
1483
1484 if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1485 return false;
1486
1487 for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
1488 Register SrcElt = Def->getOperand(I).getReg();
1489 const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
1490 if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1491 if (!Match(nullptr))
1492 return false;
1493 continue;
1494 }
1495
1496 if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||
1497 !Match(SrcDef->getOperand(1).getCImm()))
1498 return false;
1499 }
1500
1501 return true;
1502}
1503
1504bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
1505 bool IsFP) {
1506 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1507 case TargetLowering::UndefinedBooleanContent:
1508 return Val & 0x1;
1509 case TargetLowering::ZeroOrOneBooleanContent:
1510 return Val == 1;
1511 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1512 return Val == -1;
1513 }
1514 llvm_unreachable("Invalid boolean contents");
1515}
1516
1517bool llvm::isConstFalseVal(const TargetLowering &TLI, int64_t Val,
1518 bool IsVector, bool IsFP) {
1519 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1520 case TargetLowering::UndefinedBooleanContent:
1521 return ~Val & 0x1;
1522 case TargetLowering::ZeroOrOneBooleanContent:
1523 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1524 return Val == 0;
1525 }
1526 llvm_unreachable("Invalid boolean contents");
1527}
1528
1529int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
1530 bool IsFP) {
1531 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1532 case TargetLowering::UndefinedBooleanContent:
1533 case TargetLowering::ZeroOrOneBooleanContent:
1534 return 1;
1535 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1536 return -1;
1537 }
1538 llvm_unreachable("Invalid boolean contents");
1539}
1540
1543 const auto &F = MBB.getParent()->getFunction();
1544 return F.hasOptSize() || F.hasMinSize() ||
1546}
1547
1549 LostDebugLocObserver *LocObserver,
1550 SmallInstListTy &DeadInstChain) {
1551 for (MachineOperand &Op : MI.uses()) {
1552 if (Op.isReg() && Op.getReg().isVirtual())
1553 DeadInstChain.insert(MRI.getVRegDef(Op.getReg()));
1554 }
1555 LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
1556 DeadInstChain.remove(&MI);
1557 MI.eraseFromParent();
1558 if (LocObserver)
1559 LocObserver->checkpoint(false);
1560}
1561
1564 LostDebugLocObserver *LocObserver) {
1565 SmallInstListTy DeadInstChain;
1566 for (MachineInstr *MI : DeadInstrs)
1567 saveUsesAndErase(*MI, MRI, LocObserver, DeadInstChain);
1568
1569 while (!DeadInstChain.empty()) {
1570 MachineInstr *Inst = DeadInstChain.pop_back_val();
1571 if (!isTriviallyDead(*Inst, MRI))
1572 continue;
1573 saveUsesAndErase(*Inst, MRI, LocObserver, DeadInstChain);
1574 }
1575}
1576
1578 LostDebugLocObserver *LocObserver) {
1579 return eraseInstrs({&MI}, MRI, LocObserver);
1580}
1581
1583 for (auto &Def : MI.defs()) {
1584 assert(Def.isReg() && "Must be a reg");
1585
1587 for (auto &MOUse : MRI.use_operands(Def.getReg())) {
1588 MachineInstr *DbgValue = MOUse.getParent();
1589 // Ignore partially formed DBG_VALUEs.
1590 if (DbgValue->isNonListDebugValue() && DbgValue->getNumOperands() == 4) {
1591 DbgUsers.push_back(&MOUse);
1592 }
1593 }
1594
1595 if (!DbgUsers.empty()) {
1597 }
1598 }
1599}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned RegSize
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
basic Basic Alias true
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Definition: Utils.cpp:249
static bool isBuildVectorOp(unsigned Opcode)
Definition: Utils.cpp:1239
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Definition: Utils.cpp:1370
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Tracks DebugLocs between checkpoints and verifies that they are transferred.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
static const char PassName[]
BinaryOperator * Mul
Class recording the (high level) value of a variable.
opStatus divide(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1069
void copySign(const APFloat &RHS)
Definition: APFloat.h:1163
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:5196
opStatus subtract(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1051
opStatus add(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1042
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
Definition: APFloat.h:1193
opStatus multiply(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1060
APInt bitcastToAPInt() const
Definition: APFloat.h:1210
opStatus mod(const APFloat &RHS)
Definition: APFloat.h:1087
Class for arbitrary precision integers.
Definition: APInt.h:76
APInt udiv(const APInt &RHS) const
Unsigned division operation.
Definition: APInt.cpp:1579
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:981
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:1002
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:906
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1672
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1439
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
Definition: APInt.cpp:1650
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:1010
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:805
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
Definition: APInt.cpp:1742
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:954
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition: APInt.h:418
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:829
Represent the analysis usage information of a pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:268
const APFloat & getValueAPF() const
Definition: Constants.h:311
bool isNegative() const
Return true if the sign bit is set.
Definition: Constants.h:318
bool isZero() const
Return true if the value is positive or negative zero.
Definition: Constants.h:315
This is the shared class of boolean and integer constants.
Definition: Constants.h:80
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:145
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
static constexpr ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:296
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:302
Represents a G_BUILD_VECTOR.
Abstract class that contains various methods for clients to notify about changes.
KnownBits getKnownBits(Register R)
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
Definition: GISelWorkList.h:74
MachineInstr * pop_back_val()
bool empty() const
Definition: GISelWorkList.h:38
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Definition: GISelWorkList.h:83
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
Definition: LowLevelType.h:182
constexpr unsigned getScalarSizeInBits() const
Definition: LowLevelType.h:267
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelType.h:64
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr bool isValid() const
Definition: LowLevelType.h:145
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:159
constexpr bool isVector() const
Definition: LowLevelType.h:148
constexpr bool isScalable() const
Returns true if the LLT is a scalable vector.
Definition: LowLevelType.h:170
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:193
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:290
constexpr ElementCount getElementCount() const
Definition: LowLevelType.h:184
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelType.h:100
constexpr bool isFixedVector() const
Returns true if the LLT is a fixed vector.
Definition: LowLevelType.h:178
constexpr LLT getScalarType() const
Definition: LowLevelType.h:208
static constexpr LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
Definition: LowLevelType.h:124
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:230
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFunctionProperties & set(Property P)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
GISelChangeObserver * getObserver() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Helper class to build MachineInstr.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:546
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:329
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:379
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:710
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:475
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:556
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Diagnostic information for missed-optimization remarks.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Analysis providing profile information.
Represents a value which can be a Register or a constant.
Definition: Utils.h:387
Holds all the information related to register banks.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:950
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
Target-Independent Code Generator Pass Configuration Options.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:187
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
constexpr LeafTy multiplyCoefficientBy(ScalarTy RHS) const
Definition: TypeSize.h:243
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
Definition: APInt.h:2178
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
Definition: APInt.h:2183
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
Definition: APInt.h:2188
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
Definition: APInt.h:2193
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
DiagnosticInfoMIROptimization::MachineArgument MNV
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:882
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:329
@ Offset
Definition: DWP.cpp:456
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1344
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:54
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:625
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:438
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:293
std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:956
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1304
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
Definition: Utils.cpp:1457
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:713
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition: Utils.cpp:1582
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:153
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
std::optional< SmallVector< unsigned > > ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB)
Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.
Definition: Utils.cpp:969
std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:915
std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1357
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
Definition: APFloat.h:1436
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1427
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Definition: Utils.cpp:1439
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:465
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1472
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1504
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:1076
std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:305
std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:644
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1541
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1738
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 maximumNumber semantics.
Definition: APFloat.h:1410
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
Definition: Utils.cpp:1407
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:428
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:199
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1548
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:273
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:419
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1350
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:767
std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1337
std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:932
void extractParts(Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Helper function to split a wide generic register into bitwise blocks with the given Type (which impli...
Definition: Utils.cpp:479
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:1072
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:1143
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 minimumNumber semantics.
Definition: APFloat.h:1396
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:427
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Definition: Utils.cpp:1517
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:631
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1288
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1577
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
@ DS_Warning
@ DS_Error
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:44
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1529
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:413
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1758
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:330
std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:446
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1562
void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
bool isKnownNeverNaN(const Value *V, unsigned Depth, const SimplifyQuery &SQ)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:472
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:1164
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
Definition: APFloat.h:1423
std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1322
void extractVectorParts(Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Version which handles irregular sub-vector splits.
Definition: Utils.cpp:583
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:220
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:865
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:267
#define MORE()
Definition: regcomp.c:252
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:224
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
Definition: KnownBits.h:285
unsigned countMinPopulation() const
Returns the number of bits known to be one.
Definition: KnownBits.h:282
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:183