39#define DEBUG_TYPE "globalisel-utils"
42using namespace MIPatternMatch;
49 return MRI.createVirtualRegister(&RegClass);
61 assert(Reg.isVirtual() &&
"PhysReg not implemented");
67 auto *OldRegClass =
MRI.getRegClassOrNull(Reg);
71 if (ConstrainedReg != Reg) {
78 TII.get(TargetOpcode::COPY), ConstrainedReg)
83 TII.get(TargetOpcode::COPY), Reg)
87 Observer->changingInstr(*RegMO.
getParent());
89 RegMO.
setReg(ConstrainedReg);
91 Observer->changedInstr(*RegMO.
getParent());
93 }
else if (OldRegClass !=
MRI.getRegClassOrNull(Reg)) {
97 Observer->changedInstr(*RegDef);
99 Observer->changingAllUsesOfReg(
MRI, Reg);
100 Observer->finishedChangingAllUsesOfReg();
103 return ConstrainedReg;
113 assert(Reg.isVirtual() &&
"PhysReg not implemented");
126 if (
const auto *SubRC =
TRI.getCommonSubClass(
127 OpRC,
TRI.getConstrainedRegClassForOperand(RegMO,
MRI)))
130 OpRC =
TRI.getAllocatableClass(OpRC);
135 "Register class constraint is required unless either the "
136 "instruction is target independent or the operand is a use");
158 "A selected instruction is expected");
163 for (
unsigned OpI = 0, OpE =
I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
171 assert(MO.
isReg() &&
"Unsupported non-reg operand");
175 if (Reg.isPhysical())
191 int DefIdx =
I.getDesc().getOperandConstraint(OpI,
MCOI::TIED_TO);
192 if (DefIdx != -1 && !
I.isRegTiedToUseOperand(DefIdx))
193 I.tieOperands(DefIdx, OpI);
205 if (
MRI.getType(DstReg) !=
MRI.getType(SrcReg))
209 const auto &DstRBC =
MRI.getRegClassOrRegBank(DstReg);
210 if (!DstRBC || DstRBC ==
MRI.getRegClassOrRegBank(SrcReg))
215 return DstRBC.is<
const RegisterBank *>() &&
MRI.getRegClassOrNull(SrcReg) &&
217 *
MRI.getRegClassOrNull(SrcReg));
227 if (
MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
230 if (
MI.getOpcode() == TargetOpcode::LIFETIME_START ||
231 MI.getOpcode() == TargetOpcode::LIFETIME_END)
236 bool SawStore =
false;
237 if (!
MI.isSafeToMove(
nullptr, SawStore) && !
MI.isPHI())
241 for (
const auto &MO :
MI.all_defs()) {
243 if (Reg.isPhysical() || !
MRI.use_nodbg_empty(Reg))
254 bool IsFatal = Severity ==
DS_Error &&
258 if (!R.getLocation().isValid() || IsFatal)
259 R << (
" (in function: " + MF.
getName() +
")").str();
285 MI.getDebugLoc(),
MI.getParent());
297 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
298 "Value found while looking through instrs");
301 return ValAndVReg->Value;
304std::optional<int64_t>
307 if (Val && Val->getBitWidth() <= 64)
308 return Val->getSExtValue();
315typedef std::function<std::optional<APInt>(
const MachineInstr *
MI)> GetAPCstFn;
317std::optional<ValueAndVReg> getConstantVRegValWithLookThrough(
319 GetAPCstFn getAPCstValue,
bool LookThroughInstrs =
true,
320 bool LookThroughAnyExt =
false) {
324 while ((
MI =
MRI.getVRegDef(VReg)) && !IsConstantOpcode(
MI) &&
326 switch (
MI->getOpcode()) {
327 case TargetOpcode::G_ANYEXT:
328 if (!LookThroughAnyExt)
331 case TargetOpcode::G_TRUNC:
332 case TargetOpcode::G_SEXT:
333 case TargetOpcode::G_ZEXT:
336 MRI.getType(
MI->getOperand(0).getReg()).getSizeInBits()));
337 VReg =
MI->getOperand(1).getReg();
339 case TargetOpcode::COPY:
340 VReg =
MI->getOperand(1).getReg();
344 case TargetOpcode::G_INTTOPTR:
345 VReg =
MI->getOperand(1).getReg();
351 if (!
MI || !IsConstantOpcode(
MI))
354 std::optional<APInt> MaybeVal = getAPCstValue(
MI);
357 APInt &Val = *MaybeVal;
360 case TargetOpcode::G_TRUNC:
363 case TargetOpcode::G_ANYEXT:
364 case TargetOpcode::G_SEXT:
367 case TargetOpcode::G_ZEXT:
379 return MI->getOpcode() == TargetOpcode::G_CONSTANT;
385 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
391 unsigned Opc =
MI->getOpcode();
392 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
402std::optional<APInt> getCImmOrFPImmAsAPInt(
const MachineInstr *
MI) {
415 return getConstantVRegValWithLookThrough(VReg,
MRI, isIConstant,
416 getCImmAsAPInt, LookThroughInstrs);
421 bool LookThroughAnyExt) {
422 return getConstantVRegValWithLookThrough(
423 VReg,
MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
429 auto Reg = getConstantVRegValWithLookThrough(
430 VReg,
MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
440 if (TargetOpcode::G_FCONSTANT !=
MI->getOpcode())
442 return MI->getOperand(1).getFPImm();
445std::optional<DefinitionAndSourceRegister>
450 if (!DstTy.isValid())
455 auto SrcTy =
MRI.getType(SrcReg);
456 if (!SrcTy.isValid())
467 std::optional<DefinitionAndSourceRegister> DefSrcReg =
469 return DefSrcReg ? DefSrcReg->MI :
nullptr;
474 std::optional<DefinitionAndSourceRegister> DefSrcReg =
476 return DefSrcReg ? DefSrcReg->Reg :
Register();
483 for (
int i = 0; i < NumParts; ++i)
497 unsigned NumParts =
RegSize / MainSize;
498 unsigned LeftoverSize =
RegSize - NumParts * MainSize;
501 if (LeftoverSize == 0) {
502 for (
unsigned I = 0;
I < NumParts; ++
I)
503 VRegs.
push_back(
MRI.createGenericVirtualRegister(MainTy));
516 unsigned LeftoverNumElts = RegNumElts % MainNumElts;
518 if (MainNumElts % LeftoverNumElts == 0 &&
519 RegNumElts % LeftoverNumElts == 0 &&
521 LeftoverNumElts > 1) {
527 extractParts(Reg, LeftoverTy, RegNumElts / LeftoverNumElts, UnmergeValues,
531 unsigned LeftoverPerMain = MainNumElts / LeftoverNumElts;
532 unsigned NumOfLeftoverVal =
533 ((RegNumElts % MainNumElts) / LeftoverNumElts);
537 for (
unsigned I = 0;
I < UnmergeValues.
size() - NumOfLeftoverVal;
I++) {
539 if (MergeValues.
size() == LeftoverPerMain) {
546 for (
unsigned I = UnmergeValues.
size() - NumOfLeftoverVal;
547 I < UnmergeValues.
size();
I++) {
558 for (
unsigned i = 0; i < RegPieces.
size() - 1; ++i)
561 LeftoverTy =
MRI.getType(LeftoverRegs[0]);
567 for (
unsigned I = 0;
I != NumParts; ++
I) {
568 Register NewReg =
MRI.createGenericVirtualRegister(MainTy);
575 Register NewReg =
MRI.createGenericVirtualRegister(LeftoverTy);
587 LLT RegTy =
MRI.getType(Reg);
593 unsigned LeftoverNumElts = RegNumElts % NumElts;
594 unsigned NumNarrowTyPieces = RegNumElts / NumElts;
597 if (LeftoverNumElts == 0)
598 return extractParts(Reg, NarrowTy, NumNarrowTyPieces, VRegs, MIRBuilder,
609 for (
unsigned i = 0; i < NumNarrowTyPieces; ++i,
Offset += NumElts) {
615 if (LeftoverNumElts == 1) {
640 APF.
convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
656 const APInt &C1 = MaybeOp1Cst->Value;
657 const APInt &C2 = MaybeOp2Cst->Value;
661 case TargetOpcode::G_ADD:
663 case TargetOpcode::G_PTR_ADD:
667 case TargetOpcode::G_AND:
669 case TargetOpcode::G_ASHR:
671 case TargetOpcode::G_LSHR:
673 case TargetOpcode::G_MUL:
675 case TargetOpcode::G_OR:
677 case TargetOpcode::G_SHL:
679 case TargetOpcode::G_SUB:
681 case TargetOpcode::G_XOR:
683 case TargetOpcode::G_UDIV:
684 if (!C2.getBoolValue())
687 case TargetOpcode::G_SDIV:
688 if (!C2.getBoolValue())
691 case TargetOpcode::G_UREM:
692 if (!C2.getBoolValue())
695 case TargetOpcode::G_SREM:
696 if (!C2.getBoolValue())
699 case TargetOpcode::G_SMIN:
701 case TargetOpcode::G_SMAX:
703 case TargetOpcode::G_UMIN:
705 case TargetOpcode::G_UMAX:
712std::optional<APFloat>
726 case TargetOpcode::G_FADD:
727 C1.
add(C2, APFloat::rmNearestTiesToEven);
729 case TargetOpcode::G_FSUB:
730 C1.
subtract(C2, APFloat::rmNearestTiesToEven);
732 case TargetOpcode::G_FMUL:
733 C1.
multiply(C2, APFloat::rmNearestTiesToEven);
735 case TargetOpcode::G_FDIV:
736 C1.
divide(C2, APFloat::rmNearestTiesToEven);
738 case TargetOpcode::G_FREM:
741 case TargetOpcode::G_FCOPYSIGN:
744 case TargetOpcode::G_FMINNUM:
746 case TargetOpcode::G_FMAXNUM:
748 case TargetOpcode::G_FMINIMUM:
750 case TargetOpcode::G_FMAXIMUM:
752 case TargetOpcode::G_FMINNUM_IEEE:
753 case TargetOpcode::G_FMAXNUM_IEEE:
770 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2,
MRI);
774 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1,
MRI);
779 for (
unsigned Idx = 0, E = SrcVec1->getNumSources();
Idx < E; ++
Idx) {
781 SrcVec2->getSourceReg(
Idx),
MRI);
786 return FoldedElements;
801 return !FPVal->getValueAPF().isNaN() ||
802 (SNaN && !FPVal->getValueAPF().isSignaling());
815 case TargetOpcode::G_FADD:
816 case TargetOpcode::G_FSUB:
817 case TargetOpcode::G_FMUL:
818 case TargetOpcode::G_FDIV:
819 case TargetOpcode::G_FREM:
820 case TargetOpcode::G_FSIN:
821 case TargetOpcode::G_FCOS:
822 case TargetOpcode::G_FMA:
823 case TargetOpcode::G_FMAD:
829 case TargetOpcode::G_FMINNUM_IEEE:
830 case TargetOpcode::G_FMAXNUM_IEEE: {
840 case TargetOpcode::G_FMINNUM:
841 case TargetOpcode::G_FMAXNUM: {
853 case TargetOpcode::G_FPEXT:
854 case TargetOpcode::G_FPTRUNC:
855 case TargetOpcode::G_FCANONICALIZE:
867 auto PSV = dyn_cast_if_present<const PseudoSourceValue *>(MPO.
V);
868 if (
auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
874 if (
const Value *V = dyn_cast_if_present<const Value *>(MPO.
V)) {
876 return V->getPointerAlignment(M->getDataLayout());
894 assert(Def->getParent() == &EntryMBB &&
"live-in copy not in entry block");
905 MRI.setType(LiveIn, RegTy);
923 case TargetOpcode::G_SEXT_INREG: {
924 LLT Ty =
MRI.getType(Op1);
942 case TargetOpcode::G_SEXT:
943 return Val->sext(DstSize);
944 case TargetOpcode::G_ZEXT:
945 case TargetOpcode::G_ANYEXT:
947 return Val->zext(DstSize);
955std::optional<APFloat>
958 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
962 APFloat::rmNearestTiesToEven);
968std::optional<SmallVector<unsigned>>
970 std::function<
unsigned(
APInt)> CB) {
971 LLT Ty =
MRI.getType(Src);
973 auto tryFoldScalar = [&](
Register R) -> std::optional<unsigned> {
977 return CB(*MaybeCst);
981 auto *BV = getOpcodeDef<GBuildVector>(Src,
MRI);
984 for (
unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
985 if (
auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
993 if (
auto MaybeCst = tryFoldScalar(Src)) {
1002 std::optional<DefinitionAndSourceRegister> DefSrcReg =
1008 const LLT Ty =
MRI.getType(Reg);
1010 switch (
MI.getOpcode()) {
1011 case TargetOpcode::G_CONSTANT: {
1016 case TargetOpcode::G_SHL: {
1028 case TargetOpcode::G_LSHR: {
1030 if (ConstLHS->isSignMask())
1036 case TargetOpcode::G_BUILD_VECTOR: {
1045 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1051 if (!Const || !Const->zextOrTrunc(
BitWidth).isPowerOf2())
1092 "getLCMType not implemented between fixed and scalable vectors.");
1112 LLT VecTy = OrigTy.
isVector() ? OrigTy : TargetTy;
1113 LLT ScalarTy = OrigTy.
isVector() ? TargetTy : OrigTy;
1148 "getCoverTy not implemented between fixed and scalable vectors.");
1156 if (OrigTyNumElts % TargetTyNumElts == 0)
1159 unsigned NumElts =
alignTo(OrigTyNumElts, TargetTyNumElts);
1179 "getGCDType not implemented between fixed and scalable vectors.");
1219 assert(
MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
1220 "Only G_SHUFFLE_VECTOR can have a splat index!");
1222 auto FirstDefinedIdx =
find_if(Mask, [](
int Elt) {
return Elt >= 0; });
1226 if (FirstDefinedIdx == Mask.end())
1231 int SplatValue = *FirstDefinedIdx;
1233 [&SplatValue](
int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1234 return std::nullopt;
1240 return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1241 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1246std::optional<ValueAndVReg> getAnyConstantSplat(
Register VReg,
1251 return std::nullopt;
1253 bool isConcatVectorsOp =
MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
1255 return std::nullopt;
1257 std::optional<ValueAndVReg> SplatValAndReg;
1262 auto ElementValAndReg =
1264 ? getAnyConstantSplat(Element,
MRI, AllowUndef)
1268 if (!ElementValAndReg) {
1269 if (AllowUndef && isa<GImplicitDef>(
MRI.getVRegDef(Element)))
1271 return std::nullopt;
1275 if (!SplatValAndReg)
1276 SplatValAndReg = ElementValAndReg;
1279 if (SplatValAndReg->Value != ElementValAndReg->Value)
1280 return std::nullopt;
1283 return SplatValAndReg;
1290 int64_t SplatValue,
bool AllowUndef) {
1291 if (
auto SplatValAndReg = getAnyConstantSplat(Reg,
MRI, AllowUndef))
1298 int64_t SplatValue,
bool AllowUndef) {
1305 if (
auto SplatValAndReg =
1306 getAnyConstantSplat(Reg,
MRI,
false)) {
1307 if (std::optional<ValueAndVReg> ValAndVReg =
1309 return ValAndVReg->Value;
1312 return std::nullopt;
1321std::optional<int64_t>
1324 if (
auto SplatValAndReg =
1325 getAnyConstantSplat(Reg,
MRI,
false))
1327 return std::nullopt;
1330std::optional<int64_t>
1336std::optional<FPValueAndVReg>
1339 if (
auto SplatValAndReg = getAnyConstantSplat(VReg,
MRI, AllowUndef))
1341 return std::nullopt;
1356std::optional<RegOrConstant>
1358 unsigned Opc =
MI.getOpcode();
1360 return std::nullopt;
1363 auto Reg =
MI.getOperand(1).getReg();
1366 return std::nullopt;
1372 bool AllowFP =
true,
1373 bool AllowOpaqueConstants =
true) {
1374 switch (
MI.getOpcode()) {
1375 case TargetOpcode::G_CONSTANT:
1376 case TargetOpcode::G_IMPLICIT_DEF:
1378 case TargetOpcode::G_FCONSTANT:
1380 case TargetOpcode::G_GLOBAL_VALUE:
1381 case TargetOpcode::G_FRAME_INDEX:
1382 case TargetOpcode::G_BLOCK_ADDR:
1383 case TargetOpcode::G_JUMP_TABLE:
1384 return AllowOpaqueConstants;
1398 for (
unsigned SrcIdx = 0; SrcIdx < BV->
getNumSources(); ++SrcIdx) {
1409 bool AllowFP,
bool AllowOpaqueConstants) {
1416 const unsigned NumOps =
MI.getNumOperands();
1417 for (
unsigned I = 1;
I != NumOps; ++
I) {
1434 return std::nullopt;
1435 const unsigned ScalarSize =
MRI.getType(Def).getScalarSizeInBits();
1436 return APInt(ScalarSize, *MaybeCst,
true);
1441 switch (
MI.getOpcode()) {
1442 case TargetOpcode::G_IMPLICIT_DEF:
1444 case TargetOpcode::G_CONSTANT:
1445 return MI.getOperand(1).getCImm()->isNullValue();
1446 case TargetOpcode::G_FCONSTANT: {
1460 switch (
MI.getOpcode()) {
1461 case TargetOpcode::G_IMPLICIT_DEF:
1463 case TargetOpcode::G_CONSTANT:
1464 return MI.getOperand(1).getCImm()->isAllOnesValue();
1474 std::function<
bool(
const Constant *ConstVal)>
Match,
bool AllowUndefs) {
1477 if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1478 return Match(
nullptr);
1481 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1482 return Match(Def->getOperand(1).getCImm());
1484 if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1487 for (
unsigned I = 1, E = Def->getNumOperands();
I != E; ++
I) {
1488 Register SrcElt = Def->getOperand(
I).getReg();
1490 if (AllowUndefs && SrcDef->
getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1491 if (!
Match(
nullptr))
1496 if (SrcDef->
getOpcode() != TargetOpcode::G_CONSTANT ||
1507 case TargetLowering::UndefinedBooleanContent:
1509 case TargetLowering::ZeroOrOneBooleanContent:
1511 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1518 bool IsVector,
bool IsFP) {
1520 case TargetLowering::UndefinedBooleanContent:
1522 case TargetLowering::ZeroOrOneBooleanContent:
1523 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1532 case TargetLowering::UndefinedBooleanContent:
1533 case TargetLowering::ZeroOrOneBooleanContent:
1535 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1544 return F.hasOptSize() ||
F.hasMinSize() ||
1552 if (
Op.isReg() &&
Op.getReg().isVirtual())
1553 DeadInstChain.
insert(
MRI.getVRegDef(
Op.getReg()));
1557 MI.eraseFromParent();
1569 while (!DeadInstChain.
empty()) {
1583 for (
auto &Def :
MI.defs()) {
1584 assert(Def.isReg() &&
"Must be a reg");
1587 for (
auto &MOUse :
MRI.use_operands(Def.getReg())) {
1595 if (!DbgUsers.
empty()) {
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
static bool isBuildVectorOp(unsigned Opcode)
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
Tracks DebugLocs between checkpoints and verifies that they are transferred.
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
static const char PassName[]
Class recording the (high level) value of a variable.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
APInt bitcastToAPInt() const
opStatus mod(const APFloat &RHS)
Class for arbitrary precision integers.
APInt udiv(const APInt &RHS) const
Unsigned division operation.
APInt zext(unsigned width) const
Zero extend to a new width.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
APInt trunc(unsigned width) const
Truncate to new width.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
unsigned getBitWidth() const
Return the number of bits in the APInt.
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
APInt sext(unsigned width) const
Sign extend to a new width.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
bool isNegative() const
Return true if the sign bit is set.
bool isZero() const
Return true if the value is positive or negative zero.
This is the shared class of boolean and integer constants.
const APInt & getValue() const
Return the constant as an APInt value reference.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
static constexpr ElementCount getFixed(ScalarTy MinVal)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Represents a G_BUILD_VECTOR.
Abstract class that contains various methods for clients to notify about changes.
KnownBits getKnownBits(Register R)
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
MachineInstr * pop_back_val()
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
Module * getParent()
Get the module that this global value is contained inside of...
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr bool isScalable() const
Returns true if the LLT is a scalable vector.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
constexpr bool isFixedVector() const
Returns true if the LLT is a fixed vector.
constexpr LLT getScalarType() const
static constexpr LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Describe properties that are true of each instruction in the target description file.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Wrapper class representing physical registers. Should be passed by value.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFunctionProperties & set(Property P)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
GISelChangeObserver * getObserver() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Helper class to build MachineInstr.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Analysis providing profile information.
Represents a value which can be a Register or a constant.
Holds all the information related to register banks.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Target-Independent Code Generator Pass Configuration Options.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
constexpr ScalarTy getFixedValue() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr LeafTy multiplyCoefficientBy(ScalarTy RHS) const
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
@ C
The default llvm calling convention, compatible with C.
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
DiagnosticInfoMIROptimization::MachineArgument MNV
This is an optimization pass for GlobalISel generic memory operations.
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
std::optional< SmallVector< unsigned > > ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB)
Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.
std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 maximumNumber semantics.
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
auto reverse(ContainerTy &&C)
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)
void extractParts(Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Helper function to split a wide generic register into bitwise blocks with the given Type (which impli...
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 minimumNumber semantics.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
constexpr unsigned BitWidth
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
bool isKnownNeverNaN(const Value *V, unsigned Depth, const SimplifyQuery &SQ)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
void extractVectorParts(Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Version which handles irregular sub-vector splits.
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Simple struct used to hold a Register value and the instruction which defines it.
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
unsigned countMinPopulation() const
Returns the number of bits known to be one.
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Simple struct used to hold a constant integer value and a virtual register.