LLVM  10.0.0svn
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/Register.h"
21 
22 namespace llvm {
23 
24 class AnalysisUsage;
25 class MachineFunction;
26 class MachineInstr;
27 class MachineOperand;
28 class MachineOptimizationRemarkEmitter;
29 class MachineOptimizationRemarkMissed;
30 class MachineRegisterInfo;
31 class MCInstrDesc;
32 class RegisterBankInfo;
33 class TargetInstrInfo;
34 class TargetPassConfig;
35 class TargetRegisterInfo;
36 class TargetRegisterClass;
37 class Twine;
38 class ConstantFP;
39 class APFloat;
40 
41 /// Try to constrain Reg to the specified register class. If this fails,
42 /// create a new virtual register in the correct class.
43 ///
44 /// \return The virtual register constrained to the right register class.
45 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
46  const TargetInstrInfo &TII,
47  const RegisterBankInfo &RBI, unsigned Reg,
48  const TargetRegisterClass &RegClass);
49 
50 /// Constrain the Register operand OpIdx, so that it is now constrained to the
51 /// TargetRegisterClass passed as an argument (RegClass).
52 /// If this fails, create a new virtual register in the correct class and
53 /// insert a COPY before \p InsertPt if it is a use or after if it is a
54 /// definition. The debug location of \p InsertPt is used for the new copy.
55 ///
56 /// \return The virtual register constrained to the right register class.
57 unsigned constrainOperandRegClass(const MachineFunction &MF,
58  const TargetRegisterInfo &TRI,
59  MachineRegisterInfo &MRI,
60  const TargetInstrInfo &TII,
61  const RegisterBankInfo &RBI,
62  MachineInstr &InsertPt,
63  const TargetRegisterClass &RegClass,
64  const MachineOperand &RegMO, unsigned OpIdx);
65 
66 /// Try to constrain Reg so that it is usable by argument OpIdx of the
67 /// provided MCInstrDesc \p II. If this fails, create a new virtual
68 /// register in the correct class and insert a COPY before \p InsertPt
69 /// if it is a use or after if it is a definition.
70 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
71 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
72 /// InsertPt is used for the new copy.
73 ///
74 /// \return The virtual register constrained to the right register class.
75 unsigned constrainOperandRegClass(const MachineFunction &MF,
76  const TargetRegisterInfo &TRI,
77  MachineRegisterInfo &MRI,
78  const TargetInstrInfo &TII,
79  const RegisterBankInfo &RBI,
80  MachineInstr &InsertPt, const MCInstrDesc &II,
81  const MachineOperand &RegMO, unsigned OpIdx);
82 
83 /// Mutate the newly-selected instruction \p I to constrain its (possibly
84 /// generic) virtual register operands to the instruction's register class.
85 /// This could involve inserting COPYs before (for uses) or after (for defs).
86 /// This requires the number of operands to match the instruction description.
87 /// \returns whether operand regclass constraining succeeded.
88 ///
89 // FIXME: Not all instructions have the same number of operands. We should
90 // probably expose a constrain helper per operand and let the target selector
91 // constrain individual registers, like fast-isel.
92 bool constrainSelectedInstRegOperands(MachineInstr &I,
93  const TargetInstrInfo &TII,
94  const TargetRegisterInfo &TRI,
95  const RegisterBankInfo &RBI);
96 /// Check whether an instruction \p MI is dead: it only defines dead virtual
97 /// registers, and doesn't have other side effects.
98 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
99 
100 /// Report an ISel error as a missed optimization remark to the LLVMContext's
101 /// diagnostic stream. Set the FailedISel MachineFunction property.
102 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
103  MachineOptimizationRemarkEmitter &MORE,
104  MachineOptimizationRemarkMissed &R);
105 
106 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
107  MachineOptimizationRemarkEmitter &MORE,
108  const char *PassName, StringRef Msg,
109  const MachineInstr &MI);
110 
111 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
112 /// returns it.
113 Optional<int64_t> getConstantVRegVal(unsigned VReg,
114  const MachineRegisterInfo &MRI);
115 /// Simple struct used to hold a constant integer value and a virtual
116 /// register.
117 struct ValueAndVReg {
118  int64_t Value;
119  unsigned VReg;
120 };
121 /// If \p VReg is defined by a statically evaluable chain of
122 /// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true)
123 /// and that constant fits in int64_t, returns its value as well as the
124 /// virtual register defined by this G_F/CONSTANT.
125 /// When \p LookThroughInstrs == false this function behaves like
126 /// getConstantVRegVal.
127 /// When \p HandleFConstants == false the function bails on G_FCONSTANTs.
130  bool LookThroughInstrs = true,
131  bool HandleFConstants = true);
132 const ConstantFP* getConstantFPVRegVal(unsigned VReg,
133  const MachineRegisterInfo &MRI);
134 
135 /// See if Reg is defined by an single def instruction that is
136 /// Opcode. Also try to do trivial folding if it's a COPY with
137 /// same types. Returns null otherwise.
138 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
139  const MachineRegisterInfo &MRI);
140 
141 /// Find the def instruction for \p Reg, folding away any trivial copies. Note
142 /// it may still return a COPY, if it changes the type. May return nullptr if \p
143 /// Reg is not a generic virtual register.
145  const MachineRegisterInfo &MRI);
146 
147 /// Returns an APFloat from Val converted to the appropriate size.
148 APFloat getAPFloatFromSize(double Val, unsigned Size);
149 
150 /// Modify analysis usage so it preserves passes required for the SelectionDAG
151 /// fallback.
153 
154 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const unsigned Op1,
155  const unsigned Op2,
156  const MachineRegisterInfo &MRI);
157 
158 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const unsigned Op1,
159  uint64_t Imm, const MachineRegisterInfo &MRI);
160 
161 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
162 /// this returns if \p Val can be assumed to never be a signaling NaN.
164  bool SNaN = false);
165 
166 /// Returns true if \p Val can be assumed to never be a signaling NaN.
168  return isKnownNeverNaN(Val, MRI, true);
169 }
170 
171 /// Get a rough equivalent of an MVT for a given LLT.
172 MVT getMVTForLLT(LLT Ty);
173 /// Get a rough equivalent of an LLT for a given MVT.
174 LLT getLLTForMVT(MVT Ty);
175 
176 } // End namespace llvm.
177 #endif
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:117
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:431
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:295
unsigned Reg
unsigned const TargetRegisterInfo * TRI
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:303
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:167
int64_t Value
Definition: Utils.h:118
const HexagonInstrInfo * TII
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, const unsigned Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:338
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:30
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:325
MVT getMVTForLLT(LLT Ty)
Get a rough equivalent of an MVT for a given LLT.
Definition: Utils.cpp:435
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
LLT getLLTForMVT(MVT Ty)
Get a rough equivalent of an LLT for a given MVT.
Definition: Utils.cpp:444
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Represent the analysis usage information of a pass.
unsigned VReg
Definition: Utils.h:119
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThro...
Definition: Utils.cpp:218
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:319
#define MORE()
Definition: regcomp.c:252
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:111
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:207
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:158
Representation of each machine instruction.
Definition: MachineInstr.h:64
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const unsigned Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:414
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t Size
Definition: Profile.cpp:46
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
IRTranslator LLVM IR MI
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:178
Wrapper class representing virtual and physical registers.
Definition: Register.h:19