LLVM  10.0.0svn
Context.h
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1 //===---------------------------- Context.h ---------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines a class for holding ownership of various simulated
11 /// hardware units. A Context also provides a utility routine for constructing
12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13 /// stages.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_MCA_CONTEXT_H
18 #define LLVM_MCA_CONTEXT_H
19 
20 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MCA/Pipeline.h"
24 #include "llvm/MCA/SourceMgr.h"
25 #include <memory>
26 
27 namespace llvm {
28 namespace mca {
29 
30 /// This is a convenience struct to hold the parameters necessary for creating
31 /// the pre-built "default" out-of-order pipeline.
33  PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS,
34  unsigned LQS, unsigned SQS, bool NoAlias,
35  bool ShouldEnableBottleneckAnalysis = false)
36  : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr),
38  StoreQueueSize(SQS), AssumeNoAlias(NoAlias),
39  EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {}
40  unsigned MicroOpQueueSize;
41  unsigned DecodersThroughput; // Instructions per cycle.
42  unsigned DispatchWidth;
43  unsigned RegisterFileSize;
44  unsigned LoadQueueSize;
45  unsigned StoreQueueSize;
48 };
49 
50 class Context {
52  const MCRegisterInfo &MRI;
53  const MCSubtargetInfo &STI;
54 
55 public:
56  Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
57  Context(const Context &C) = delete;
58  Context &operator=(const Context &C) = delete;
59 
60  const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
61  const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
62 
63  void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
64  Hardware.push_back(std::move(H));
65  }
66 
67  /// Construct a basic pipeline for simulating an out-of-order pipeline.
68  /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
69  std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
70  SourceMgr &SrcMgr);
71 };
72 
73 } // namespace mca
74 } // namespace llvm
75 #endif // LLVM_MCA_CONTEXT_H
uint64_t CallInst * C
void addHardwareUnit(std::unique_ptr< HardwareUnit > H)
Definition: Context.h:63
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
SourceMgr SrcMgr
Definition: Error.cpp:23
The two locations do not alias at all.
Definition: AliasAnalysis.h:84
This is a convenience struct to hold the parameters necessary for creating the pre-built "default" ou...
Definition: Context.h:32
const MCSubtargetInfo & getMCSubtargetInfo() const
Definition: Context.h:61
unsigned DecodersThroughput
Definition: Context.h:41
This file implements an ordered container of stages that simulate the pipeline of a hardware backend...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
const MCRegisterInfo & getMCRegisterInfo() const
Definition: Context.h:60
#define H(x, y, z)
Definition: MD5.cpp:57
This file defines a base class for describing a simulated hardware unit.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
This file implements class SourceMgr.
Generic base class for all target subtargets.
PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS, bool NoAlias, bool ShouldEnableBottleneckAnalysis=false)
Definition: Context.h:33
Context(const MCRegisterInfo &R, const MCSubtargetInfo &S)
Definition: Context.h:56