LLVM  10.0.0svn
DetectDeadLanes.cpp
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1 //===- DetectDeadLanes.cpp - SubRegister Lane Usage Analysis --*- C++ -*---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Analysis that tracks defined/used subregister lanes across COPY instructions
11 /// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
12 /// INSERT_SUBREG, EXTRACT_SUBREG).
13 /// The information is used to detect dead definitions and the usage of
14 /// (completely) undefined values and mark the operands as such.
15 /// This pass is necessary because the dead/undef status is not obvious anymore
16 /// when subregisters are involved.
17 ///
18 /// Example:
19 /// %0 = some definition
20 /// %1 = IMPLICIT_DEF
21 /// %2 = REG_SEQUENCE %0, sub0, %1, sub1
22 /// %3 = EXTRACT_SUBREG %2, sub1
23 /// = use %3
24 /// The %0 definition is dead and %3 contains an undefined value.
25 //
26 //===----------------------------------------------------------------------===//
27 
28 #include <deque>
29 #include <vector>
30 
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/SetVector.h"
35 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Pass.h"
40 #include "llvm/PassRegistry.h"
41 #include "llvm/Support/Debug.h"
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "detect-dead-lanes"
47 
48 namespace {
49 
50 /// Contains a bitmask of which lanes of a given virtual register are
51 /// defined and which ones are actually used.
52 struct VRegInfo {
53  LaneBitmask UsedLanes;
54  LaneBitmask DefinedLanes;
55 };
56 
57 class DetectDeadLanes : public MachineFunctionPass {
58 public:
59  bool runOnMachineFunction(MachineFunction &MF) override;
60 
61  static char ID;
62  DetectDeadLanes() : MachineFunctionPass(ID) {}
63 
64  StringRef getPassName() const override { return "Detect Dead Lanes"; }
65 
66  void getAnalysisUsage(AnalysisUsage &AU) const override {
67  AU.setPreservesCFG();
69  }
70 
71 private:
72  /// Add used lane bits on the register used by operand \p MO. This translates
73  /// the bitmask based on the operands subregister, and puts the register into
74  /// the worklist if any new bits were added.
75  void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
76 
77  /// Given a bitmask \p UsedLanes for the used lanes on a def output of a
78  /// COPY-like instruction determine the lanes used on the use operands
79  /// and call addUsedLanesOnOperand() for them.
80  void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
81 
82  /// Given a use regiser operand \p Use and a mask of defined lanes, check
83  /// if the operand belongs to a lowersToCopies() instruction, transfer the
84  /// mask to the def and put the instruction into the worklist.
85  void transferDefinedLanesStep(const MachineOperand &Use,
86  LaneBitmask DefinedLanes);
87 
88  /// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
89  /// of COPY-like instruction, determine which lanes are defined at the output
90  /// operand \p Def.
91  LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
92  LaneBitmask DefinedLanes) const;
93 
94  /// Given a mask \p UsedLanes used from the output of instruction \p MI
95  /// determine which lanes are used from operand \p MO of this instruction.
96  LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
97  const MachineOperand &MO) const;
98 
99  bool runOnce(MachineFunction &MF);
100 
101  LaneBitmask determineInitialDefinedLanes(unsigned Reg);
102  LaneBitmask determineInitialUsedLanes(unsigned Reg);
103 
104  bool isUndefRegAtInput(const MachineOperand &MO,
105  const VRegInfo &RegInfo) const;
106 
107  bool isUndefInput(const MachineOperand &MO, bool *CrossCopy) const;
108 
109  const MachineRegisterInfo *MRI;
110  const TargetRegisterInfo *TRI;
111 
112  void PutInWorklist(unsigned RegIdx) {
113  if (WorklistMembers.test(RegIdx))
114  return;
115  WorklistMembers.set(RegIdx);
116  Worklist.push_back(RegIdx);
117  }
118 
119  VRegInfo *VRegInfos;
120  /// Worklist containing virtreg indexes.
121  std::deque<unsigned> Worklist;
122  BitVector WorklistMembers;
123  /// This bitvector is set for each vreg index where the vreg is defined
124  /// by an instruction where lowersToCopies()==true.
125  BitVector DefinedByCopy;
126 };
127 
128 } // end anonymous namespace
129 
130 char DetectDeadLanes::ID = 0;
132 
133 INITIALIZE_PASS(DetectDeadLanes, DEBUG_TYPE, "Detect Dead Lanes", false, false)
134 
135 /// Returns true if \p MI will get lowered to a series of COPY instructions.
136 /// We call this a COPY-like instruction.
138  // Note: We could support instructions with MCInstrDesc::isRegSequenceLike(),
139  // isExtractSubRegLike(), isInsertSubregLike() in the future even though they
140  // are not lowered to a COPY.
141  switch (MI.getOpcode()) {
142  case TargetOpcode::COPY:
143  case TargetOpcode::PHI:
144  case TargetOpcode::INSERT_SUBREG:
145  case TargetOpcode::REG_SEQUENCE:
146  case TargetOpcode::EXTRACT_SUBREG:
147  return true;
148  }
149  return false;
150 }
151 
153  const MachineInstr &MI,
154  const TargetRegisterClass *DstRC,
155  const MachineOperand &MO) {
156  assert(lowersToCopies(MI));
157  Register SrcReg = MO.getReg();
158  const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
159  if (DstRC == SrcRC)
160  return false;
161 
162  unsigned SrcSubIdx = MO.getSubReg();
163 
165  unsigned DstSubIdx = 0;
166  switch (MI.getOpcode()) {
167  case TargetOpcode::INSERT_SUBREG:
168  if (MI.getOperandNo(&MO) == 2)
169  DstSubIdx = MI.getOperand(3).getImm();
170  break;
171  case TargetOpcode::REG_SEQUENCE: {
172  unsigned OpNum = MI.getOperandNo(&MO);
173  DstSubIdx = MI.getOperand(OpNum+1).getImm();
174  break;
175  }
176  case TargetOpcode::EXTRACT_SUBREG: {
177  unsigned SubReg = MI.getOperand(2).getImm();
178  SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
179  }
180  }
181 
182  unsigned PreA, PreB; // Unused.
183  if (SrcSubIdx && DstSubIdx)
184  return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
185  PreB);
186  if (SrcSubIdx)
187  return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
188  if (DstSubIdx)
189  return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
190  return !TRI.getCommonSubClass(SrcRC, DstRC);
191 }
192 
193 void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
194  LaneBitmask UsedLanes) {
195  if (!MO.readsReg())
196  return;
197  Register MOReg = MO.getReg();
198  if (!Register::isVirtualRegister(MOReg))
199  return;
200 
201  unsigned MOSubReg = MO.getSubReg();
202  if (MOSubReg != 0)
203  UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes);
204  UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg);
205 
206  unsigned MORegIdx = Register::virtReg2Index(MOReg);
207  VRegInfo &MORegInfo = VRegInfos[MORegIdx];
208  LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes;
209  // Any change at all?
210  if ((UsedLanes & ~PrevUsedLanes).none())
211  return;
212 
213  // Set UsedLanes and remember instruction for further propagation.
214  MORegInfo.UsedLanes = PrevUsedLanes | UsedLanes;
215  if (DefinedByCopy.test(MORegIdx))
216  PutInWorklist(MORegIdx);
217 }
218 
219 void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
220  LaneBitmask UsedLanes) {
221  for (const MachineOperand &MO : MI.uses()) {
222  if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
223  continue;
224  LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO);
225  addUsedLanesOnOperand(MO, UsedOnMO);
226  }
227 }
228 
229 LaneBitmask DetectDeadLanes::transferUsedLanes(const MachineInstr &MI,
230  LaneBitmask UsedLanes,
231  const MachineOperand &MO) const {
232  unsigned OpNum = MI.getOperandNo(&MO);
233  assert(lowersToCopies(MI) &&
234  DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]);
235 
236  switch (MI.getOpcode()) {
237  case TargetOpcode::COPY:
238  case TargetOpcode::PHI:
239  return UsedLanes;
240  case TargetOpcode::REG_SEQUENCE: {
241  assert(OpNum % 2 == 1);
242  unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
243  return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
244  }
245  case TargetOpcode::INSERT_SUBREG: {
246  unsigned SubIdx = MI.getOperand(3).getImm();
247  LaneBitmask MO2UsedLanes =
248  TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
249  if (OpNum == 2)
250  return MO2UsedLanes;
251 
252  const MachineOperand &Def = MI.getOperand(0);
253  Register DefReg = Def.getReg();
254  const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
255  LaneBitmask MO1UsedLanes;
256  if (RC->CoveredBySubRegs)
257  MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
258  else
259  MO1UsedLanes = RC->LaneMask;
260 
261  assert(OpNum == 1);
262  return MO1UsedLanes;
263  }
264  case TargetOpcode::EXTRACT_SUBREG: {
265  assert(OpNum == 1);
266  unsigned SubIdx = MI.getOperand(2).getImm();
267  return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
268  }
269  default:
270  llvm_unreachable("function must be called with COPY-like instruction");
271  }
272 }
273 
274 void DetectDeadLanes::transferDefinedLanesStep(const MachineOperand &Use,
275  LaneBitmask DefinedLanes) {
276  if (!Use.readsReg())
277  return;
278  // Check whether the operand writes a vreg and is part of a COPY-like
279  // instruction.
280  const MachineInstr &MI = *Use.getParent();
281  if (MI.getDesc().getNumDefs() != 1)
282  return;
283  // FIXME: PATCHPOINT instructions announce a Def that does not always exist,
284  // they really need to be modeled differently!
285  if (MI.getOpcode() == TargetOpcode::PATCHPOINT)
286  return;
287  const MachineOperand &Def = *MI.defs().begin();
288  Register DefReg = Def.getReg();
289  if (!Register::isVirtualRegister(DefReg))
290  return;
291  unsigned DefRegIdx = Register::virtReg2Index(DefReg);
292  if (!DefinedByCopy.test(DefRegIdx))
293  return;
294 
295  unsigned OpNum = MI.getOperandNo(&Use);
296  DefinedLanes =
297  TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
298  DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);
299 
300  VRegInfo &RegInfo = VRegInfos[DefRegIdx];
301  LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes;
302  // Any change at all?
303  if ((DefinedLanes & ~PrevDefinedLanes).none())
304  return;
305 
306  RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes;
307  PutInWorklist(DefRegIdx);
308 }
309 
310 LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def,
311  unsigned OpNum, LaneBitmask DefinedLanes) const {
312  const MachineInstr &MI = *Def.getParent();
313  // Translate DefinedLanes if necessary.
314  switch (MI.getOpcode()) {
315  case TargetOpcode::REG_SEQUENCE: {
316  unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
317  DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
318  DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
319  break;
320  }
321  case TargetOpcode::INSERT_SUBREG: {
322  unsigned SubIdx = MI.getOperand(3).getImm();
323  if (OpNum == 2) {
324  DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
325  DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
326  } else {
327  assert(OpNum == 1 && "INSERT_SUBREG must have two operands");
328  // Ignore lanes defined by operand 2.
329  DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);
330  }
331  break;
332  }
333  case TargetOpcode::EXTRACT_SUBREG: {
334  unsigned SubIdx = MI.getOperand(2).getImm();
335  assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only");
336  DefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(SubIdx, DefinedLanes);
337  break;
338  }
339  case TargetOpcode::COPY:
340  case TargetOpcode::PHI:
341  break;
342  default:
343  llvm_unreachable("function must be called with COPY-like instruction");
344  }
345 
346  assert(Def.getSubReg() == 0 &&
347  "Should not have subregister defs in machine SSA phase");
348  DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());
349  return DefinedLanes;
350 }
351 
352 LaneBitmask DetectDeadLanes::determineInitialDefinedLanes(unsigned Reg) {
353  // Live-In or unused registers have no definition but are considered fully
354  // defined.
355  if (!MRI->hasOneDef(Reg))
356  return LaneBitmask::getAll();
357 
358  const MachineOperand &Def = *MRI->def_begin(Reg);
359  const MachineInstr &DefMI = *Def.getParent();
360  if (lowersToCopies(DefMI)) {
361  // Start optimisatically with no used or defined lanes for copy
362  // instructions. The following dataflow analysis will add more bits.
363  unsigned RegIdx = Register::virtReg2Index(Reg);
364  DefinedByCopy.set(RegIdx);
365  PutInWorklist(RegIdx);
366 
367  if (Def.isDead())
368  return LaneBitmask::getNone();
369 
370  // COPY/PHI can copy across unrelated register classes (example: float/int)
371  // with incompatible subregister structure. Do not include these in the
372  // dataflow analysis since we cannot transfer lanemasks in a meaningful way.
373  const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
374 
375  // Determine initially DefinedLanes.
376  LaneBitmask DefinedLanes;
377  for (const MachineOperand &MO : DefMI.uses()) {
378  if (!MO.isReg() || !MO.readsReg())
379  continue;
380  Register MOReg = MO.getReg();
381  if (!MOReg)
382  continue;
383 
384  LaneBitmask MODefinedLanes;
385  if (Register::isPhysicalRegister(MOReg)) {
386  MODefinedLanes = LaneBitmask::getAll();
387  } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
388  MODefinedLanes = LaneBitmask::getAll();
389  } else {
391  if (MRI->hasOneDef(MOReg)) {
392  const MachineOperand &MODef = *MRI->def_begin(MOReg);
393  const MachineInstr &MODefMI = *MODef.getParent();
394  // Bits from copy-like operations will be added later.
395  if (lowersToCopies(MODefMI) || MODefMI.isImplicitDef())
396  continue;
397  }
398  unsigned MOSubReg = MO.getSubReg();
399  MODefinedLanes = MRI->getMaxLaneMaskForVReg(MOReg);
400  MODefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(
401  MOSubReg, MODefinedLanes);
402  }
403 
404  unsigned OpNum = DefMI.getOperandNo(&MO);
405  DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);
406  }
407  return DefinedLanes;
408  }
409  if (DefMI.isImplicitDef() || Def.isDead())
410  return LaneBitmask::getNone();
411 
412  assert(Def.getSubReg() == 0 &&
413  "Should not have subregister defs in machine SSA phase");
414  return MRI->getMaxLaneMaskForVReg(Reg);
415 }
416 
417 LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
418  LaneBitmask UsedLanes = LaneBitmask::getNone();
419  for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
420  if (!MO.readsReg())
421  continue;
422 
423  const MachineInstr &UseMI = *MO.getParent();
424  if (UseMI.isKill())
425  continue;
426 
427  unsigned SubReg = MO.getSubReg();
428  if (lowersToCopies(UseMI)) {
429  assert(UseMI.getDesc().getNumDefs() == 1);
430  const MachineOperand &Def = *UseMI.defs().begin();
431  Register DefReg = Def.getReg();
432  // The used lanes of COPY-like instruction operands are determined by the
433  // following dataflow analysis.
434  if (Register::isVirtualRegister(DefReg)) {
435  // But ignore copies across incompatible register classes.
436  bool CrossCopy = false;
437  if (lowersToCopies(UseMI)) {
438  const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
439  CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
440  if (CrossCopy)
441  LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
442  }
443 
444  if (!CrossCopy)
445  continue;
446  }
447  }
448 
449  // Shortcut: All lanes are used.
450  if (SubReg == 0)
451  return MRI->getMaxLaneMaskForVReg(Reg);
452 
453  UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
454  }
455  return UsedLanes;
456 }
457 
458 bool DetectDeadLanes::isUndefRegAtInput(const MachineOperand &MO,
459  const VRegInfo &RegInfo) const {
460  unsigned SubReg = MO.getSubReg();
461  LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
462  return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none();
463 }
464 
465 bool DetectDeadLanes::isUndefInput(const MachineOperand &MO,
466  bool *CrossCopy) const {
467  if (!MO.isUse())
468  return false;
469  const MachineInstr &MI = *MO.getParent();
470  if (!lowersToCopies(MI))
471  return false;
472  const MachineOperand &Def = MI.getOperand(0);
473  Register DefReg = Def.getReg();
474  if (!Register::isVirtualRegister(DefReg))
475  return false;
476  unsigned DefRegIdx = Register::virtReg2Index(DefReg);
477  if (!DefinedByCopy.test(DefRegIdx))
478  return false;
479 
480  const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
481  LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
482  if (UsedLanes.any())
483  return false;
484 
485  Register MOReg = MO.getReg();
486  if (Register::isVirtualRegister(MOReg)) {
487  const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
488  *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
489  }
490  return true;
491 }
492 
493 bool DetectDeadLanes::runOnce(MachineFunction &MF) {
494  // First pass: Populate defs/uses of vregs with initial values
495  unsigned NumVirtRegs = MRI->getNumVirtRegs();
496  for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
497  unsigned Reg = Register::index2VirtReg(RegIdx);
498 
499  // Determine used/defined lanes and add copy instructions to worklist.
500  VRegInfo &Info = VRegInfos[RegIdx];
501  Info.DefinedLanes = determineInitialDefinedLanes(Reg);
502  Info.UsedLanes = determineInitialUsedLanes(Reg);
503  }
504 
505  // Iterate as long as defined lanes/used lanes keep changing.
506  while (!Worklist.empty()) {
507  unsigned RegIdx = Worklist.front();
508  Worklist.pop_front();
509  WorklistMembers.reset(RegIdx);
510  VRegInfo &Info = VRegInfos[RegIdx];
511  unsigned Reg = Register::index2VirtReg(RegIdx);
512 
513  // Transfer UsedLanes to operands of DefMI (backwards dataflow).
514  MachineOperand &Def = *MRI->def_begin(Reg);
515  const MachineInstr &MI = *Def.getParent();
516  transferUsedLanesStep(MI, Info.UsedLanes);
517  // Transfer DefinedLanes to users of Reg (forward dataflow).
518  for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
519  transferDefinedLanesStep(MO, Info.DefinedLanes);
520  }
521 
522  LLVM_DEBUG(dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0;
523  RegIdx < NumVirtRegs;
524  ++RegIdx) {
525  unsigned Reg = Register::index2VirtReg(RegIdx);
526  const VRegInfo &Info = VRegInfos[RegIdx];
527  dbgs() << printReg(Reg, nullptr)
528  << " Used: " << PrintLaneMask(Info.UsedLanes)
529  << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
530  } dbgs() << "\n";);
531 
532  bool Again = false;
533  // Mark operands as dead/unused.
534  for (MachineBasicBlock &MBB : MF) {
535  for (MachineInstr &MI : MBB) {
536  for (MachineOperand &MO : MI.operands()) {
537  if (!MO.isReg())
538  continue;
539  Register Reg = MO.getReg();
540  if (!Register::isVirtualRegister(Reg))
541  continue;
542  unsigned RegIdx = Register::virtReg2Index(Reg);
543  const VRegInfo &RegInfo = VRegInfos[RegIdx];
544  if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
545  LLVM_DEBUG(dbgs()
546  << "Marking operand '" << MO << "' as dead in " << MI);
547  MO.setIsDead();
548  }
549  if (MO.readsReg()) {
550  bool CrossCopy = false;
551  if (isUndefRegAtInput(MO, RegInfo)) {
552  LLVM_DEBUG(dbgs()
553  << "Marking operand '" << MO << "' as undef in " << MI);
554  MO.setIsUndef();
555  } else if (isUndefInput(MO, &CrossCopy)) {
556  LLVM_DEBUG(dbgs()
557  << "Marking operand '" << MO << "' as undef in " << MI);
558  MO.setIsUndef();
559  if (CrossCopy)
560  Again = true;
561  }
562  }
563  }
564  }
565  }
566 
567  return Again;
568 }
569 
570 bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
571  // Don't bother if we won't track subregister liveness later. This pass is
572  // required for correctness if subregister liveness is enabled because the
573  // register coalescer cannot deal with hidden dead defs. However without
574  // subregister liveness enabled, the expected benefits of this pass are small
575  // so we safe the compile time.
576  MRI = &MF.getRegInfo();
577  if (!MRI->subRegLivenessEnabled()) {
578  LLVM_DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
579  return false;
580  }
581 
582  TRI = MRI->getTargetRegisterInfo();
583 
584  unsigned NumVirtRegs = MRI->getNumVirtRegs();
585  VRegInfos = new VRegInfo[NumVirtRegs];
586  WorklistMembers.resize(NumVirtRegs);
587  DefinedByCopy.resize(NumVirtRegs);
588 
589  bool Again;
590  do {
591  Again = runOnce(MF);
592  } while(Again);
593 
594  DefinedByCopy.clear();
595  WorklistMembers.clear();
596  delete[] VRegInfos;
597  return true;
598 }
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:76
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:510
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:527
void setIsUndef(bool Val=true)
unsigned Reg
unsigned getSubReg() const
#define DEBUG_TYPE
unsigned const TargetRegisterInfo * TRI
void setIsDead(bool Val=true)
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:93
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:83
const TargetRegisterClass * RC
Definition: MIParser.h:40
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:477
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
unsigned SubReg
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:83
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:82
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineInstrBuilder & UseMI
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
static bool lowersToCopies(const MachineInstr &MI)
Returns true if MI will get lowered to a series of COPY instructions.
Represent the analysis usage information of a pass.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:499
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool isImplicitDef() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
static bool isCrossCopy(const MachineRegisterInfo &MRI, const MachineInstr &MI, const TargetRegisterClass *DstRC, const MachineOperand &MO)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:240
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:301
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
constexpr bool any() const
Definition: LaneBitmask.h:52
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
bool isKill() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Wrapper class representing virtual and physical registers.
Definition: Register.h:19