LLVM  10.0.0svn
ExpandPostRAPseudos.cpp
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1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
10 // instructions after register allocation.
11 //
12 //===----------------------------------------------------------------------===//
13 
18 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/Support/Debug.h"
24 
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "postrapseudos"
28 
29 namespace {
30 struct ExpandPostRA : public MachineFunctionPass {
31 private:
32  const TargetRegisterInfo *TRI;
33  const TargetInstrInfo *TII;
34 
35 public:
36  static char ID; // Pass identification, replacement for typeid
37  ExpandPostRA() : MachineFunctionPass(ID) {}
38 
39  void getAnalysisUsage(AnalysisUsage &AU) const override {
40  AU.setPreservesCFG();
44  }
45 
46  /// runOnMachineFunction - pass entry point
47  bool runOnMachineFunction(MachineFunction&) override;
48 
49 private:
50  bool LowerSubregToReg(MachineInstr *MI);
51  bool LowerCopy(MachineInstr *MI);
52 
53  void TransferImplicitOperands(MachineInstr *MI);
54 };
55 } // end anonymous namespace
56 
57 char ExpandPostRA::ID = 0;
59 
61  "Post-RA pseudo instruction expansion pass", false, false)
62 
63 /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered
64 /// replacement instructions immediately precede it. Copy any implicit
65 /// operands from MI to the replacement instruction.
66 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
68  --CopyMI;
69 
70  for (const MachineOperand &MO : MI->implicit_operands())
71  if (MO.isReg())
72  CopyMI->addOperand(MO);
73 }
74 
75 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
76  MachineBasicBlock *MBB = MI->getParent();
77  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
78  MI->getOperand(1).isImm() &&
79  (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
80  MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
81 
82  Register DstReg = MI->getOperand(0).getReg();
83  Register InsReg = MI->getOperand(2).getReg();
84  assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
85  unsigned SubIdx = MI->getOperand(3).getImm();
86 
87  assert(SubIdx != 0 && "Invalid index for insert_subreg");
88  Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
89 
91  "Insert destination must be in a physical register");
93  "Inserted value must be in a physical register");
94 
95  LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
96 
97  if (MI->allDefsAreDead()) {
98  MI->setDesc(TII->get(TargetOpcode::KILL));
99  MI->RemoveOperand(3); // SubIdx
100  MI->RemoveOperand(1); // Imm
101  LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
102  return true;
103  }
104 
105  if (DstSubReg == InsReg) {
106  // No need to insert an identity copy instruction.
107  // Watch out for case like this:
108  // %rax = SUBREG_TO_REG 0, killed %eax, 3
109  // We must leave %rax live.
110  if (DstReg != InsReg) {
111  MI->setDesc(TII->get(TargetOpcode::KILL));
112  MI->RemoveOperand(3); // SubIdx
113  MI->RemoveOperand(1); // Imm
114  LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
115  return true;
116  }
117  LLVM_DEBUG(dbgs() << "subreg: eliminated!");
118  } else {
119  TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
120  MI->getOperand(2).isKill());
121 
122  // Implicitly define DstReg for subsequent uses.
124  --CopyMI;
125  CopyMI->addRegisterDefined(DstReg);
126  LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
127  }
128 
129  LLVM_DEBUG(dbgs() << '\n');
130  MBB->erase(MI);
131  return true;
132 }
133 
134 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
135 
136  if (MI->allDefsAreDead()) {
137  LLVM_DEBUG(dbgs() << "dead copy: " << *MI);
138  MI->setDesc(TII->get(TargetOpcode::KILL));
139  LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
140  return true;
141  }
142 
143  MachineOperand &DstMO = MI->getOperand(0);
144  MachineOperand &SrcMO = MI->getOperand(1);
145 
146  bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
147  if (IdentityCopy || SrcMO.isUndef()) {
148  LLVM_DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ")
149  << *MI);
150  // No need to insert an identity copy instruction, but replace with a KILL
151  // if liveness is changed.
152  if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
153  // We must make sure the super-register gets killed. Replace the
154  // instruction with KILL.
155  MI->setDesc(TII->get(TargetOpcode::KILL));
156  LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
157  return true;
158  }
159  // Vanilla identity copy.
160  MI->eraseFromParent();
161  return true;
162  }
163 
164  LLVM_DEBUG(dbgs() << "real copy: " << *MI);
165  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
166  DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
167 
168  if (MI->getNumOperands() > 2)
169  TransferImplicitOperands(MI);
170  LLVM_DEBUG({
172  dbgs() << "replaced by: " << *(--dMI);
173  });
174  MI->eraseFromParent();
175  return true;
176 }
177 
178 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
179 /// copies.
180 ///
181 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
182  LLVM_DEBUG(dbgs() << "Machine Function\n"
183  << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
184  << "********** Function: " << MF.getName() << '\n');
186  TII = MF.getSubtarget().getInstrInfo();
187 
188  bool MadeChange = false;
189 
190  for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
191  mbbi != mbbe; ++mbbi) {
192  for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
193  mi != me;) {
194  MachineInstr &MI = *mi;
195  // Advance iterator here because MI may be erased.
196  ++mi;
197 
198  // Only expand pseudos.
199  if (!MI.isPseudo())
200  continue;
201 
202  // Give targets a chance to expand even standard pseudos.
203  if (TII->expandPostRAPseudo(MI)) {
204  MadeChange = true;
205  continue;
206  }
207 
208  // Expand standard pseudos.
209  switch (MI.getOpcode()) {
210  case TargetOpcode::SUBREG_TO_REG:
211  MadeChange |= LowerSubregToReg(&MI);
212  break;
213  case TargetOpcode::COPY:
214  MadeChange |= LowerCopy(&MI);
215  break;
216  case TargetOpcode::DBG_VALUE:
217  continue;
218  case TargetOpcode::INSERT_SUBREG:
219  case TargetOpcode::EXTRACT_SUBREG:
220  llvm_unreachable("Sub-register pseudos should have been eliminated.");
221  }
222  }
223  }
224 
225  return MadeChange;
226 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
unsigned getSubReg() const
unsigned const TargetRegisterInfo * TRI
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
AnalysisUsage & addPreservedID(const void *ID)
virtual const TargetInstrInfo * getInstrInfo() const
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:642
Represent the analysis usage information of a pass.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:301
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Representation of each machine instruction.
Definition: MachineInstr.h:63
#define DEBUG_TYPE
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE, "Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitOperands - MI is a pseudo-instruction, and the lowered replacement instructions immed...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Wrapper class representing virtual and physical registers.
Definition: Register.h:19