111using namespace PatternMatch;
113#define DEBUG_TYPE "isel"
115STATISTIC(NumFastIselSuccessIndependent,
"Number of insts selected by "
116 "target-independent selector");
117STATISTIC(NumFastIselSuccessTarget,
"Number of insts selected by "
118 "target-specific selector");
119STATISTIC(NumFastIselDead,
"Number of dead insts removed on failure");
125 "local values should be cleared after finishing a BB");
168 RegDef = MO.getReg();
169 }
else if (MO.getReg().isVirtual()) {
180 if (
P.second == DefReg)
185void FastISel::flushLocalValueMap() {
210 LocalMI.eraseFromParent();
227 if (FirstLocalValue != FirstNonValue && !FirstLocalValue->getDebugLoc())
228 FirstLocalValue->setDebugLoc(FirstNonValue->getDebugLoc());
250 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
263 if (isa<Instruction>(V) &&
264 (!isa<AllocaInst>(V) ||
272 Reg = materializeRegForValue(V, VT);
281 if (
const auto *CI = dyn_cast<ConstantInt>(V)) {
282 if (CI->getValue().getActiveBits() <= 64)
284 }
else if (isa<AllocaInst>(V))
286 else if (isa<ConstantPointerNull>(V))
291 else if (
const auto *CF = dyn_cast<ConstantFP>(V)) {
292 if (CF->isNullValue())
303 APSInt SIntVal(IntBitWidth,
false);
314 }
else if (
const auto *
Op = dyn_cast<Operator>(V)) {
316 if (!isa<Instruction>(
Op) ||
320 }
else if (isa<UndefValue>(V)) {
323 TII.
get(TargetOpcode::IMPLICIT_DEF), Reg);
334 if (isa<Constant>(V))
340 Reg = materializeConstant(V, VT);
363 if (!isa<Instruction>(
I)) {
372 else if (Reg != AssignedReg) {
374 for (
unsigned i = 0; i < NumRegs; i++) {
392 if (IdxVT.
bitsLT(PtrVT)) {
394 }
else if (IdxVT.
bitsGT(PtrVT)) {
412 assert(
I.isValid() &&
E.isValid() && std::distance(
I,
E) > 0 &&
413 "Invalid iterator!");
415 if (SavedInsertPt ==
I)
424 Dead->eraseFromParent();
446 if (VT == MVT::Other || !VT.
isSimple())
465 if (
const auto *CI = dyn_cast<ConstantInt>(
I->getOperand(0)))
487 if (
const auto *CI = dyn_cast<ConstantInt>(
I->getOperand(1))) {
491 if (ISDOpcode ==
ISD::SDIV && isa<BinaryOperator>(
I) &&
498 if (ISDOpcode ==
ISD::UREM && isa<BinaryOperator>(
I) &&
520 ISDOpcode, Op0, Op1);
538 if (isa<VectorType>(
I->getType()))
549 const Value *
Idx = GTI.getOperand();
550 if (
StructType *StTy = GTI.getStructTypeOrNull()) {
555 if (TotalOffs >= MaxOffs) {
564 if (
const auto *CI = dyn_cast<ConstantInt>(
Idx)) {
568 uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
569 TotalOffs += GTI.getSequentialElementStride(
DL) * IdxN;
570 if (TotalOffs >= MaxOffs) {
586 uint64_t ElementSize = GTI.getSequentialElementStride(
DL);
591 if (ElementSize != 1) {
613 const CallInst *CI,
unsigned StartIdx) {
614 for (
unsigned i = StartIdx, e = CI->
arg_size(); i != e; ++i) {
617 if (
const auto *
C = dyn_cast<ConstantInt>(Val)) {
620 }
else if (isa<ConstantPointerNull>(Val)) {
623 }
else if (
auto *AI = dyn_cast<AllocaInst>(Val)) {
645 assert(
I->getCalledFunction()->getReturnType()->isVoidTy() &&
646 "Stackmap cannot return a value.");
662 "Expected a constant integer.");
667 "Expected a constant integer.");
668 const auto *NumBytes =
674 if (!addStackMapLiveVars(Ops,
I, 2))
683 for (
unsigned i = 0; ScratchRegs[i]; ++i)
685 ScratchRegs[i],
true,
true,
false,
686 false,
false,
true));
692 const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
698 TII.
get(TargetOpcode::STACKMAP));
699 for (
auto const &MO : Ops)
719bool FastISel::lowerCallOperands(
const CallInst *CI,
unsigned ArgIdx,
720 unsigned NumArgs,
const Value *Callee,
721 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
723 Args.reserve(NumArgs);
726 for (
unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; ArgI != ArgE; ++ArgI) {
729 assert(!V->getType()->isEmptyTy() &&
"Empty type passed to intrinsic.");
733 Entry.Ty = V->getType();
734 Entry.setAttributes(CI, ArgI);
735 Args.push_back(Entry);
751 return setCallee(
CC, ResultTy,
Sym, std::move(ArgsList), FixedArgs);
763 bool HasDef = !
I->getType()->isVoidTy();
768 "Expected a constant integer.");
769 const auto *NumArgsVal =
771 unsigned NumArgs = NumArgsVal->getZExtValue();
776 assert(
I->arg_size() >= NumMetaOpers + NumArgs &&
777 "Not enough arguments provided to the patchpoint intrinsic");
780 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
783 if (!lowerCallOperands(
I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
786 assert(CLI.
Call &&
"No call instruction specified.");
791 if (IsAnyRegCC && HasDef) {
800 "Expected a constant integer.");
805 "Expected a constant integer.");
806 const auto *NumBytes =
811 if (
const auto *
C = dyn_cast<IntToPtrInst>(Callee)) {
813 cast<ConstantInt>(
C->getOperand(0))->getZExtValue();
815 }
else if (
const auto *
C = dyn_cast<ConstantExpr>(Callee)) {
816 if (
C->getOpcode() == Instruction::IntToPtr) {
818 cast<ConstantInt>(
C->getOperand(0))->getZExtValue();
822 }
else if (
const auto *GV = dyn_cast<GlobalValue>(Callee)) {
824 }
else if (isa<ConstantPointerNull>(Callee))
831 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.
OutRegs.size();
840 for (
unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
853 if (!addStackMapLiveVars(Ops,
I, NumMetaOpers + NumArgs))
862 for (
unsigned i = 0; ScratchRegs[i]; ++i)
864 ScratchRegs[i],
true,
true,
false,
865 false,
false,
true));
868 for (
auto Reg : CLI.
InRegs)
874 TII.
get(TargetOpcode::PATCHPOINT));
903 TII.
get(TargetOpcode::PATCHABLE_EVENT_CALL));
924 TII.
get(TargetOpcode::PATCHABLE_TYPED_EVENT_CALL));
937 Attrs.push_back(Attribute::SExt);
939 Attrs.push_back(Attribute::ZExt);
941 Attrs.push_back(Attribute::InReg);
962 Args.reserve(NumArgs);
966 for (
unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
969 assert(!V->getType()->isEmptyTy() &&
"Empty type passed to intrinsic.");
973 Entry.Ty = V->getType();
974 Entry.setAttributes(CI, ArgI);
975 Args.push_back(Entry);
1001 for (
EVT VT : RetTys) {
1004 for (
unsigned i = 0; i != NumRegs; ++i) {
1006 MyFlags.
VT = RegisterVT;
1015 CLI.
Ins.push_back(MyFlags);
1021 for (
auto &Arg : CLI.
getArgs()) {
1022 Type *FinalType = Arg.Ty;
1024 FinalType = Arg.IndirectType;
1037 if (Arg.IsSwiftSelf)
1038 Flags.setSwiftSelf();
1039 if (Arg.IsSwiftAsync)
1040 Flags.setSwiftAsync();
1041 if (Arg.IsSwiftError)
1042 Flags.setSwiftError();
1043 if (Arg.IsCFGuardTarget)
1044 Flags.setCFGuardTarget();
1047 if (Arg.IsInAlloca) {
1048 Flags.setInAlloca();
1056 if (Arg.IsPreallocated) {
1057 Flags.setPreallocated();
1066 if (Arg.IsByVal || Arg.IsInAlloca || Arg.IsPreallocated) {
1073 Flags.setByValSize(FrameSize);
1074 }
else if (!MemAlign) {
1077 Flags.setMemAlign(*MemAlign);
1081 Flags.setInConsecutiveRegs();
1083 CLI.
OutVals.push_back(Arg.Val);
1091 assert(CLI.
Call &&
"No call instruction specified.");
1117 if (V->getType()->isEmptyTy())
1121 Entry.Ty = V->getType();
1124 Entry.setAttributes(CI, i - CI->
arg_begin());
1125 Args.push_back(Entry);
1147 const CallInst *Call = cast<CallInst>(
I);
1150 if (
const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledOperand())) {
1152 if (!IA->getConstraintString().empty())
1155 unsigned ExtraInfo = 0;
1156 if (IA->hasSideEffects())
1158 if (IA->isAlignStack())
1160 if (Call->isConvergent())
1165 TII.
get(TargetOpcode::INLINEASM));
1169 const MDNode *SrcLoc = Call->getMetadata(
"srcloc");
1177 if (
const auto *II = dyn_cast<IntrinsicInst>(Call))
1192 flushLocalValueMap();
1195 if (
DPLabel *DPL = dyn_cast<DPLabel>(&DR)) {
1196 assert(DPL->getLabel() &&
"Missing label");
1198 LLVM_DEBUG(
dbgs() <<
"Dropping debug info for " << *DPL <<
"\n");
1203 TII.
get(TargetOpcode::DBG_LABEL))
1208 DPValue &DPV = cast<DPValue>(DR);
1228 LLVM_DEBUG(
dbgs() <<
"Dropping debug-info for " << DPV <<
"\n";);
1236 if (!V || isa<UndefValue>(V)) {
1242 if (
const auto *CI = dyn_cast<ConstantInt>(V)) {
1246 if (CI->getBitWidth() > 64)
1254 .
addImm(CI->getZExtValue())
1260 if (
const auto *CF = dyn_cast<ConstantFP>(V)) {
1268 if (
const auto *Arg = dyn_cast<Argument>(V);
1271 assert(Arg->hasAttribute(Attribute::AttrKind::SwiftAsync));
1275 if (Reg == VirtReg || Reg == PhysReg) {
1277 PhysReg, Var, Expr);
1281 LLVM_DEBUG(
dbgs() <<
"Dropping dbg.value: expression is entry_value but "
1282 "couldn't find a physical register\n");
1288 bool IsIndirect =
false;
1296 bool IsIndirect =
false;
1311 TII.
get(TargetOpcode::DBG_INSTR_REF),
false, MOs,
1321 LLVM_DEBUG(
dbgs() <<
"Dropping debug info (bad/undef address)\n");
1325 std::optional<MachineOperand>
Op;
1348 "Expected inlined-at fields to agree");
1357 TII.
get(TargetOpcode::DBG_INSTR_REF),
false, *
Op,
1365 TII.
get(TargetOpcode::DBG_VALUE),
true, *
Op, Var,
1373 dbgs() <<
"Dropping debug info (no materialized reg for address)\n");
1382 case Intrinsic::lifetime_start:
1383 case Intrinsic::lifetime_end:
1385 case Intrinsic::donothing:
1387 case Intrinsic::sideeffect:
1389 case Intrinsic::assume:
1391 case Intrinsic::experimental_noalias_scope_decl:
1393 case Intrinsic::dbg_declare: {
1398 <<
" (!hasDebugInfo)\n");
1412 case Intrinsic::dbg_assign:
1419 case Intrinsic::dbg_value: {
1430 "Expected inlined-at fields to agree");
1437 case Intrinsic::dbg_label: {
1449 case Intrinsic::objectsize:
1452 case Intrinsic::is_constant:
1455 case Intrinsic::launder_invariant_group:
1456 case Intrinsic::strip_invariant_group:
1457 case Intrinsic::expect: {
1464 case Intrinsic::experimental_stackmap:
1466 case Intrinsic::experimental_patchpoint_void:
1467 case Intrinsic::experimental_patchpoint_i64:
1470 case Intrinsic::xray_customevent:
1472 case Intrinsic::xray_typedevent:
1483 if (SrcVT == MVT::Other || !SrcVT.
isSimple() || DstVT == MVT::Other ||
1513 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1525 if (SrcVT == DstVT) {
1562void FastISel::removeDeadLocalValueCode(
MachineInstr *SavedLastLocalValue)
1565 if (CurLastLocalValue != SavedLastLocalValue) {
1570 if (SavedLastLocalValue)
1583 flushLocalValueMap();
1588 if (
I->isTerminator()) {
1589 if (!handlePHINodesInSuccessorBlocks(
I->getParent())) {
1594 removeDeadLocalValueCode(SavedLastLocalValue);
1600 if (
auto *Call = dyn_cast<CallBase>(
I))
1601 for (
unsigned i = 0, e = Call->getNumOperandBundles(); i != e; ++i)
1609 if (
const auto *Call = dyn_cast<CallInst>(
I)) {
1610 const Function *
F = Call->getCalledFunction();
1615 if (
F && !
F->hasLocalLinkage() &&
F->hasName() &&
1621 if (
F &&
F->getIntrinsicID() == Intrinsic::trap &&
1622 Call->hasFnAttr(
"trap-func-name"))
1629 ++NumFastIselSuccessIndependent;
1641 ++NumFastIselSuccessTarget;
1652 if (
I->isTerminator()) {
1655 removeDeadLocalValueCode(SavedLastLocalValue);
1689 if (TrueMBB != FalseMBB) {
1765 ResultReg =
I->second;
1766 else if (isa<Instruction>(Op0))
1777 for (
unsigned i = 0; i < VTIndex; i++)
1786 case Instruction::Add:
1788 case Instruction::FAdd:
1790 case Instruction::Sub:
1792 case Instruction::FSub:
1794 case Instruction::Mul:
1796 case Instruction::FMul:
1798 case Instruction::SDiv:
1800 case Instruction::UDiv:
1802 case Instruction::FDiv:
1804 case Instruction::SRem:
1806 case Instruction::URem:
1808 case Instruction::FRem:
1810 case Instruction::Shl:
1812 case Instruction::LShr:
1814 case Instruction::AShr:
1816 case Instruction::And:
1818 case Instruction::Or:
1820 case Instruction::Xor:
1823 case Instruction::FNeg:
1826 case Instruction::GetElementPtr:
1829 case Instruction::Br: {
1844 case Instruction::Unreachable:
1850 case Instruction::Alloca:
1858 case Instruction::Call:
1869 case Instruction::BitCast:
1872 case Instruction::FPToSI:
1874 case Instruction::ZExt:
1876 case Instruction::SExt:
1878 case Instruction::Trunc:
1880 case Instruction::SIToFP:
1883 case Instruction::IntToPtr:
1884 case Instruction::PtrToInt: {
1898 case Instruction::ExtractValue:
1901 case Instruction::Freeze:
1904 case Instruction::PHI:
1919 TII(*
MF->getSubtarget().getInstrInfo()),
1920 TLI(*
MF->getSubtarget().getTargetLowering()),
1995 return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
2004 if (
Op.isVirtual()) {
2075 unsigned Op1,
unsigned Op2) {
2215 "Cannot yet extract from physregs");
2235bool FastISel::handlePHINodesInSuccessorBlocks(
const BasicBlock *LLVMBB) {
2242 if (!isa<PHINode>(SuccBB->begin()))
2248 if (!SuccsHandled.
insert(SuccMBB).second)
2256 for (
const PHINode &PN : SuccBB->phis()) {
2270 if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2276 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
2281 if (
const auto *Inst = dyn_cast<Instruction>(PHIOp))
2299 "tryToFoldLoad expected a LoadInst with a single use");
2303 unsigned MaxUsers = 6;
2306 while (TheUser != FoldInst &&
2319 if (TheUser != FoldInst)
2360 if (!isa<AddOperator>(
Add))
2367 if (isa<Instruction>(
Add) &&
2371 return isa<ConstantInt>(cast<AddOperator>(
Add)->getOperand(1));
2382 if (
const auto *LI = dyn_cast<LoadInst>(
I)) {
2383 Alignment = LI->getAlign();
2384 IsVolatile = LI->isVolatile();
2386 Ptr = LI->getPointerOperand();
2387 ValTy = LI->getType();
2388 }
else if (
const auto *SI = dyn_cast<StoreInst>(
I)) {
2389 Alignment = SI->getAlign();
2390 IsVolatile = SI->isVolatile();
2392 Ptr = SI->getPointerOperand();
2393 ValTy = SI->getValueOperand()->getType();
2397 bool IsNonTemporal =
I->hasMetadata(LLVMContext::MD_nontemporal);
2398 bool IsInvariant =
I->hasMetadata(LLVMContext::MD_invariant_load);
2399 bool IsDereferenceable =
I->hasMetadata(LLVMContext::MD_dereferenceable);
2400 const MDNode *Ranges =
I->getMetadata(LLVMContext::MD_range);
2413 if (IsDereferenceable)
2419 *Alignment, AAInfo, Ranges);
2428 switch (Predicate) {
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
This file contains the simple types necessary to represent the attributes associated with functions a...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
static Register findLocalRegDef(MachineInstr &MI)
Return the defined register if this instruction defines exactly one virtual register and uses no othe...
static bool isRegUsedByPhiNodes(Register DefReg, FunctionLoweringInfo &FuncInfo)
static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI)
Returns an AttributeList representing the attributes applied to the return value of the given call.
This file defines the FastISel class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isCommutative(Instruction *I)
This file defines the SmallPtrSet class.
This file defines the SmallString class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static SymbolRef::Type getType(const Symbol *Sym)
This file describes how to lower LLVM code to machine code.
An arbitrary precision integer that knows its signedness.
This class represents an incoming formal argument to a Function.
static AttributeList get(LLVMContext &C, ArrayRef< std::pair< unsigned, Attribute > > Attrs)
Create an AttributeList with the specified parameters in it.
bool getValueAsBool() const
Return the attribute's value as a boolean.
LLVM Basic Block Representation.
filter_iterator< BasicBlock::const_iterator, std::function< bool(constInstruction &)> >::difference_type sizeWithoutDebug() const
Return the size of the basic block ignoring debug instructions.
Conditional or Unconditional Branch instruction.
BasicBlock * getSuccessor(unsigned i) const
bool isUnconditional() const
BranchProbability getEdgeProbability(const BasicBlock *Src, unsigned IndexInSuccessors) const
Get an edge's probability, relative to other out-edges of the Src.
CallingConv::ID getCallingConv() const
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Value * getCalledOperand() const
Value * getArgOperand(unsigned i) const
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
FunctionType * getFunctionType() const
unsigned arg_size() const
This class represents a function call, abstracting a target machine's calling convention.
bool isMustTailCall() const
This class is the base class for the comparison instructions.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Predicate getPredicate() const
Return the predicate for this instruction.
ConstantFP - Floating Point Values [float, double].
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Records a position in IR for a source label (DILabel).
Record of a variable value-assignment, aka a non instruction representation of the dbg....
DIExpression * getExpression() const
LocationType getType() const
Value * getVariableLocationOp(unsigned OpIdx) const
DILocalVariable * getVariable() const
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
This represents the llvm.dbg.declare instruction.
Value * getAddress() const
This represents the llvm.dbg.label instruction.
DILabel * getLabel() const
Base class for non-instruction debug metadata records that have positions within IR.
DebugLoc getDebugLoc() const
This represents the llvm.dbg.value instruction.
Value * getValue(unsigned OpIdx=0) const
DILocalVariable * getVariable() const
DIExpression * getExpression() const
MachineRegisterInfo & MRI
Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx)
Emit a MachineInstr for an extract_subreg from a specified index of a superregister to a specified ty...
const TargetLibraryInfo * LibInfo
bool selectGetElementPtr(const User *I)
void setLastLocalValue(MachineInstr *I)
Update the position of the last instruction emitted for materializing constants for use in the curren...
bool selectStackmap(const CallInst *I)
bool selectExtractValue(const User *U)
DenseMap< const Value *, Register > LocalValueMap
void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc)
Emit an unconditional branch to the given block, unless it is the immediate (fall-through) successor,...
virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF)
Emit the floating-point constant +0.0 in a register using target- specific logic.
MachineInstr * EmitStartPt
The top most instruction in the current block that is allowed for emitting local variables.
bool selectXRayCustomEvent(const CallInst *II)
Register fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC)
Emit a MachineInstr with no operands and a result register in the given register class.
virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II)
This method is called by target-independent code to do target- specific intrinsic lowering.
virtual bool lowerDbgDeclare(const Value *V, DIExpression *Expr, DILocalVariable *Var, const DebugLoc &DL)
Target-independent lowering of debug information.
MachineInstr * getLastLocalValue()
Return the position of the last instruction emitted for materializing constants for use in the curren...
bool lowerCall(const CallInst *I)
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
void leaveLocalValueArea(SavePoint Old)
Reset InsertPt to the given old insert position.
bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs)
Register fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0)
Emit a MachineInstr with one register operand and a result register in the given register class.
void handleDbgInfo(const Instruction *II)
Target-independent lowering of non-instruction debug info associated with this instruction.
bool selectFreeze(const User *I)
bool selectIntrinsicCall(const IntrinsicInst *II)
bool selectCast(const User *I, unsigned Opcode)
bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst)
We're checking to see if we can fold LI into FoldInst.
Register getRegForValue(const Value *V)
Create a virtual register and arrange for it to be assigned the value for the given LLVM value.
void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E)
Remove all dead instructions between the I and E.
void startNewBlock()
Set the current block to which generated machine instructions will be appended.
MachineMemOperand * createMachineMemOperandFor(const Instruction *I) const
Create a machine mem operand from the given instruction.
virtual bool tryToFoldLoadIntoMI(MachineInstr *, unsigned, const LoadInst *)
The specified machine instr operand is a vreg, and that vreg is being provided by the specified load ...
Register fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm)
Emit a MachineInstr with a single immediate operand, and a result register in the given register clas...
bool canFoldAddIntoGEP(const User *GEP, const Value *Add)
Check if Add is an add that can be safely folded into GEP.
virtual bool lowerDbgValue(const Value *V, DIExpression *Expr, DILocalVariable *Var, const DebugLoc &DL)
Target-independent lowering of debug information.
virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode)
This method is called by target-independent code to request that an instruction with the given type a...
TargetLoweringBase::ArgListTy ArgListTy
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
virtual unsigned fastMaterializeConstant(const Constant *C)
Emit a constant in a register using target-specific logic, such as constant pool loads.
virtual bool fastLowerCall(CallLoweringInfo &CLI)
This method is called by target-independent code to do target- specific call lowering.
bool selectXRayTypedEvent(const CallInst *II)
Register fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1)
Emit a MachineInstr with two register operands and a result register in the given register class.
Register fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm1, uint64_t Imm2)
Emit a MachineInstr with one register operand and two immediate operands.
Register createResultReg(const TargetRegisterClass *RC)
virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *FPImm)
This method is called by target-independent code to request that an instruction with the given type,...
virtual bool fastLowerArguments()
This method is called by target-independent code to do target- specific argument lowering.
bool selectFNeg(const User *I, const Value *In)
Emit an FNeg operation.
const TargetInstrInfo & TII
bool selectCall(const User *I)
Register lookUpRegForValue(const Value *V)
Look up the value to see if its value is already cached in a register.
CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const
void finishBasicBlock()
Flush the local value map.
FunctionLoweringInfo & FuncInfo
Register getRegForGEPIndex(const Value *Idx)
This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the give...
MachineConstantPool & MCP
bool selectOperator(const User *I, unsigned Opcode)
Do "fast" instruction selection for the given LLVM IR operator (Instruction or ConstantExpr),...
bool SkipTargetIndependentISel
Register fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm)
Emit a MachineInstr with a floating point immediate, and a result register in the given register clas...
Register constrainOperandRegClass(const MCInstrDesc &II, Register Op, unsigned OpNum)
Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc.
void updateValueMap(const Value *I, Register Reg, unsigned NumRegs=1)
Update the value map to include the new mapping for this instruction, or insert an extra copy to get ...
bool selectBinaryOp(const User *I, unsigned ISDOpcode)
Select and emit code for a binary operator instruction, which has an opcode which directly correspond...
FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, bool SkipTargetIndependentISel=false)
bool selectPatchpoint(const CallInst *I)
void recomputeInsertPt()
Reset InsertPt to prepare for inserting instructions into the current block.
virtual bool fastSelectInstruction(const Instruction *I)=0
This method is called by target-independent code when the normal FastISel process fails to select an ...
const TargetLowering & TLI
virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1)
This method is called by target-independent code to request that an instruction with the given type,...
Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm, MVT ImmType)
This method is a wrapper of fastEmit_ri.
Register fastEmitZExtFromI1(MVT VT, unsigned Op0)
Emit MachineInstrs to compute the value of Op with all but the least significant bit set to zero.
MachineInstr * LastLocalValue
The position of the last instruction for materializing constants for use in the current block.
Register fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, uint64_t Imm)
Emit a MachineInstr with two register operands, an immediate, and a result register in the given regi...
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
SavePoint enterLocalValueArea()
Prepare InsertPt to begin inserting instructions into the local value area and return the old insert ...
void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB)
Emit an unconditional branch to FalseMBB, obtains the branch weight and adds TrueMBB and FalseMBB to ...
bool selectBitCast(const User *I)
Register fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0)
This method is called by target-independent code to request that an instruction with the given type,...
virtual unsigned fastMaterializeAlloca(const AllocaInst *C)
Emit an alloca address in a register using target-specific logic.
virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
const TargetRegisterInfo & TRI
Register fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2)
Emit a MachineInstr with three register operands and a result register in the given register class.
TargetLoweringBase::ArgListEntry ArgListEntry
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
BranchProbabilityInfo * BPI
DenseSet< Register > RegsWithFixups
unsigned OrigNumPHINodesToUpdate
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
SmallPtrSet< const DPValue *, 8 > PreprocessedDPVDeclares
Register InitializeRegForValue(const Value *V)
SmallPtrSet< const DbgDeclareInst *, 8 > PreprocessedDbgDeclares
Collection of dbg.declare instructions handled after argument lowering and before ISel proper.
DenseMap< const Value *, Register > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
MachineBasicBlock * MBB
MBB - The current block.
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
DenseMap< Register, Register > RegFixups
RegFixups - Registers which need to be replaced after isel is done.
MachineRegisterInfo * RegInfo
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
Class to represent function types.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
iterator_range< simple_ilist< DbgRecord >::iterator > getDbgRecordRange() const
Return a range over the DbgRecords attached to this instruction.
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
const BasicBlock * getParent() const
Instruction * user_back()
Specialize the methods defined in Value, as we know that an instruction can only be used by other ins...
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
bool hasDbgRecords() const
Returns true if any DbgRecords are attached to this instruction.
Class to represent integer types.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
An instruction for reading from memory.
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Context object for machine code objects.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
void addSuccessorWithoutProb(MachineBasicBlock *Succ)
Add Succ as a successor of this MachineBasicBlock.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
MachineInstrBundleIterator< MachineInstr, true > reverse_iterator
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstrBundleIterator< MachineInstr > iterator
void setHasPatchPoint(bool s=true)
void setHasStackMap(bool s=true)
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Representation of each machine instruction.
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
bool hasDebugInfo() const
Returns true if valid debug info is present.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateFI(int Idx)
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
reg_iterator reg_begin(Register RegNo) const
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
ArrayRef< std::pair< MCRegister, Register > > liveins() const
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
Wrapper class representing virtual and physical registers.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TypeSize getElementOffset(unsigned Idx) const
Class to represent struct types.
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
unsigned getCallFrameDestroyOpcode() const
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Provides information about what library functions are available for the current target.
bool hasOptimizedCodeGen(LibFunc F) const
Tests if the function is both available and a candidate for optimized code generation.
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
const Triple & getTargetTriple() const
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isOSAIX() const
Tests whether the OS is AIX.
bool isAArch64() const
Tests whether the target is AArch64 (little and big endian).
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getVoidTy(LLVMContext &C)
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Value * getOperand(unsigned i) const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
@ C
The default llvm calling convention, compatible with C.
@ ADD
Simple integer binary arithmetic operators.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ SIGN_EXTEND
Conversion operators.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
bool isBitwiseLogicOp(unsigned Opcode)
Whether this is bitwise logic opcode.
Reg
All possible values of the reg field in the ModR/M byte.
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
reverse_iterator rend(StringRef path)
Get reverse end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void diagnoseDontCall(const CallInst &CI)
auto successors(const MachineBasicBlock *BB)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
gep_type_iterator gep_type_end(const User *GEP)
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
DWARFExpression::Operation Op
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
gep_type_iterator gep_type_begin(const User *GEP)
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
Compute the linearized index of a member in a nested aggregate/struct/array.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static constexpr roundingMode rmTowardZero
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
SmallVector< ISD::ArgFlagsTy, 16 > OutFlags
SmallVector< Value *, 16 > OutVals
SmallVector< Register, 16 > OutRegs
CallLoweringInfo & setTailCall(bool Value=true)
SmallVector< Register, 4 > InRegs
CallLoweringInfo & setIsPatchPoint(bool Value=true)
CallLoweringInfo & setCallee(Type *ResultTy, FunctionType *FuncTy, const Value *Target, ArgListTy &&ArgsList, const CallBase &Call)
SmallVector< ISD::InputArg, 4 > Ins
This class contains a discriminated union of information about pointers in memory operands,...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.