LLVM  10.0.0svn
HexagonISelLowering.cpp
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1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that Hexagon uses to lower LLVM code
10 // into a selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonISelLowering.h"
15 #include "Hexagon.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
46 #include "llvm/IR/Value.h"
47 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/CodeGen.h"
51 #include "llvm/Support/Debug.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstddef>
59 #include <cstdint>
60 #include <limits>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-lowering"
66 
67 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
68  cl::init(true), cl::Hidden,
69  cl::desc("Control jump table emission on Hexagon target"));
70 
71 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
73  cl::desc("Enable Hexagon SDNode scheduling"));
74 
75 static cl::opt<bool> EnableFastMath("ffast-math",
77  cl::desc("Enable Fast Math processing"));
78 
79 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
81  cl::desc("Set minimum jump tables"));
82 
83 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
85  cl::desc("Max #stores to inline memcpy"));
86 
87 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
89  cl::desc("Max #stores to inline memcpy"));
90 
91 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
93  cl::desc("Max #stores to inline memmove"));
94 
95 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
97  cl::desc("Max #stores to inline memmove"));
98 
99 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
101  cl::desc("Max #stores to inline memset"));
102 
103 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
105  cl::desc("Max #stores to inline memset"));
106 
107 static cl::opt<bool> AlignLoads("hexagon-align-loads",
108  cl::Hidden, cl::init(false),
109  cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
110 
111 
112 namespace {
113 
114  class HexagonCCState : public CCState {
115  unsigned NumNamedVarArgParams = 0;
116 
117  public:
118  HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
120  unsigned NumNamedArgs)
121  : CCState(CC, IsVarArg, MF, locs, C),
122  NumNamedVarArgParams(NumNamedArgs) {}
123  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
124  };
125 
126 } // end anonymous namespace
127 
128 
129 // Implement calling convention for Hexagon.
130 
131 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
132  CCValAssign::LocInfo &LocInfo,
133  ISD::ArgFlagsTy &ArgFlags, CCState &State) {
134  static const MCPhysReg ArgRegs[] = {
135  Hexagon::R0, Hexagon::R1, Hexagon::R2,
136  Hexagon::R3, Hexagon::R4, Hexagon::R5
137  };
138  const unsigned NumArgRegs = array_lengthof(ArgRegs);
139  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
140 
141  // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
142  if (RegNum != NumArgRegs && RegNum % 2 == 1)
143  State.AllocateReg(ArgRegs[RegNum]);
144 
145  // Always return false here, as this function only makes sure that the first
146  // unallocated register has an even register number and does not actually
147  // allocate a register for the current argument.
148  return false;
149 }
150 
151 #include "HexagonGenCallingConv.inc"
152 
153 
154 SDValue
156  const {
157  return SDValue();
158 }
159 
160 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
161 /// by "Src" to address "Dst" of size "Size". Alignment information is
162 /// specified by the specific parameter attribute. The copy will be passed as
163 /// a byval function parameter. Sometimes what we are copying is the end of a
164 /// larger object, the part that does not fit in registers.
166  SDValue Chain, ISD::ArgFlagsTy Flags,
167  SelectionDAG &DAG, const SDLoc &dl) {
168  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
169  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
170  /*isVolatile=*/false, /*AlwaysInline=*/false,
171  /*isTailCall=*/false,
173 }
174 
175 bool
177  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
179  LLVMContext &Context) const {
181  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
182 
184  return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
185  return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
186 }
187 
188 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
189 // passed by value, the function prototype is modified to return void and
190 // the value is stored in memory pointed by a pointer passed by caller.
191 SDValue
193  bool IsVarArg,
195  const SmallVectorImpl<SDValue> &OutVals,
196  const SDLoc &dl, SelectionDAG &DAG) const {
197  // CCValAssign - represent the assignment of the return value to locations.
199 
200  // CCState - Info about the registers and stack slot.
201  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
202  *DAG.getContext());
203 
204  // Analyze return values of ISD::RET
205  if (Subtarget.useHVXOps())
206  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
207  else
208  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
209 
210  SDValue Flag;
211  SmallVector<SDValue, 4> RetOps(1, Chain);
212 
213  // Copy the result values into the output registers.
214  for (unsigned i = 0; i != RVLocs.size(); ++i) {
215  CCValAssign &VA = RVLocs[i];
216 
217  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
218 
219  // Guarantee that all emitted copies are stuck together with flags.
220  Flag = Chain.getValue(1);
221  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
222  }
223 
224  RetOps[0] = Chain; // Update chain.
225 
226  // Add the flag if we have it.
227  if (Flag.getNode())
228  RetOps.push_back(Flag);
229 
230  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
231 }
232 
234  // If either no tail call or told not to tail call at all, don't.
235  auto Attr =
236  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
237  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
238  return false;
239 
240  return true;
241 }
242 
243 unsigned HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
244  SelectionDAG &DAG) const {
245  // Just support r19, the linux kernel uses it.
246  unsigned Reg = StringSwitch<unsigned>(RegName)
247  .Case("r19", Hexagon::R19)
248  .Default(0);
249  if (Reg)
250  return Reg;
251 
252  report_fatal_error("Invalid register name global variable");
253 }
254 
255 /// LowerCallResult - Lower the result values of an ISD::CALL into the
256 /// appropriate copies out of appropriate physical registers. This assumes that
257 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call
258 /// being lowered. Returns a SDNode with the same number of values as the
259 /// ISD::CALL.
261  SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
262  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
264  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
265  // Assign locations to each value returned by this call.
267 
268  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
269  *DAG.getContext());
270 
271  if (Subtarget.useHVXOps())
272  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
273  else
274  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
275 
276  // Copy all of the result registers out of their specified physreg.
277  for (unsigned i = 0; i != RVLocs.size(); ++i) {
278  SDValue RetVal;
279  if (RVLocs[i].getValVT() == MVT::i1) {
280  // Return values of type MVT::i1 require special handling. The reason
281  // is that MVT::i1 is associated with the PredRegs register class, but
282  // values of that type are still returned in R0. Generate an explicit
283  // copy into a predicate register from R0, and treat the value of the
284  // predicate register as the call result.
285  auto &MRI = DAG.getMachineFunction().getRegInfo();
286  SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
287  MVT::i32, Glue);
288  // FR0 = (Value, Chain, Glue)
289  unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
290  SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
291  FR0.getValue(0), FR0.getValue(2));
292  // TPR = (Chain, Glue)
293  // Don't glue this CopyFromReg, because it copies from a virtual
294  // register. If it is glued to the call, InstrEmitter will add it
295  // as an implicit def to the call (EmitMachineNode).
296  RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
297  Glue = TPR.getValue(1);
298  Chain = TPR.getValue(0);
299  } else {
300  RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
301  RVLocs[i].getValVT(), Glue);
302  Glue = RetVal.getValue(2);
303  Chain = RetVal.getValue(1);
304  }
305  InVals.push_back(RetVal.getValue(0));
306  }
307 
308  return Chain;
309 }
310 
311 /// LowerCall - Functions arguments are copied from virtual regs to
312 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
313 SDValue
315  SmallVectorImpl<SDValue> &InVals) const {
316  SelectionDAG &DAG = CLI.DAG;
317  SDLoc &dl = CLI.DL;
319  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
321  SDValue Chain = CLI.Chain;
322  SDValue Callee = CLI.Callee;
323  CallingConv::ID CallConv = CLI.CallConv;
324  bool IsVarArg = CLI.IsVarArg;
325  bool DoesNotReturn = CLI.DoesNotReturn;
326 
327  bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
329  MachineFrameInfo &MFI = MF.getFrameInfo();
330  auto PtrVT = getPointerTy(MF.getDataLayout());
331 
332  unsigned NumParams = CLI.CS.getInstruction()
333  ? CLI.CS.getFunctionType()->getNumParams()
334  : 0;
335  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
336  Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
337 
338  // Analyze operands of the call, assigning locations to each operand.
340  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
341  NumParams);
342 
343  if (Subtarget.useHVXOps())
344  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
345  else
346  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
347 
348  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
349  if (Attr.getValueAsString() == "true")
350  CLI.IsTailCall = false;
351 
352  if (CLI.IsTailCall) {
353  bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
354  CLI.IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
355  IsVarArg, IsStructRet, StructAttrFlag, Outs,
356  OutVals, Ins, DAG);
357  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
358  CCValAssign &VA = ArgLocs[i];
359  if (VA.isMemLoc()) {
360  CLI.IsTailCall = false;
361  break;
362  }
363  }
364  LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
365  : "Argument must be passed on stack. "
366  "Not eligible for Tail Call\n"));
367  }
368  // Get a count of how many bytes are to be pushed on the stack.
369  unsigned NumBytes = CCInfo.getNextStackOffset();
371  SmallVector<SDValue, 8> MemOpChains;
372 
373  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
374  SDValue StackPtr =
375  DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
376 
377  bool NeedsArgAlign = false;
378  unsigned LargestAlignSeen = 0;
379  // Walk the register/memloc assignments, inserting copies/loads.
380  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
381  CCValAssign &VA = ArgLocs[i];
382  SDValue Arg = OutVals[i];
383  ISD::ArgFlagsTy Flags = Outs[i].Flags;
384  // Record if we need > 8 byte alignment on an argument.
385  bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
386  NeedsArgAlign |= ArgAlign;
387 
388  // Promote the value if needed.
389  switch (VA.getLocInfo()) {
390  default:
391  // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
392  llvm_unreachable("Unknown loc info!");
393  case CCValAssign::Full:
394  break;
395  case CCValAssign::BCvt:
396  Arg = DAG.getBitcast(VA.getLocVT(), Arg);
397  break;
398  case CCValAssign::SExt:
399  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
400  break;
401  case CCValAssign::ZExt:
402  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
403  break;
404  case CCValAssign::AExt:
405  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
406  break;
407  }
408 
409  if (VA.isMemLoc()) {
410  unsigned LocMemOffset = VA.getLocMemOffset();
411  SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
412  StackPtr.getValueType());
413  MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
414  if (ArgAlign)
415  LargestAlignSeen = std::max(LargestAlignSeen,
416  VA.getLocVT().getStoreSizeInBits() >> 3);
417  if (Flags.isByVal()) {
418  // The argument is a struct passed by value. According to LLVM, "Arg"
419  // is a pointer.
420  MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
421  Flags, DAG, dl));
422  } else {
424  DAG.getMachineFunction(), LocMemOffset);
425  SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
426  MemOpChains.push_back(S);
427  }
428  continue;
429  }
430 
431  // Arguments that can be passed on register must be kept at RegsToPass
432  // vector.
433  if (VA.isRegLoc())
434  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
435  }
436 
437  if (NeedsArgAlign && Subtarget.hasV60Ops()) {
438  LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
439  unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
440  LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
441  MFI.ensureMaxAlignment(LargestAlignSeen);
442  }
443  // Transform all store nodes into one single node because all store
444  // nodes are independent of each other.
445  if (!MemOpChains.empty())
446  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
447 
448  SDValue Glue;
449  if (!CLI.IsTailCall) {
450  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
451  Glue = Chain.getValue(1);
452  }
453 
454  // Build a sequence of copy-to-reg nodes chained together with token
455  // chain and flag operands which copy the outgoing args into registers.
456  // The Glue is necessary since all emitted instructions must be
457  // stuck together.
458  if (!CLI.IsTailCall) {
459  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
460  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
461  RegsToPass[i].second, Glue);
462  Glue = Chain.getValue(1);
463  }
464  } else {
465  // For tail calls lower the arguments to the 'real' stack slot.
466  //
467  // Force all the incoming stack arguments to be loaded from the stack
468  // before any new outgoing arguments are stored to the stack, because the
469  // outgoing stack slots may alias the incoming argument stack slots, and
470  // the alias isn't otherwise explicit. This is slightly more conservative
471  // than necessary, because it means that each store effectively depends
472  // on every argument instead of just those arguments it would clobber.
473  //
474  // Do not flag preceding copytoreg stuff together with the following stuff.
475  Glue = SDValue();
476  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
477  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
478  RegsToPass[i].second, Glue);
479  Glue = Chain.getValue(1);
480  }
481  Glue = SDValue();
482  }
483 
484  bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
485  unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
486 
487  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
488  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
489  // node so that legalize doesn't hack it.
490  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
491  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
492  } else if (ExternalSymbolSDNode *S =
493  dyn_cast<ExternalSymbolSDNode>(Callee)) {
494  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
495  }
496 
497  // Returns a chain & a flag for retval copy to use.
498  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
500  Ops.push_back(Chain);
501  Ops.push_back(Callee);
502 
503  // Add argument registers to the end of the list so that they are
504  // known live into the call.
505  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
506  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
507  RegsToPass[i].second.getValueType()));
508  }
509 
510  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
511  assert(Mask && "Missing call preserved mask for calling convention");
512  Ops.push_back(DAG.getRegisterMask(Mask));
513 
514  if (Glue.getNode())
515  Ops.push_back(Glue);
516 
517  if (CLI.IsTailCall) {
518  MFI.setHasTailCall();
519  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
520  }
521 
522  // Set this here because we need to know this for "hasFP" in frame lowering.
523  // The target-independent code calls getFrameRegister before setting it, and
524  // getFrameRegister uses hasFP to determine whether the function has FP.
525  MFI.setHasCalls(true);
526 
527  unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
528  Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
529  Glue = Chain.getValue(1);
530 
531  // Create the CALLSEQ_END node.
532  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
533  DAG.getIntPtrConstant(0, dl, true), Glue, dl);
534  Glue = Chain.getValue(1);
535 
536  // Handle result values, copying them out of physregs into vregs that we
537  // return.
538  return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
539  InVals, OutVals, Callee);
540 }
541 
542 /// Returns true by value, base pointer and offset pointer and addressing
543 /// mode by reference if this node can be combined with a load / store to
544 /// form a post-indexed load / store.
547  SelectionDAG &DAG) const {
549  if (!LSN)
550  return false;
551  EVT VT = LSN->getMemoryVT();
552  if (!VT.isSimple())
553  return false;
554  bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
555  VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
556  VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
557  VT == MVT::v4i16 || VT == MVT::v8i8 ||
558  Subtarget.isHVXVectorType(VT.getSimpleVT());
559  if (!IsLegalType)
560  return false;
561 
562  if (Op->getOpcode() != ISD::ADD)
563  return false;
564  Base = Op->getOperand(0);
565  Offset = Op->getOperand(1);
566  if (!isa<ConstantSDNode>(Offset.getNode()))
567  return false;
568  AM = ISD::POST_INC;
569 
570  int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
571  return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
572 }
573 
574 SDValue
577  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
578  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
579  unsigned LR = HRI.getRARegister();
580 
581  if ((Op.getOpcode() != ISD::INLINEASM &&
582  Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
583  return Op;
584 
585  unsigned NumOps = Op.getNumOperands();
586  if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
587  --NumOps; // Ignore the flag operand.
588 
589  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
590  unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
591  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
592  ++i; // Skip the ID value.
593 
594  switch (InlineAsm::getKind(Flags)) {
595  default:
596  llvm_unreachable("Bad flags!");
598  case InlineAsm::Kind_Imm:
599  case InlineAsm::Kind_Mem:
600  i += NumVals;
601  break;
605  for (; NumVals; --NumVals, ++i) {
606  unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
607  if (Reg != LR)
608  continue;
609  HMFI.setHasClobberLR(true);
610  return Op;
611  }
612  break;
613  }
614  }
615  }
616 
617  return Op;
618 }
619 
620 // Need to transform ISD::PREFETCH into something that doesn't inherit
621 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
622 // SDNPMayStore.
624  SelectionDAG &DAG) const {
625  SDValue Chain = Op.getOperand(0);
626  SDValue Addr = Op.getOperand(1);
627  // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
628  // if the "reg" is fed by an "add".
629  SDLoc DL(Op);
630  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
631  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
632 }
633 
634 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
635 // is marked as having side-effects, while the register read on Hexagon does
636 // not have any. TableGen refuses to accept the direct pattern from that node
637 // to the A4_tfrcpp.
639  SelectionDAG &DAG) const {
640  SDValue Chain = Op.getOperand(0);
641  SDLoc dl(Op);
643  return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
644 }
645 
647  SelectionDAG &DAG) const {
648  SDValue Chain = Op.getOperand(0);
649  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
650  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
651  if (IntNo == Intrinsic::hexagon_prefetch) {
652  SDValue Addr = Op.getOperand(2);
653  SDLoc DL(Op);
654  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
655  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
656  }
657  return SDValue();
658 }
659 
660 SDValue
662  SelectionDAG &DAG) const {
663  SDValue Chain = Op.getOperand(0);
664  SDValue Size = Op.getOperand(1);
665  SDValue Align = Op.getOperand(2);
666  SDLoc dl(Op);
667 
669  assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
670 
671  unsigned A = AlignConst->getSExtValue();
672  auto &HFI = *Subtarget.getFrameLowering();
673  // "Zero" means natural stack alignment.
674  if (A == 0)
675  A = HFI.getStackAlignment();
676 
677  LLVM_DEBUG({
678  dbgs () << __func__ << " Align: " << A << " Size: ";
679  Size.getNode()->dump(&DAG);
680  dbgs() << "\n";
681  });
682 
683  SDValue AC = DAG.getConstant(A, dl, MVT::i32);
685  SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
686 
687  DAG.ReplaceAllUsesOfValueWith(Op, AA);
688  return AA;
689 }
690 
692  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
693  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
694  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
696  MachineFrameInfo &MFI = MF.getFrameInfo();
698 
699  // Assign locations to all of the incoming arguments.
701  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
703 
704  if (Subtarget.useHVXOps())
705  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
706  else
707  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
708 
709  // For LLVM, in the case when returning a struct by value (>8byte),
710  // the first argument is a pointer that points to the location on caller's
711  // stack where the return value will be stored. For Hexagon, the location on
712  // caller's stack is passed only when the struct size is smaller than (and
713  // equal to) 8 bytes. If not, no address will be passed into callee and
714  // callee return the result direclty through R0/R1.
715 
716  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
717 
718  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
719  CCValAssign &VA = ArgLocs[i];
720  ISD::ArgFlagsTy Flags = Ins[i].Flags;
721  bool ByVal = Flags.isByVal();
722 
723  // Arguments passed in registers:
724  // 1. 32- and 64-bit values and HVX vectors are passed directly,
725  // 2. Large structs are passed via an address, and the address is
726  // passed in a register.
727  if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
728  llvm_unreachable("ByValSize must be bigger than 8 bytes");
729 
730  bool InReg = VA.isRegLoc() &&
731  (!ByVal || (ByVal && Flags.getByValSize() > 8));
732 
733  if (InReg) {
734  MVT RegVT = VA.getLocVT();
735  if (VA.getLocInfo() == CCValAssign::BCvt)
736  RegVT = VA.getValVT();
737 
738  const TargetRegisterClass *RC = getRegClassFor(RegVT);
739  unsigned VReg = MRI.createVirtualRegister(RC);
740  SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
741 
742  // Treat values of type MVT::i1 specially: they are passed in
743  // registers of type i32, but they need to remain as values of
744  // type i1 for consistency of the argument lowering.
745  if (VA.getValVT() == MVT::i1) {
746  assert(RegVT.getSizeInBits() <= 32);
747  SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
748  Copy, DAG.getConstant(1, dl, RegVT));
749  Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
750  ISD::SETNE);
751  } else {
752 #ifndef NDEBUG
753  unsigned RegSize = RegVT.getSizeInBits();
754  assert(RegSize == 32 || RegSize == 64 ||
755  Subtarget.isHVXVectorType(RegVT));
756 #endif
757  }
758  InVals.push_back(Copy);
759  MRI.addLiveIn(VA.getLocReg(), VReg);
760  } else {
761  assert(VA.isMemLoc() && "Argument should be passed in memory");
762 
763  // If it's a byval parameter, then we need to compute the
764  // "real" size, not the size of the pointer.
765  unsigned ObjSize = Flags.isByVal()
766  ? Flags.getByValSize()
767  : VA.getLocVT().getStoreSizeInBits() / 8;
768 
769  // Create the frame index object for this incoming parameter.
771  int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
772  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
773 
774  if (Flags.isByVal()) {
775  // If it's a pass-by-value aggregate, then do not dereference the stack
776  // location. Instead, we should generate a reference to the stack
777  // location.
778  InVals.push_back(FIN);
779  } else {
780  SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
782  InVals.push_back(L);
783  }
784  }
785  }
786 
787 
788  if (IsVarArg) {
789  // This will point to the next argument passed via stack.
790  int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
791  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
792  HMFI.setVarArgsFrameIndex(FI);
793  }
794 
795  return Chain;
796 }
797 
798 SDValue
800  // VASTART stores the address of the VarArgsFrameIndex slot into the
801  // memory location argument.
805  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
806  return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
807  MachinePointerInfo(SV));
808 }
809 
811  const SDLoc &dl(Op);
812  SDValue LHS = Op.getOperand(0);
813  SDValue RHS = Op.getOperand(1);
814  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
815  MVT ResTy = ty(Op);
816  MVT OpTy = ty(LHS);
817 
818  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
819  MVT ElemTy = OpTy.getVectorElementType();
820  assert(ElemTy.isScalarInteger());
822  OpTy.getVectorNumElements());
823  return DAG.getSetCC(dl, ResTy,
824  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
825  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
826  }
827 
828  // Treat all other vector types as legal.
829  if (ResTy.isVector())
830  return Op;
831 
832  // Comparisons of short integers should use sign-extend, not zero-extend,
833  // since we can represent small negative values in the compare instructions.
834  // The LLVM default is to use zero-extend arbitrarily in these cases.
835  auto isSExtFree = [this](SDValue N) {
836  switch (N.getOpcode()) {
837  case ISD::TRUNCATE: {
838  // A sign-extend of a truncate of a sign-extend is free.
839  SDValue Op = N.getOperand(0);
840  if (Op.getOpcode() != ISD::AssertSext)
841  return false;
842  EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
843  unsigned ThisBW = ty(N).getSizeInBits();
844  unsigned OrigBW = OrigTy.getSizeInBits();
845  // The type that was sign-extended to get the AssertSext must be
846  // narrower than the type of N (so that N has still the same value
847  // as the original).
848  return ThisBW >= OrigBW;
849  }
850  case ISD::LOAD:
851  // We have sign-extended loads.
852  return true;
853  }
854  return false;
855  };
856 
857  if (OpTy == MVT::i8 || OpTy == MVT::i16) {
859  bool IsNegative = C && C->getAPIntValue().isNegative();
860  if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
861  return DAG.getSetCC(dl, ResTy,
862  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32),
863  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
864  }
865 
866  return SDValue();
867 }
868 
869 SDValue
871  SDValue PredOp = Op.getOperand(0);
872  SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
873  EVT OpVT = Op1.getValueType();
874  SDLoc DL(Op);
875 
876  if (OpVT == MVT::v2i16) {
877  SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
878  SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
879  SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
880  SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
881  return TR;
882  }
883 
884  return SDValue();
885 }
886 
887 static Constant *convert_i1_to_i8(const Constant *ConstVal) {
889  const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
890  if (!CV)
891  return nullptr;
892 
893  LLVMContext &Ctx = ConstVal->getContext();
894  IRBuilder<> IRB(Ctx);
895  unsigned NumVectorElements = CV->getNumOperands();
896  assert(isPowerOf2_32(NumVectorElements) &&
897  "conversion only supported for pow2 VectorSize!");
898 
899  for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
900  uint8_t x = 0;
901  for (unsigned j = 0; j < 8; ++j) {
902  uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
903  x |= y << (7 - j);
904  }
905  assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!");
906  NewConst.push_back(IRB.getInt8(x));
907  }
908  return ConstantVector::get(NewConst);
909 }
910 
911 SDValue
913  EVT ValTy = Op.getValueType();
914  ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
915  Constant *CVal = nullptr;
916  bool isVTi1Type = false;
917  if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
918  Type *CValTy = ConstVal->getType();
919  if (CValTy->isVectorTy() &&
920  CValTy->getVectorElementType()->isIntegerTy(1)) {
921  CVal = convert_i1_to_i8(ConstVal);
922  isVTi1Type = (CVal != nullptr);
923  }
924  }
925  unsigned Align = CPN->getAlignment();
926  bool IsPositionIndependent = isPositionIndependent();
927  unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
928 
929  unsigned Offset = 0;
930  SDValue T;
931  if (CPN->isMachineConstantPoolEntry())
932  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
933  TF);
934  else if (isVTi1Type)
935  T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
936  else
937  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset, TF);
938 
939  assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
940  "Inconsistent target flag encountered");
941 
942  if (IsPositionIndependent)
943  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
944  return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
945 }
946 
947 SDValue
949  EVT VT = Op.getValueType();
950  int Idx = cast<JumpTableSDNode>(Op)->getIndex();
951  if (isPositionIndependent()) {
953  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
954  }
955 
956  SDValue T = DAG.getTargetJumpTable(Idx, VT);
957  return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
958 }
959 
960 SDValue
962  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
964  MachineFrameInfo &MFI = MF.getFrameInfo();
965  MFI.setReturnAddressIsTaken(true);
966 
967  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
968  return SDValue();
969 
970  EVT VT = Op.getValueType();
971  SDLoc dl(Op);
972  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
973  if (Depth) {
974  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
975  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
976  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
977  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
979  }
980 
981  // Return LR, which contains the return address. Mark it an implicit live-in.
982  unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
983  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
984 }
985 
986 SDValue
988  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
990  MFI.setFrameAddressIsTaken(true);
991 
992  EVT VT = Op.getValueType();
993  SDLoc dl(Op);
994  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
995  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
996  HRI.getFrameRegister(), VT);
997  while (Depth--)
998  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1000  return FrameAddr;
1001 }
1002 
1003 SDValue
1005  SDLoc dl(Op);
1006  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1007 }
1008 
1009 SDValue
1011  SDLoc dl(Op);
1012  auto *GAN = cast<GlobalAddressSDNode>(Op);
1013  auto PtrVT = getPointerTy(DAG.getDataLayout());
1014  auto *GV = GAN->getGlobal();
1015  int64_t Offset = GAN->getOffset();
1016 
1017  auto &HLOF = *HTM.getObjFileLowering();
1018  Reloc::Model RM = HTM.getRelocationModel();
1019 
1020  if (RM == Reloc::Static) {
1021  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1022  const GlobalObject *GO = GV->getBaseObject();
1023  if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1024  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1025  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1026  }
1027 
1028  bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1029  if (UsePCRel) {
1030  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1032  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1033  }
1034 
1035  // Use GOT index.
1036  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1037  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1038  SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1039  return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1040 }
1041 
1042 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1043 SDValue
1045  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1046  SDLoc dl(Op);
1047  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1048 
1049  Reloc::Model RM = HTM.getRelocationModel();
1050  if (RM == Reloc::Static) {
1051  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1052  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1053  }
1054 
1055  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1056  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1057 }
1058 
1059 SDValue
1061  const {
1062  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1065  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1066 }
1067 
1068 SDValue
1070  GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1071  unsigned char OperandFlags) const {
1072  MachineFunction &MF = DAG.getMachineFunction();
1073  MachineFrameInfo &MFI = MF.getFrameInfo();
1074  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1075  SDLoc dl(GA);
1076  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1077  GA->getValueType(0),
1078  GA->getOffset(),
1079  OperandFlags);
1080  // Create Operands for the call.The Operands should have the following:
1081  // 1. Chain SDValue
1082  // 2. Callee which in this case is the Global address value.
1083  // 3. Registers live into the call.In this case its R0, as we
1084  // have just one argument to be passed.
1085  // 4. Glue.
1086  // Note: The order is important.
1087 
1088  const auto &HRI = *Subtarget.getRegisterInfo();
1089  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1090  assert(Mask && "Missing call preserved mask for calling convention");
1091  SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1092  DAG.getRegisterMask(Mask), Glue };
1093  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1094 
1095  // Inform MFI that function has calls.
1096  MFI.setAdjustsStack(true);
1097 
1098  Glue = Chain.getValue(1);
1099  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1100 }
1101 
1102 //
1103 // Lower using the intial executable model for TLS addresses
1104 //
1105 SDValue
1107  SelectionDAG &DAG) const {
1108  SDLoc dl(GA);
1109  int64_t Offset = GA->getOffset();
1110  auto PtrVT = getPointerTy(DAG.getDataLayout());
1111 
1112  // Get the thread pointer.
1113  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1114 
1115  bool IsPositionIndependent = isPositionIndependent();
1116  unsigned char TF =
1117  IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1118 
1119  // First generate the TLS symbol address
1120  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1121  Offset, TF);
1122 
1123  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1124 
1125  if (IsPositionIndependent) {
1126  // Generate the GOT pointer in case of position independent code
1127  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1128 
1129  // Add the TLS Symbol address to GOT pointer.This gives
1130  // GOT relative relocation for the symbol.
1131  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1132  }
1133 
1134  // Load the offset value for TLS symbol.This offset is relative to
1135  // thread pointer.
1136  SDValue LoadOffset =
1137  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1138 
1139  // Address of the thread local variable is the add of thread
1140  // pointer and the offset of the variable.
1141  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1142 }
1143 
1144 //
1145 // Lower using the local executable model for TLS addresses
1146 //
1147 SDValue
1149  SelectionDAG &DAG) const {
1150  SDLoc dl(GA);
1151  int64_t Offset = GA->getOffset();
1152  auto PtrVT = getPointerTy(DAG.getDataLayout());
1153 
1154  // Get the thread pointer.
1155  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1156  // Generate the TLS symbol address
1157  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1159  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1160 
1161  // Address of the thread local variable is the add of thread
1162  // pointer and the offset of the variable.
1163  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1164 }
1165 
1166 //
1167 // Lower using the general dynamic model for TLS addresses
1168 //
1169 SDValue
1171  SelectionDAG &DAG) const {
1172  SDLoc dl(GA);
1173  int64_t Offset = GA->getOffset();
1174  auto PtrVT = getPointerTy(DAG.getDataLayout());
1175 
1176  // First generate the TLS symbol address
1177  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1179 
1180  // Then, generate the GOT pointer
1181  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1182 
1183  // Add the TLS symbol and the GOT pointer
1184  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1185  SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1186 
1187  // Copy over the argument to R0
1188  SDValue InFlag;
1189  Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1190  InFlag = Chain.getValue(1);
1191 
1192  unsigned Flags =
1193  static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1196 
1197  return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1198  Hexagon::R0, Flags);
1199 }
1200 
1201 //
1202 // Lower TLS addresses.
1203 //
1204 // For now for dynamic models, we only support the general dynamic model.
1205 //
1206 SDValue
1208  SelectionDAG &DAG) const {
1209  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1210 
1211  switch (HTM.getTLSModel(GA->getGlobal())) {
1214  return LowerToTLSGeneralDynamicModel(GA, DAG);
1215  case TLSModel::InitialExec:
1216  return LowerToTLSInitialExecModel(GA, DAG);
1217  case TLSModel::LocalExec:
1218  return LowerToTLSLocalExecModel(GA, DAG);
1219  }
1220  llvm_unreachable("Bogus TLS model");
1221 }
1222 
1223 //===----------------------------------------------------------------------===//
1224 // TargetLowering Implementation
1225 //===----------------------------------------------------------------------===//
1226 
1228  const HexagonSubtarget &ST)
1229  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1230  Subtarget(ST) {
1231  auto &HRI = *Subtarget.getRegisterInfo();
1232 
1236  setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1239 
1242 
1245  else
1247 
1248  // Limits for inline expansion of memcpy/memmove
1255 
1256  //
1257  // Set up register classes.
1258  //
1259 
1260  addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1261  addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1262  addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1263  addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1264  addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1265  addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1266  addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1267  addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1268  addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1269  addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1270  addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1271 
1272  addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1273  addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1274 
1275  //
1276  // Handling of scalar operations.
1277  //
1278  // All operations default to "legal", except:
1279  // - indexed loads and stores (pre-/post-incremented),
1280  // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1281  // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1282  // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1283  // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1284  // which default to "expand" for at least one type.
1285 
1286  // Misc operations.
1303 
1304  // Custom legalize GlobalAddress nodes into CONST32.
1308 
1309  // Hexagon needs to optimize cases with negative constants.
1314 
1315  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1320 
1324 
1325  if (EmitJumpTables)
1327  else
1330 
1333 
1334  // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
1335  // but they only operate on i64.
1336  for (MVT VT : MVT::integer_valuetypes()) {
1343  }
1346 
1351 
1352  // Popcount can count # of 1s in i64 but returns i32.
1357 
1362 
1367 
1368  for (unsigned IntExpOp :
1373  for (MVT VT : MVT::integer_valuetypes())
1374  setOperationAction(IntExpOp, VT, Expand);
1375  }
1376 
1377  for (unsigned FPExpOp :
1380  for (MVT VT : MVT::fp_valuetypes())
1381  setOperationAction(FPExpOp, VT, Expand);
1382  }
1383 
1384  // No extending loads from i32.
1385  for (MVT VT : MVT::integer_valuetypes()) {
1389  }
1390  // Turn FP truncstore into trunc + store.
1392  // Turn FP extload into load/fpextend.
1393  for (MVT VT : MVT::fp_valuetypes())
1395 
1396  // Expand BR_CC and SELECT_CC for all integer and fp types.
1397  for (MVT VT : MVT::integer_valuetypes()) {
1400  }
1401  for (MVT VT : MVT::fp_valuetypes()) {
1404  }
1406 
1407  //
1408  // Handling of vector operations.
1409  //
1410 
1411  // Set the action for vector operations to "expand", then override it with
1412  // either "custom" or "legal" for specific cases.
1413  static const unsigned VectExpOps[] = {
1414  // Integer arithmetic:
1418  // Logical/bit:
1421  // Floating point arithmetic/math functions:
1428  // Misc:
1430  // Vector:
1435  };
1436 
1437  for (MVT VT : MVT::vector_valuetypes()) {
1438  for (unsigned VectExpOp : VectExpOps)
1439  setOperationAction(VectExpOp, VT, Expand);
1440 
1441  // Expand all extending loads and truncating stores:
1442  for (MVT TargetVT : MVT::vector_valuetypes()) {
1443  if (TargetVT == VT)
1444  continue;
1445  setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1446  setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1447  setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1448  setTruncStoreAction(VT, TargetVT, Expand);
1449  }
1450 
1451  // Normalize all inputs to SELECT to be vectors of i32.
1452  if (VT.getVectorElementType() != MVT::i32) {
1453  MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1455  AddPromotedToType(ISD::SELECT, VT, VT32);
1456  }
1460  }
1461 
1462  // Extending loads from (native) vectors of i8 into (native) vectors of i16
1463  // are legal.
1470 
1471  // Types natively supported:
1472  for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1480 
1481  setOperationAction(ISD::ADD, NativeVT, Legal);
1482  setOperationAction(ISD::SUB, NativeVT, Legal);
1483  setOperationAction(ISD::MUL, NativeVT, Legal);
1484  setOperationAction(ISD::AND, NativeVT, Legal);
1485  setOperationAction(ISD::OR, NativeVT, Legal);
1486  setOperationAction(ISD::XOR, NativeVT, Legal);
1487  }
1488 
1489  // Custom lower unaligned loads.
1490  // Also, for both loads and stores, verify the alignment of the address
1491  // in case it is a compile-time constant. This is a usability feature to
1492  // provide a meaningful error message to users.
1497  }
1498 
1499  for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v2i32, MVT::v4i16, MVT::v2i32}) {
1504  }
1505 
1506  // Custom-lower bitcasts from i8 to v8i1.
1510  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1511  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1512  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1513 
1514  // V5+.
1519 
1522 
1535 
1536  // Handling of indexed loads/stores: default is "expand".
1537  //
1542  }
1543 
1544  // Subtarget-specific operation actions.
1545  //
1546  if (Subtarget.hasV60Ops()) {
1551  }
1552  if (Subtarget.hasV66Ops()) {
1555  }
1556 
1557  if (Subtarget.useHVXOps())
1558  initializeHVXLowering();
1559 
1561 
1562  //
1563  // Library calls for unsupported operations
1564  //
1565  bool FastMath = EnableFastMath;
1566 
1567  setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1568  setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1569  setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1570  setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1571  setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1572  setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1573  setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1574  setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1575 
1576  setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1577  setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1578  setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1579  setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1580  setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1581  setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1582 
1583  // This is the only fast library function for sqrtd.
1584  if (FastMath)
1585  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1586 
1587  // Prefix is: nothing for "slow-math",
1588  // "fast2_" for V5+ fast-math double-precision
1589  // (actually, keep fast-math and fast-math2 separate for now)
1590  if (FastMath) {
1591  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1592  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1593  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1594  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1595  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1596  } else {
1597  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1598  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1599  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1600  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1601  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1602  }
1603 
1604  if (FastMath)
1605  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1606  else
1607  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1608 
1609  // These cause problems when the shift amount is non-constant.
1610  setLibcallName(RTLIB::SHL_I128, nullptr);
1611  setLibcallName(RTLIB::SRL_I128, nullptr);
1612  setLibcallName(RTLIB::SRA_I128, nullptr);
1613 }
1614 
1615 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1616  switch ((HexagonISD::NodeType)Opcode) {
1617  case HexagonISD::ADDC: return "HexagonISD::ADDC";
1618  case HexagonISD::SUBC: return "HexagonISD::SUBC";
1619  case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1620  case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1621  case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1622  case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1623  case HexagonISD::CALL: return "HexagonISD::CALL";
1624  case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1625  case HexagonISD::CALLR: return "HexagonISD::CALLR";
1626  case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1627  case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1628  case HexagonISD::CONST32: return "HexagonISD::CONST32";
1629  case HexagonISD::CP: return "HexagonISD::CP";
1630  case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1631  case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1632  case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1633  case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1634  case HexagonISD::INSERT: return "HexagonISD::INSERT";
1635  case HexagonISD::JT: return "HexagonISD::JT";
1636  case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1637  case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1638  case HexagonISD::VASL: return "HexagonISD::VASL";
1639  case HexagonISD::VASR: return "HexagonISD::VASR";
1640  case HexagonISD::VLSR: return "HexagonISD::VLSR";
1641  case HexagonISD::VSPLAT: return "HexagonISD::VSPLAT";
1642  case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1643  case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1644  case HexagonISD::VROR: return "HexagonISD::VROR";
1645  case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1646  case HexagonISD::VZERO: return "HexagonISD::VZERO";
1647  case HexagonISD::VSPLATW: return "HexagonISD::VSPLATW";
1648  case HexagonISD::D2P: return "HexagonISD::D2P";
1649  case HexagonISD::P2D: return "HexagonISD::P2D";
1650  case HexagonISD::V2Q: return "HexagonISD::V2Q";
1651  case HexagonISD::Q2V: return "HexagonISD::Q2V";
1652  case HexagonISD::QCAT: return "HexagonISD::QCAT";
1653  case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1654  case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1655  case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1656  case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1657  case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1658  case HexagonISD::OP_END: break;
1659  }
1660  return nullptr;
1661 }
1662 
1663 void
1664 HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
1665  unsigned NeedAlign) const {
1666  auto *CA = dyn_cast<ConstantSDNode>(Ptr);
1667  if (!CA)
1668  return;
1669  unsigned Addr = CA->getZExtValue();
1670  unsigned HaveAlign = Addr != 0 ? 1u << countTrailingZeros(Addr) : NeedAlign;
1671  if (HaveAlign < NeedAlign) {
1672  std::string ErrMsg;
1673  raw_string_ostream O(ErrMsg);
1674  O << "Misaligned constant address: " << format_hex(Addr, 10)
1675  << " has alignment " << HaveAlign
1676  << ", but the memory access requires " << NeedAlign;
1677  if (DebugLoc DL = dl.getDebugLoc())
1678  DL.print(O << ", at ");
1679  report_fatal_error(O.str());
1680  }
1681 }
1682 
1683 // Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
1684 // intrinsic.
1685 static bool isBrevLdIntrinsic(const Value *Inst) {
1686  unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
1687  return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
1688  ID == Intrinsic::hexagon_L2_loadri_pbr ||
1689  ID == Intrinsic::hexagon_L2_loadrh_pbr ||
1690  ID == Intrinsic::hexagon_L2_loadruh_pbr ||
1691  ID == Intrinsic::hexagon_L2_loadrb_pbr ||
1692  ID == Intrinsic::hexagon_L2_loadrub_pbr);
1693 }
1694 
1695 // Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
1696 // instruction. So far we only handle bitcast, extract value and bit reverse
1697 // load intrinsic instructions. Should we handle CGEP ?
1699  if (Operator::getOpcode(V) == Instruction::ExtractValue ||
1700  Operator::getOpcode(V) == Instruction::BitCast)
1701  V = cast<Operator>(V)->getOperand(0);
1702  else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
1703  V = cast<Instruction>(V)->getOperand(0);
1704  return V;
1705 }
1706 
1707 // Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
1708 // a back edge. If the back edge comes from the intrinsic itself, the incoming
1709 // edge is returned.
1710 static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
1711  const BasicBlock *Parent = PN->getParent();
1712  int Idx = -1;
1713  for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
1714  BasicBlock *Blk = PN->getIncomingBlock(i);
1715  // Determine if the back edge is originated from intrinsic.
1716  if (Blk == Parent) {
1717  Value *BackEdgeVal = PN->getIncomingValue(i);
1718  Value *BaseVal;
1719  // Loop over till we return the same Value or we hit the IntrBaseVal.
1720  do {
1721  BaseVal = BackEdgeVal;
1722  BackEdgeVal = getBrevLdObject(BackEdgeVal);
1723  } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
1724  // If the getBrevLdObject returns IntrBaseVal, we should return the
1725  // incoming edge.
1726  if (IntrBaseVal == BackEdgeVal)
1727  continue;
1728  Idx = i;
1729  break;
1730  } else // Set the node to incoming edge.
1731  Idx = i;
1732  }
1733  assert(Idx >= 0 && "Unexpected index to incoming argument in PHI");
1734  return PN->getIncomingValue(Idx);
1735 }
1736 
1737 // Bit-reverse Load Intrinsic: Figure out the underlying object the base
1738 // pointer points to, for the bit-reverse load intrinsic. Setting this to
1739 // memoperand might help alias analysis to figure out the dependencies.
1741  Value *IntrBaseVal = V;
1742  Value *BaseVal;
1743  // Loop over till we return the same Value, implies we either figure out
1744  // the object or we hit a PHI
1745  do {
1746  BaseVal = V;
1747  V = getBrevLdObject(V);
1748  } while (BaseVal != V);
1749 
1750  // Identify the object from PHINode.
1751  if (const PHINode *PN = dyn_cast<PHINode>(V))
1752  return returnEdge(PN, IntrBaseVal);
1753  // For non PHI nodes, the object is the last value returned by getBrevLdObject
1754  else
1755  return V;
1756 }
1757 
1758 /// Given an intrinsic, checks if on the target the intrinsic will need to map
1759 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1760 /// true and store the intrinsic information into the IntrinsicInfo that was
1761 /// passed to the function.
1763  const CallInst &I,
1764  MachineFunction &MF,
1765  unsigned Intrinsic) const {
1766  switch (Intrinsic) {
1767  case Intrinsic::hexagon_L2_loadrd_pbr:
1768  case Intrinsic::hexagon_L2_loadri_pbr:
1769  case Intrinsic::hexagon_L2_loadrh_pbr:
1770  case Intrinsic::hexagon_L2_loadruh_pbr:
1771  case Intrinsic::hexagon_L2_loadrb_pbr:
1772  case Intrinsic::hexagon_L2_loadrub_pbr: {
1773  Info.opc = ISD::INTRINSIC_W_CHAIN;
1774  auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
1775  auto &Cont = I.getCalledFunction()->getParent()->getContext();
1776  // The intrinsic function call is of the form { ElTy, i8* }
1777  // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
1778  // should be derived from ElTy.
1780  Info.memVT = MVT::getVT(ElTy);
1781  llvm::Value *BasePtrVal = I.getOperand(0);
1782  Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
1783  // The offset value comes through Modifier register. For now, assume the
1784  // offset is 0.
1785  Info.offset = 0;
1786  Info.align = DL.getABITypeAlignment(Info.memVT.getTypeForEVT(Cont));
1788  return true;
1789  }
1790  case Intrinsic::hexagon_V6_vgathermw:
1791  case Intrinsic::hexagon_V6_vgathermw_128B:
1792  case Intrinsic::hexagon_V6_vgathermh:
1793  case Intrinsic::hexagon_V6_vgathermh_128B:
1794  case Intrinsic::hexagon_V6_vgathermhw:
1795  case Intrinsic::hexagon_V6_vgathermhw_128B:
1796  case Intrinsic::hexagon_V6_vgathermwq:
1797  case Intrinsic::hexagon_V6_vgathermwq_128B:
1798  case Intrinsic::hexagon_V6_vgathermhq:
1799  case Intrinsic::hexagon_V6_vgathermhq_128B:
1800  case Intrinsic::hexagon_V6_vgathermhwq:
1801  case Intrinsic::hexagon_V6_vgathermhwq_128B: {
1802  const Module &M = *I.getParent()->getParent()->getParent();
1803  Info.opc = ISD::INTRINSIC_W_CHAIN;
1804  Type *VecTy = I.getArgOperand(1)->getType();
1805  Info.memVT = MVT::getVT(VecTy);
1806  Info.ptrVal = I.getArgOperand(0);
1807  Info.offset = 0;
1808  Info.align = M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8;
1812  return true;
1813  }
1814  default:
1815  break;
1816  }
1817  return false;
1818 }
1819 
1821  return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
1822 }
1823 
1825  if (!VT1.isSimple() || !VT2.isSimple())
1826  return false;
1827  return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1828 }
1829 
1831  return isOperationLegalOrCustom(ISD::FMA, VT);
1832 }
1833 
1834 // Should we expand the build vector with shuffles?
1836  unsigned DefinedValues) const {
1837  return false;
1838 }
1839 
1841  EVT VT) const {
1842  return true;
1843 }
1844 
1847  if (VT.getVectorNumElements() == 1)
1849 
1850  // Always widen vectors of i1.
1851  MVT ElemTy = VT.getVectorElementType();
1852  if (ElemTy == MVT::i1)
1854 
1855  if (Subtarget.useHVXOps()) {
1856  // If the size of VT is at least half of the vector length,
1857  // widen the vector. Note: the threshold was not selected in
1858  // any scientific way.
1859  ArrayRef<MVT> Tys = Subtarget.getHVXElementTypes();
1860  if (llvm::find(Tys, ElemTy) != Tys.end()) {
1861  unsigned HwWidth = 8*Subtarget.getVectorLength();
1862  unsigned VecWidth = VT.getSizeInBits();
1863  if (VecWidth >= HwWidth/2 && VecWidth < HwWidth)
1865  }
1866  }
1868 }
1869 
1870 std::pair<SDValue, int>
1871 HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
1872  if (Addr.getOpcode() == ISD::ADD) {
1873  SDValue Op1 = Addr.getOperand(1);
1874  if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
1875  return { Addr.getOperand(0), CN->getSExtValue() };
1876  }
1877  return { Addr, 0 };
1878 }
1879 
1880 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
1881 // to select data from, V3 is the permutation.
1882 SDValue
1884  const {
1885  const auto *SVN = cast<ShuffleVectorSDNode>(Op);
1886  ArrayRef<int> AM = SVN->getMask();
1887  assert(AM.size() <= 8 && "Unexpected shuffle mask");
1888  unsigned VecLen = AM.size();
1889 
1890  MVT VecTy = ty(Op);
1891  assert(!Subtarget.isHVXVectorType(VecTy, true) &&
1892  "HVX shuffles should be legal");
1893  assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length");
1894 
1895  SDValue Op0 = Op.getOperand(0);
1896  SDValue Op1 = Op.getOperand(1);
1897  const SDLoc &dl(Op);
1898 
1899  // If the inputs are not the same as the output, bail. This is not an
1900  // error situation, but complicates the handling and the default expansion
1901  // (into BUILD_VECTOR) should be adequate.
1902  if (ty(Op0) != VecTy || ty(Op1) != VecTy)
1903  return SDValue();
1904 
1905  // Normalize the mask so that the first non-negative index comes from
1906  // the first operand.
1907  SmallVector<int,8> Mask(AM.begin(), AM.end());
1908  unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
1909  if (F == AM.size())
1910  return DAG.getUNDEF(VecTy);
1911  if (AM[F] >= int(VecLen)) {
1913  std::swap(Op0, Op1);
1914  }
1915 
1916  // Express the shuffle mask in terms of bytes.
1917  SmallVector<int,8> ByteMask;
1918  unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
1919  for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
1920  int M = Mask[i];
1921  if (M < 0) {
1922  for (unsigned j = 0; j != ElemBytes; ++j)
1923  ByteMask.push_back(-1);
1924  } else {
1925  for (unsigned j = 0; j != ElemBytes; ++j)
1926  ByteMask.push_back(M*ElemBytes + j);
1927  }
1928  }
1929  assert(ByteMask.size() <= 8);
1930 
1931  // All non-undef (non-negative) indexes are well within [0..127], so they
1932  // fit in a single byte. Build two 64-bit words:
1933  // - MaskIdx where each byte is the corresponding index (for non-negative
1934  // indexes), and 0xFF for negative indexes, and
1935  // - MaskUnd that has 0xFF for each negative index.
1936  uint64_t MaskIdx = 0;
1937  uint64_t MaskUnd = 0;
1938  for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
1939  unsigned S = 8*i;
1940  uint64_t M = ByteMask[i] & 0xFF;
1941  if (M == 0xFF)
1942  MaskUnd |= M << S;
1943  MaskIdx |= M << S;
1944  }
1945 
1946  if (ByteMask.size() == 4) {
1947  // Identity.
1948  if (MaskIdx == (0x03020100 | MaskUnd))
1949  return Op0;
1950  // Byte swap.
1951  if (MaskIdx == (0x00010203 | MaskUnd)) {
1952  SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
1953  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
1954  return DAG.getBitcast(VecTy, T1);
1955  }
1956 
1957  // Byte packs.
1958  SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
1959  typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
1960  if (MaskIdx == (0x06040200 | MaskUnd))
1961  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
1962  if (MaskIdx == (0x07050301 | MaskUnd))
1963  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
1964 
1965  SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
1966  typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
1967  if (MaskIdx == (0x02000604 | MaskUnd))
1968  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
1969  if (MaskIdx == (0x03010705 | MaskUnd))
1970  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
1971  }
1972 
1973  if (ByteMask.size() == 8) {
1974  // Identity.
1975  if (MaskIdx == (0x0706050403020100ull | MaskUnd))
1976  return Op0;
1977  // Byte swap.
1978  if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
1979  SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
1980  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
1981  return DAG.getBitcast(VecTy, T1);
1982  }
1983 
1984  // Halfword picks.
1985  if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
1986  return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
1987  if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
1988  return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
1989  if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
1990  return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
1991  if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
1992  return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
1993  if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
1994  VectorPair P = opSplit(Op0, dl, DAG);
1995  return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
1996  }
1997 
1998  // Byte packs.
1999  if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2000  return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2001  if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2002  return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2003  }
2004 
2005  return SDValue();
2006 }
2007 
2008 // Create a Hexagon-specific node for shifting a vector by an integer.
2009 SDValue
2010 HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
2011  const {
2012  if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) {
2013  if (SDValue S = BVN->getSplatValue()) {
2014  unsigned NewOpc;
2015  switch (Op.getOpcode()) {
2016  case ISD::SHL:
2017  NewOpc = HexagonISD::VASL;
2018  break;
2019  case ISD::SRA:
2020  NewOpc = HexagonISD::VASR;
2021  break;
2022  case ISD::SRL:
2023  NewOpc = HexagonISD::VLSR;
2024  break;
2025  default:
2026  llvm_unreachable("Unexpected shift opcode");
2027  }
2028  return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), S);
2029  }
2030  }
2031 
2032  return SDValue();
2033 }
2034 
2035 SDValue
2037  return getVectorShiftByInt(Op, DAG);
2038 }
2039 
2040 SDValue
2042  if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
2043  return Op;
2044  return SDValue();
2045 }
2046 
2047 SDValue
2049  MVT ResTy = ty(Op);
2050  SDValue InpV = Op.getOperand(0);
2051  MVT InpTy = ty(InpV);
2052  assert(ResTy.getSizeInBits() == InpTy.getSizeInBits());
2053  const SDLoc &dl(Op);
2054 
2055  // Handle conversion from i8 to v8i1.
2056  if (ResTy == MVT::v8i1) {
2057  SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
2058  SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
2059  return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2060  }
2061 
2062  return SDValue();
2063 }
2064 
2065 bool
2066 HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
2067  MVT VecTy, SelectionDAG &DAG,
2068  MutableArrayRef<ConstantInt*> Consts) const {
2069  MVT ElemTy = VecTy.getVectorElementType();
2070  unsigned ElemWidth = ElemTy.getSizeInBits();
2071  IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
2072  bool AllConst = true;
2073 
2074  for (unsigned i = 0, e = Values.size(); i != e; ++i) {
2075  SDValue V = Values[i];
2076  if (V.isUndef()) {
2077  Consts[i] = ConstantInt::get(IntTy, 0);
2078  continue;
2079  }
2080  // Make sure to always cast to IntTy.
2081  if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2082  const ConstantInt *CI = CN->getConstantIntValue();
2083  Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2084  } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
2085  const ConstantFP *CF = CN->getConstantFPValue();
2086  APInt A = CF->getValueAPF().bitcastToAPInt();
2087  Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
2088  } else {
2089  AllConst = false;
2090  }
2091  }
2092  return AllConst;
2093 }
2094 
2095 SDValue
2096 HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
2097  MVT VecTy, SelectionDAG &DAG) const {
2098  MVT ElemTy = VecTy.getVectorElementType();
2099  assert(VecTy.getVectorNumElements() == Elem.size());
2100 
2101  SmallVector<ConstantInt*,4> Consts(Elem.size());
2102  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2103 
2104  unsigned First, Num = Elem.size();
2105  for (First = 0; First != Num; ++First)
2106  if (!isUndef(Elem[First]))
2107  break;
2108  if (First == Num)
2109  return DAG.getUNDEF(VecTy);
2110 
2111  if (AllConst &&
2112  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2113  return getZero(dl, VecTy, DAG);
2114 
2115  if (ElemTy == MVT::i16) {
2116  assert(Elem.size() == 2);
2117  if (AllConst) {
2118  uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2119  Consts[1]->getZExtValue() << 16;
2120  return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
2121  }
2122  SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
2123  {Elem[1], Elem[0]}, DAG);
2124  return DAG.getBitcast(MVT::v2i16, N);
2125  }
2126 
2127  if (ElemTy == MVT::i8) {
2128  // First try generating a constant.
2129  if (AllConst) {
2130  int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2131  (Consts[1]->getZExtValue() & 0xFF) << 8 |
2132  (Consts[1]->getZExtValue() & 0xFF) << 16 |
2133  Consts[2]->getZExtValue() << 24;
2134  return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2135  }
2136 
2137  // Then try splat.
2138  bool IsSplat = true;
2139  for (unsigned i = 0; i != Num; ++i) {
2140  if (i == First)
2141  continue;
2142  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2143  continue;
2144  IsSplat = false;
2145  break;
2146  }
2147  if (IsSplat) {
2148  // Legalize the operand to VSPLAT.
2149  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2150  return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2151  }
2152 
2153  // Generate
2154  // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
2155  // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
2156  assert(Elem.size() == 4);
2157  SDValue Vs[4];
2158  for (unsigned i = 0; i != 4; ++i) {
2159  Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2160  Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2161  }
2162  SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
2163  SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2164  SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2165  SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2166  SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2167 
2168  SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2169  return DAG.getBitcast(MVT::v4i8, R);
2170  }
2171 
2172 #ifndef NDEBUG
2173  dbgs() << "VecTy: " << EVT(VecTy).getEVTString() << '\n';
2174 #endif
2175  llvm_unreachable("Unexpected vector element type");
2176 }
2177 
2178 SDValue
2179 HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
2180  MVT VecTy, SelectionDAG &DAG) const {
2181  MVT ElemTy = VecTy.getVectorElementType();
2182  assert(VecTy.getVectorNumElements() == Elem.size());
2183 
2184  SmallVector<ConstantInt*,8> Consts(Elem.size());
2185  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2186 
2187  unsigned First, Num = Elem.size();
2188  for (First = 0; First != Num; ++First)
2189  if (!isUndef(Elem[First]))
2190  break;
2191  if (First == Num)
2192  return DAG.getUNDEF(VecTy);
2193 
2194  if (AllConst &&
2195  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2196  return getZero(dl, VecTy, DAG);
2197 
2198  // First try splat if possible.
2199  if (ElemTy == MVT::i16) {
2200  bool IsSplat = true;
2201  for (unsigned i = 0; i != Num; ++i) {
2202  if (i == First)
2203  continue;
2204  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2205  continue;
2206  IsSplat = false;
2207  break;
2208  }
2209  if (IsSplat) {
2210  // Legalize the operand to VSPLAT.
2211  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2212  return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2213  }
2214  }
2215 
2216  // Then try constant.
2217  if (AllConst) {
2218  uint64_t Val = 0;
2219  unsigned W = ElemTy.getSizeInBits();
2220  uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
2221  : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
2222  for (unsigned i = 0; i != Num; ++i)
2223  Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2224  SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2225  return DAG.getBitcast(VecTy, V0);
2226  }
2227 
2228  // Build two 32-bit vectors and concatenate.
2229  MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2230  SDValue L = (ElemTy == MVT::i32)
2231  ? Elem[0]
2232  : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2233  SDValue H = (ElemTy == MVT::i32)
2234  ? Elem[1]
2235  : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
2236  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
2237 }
2238 
2239 SDValue
2240 HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
2241  const SDLoc &dl, MVT ValTy, MVT ResTy,
2242  SelectionDAG &DAG) const {
2243  MVT VecTy = ty(VecV);
2244  assert(!ValTy.isVector() ||
2245  VecTy.getVectorElementType() == ValTy.getVectorElementType());
2246  unsigned VecWidth = VecTy.getSizeInBits();
2247  unsigned ValWidth = ValTy.getSizeInBits();
2248  unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
2249  assert((VecWidth % ElemWidth) == 0);
2250  auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);
2251 
2252  // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2253  // without any coprocessors).
2254  if (ElemWidth == 1) {
2255  assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure");
2256  assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2257  // Check if this is an extract of the lowest bit.
2258  if (IdxN) {
2259  // Extracting the lowest bit is a no-op, but it changes the type,
2260  // so it must be kept as an operation to avoid errors related to
2261  // type mismatches.
2262  if (IdxN->isNullValue() && ValTy.getSizeInBits() == 1)
2263  return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
2264  }
2265 
2266  // If the value extracted is a single bit, use tstbit.
2267  if (ValWidth == 1) {
2268  SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2269  SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
2270  SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2271  return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
2272  }
2273 
2274  // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2275  // a predicate register. The elements of the vector are repeated
2276  // in the register (if necessary) so that the total number is 8.
2277  // The extracted subvector will need to be expanded in such a way.
2278  unsigned Scale = VecWidth / ValWidth;
2279 
2280  // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
2281  // position 0.
2282  assert(ty(IdxV) == MVT::i32);
2283  unsigned VecRep = 8 / VecWidth;
2284  SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2285  DAG.getConstant(8*VecRep, dl, MVT::i32));
2286  SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2287  SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2288  while (Scale > 1) {
2289  // The longest possible subvector is at most 32 bits, so it is always
2290  // contained in the low subregister.
2291  T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
2292  T1 = expandPredicate(T1, dl, DAG);
2293  Scale /= 2;
2294  }
2295 
2296  return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
2297  }
2298 
2299  assert(VecWidth == 32 || VecWidth == 64);
2300 
2301  // Cast everything to scalar integer types.
2302  MVT ScalarTy = tyScalar(VecTy);
2303  VecV = DAG.getBitcast(ScalarTy, VecV);
2304 
2305  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2306  SDValue ExtV;
2307 
2308  if (IdxN) {
2309  unsigned Off = IdxN->getZExtValue() * ElemWidth;
2310  if (VecWidth == 64 && ValWidth == 32) {
2311  assert(Off == 0 || Off == 32);
2312  unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
2313  ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
2314  } else if (Off == 0 && (ValWidth % 8) == 0) {
2315  ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
2316  } else {
2317  SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
2318  // The return type of EXTRACTU must be the same as the type of the
2319  // input vector.
2320  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2321  {VecV, WidthV, OffV});
2322  }
2323  } else {
2324  if (ty(IdxV) != MVT::i32)
2325  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2326  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2327  DAG.getConstant(ElemWidth, dl, MVT::i32));
2328  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2329  {VecV, WidthV, OffV});
2330  }
2331 
2332  // Cast ExtV to the requested result type.
2333  ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
2334  ExtV = DAG.getBitcast(ResTy, ExtV);
2335  return ExtV;
2336 }
2337 
2338 SDValue
2339 HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
2340  const SDLoc &dl, MVT ValTy,
2341  SelectionDAG &DAG) const {
2342  MVT VecTy = ty(VecV);
2343  if (VecTy.getVectorElementType() == MVT::i1) {
2344  MVT ValTy = ty(ValV);
2345  assert(ValTy.getVectorElementType() == MVT::i1);
2346  SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV);
2347  unsigned VecLen = VecTy.getVectorNumElements();
2348  unsigned Scale = VecLen / ValTy.getVectorNumElements();
2349  assert(Scale > 1);
2350 
2351  for (unsigned R = Scale; R > 1; R /= 2) {
2352  ValR = contractPredicate(ValR, dl, DAG);
2353  ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2354  DAG.getUNDEF(MVT::i32), ValR);
2355  }
2356  // The longest possible subvector is at most 32 bits, so it is always
2357  // contained in the low subregister.
2358  ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);
2359 
2360  unsigned ValBytes = 64 / Scale;
2361  SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32);
2362  SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2363  DAG.getConstant(8, dl, MVT::i32));
2364  SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2366  {VecR, ValR, Width, Idx});
2367  return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
2368  }
2369 
2370  unsigned VecWidth = VecTy.getSizeInBits();
2371  unsigned ValWidth = ValTy.getSizeInBits();
2372  assert(VecWidth == 32 || VecWidth == 64);
2373  assert((VecWidth % ValWidth) == 0);
2374 
2375  // Cast everything to scalar integer types.
2376  MVT ScalarTy = MVT::getIntegerVT(VecWidth);
2377  // The actual type of ValV may be different than ValTy (which is related
2378  // to the vector type).
2379  unsigned VW = ty(ValV).getSizeInBits();
2380  ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
2381  VecV = DAG.getBitcast(ScalarTy, VecV);
2382  if (VW != VecWidth)
2383  ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
2384 
2385  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2386  SDValue InsV;
2387 
2388  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
2389  unsigned W = C->getZExtValue() * ValWidth;
2390  SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
2391  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2392  {VecV, ValV, WidthV, OffV});
2393  } else {
2394  if (ty(IdxV) != MVT::i32)
2395  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2396  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2397  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2398  {VecV, ValV, WidthV, OffV});
2399  }
2400 
2401  return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2402 }
2403 
2404 SDValue
2405 HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
2406  SelectionDAG &DAG) const {
2407  assert(ty(Vec32).getSizeInBits() == 32);
2408  if (isUndef(Vec32))
2409  return DAG.getUNDEF(MVT::i64);
2410  return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2411 }
2412 
2413 SDValue
2414 HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
2415  SelectionDAG &DAG) const {
2416  assert(ty(Vec64).getSizeInBits() == 64);
2417  if (isUndef(Vec64))
2418  return DAG.getUNDEF(MVT::i32);
2419  return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2420 }
2421 
2422 SDValue
2423 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
2424  const {
2425  if (Ty.isVector()) {
2426  assert(Ty.isInteger() && "Only integer vectors are supported here");
2427  unsigned W = Ty.getSizeInBits();
2428  if (W <= 64)
2429  return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
2430  return DAG.getNode(HexagonISD::VZERO, dl, Ty);
2431  }
2432 
2433  if (Ty.isInteger())
2434  return DAG.getConstant(0, dl, Ty);
2435  if (Ty.isFloatingPoint())
2436  return DAG.getConstantFP(0.0, dl, Ty);
2437  llvm_unreachable("Invalid type for zero");
2438 }
2439 
2440 SDValue
2442  MVT VecTy = ty(Op);
2443  unsigned BW = VecTy.getSizeInBits();
2444  const SDLoc &dl(Op);
2446  for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
2447  Ops.push_back(Op.getOperand(i));
2448 
2449  if (BW == 32)
2450  return buildVector32(Ops, dl, VecTy, DAG);
2451  if (BW == 64)
2452  return buildVector64(Ops, dl, VecTy, DAG);
2453 
2454  if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2455  // For each i1 element in the resulting predicate register, put 1
2456  // shifted by the index of the element into a general-purpose register,
2457  // then or them together and transfer it back into a predicate register.
2458  SDValue Rs[8];
2459  SDValue Z = getZero(dl, MVT::i32, DAG);
2460  // Always produce 8 bits, repeat inputs if necessary.
2461  unsigned Rep = 8 / VecTy.getVectorNumElements();
2462  for (unsigned i = 0; i != 8; ++i) {
2463  SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
2464  Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2465  }
2466  for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2467  for (unsigned i = 0, e = A.size()/2; i != e; ++i)
2468  Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2469  }
2470  // Move the value directly to a predicate register.
2471  return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2472  }
2473 
2474  return SDValue();
2475 }
2476 
2477 SDValue
2479  SelectionDAG &DAG) const {
2480  MVT VecTy = ty(Op);
2481  const SDLoc &dl(Op);
2482  if (VecTy.getSizeInBits() == 64) {
2483  assert(Op.getNumOperands() == 2);
2484  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1),
2485  Op.getOperand(0));
2486  }
2487 
2488  MVT ElemTy = VecTy.getVectorElementType();
2489  if (ElemTy == MVT::i1) {
2490  assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2491  MVT OpTy = ty(Op.getOperand(0));
2492  // Scale is how many times the operands need to be contracted to match
2493  // the representation in the target register.
2494  unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
2495  assert(Scale == Op.getNumOperands() && Scale > 1);
2496 
2497  // First, convert all bool vectors to integers, then generate pairwise
2498  // inserts to form values of doubled length. Up until there are only
2499  // two values left to concatenate, all of these values will fit in a
2500  // 32-bit integer, so keep them as i32 to use 32-bit inserts.
2501  SmallVector<SDValue,4> Words[2];
2502  unsigned IdxW = 0;
2503 
2504  for (SDValue P : Op.getNode()->op_values()) {
2505  SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
2506  for (unsigned R = Scale; R > 1; R /= 2) {
2507  W = contractPredicate(W, dl, DAG);
2508  W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2509  DAG.getUNDEF(MVT::i32), W);
2510  }
2511  W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
2512  Words[IdxW].push_back(W);
2513  }
2514 
2515  while (Scale > 2) {
2516  SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
2517  Words[IdxW ^ 1].clear();
2518 
2519  for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
2520  SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
2521  // Insert W1 into W0 right next to the significant bits of W0.
2523  {W0, W1, WidthV, WidthV});
2524  Words[IdxW ^ 1].push_back(T);
2525  }
2526  IdxW ^= 1;
2527  Scale /= 2;
2528  }
2529 
2530  // Another sanity check. At this point there should only be two words
2531  // left, and Scale should be 2.
2532  assert(Scale == 2 && Words[IdxW].size() == 2);
2533 
2535  Words[IdxW][1], Words[IdxW][0]);
2536  return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
2537  }
2538 
2539  return SDValue();
2540 }
2541 
2542 SDValue
2544  SelectionDAG &DAG) const {
2545  SDValue Vec = Op.getOperand(0);
2546  MVT ElemTy = ty(Vec).getVectorElementType();
2547  return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
2548 }
2549 
2550 SDValue
2552  SelectionDAG &DAG) const {
2553  return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
2554  ty(Op), ty(Op), DAG);
2555 }
2556 
2557 SDValue
2559  SelectionDAG &DAG) const {
2560  return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
2561  SDLoc(Op), ty(Op).getVectorElementType(), DAG);
2562 }
2563 
2564 SDValue
2566  SelectionDAG &DAG) const {
2567  SDValue ValV = Op.getOperand(1);
2568  return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
2569  SDLoc(Op), ty(ValV), DAG);
2570 }
2571 
2572 bool
2574  // Assuming the caller does not have either a signext or zeroext modifier, and
2575  // only one value is accepted, any reasonable truncation is allowed.
2576  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2577  return false;
2578 
2579  // FIXME: in principle up to 64-bit could be made safe, but it would be very
2580  // fragile at the moment: any support for multiple value returns would be
2581  // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2582  return Ty1->getPrimitiveSizeInBits() <= 32;
2583 }
2584 
2585 SDValue
2587  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2588  unsigned ClaimAlign = LN->getAlignment();
2589  validateConstPtrAlignment(LN->getBasePtr(), SDLoc(Op), ClaimAlign);
2590  // Call LowerUnalignedLoad for all loads, it recognizes loads that
2591  // don't need extra aligning.
2592  return LowerUnalignedLoad(Op, DAG);
2593 }
2594 
2595 SDValue
2597  StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
2598  unsigned ClaimAlign = SN->getAlignment();
2599  SDValue Ptr = SN->getBasePtr();
2600  const SDLoc &dl(Op);
2601  validateConstPtrAlignment(Ptr, dl, ClaimAlign);
2602 
2603  MVT StoreTy = SN->getMemoryVT().getSimpleVT();
2604  unsigned NeedAlign = Subtarget.getTypeAlignment(StoreTy);
2605  if (ClaimAlign < NeedAlign)
2606  return expandUnalignedStore(SN, DAG);
2607  return Op;
2608 }
2609 
2610 SDValue
2612  const {
2613  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2614  MVT LoadTy = ty(Op);
2615  unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
2616  unsigned HaveAlign = LN->getAlignment();
2617  if (HaveAlign >= NeedAlign)
2618  return Op;
2619 
2620  const SDLoc &dl(Op);
2621  const DataLayout &DL = DAG.getDataLayout();
2622  LLVMContext &Ctx = *DAG.getContext();
2623 
2624  // If the load aligning is disabled or the load can be broken up into two
2625  // smaller legal loads, do the default (target-independent) expansion.
2626  bool DoDefault = false;
2627  // Handle it in the default way if this is an indexed load.
2628  if (!LN->isUnindexed())
2629  DoDefault = true;
2630 
2631  if (!AlignLoads) {
2632  if (allowsMemoryAccess(Ctx, DL, LN->getMemoryVT(), *LN->getMemOperand()))
2633  return Op;
2634  DoDefault = true;
2635  }
2636  if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
2637  // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
2638  MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign)
2639  : MVT::getVectorVT(MVT::i8, HaveAlign);
2640  DoDefault = allowsMemoryAccess(Ctx, DL, PartTy, *LN->getMemOperand());
2641  }
2642  if (DoDefault) {
2643  std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
2644  return DAG.getMergeValues({P.first, P.second}, dl);
2645  }
2646 
2647  // The code below generates two loads, both aligned as NeedAlign, and
2648  // with the distance of NeedAlign between them. For that to cover the
2649  // bits that need to be loaded (and without overlapping), the size of
2650  // the loads should be equal to NeedAlign. This is true for all loadable
2651  // types, but add an assertion in case something changes in the future.
2652  assert(LoadTy.getSizeInBits() == 8*NeedAlign);
2653 
2654  unsigned LoadLen = NeedAlign;
2655  SDValue Base = LN->getBasePtr();
2656  SDValue Chain = LN->getChain();
2657  auto BO = getBaseAndOffset(Base);
2658  unsigned BaseOpc = BO.first.getOpcode();
2659  if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
2660  return Op;
2661 
2662  if (BO.second % LoadLen != 0) {
2663  BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
2664  DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
2665  BO.second -= BO.second % LoadLen;
2666  }
2667  SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
2668  ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
2669  DAG.getConstant(NeedAlign, dl, MVT::i32))
2670  : BO.first;
2671  SDValue Base0 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second, dl);
2672  SDValue Base1 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second+LoadLen, dl);
2673 
2674  MachineMemOperand *WideMMO = nullptr;
2675  if (MachineMemOperand *MMO = LN->getMemOperand()) {
2676  MachineFunction &MF = DAG.getMachineFunction();
2677  WideMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), MMO->getFlags(),
2678  2*LoadLen, LoadLen, MMO->getAAInfo(), MMO->getRanges(),
2679  MMO->getSyncScopeID(), MMO->getOrdering(),
2680  MMO->getFailureOrdering());
2681  }
2682 
2683  SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
2684  SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
2685 
2686  SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
2687  {Load1, Load0, BaseNoOff.getOperand(0)});
2688  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2689  Load0.getValue(1), Load1.getValue(1));
2690  SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
2691  return M;
2692 }
2693 
2694 SDValue
2696  SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
2697  auto *CY = dyn_cast<ConstantSDNode>(Y);
2698  if (!CY)
2699  return SDValue();
2700 
2701  const SDLoc &dl(Op);
2702  SDVTList VTs = Op.getNode()->getVTList();
2703  assert(VTs.NumVTs == 2);
2704  assert(VTs.VTs[1] == MVT::i1);
2705  unsigned Opc = Op.getOpcode();
2706 
2707  if (CY) {
2708  uint32_t VY = CY->getZExtValue();
2709  assert(VY != 0 && "This should have been folded");
2710  // X +/- 1
2711  if (VY != 1)
2712  return SDValue();
2713 
2714  if (Opc == ISD::UADDO) {
2715  SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y});
2716  SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG),
2717  ISD::SETEQ);
2718  return DAG.getMergeValues({Op, Ov}, dl);
2719  }
2720  if (Opc == ISD::USUBO) {
2721  SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
2722  SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op,
2723  DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
2724  return DAG.getMergeValues({Op, Ov}, dl);
2725  }
2726  }
2727 
2728  return SDValue();
2729 }
2730 
2731 SDValue
2733  const SDLoc &dl(Op);
2734  unsigned Opc = Op.getOpcode();
2735  SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
2736 
2737  if (Opc == ISD::ADDCARRY)
2738  return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
2739  { X, Y, C });
2740 
2741  EVT CarryTy = C.getValueType();
2742  SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
2743  { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
2744  SDValue Out[] = { SubC.getValue(0),
2745  DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
2746  return DAG.getMergeValues(Out, dl);
2747 }
2748 
2749 SDValue
2751  SDValue Chain = Op.getOperand(0);
2752  SDValue Offset = Op.getOperand(1);
2753  SDValue Handler = Op.getOperand(2);
2754  SDLoc dl(Op);
2755  auto PtrVT = getPointerTy(DAG.getDataLayout());
2756 
2757  // Mark function as containing a call to EH_RETURN.
2758  HexagonMachineFunctionInfo *FuncInfo =
2760  FuncInfo->setHasEHReturn();
2761 
2762  unsigned OffsetReg = Hexagon::R28;
2763 
2764  SDValue StoreAddr =
2765  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2766  DAG.getIntPtrConstant(4, dl));
2767  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2768  Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2769 
2770  // Not needed we already use it as explict input to EH_RETURN.
2771  // MF.getRegInfo().addLiveOut(OffsetReg);
2772 
2773  return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2774 }
2775 
2776 SDValue
2778  unsigned Opc = Op.getOpcode();
2779 
2780  // Handle INLINEASM first.
2781  if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
2782  return LowerINLINEASM(Op, DAG);
2783 
2784  if (isHvxOperation(Op)) {
2785  // If HVX lowering returns nothing, try the default lowering.
2786  if (SDValue V = LowerHvxOperation(Op, DAG))
2787  return V;
2788  }
2789 
2790  switch (Opc) {
2791  default:
2792 #ifndef NDEBUG
2793  Op.getNode()->dumpr(&DAG);
2794  if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2795  errs() << "Error: check for a non-legal type in this operation\n";
2796 #endif
2797  llvm_unreachable("Should not custom lower this!");
2798  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2799  case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
2800  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
2801  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
2802  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2803  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2804  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2805  case ISD::BITCAST: return LowerBITCAST(Op, DAG);
2806  case ISD::LOAD: return LowerLoad(Op, DAG);
2807  case ISD::STORE: return LowerStore(Op, DAG);
2808  case ISD::UADDO:
2809  case ISD::USUBO: return LowerUAddSubO(Op, DAG);
2810  case ISD::ADDCARRY:
2811  case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
2812  case ISD::SRA:
2813  case ISD::SHL:
2814  case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2815  case ISD::ROTL: return LowerROTL(Op, DAG);
2816  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2817  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2818  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2819  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2820  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2821  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2822  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2823  case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2824  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2825  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2826  case ISD::VASTART: return LowerVASTART(Op, DAG);
2827  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2828  case ISD::SETCC: return LowerSETCC(Op, DAG);
2829  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2830  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2831  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2832  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2833  case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
2834  break;
2835  }
2836 
2837  return SDValue();
2838 }
2839 
2840 void
2843  SelectionDAG &DAG) const {
2844  // We are only custom-lowering stores to verify the alignment of the
2845  // address if it is a compile-time constant. Since a store can be modified
2846  // during type-legalization (the value being stored may need legalization),
2847  // return empty Results here to indicate that we don't really make any
2848  // changes in the custom lowering.
2849  if (N->getOpcode() != ISD::STORE)
2850  return TargetLowering::LowerOperationWrapper(N, Results, DAG);
2851 }
2852 
2853 void
2856  SelectionDAG &DAG) const {
2857  const SDLoc &dl(N);
2858  switch (N->getOpcode()) {
2859  case ISD::SRL:
2860  case ISD::SRA:
2861  case ISD::SHL:
2862  return;
2863  case ISD::BITCAST:
2864  // Handle a bitcast from v8i1 to i8.
2865  if (N->getValueType(0) == MVT::i8) {
2866  SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
2867  N->getOperand(0), DAG);
2868  Results.push_back(P);
2869  }
2870  break;
2871  }
2872 }
2873 
2874 /// Returns relocation base for the given PIC jumptable.
2875 SDValue
2877  SelectionDAG &DAG) const {
2878  int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2879  EVT VT = Table.getValueType();
2881  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2882 }
2883 
2884 //===----------------------------------------------------------------------===//
2885 // Inline Assembly Support
2886 //===----------------------------------------------------------------------===//
2887 
2890  if (Constraint.size() == 1) {
2891  switch (Constraint[0]) {
2892  case 'q':
2893  case 'v':
2894  if (Subtarget.useHVXOps())
2895  return C_RegisterClass;
2896  break;
2897  case 'a':
2898  return C_RegisterClass;
2899  default:
2900  break;
2901  }
2902  }
2903  return TargetLowering::getConstraintType(Constraint);
2904 }
2905 
2906 std::pair<unsigned, const TargetRegisterClass*>
2908  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
2909 
2910  if (Constraint.size() == 1) {
2911  switch (Constraint[0]) {
2912  case 'r': // R0-R31
2913  switch (VT.SimpleTy) {
2914  default:
2915  return {0u, nullptr};
2916  case MVT::i1:
2917  case MVT::i8:
2918  case MVT::i16:
2919  case MVT::i32:
2920  case MVT::f32:
2921  return {0u, &Hexagon::IntRegsRegClass};
2922  case MVT::i64:
2923  case MVT::f64:
2924  return {0u, &Hexagon::DoubleRegsRegClass};
2925  }
2926  break;
2927  case 'a': // M0-M1
2928  if (VT != MVT::i32)
2929  return {0u, nullptr};
2930  return {0u, &Hexagon::ModRegsRegClass};
2931  case 'q': // q0-q3
2932  switch (VT.getSizeInBits()) {
2933  default:
2934  return {0u, nullptr};
2935  case 512:
2936  case 1024:
2937  return {0u, &Hexagon::HvxQRRegClass};
2938  }
2939  break;
2940  case 'v': // V0-V31
2941  switch (VT.getSizeInBits()) {
2942  default:
2943  return {0u, nullptr};
2944  case 512:
2945  return {0u, &Hexagon::HvxVRRegClass};
2946  case 1024:
2947  if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
2948  return {0u, &Hexagon::HvxVRRegClass};
2949  return {0u, &Hexagon::HvxWRRegClass};
2950  case 2048:
2951  return {0u, &Hexagon::HvxWRRegClass};
2952  }
2953  break;
2954  default:
2955  return {0u, nullptr};
2956  }
2957  }
2958 
2959  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2960 }
2961 
2962 /// isFPImmLegal - Returns true if the target can instruction select the
2963 /// specified FP immediate natively. If false, the legalizer will
2964 /// materialize the FP immediate as a load from a constant pool.
2966  bool ForCodeSize) const {
2967  return true;
2968 }
2969 
2970 /// isLegalAddressingMode - Return true if the addressing mode represented by
2971 /// AM is legal for this target, for a load/store of the specified type.
2973  const AddrMode &AM, Type *Ty,
2974  unsigned AS, Instruction *I) const {
2975  if (Ty->isSized()) {
2976  // When LSR detects uses of the same base address to access different
2977  // types (e.g. unions), it will assume a conservative type for these
2978  // uses:
2979  // LSR Use: Kind=Address of void in addrspace(4294967295), ...
2980  // The type Ty passed here would then be "void". Skip the alignment
2981  // checks, but do not return false right away, since that confuses
2982  // LSR into crashing.
2983  unsigned A = DL.getABITypeAlignment(Ty);
2984  // The base offset must be a multiple of the alignment.
2985  if ((AM.BaseOffs % A) != 0)
2986  return false;
2987  // The shifted offset must fit in 11 bits.
2988  if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
2989  return false;
2990  }
2991 
2992  // No global is ever allowed as a base.
2993  if (AM.BaseGV)
2994  return false;
2995 
2996  int Scale = AM.Scale;
2997  if (Scale < 0)
2998  Scale = -Scale;
2999  switch (Scale) {
3000  case 0: // No scale reg, "r+i", "r", or just "i".
3001  break;
3002  default: // No scaled addressing mode.
3003  return false;
3004  }
3005  return true;
3006 }
3007 
3008 /// Return true if folding a constant offset with the given GlobalAddress is
3009 /// legal. It is frequently not legal in PIC relocation models.
3011  const {
3012  return HTM.getRelocationModel() == Reloc::Static;
3013 }
3014 
3015 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3016 /// icmp immediate, that is the target has icmp instructions which can compare
3017 /// a register against the immediate without having to materialize the
3018 /// immediate into a register.
3020  return Imm >= -512 && Imm <= 511;
3021 }
3022 
3023 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3024 /// for tail call optimization. Targets which want to do tail call
3025 /// optimization should implement this function.
3027  SDValue Callee,
3028  CallingConv::ID CalleeCC,
3029  bool IsVarArg,
3030  bool IsCalleeStructRet,
3031  bool IsCallerStructRet,
3032  const SmallVectorImpl<ISD::OutputArg> &Outs,
3033  const SmallVectorImpl<SDValue> &OutVals,
3035  SelectionDAG& DAG) const {
3036  const Function &CallerF = DAG.getMachineFunction().getFunction();
3037  CallingConv::ID CallerCC = CallerF.getCallingConv();
3038  bool CCMatch = CallerCC == CalleeCC;
3039 
3040  // ***************************************************************************
3041  // Look for obvious safe cases to perform tail call optimization that do not
3042  // require ABI changes.
3043  // ***************************************************************************
3044 
3045  // If this is a tail call via a function pointer, then don't do it!
3046  if (!isa<GlobalAddressSDNode>(Callee) &&
3047  !isa<ExternalSymbolSDNode>(Callee)) {
3048  return false;
3049  }
3050 
3051  // Do not optimize if the calling conventions do not match and the conventions
3052  // used are not C or Fast.
3053  if (!CCMatch) {
3054  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3055  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3056  // If R & E, then ok.
3057  if (!R || !E)
3058  return false;
3059  }
3060 
3061  // Do not tail call optimize vararg calls.
3062  if (IsVarArg)
3063  return false;
3064 
3065  // Also avoid tail call optimization if either caller or callee uses struct
3066  // return semantics.
3067  if (IsCalleeStructRet || IsCallerStructRet)
3068  return false;
3069 
3070  // In addition to the cases above, we also disable Tail Call Optimization if
3071  // the calling convention code that at least one outgoing argument needs to
3072  // go on the stack. We cannot check that here because at this point that
3073  // information is not available.
3074  return true;
3075 }
3076 
3077 /// Returns the target specific optimal type for load and store operations as
3078 /// a result of memset, memcpy, and memmove lowering.
3079 ///
3080 /// If DstAlign is zero that means it's safe to destination alignment can
3081 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3082 /// a need to check it against alignment requirement, probably because the
3083 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3084 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3085 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3086 /// does not need to be loaded. It returns EVT::Other if the type should be
3087 /// determined using generic target-independent logic.
3089  unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3090  bool MemcpyStrSrc, const AttributeList &FuncAttributes) const {
3091 
3092  auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3093  return (GivenA % MinA) == 0;
3094  };
3095 
3096  if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3097  return MVT::i64;
3098  if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3099  return MVT::i32;
3100  if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3101  return MVT::i16;
3102 
3103  return MVT::Other;
3104 }
3105 
3107  EVT VT, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags,
3108  bool *Fast) const {
3109  if (Fast)
3110  *Fast = false;
3111  return Subtarget.isHVXVectorType(VT.getSimpleVT());
3112 }
3113 
3114 std::pair<const TargetRegisterClass*, uint8_t>
3115 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3116  MVT VT) const {
3117  if (Subtarget.isHVXVectorType(VT, true)) {
3118  unsigned BitWidth = VT.getSizeInBits();
3119  unsigned VecWidth = Subtarget.getVectorLength() * 8;
3120 
3121  if (VT.getVectorElementType() == MVT::i1)
3122  return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3123  if (BitWidth == VecWidth)
3124  return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3125  assert(BitWidth == 2 * VecWidth);
3126  return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3127  }
3128 
3130 }
3131 
3133  ISD::LoadExtType ExtTy, EVT NewVT) const {
3134  // TODO: This may be worth removing. Check regression tests for diffs.
3135  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
3136  return false;
3137 
3138  auto *L = cast<LoadSDNode>(Load);
3139  std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3140  // Small-data object, do not shrink.
3141  if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
3142  return false;
3143  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
3144  auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
3145  const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3146  return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3147  }
3148  return true;
3149 }
3150 
3152  AtomicOrdering Ord) const {
3153  BasicBlock *BB = Builder.GetInsertBlock();
3154  Module *M = BB->getParent()->getParent();
3155  auto PT = cast<PointerType>(Addr->getType());
3156  Type *Ty = PT->getElementType();
3157  unsigned SZ = Ty->getPrimitiveSizeInBits();
3158  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3159  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3160  : Intrinsic::hexagon_L4_loadd_locked;
3161  Function *Fn = Intrinsic::getDeclaration(M, IntID);
3162 
3163  PointerType *NewPtrTy
3164  = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
3165  Addr = Builder.CreateBitCast(Addr, NewPtrTy);
3166 
3167  Value *Call = Builder.CreateCall(Fn, Addr, "larx");
3168 
3169  return Builder.CreateBitCast(Call, Ty);
3170 }
3171 
3172 /// Perform a store-conditional operation to Addr. Return the status of the
3173 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3175  Value *Val, Value *Addr, AtomicOrdering Ord) const {
3176  BasicBlock *BB = Builder.GetInsertBlock();
3177  Module *M = BB->getParent()->getParent();
3178  Type *Ty = Val->getType();
3179  unsigned SZ = Ty->getPrimitiveSizeInBits();
3180 
3181  Type *CastTy = Builder.getIntNTy(SZ);
3182  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3183  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3184  : Intrinsic::hexagon_S4_stored_locked;
3185  Function *Fn = Intrinsic::getDeclaration(M, IntID);
3186 
3187  unsigned AS = Addr->getType()->getPointerAddressSpace();
3188  Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
3189  Val = Builder.CreateBitCast(Val, CastTy);
3190 
3191  Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3192  Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3193  Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3194  return Ext;
3195 }
3196 
3199  // Do not expand loads and stores that don't exceed 64 bits.
3200  return LI->getType()->getPrimitiveSizeInBits() > 64
3203 }
3204 
3206  // Do not expand loads and stores that don't exceed 64 bits.
3207  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3208 }
3209 
3212  AtomicCmpXchgInst *AI) const {
3213  const DataLayout &DL = AI->getModule()->getDataLayout();
3214  unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3215  if (Size >= 4 && Size <= 8)
3218 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
bool isMachineConstantPoolEntry() const
bool isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const
Return true if this global value should be placed into small data/bss section.
Type * getVectorElementType() const
Definition: Type.h:371
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
Value * getValueOperand()
Definition: Instructions.h:409
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool isUndef() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
const GlobalValue * getGlobal() const
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:211
#define R4(n)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:957
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:856
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:382
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:391
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:264
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
An instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:530
HexagonTargetObjectFile * getObjFileLowering() const override
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Definition: Format.h:185
bool isVector() const
Return true if this is a vector value type.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const SDValue & getBasePtr() const
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:730
SDVTList getVTList() const
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
unsigned getVectorNumElements() const
ArrayRef< MVT > getHVXElementTypes() const
unsigned getStoreSizeInBits() const
Return the number of bits overwritten by a store of the specified value type.
const SDValue & getChain() const
Function Alias Analysis Results
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:732
unsigned getAlignment() const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Hexagon target-specific information for each MachineFunction.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
unsigned second
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
unsigned const TargetRegisterInfo * TRI
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
A debug info location.
Definition: DebugLoc.h:33
F(f)
Type * getStructElementType(unsigned N) const
Definition: DerivedTypes.h:365
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:970
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:580
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
An instruction for reading from memory.
Definition: Instructions.h:167
SDNode * getNode() const
get the SDNode which holds the desired result
#define R2(n)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Same for subtraction.
Definition: ISDOpcodes.h:253
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:377
unsigned int NumVTs
The address of the GOT.
Definition: ISDOpcodes.h:65
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:812
#define HEXAGON_LRFP_SIZE
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:459
FunctionType * getFunctionType() const
Definition: CallSite.h:328
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isMemLoc() const
SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, const SDLoc &DL)
Returns sum of the base pointer and offset.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:600
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1241
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:480
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:839
A description of a memory reference used in the backend.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
static Value * returnEdge(const PHINode *PN, Value *IntrBaseVal)
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Register getFrameRegister(const MachineFunction &MF) const override
Shift and rotation operations.
Definition: ISDOpcodes.h:434
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:217
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:244
Base class for LoadSDNode and StoreSDNode.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:417
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:654
const HexagonRegisterInfo * getRegisterInfo() const override
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:779
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:467
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:407
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
zlib style complession
This file implements a class to represent arbitrary precision integral constant values and operations...
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:726
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
InstrTy * getInstruction() const
Definition: CallSite.h:96
int64_t getSExtValue() const
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
static Value * getBrevLdObject(Value *V)
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1958
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:404
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:502
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:126
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:453
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:137
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:872
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
An instruction for storing to memory.
Definition: Instructions.h:320
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors...
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1878
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:778
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1043
MVT getVectorElementType() const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Class to represent pointers.
Definition: DerivedTypes.h:544
unsigned getByValSize() const
This class is used to represent ISD::STORE nodes.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:548
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:351
The memory access is volatile.
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:363
#define P(N)
const SDValue & getBasePtr() const
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
static bool isBrevLdIntrinsic(const Value *Inst)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:759
iterator_range< value_op_iterator > op_values() const
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:970
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:356
#define H(x, y, z)
Definition: MD5.cpp:57
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:40
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:844
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
#define HEXAGON_GOT_SYM_NAME
static mvt_range fp_valuetypes()
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:798
const APInt & getAPIntValue() const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:324
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:114
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
static mvt_range vector_valuetypes()
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:2088
Class to represent integer types.
Definition: DerivedTypes.h:40
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:312
Constant Vector Declarations.
Definition: Constants.h:499
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:750
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1220
IntegerType * getIntNTy(unsigned N)
Fetch the type representing an N-bit integer.
Definition: IRBuilder.h:396
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Extended Value Type.
Definition: ValueTypes.h:33
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1213
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
unsigned first
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:302
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:649
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:643
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
void dump() const
Dump this node, for debugging.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
unsigned getNumOperands() const
Definition: User.h:191
CCState - This class holds information needed while lowering arguments and return values...
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
Return true if it is profitable to reduce a load to a smaller type.
static unsigned getIntrinsicID(const SDNode *N)
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1173
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:363
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Module.h This file contains the declarations for the Module class.
const DebugLoc & getDebugLoc() const
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1050
iterator end() const
Definition: ArrayRef.h:137
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:746
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:437
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Definition: IRBuilder.h:343
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:643
Represents one node in the SelectionDAG.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:689
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static mvt_range integer_valuetypes()
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:163
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:55
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
unsigned getByValAlign() const
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
amdgpu Simplify well known AMD library false FunctionCallee Callee
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:444
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:492
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:495
bool isTailCall() const
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors...
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:336
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::ZeroOrMore, cl::init(8), cl::desc("Max #stores to inline memset"))
Flags
Flags values. These may be or&#39;d together.
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:666
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:755
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:683
SmallVector< SDValue, 32 > OutVals
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
unsigned getVectorLength() const
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
MO_GOT - Indicates a GOT-relative relocation.
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const
unsigned getTypeAlignment(MVT Ty) const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:715
SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:510
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:187
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:642
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1287
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:409
static cl::opt< int > MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memcpy"))
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:192
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...