LLVM  10.0.0svn
HexagonISelLowering.cpp
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1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that Hexagon uses to lower LLVM code
10 // into a selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonISelLowering.h"
15 #include "Hexagon.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
46 #include "llvm/IR/Value.h"
47 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/CodeGen.h"
51 #include "llvm/Support/Debug.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstddef>
59 #include <cstdint>
60 #include <limits>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-lowering"
66 
67 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
68  cl::init(true), cl::Hidden,
69  cl::desc("Control jump table emission on Hexagon target"));
70 
71 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
73  cl::desc("Enable Hexagon SDNode scheduling"));
74 
75 static cl::opt<bool> EnableFastMath("ffast-math",
77  cl::desc("Enable Fast Math processing"));
78 
79 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
81  cl::desc("Set minimum jump tables"));
82 
83 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
85  cl::desc("Max #stores to inline memcpy"));
86 
87 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
89  cl::desc("Max #stores to inline memcpy"));
90 
91 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
93  cl::desc("Max #stores to inline memmove"));
94 
95 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
97  cl::desc("Max #stores to inline memmove"));
98 
99 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
101  cl::desc("Max #stores to inline memset"));
102 
103 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
105  cl::desc("Max #stores to inline memset"));
106 
107 static cl::opt<bool> AlignLoads("hexagon-align-loads",
108  cl::Hidden, cl::init(false),
109  cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
110 
111 
112 namespace {
113 
114  class HexagonCCState : public CCState {
115  unsigned NumNamedVarArgParams = 0;
116 
117  public:
118  HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
120  unsigned NumNamedArgs)
121  : CCState(CC, IsVarArg, MF, locs, C),
122  NumNamedVarArgParams(NumNamedArgs) {}
123  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
124  };
125 
126 } // end anonymous namespace
127 
128 
129 // Implement calling convention for Hexagon.
130 
131 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
132  CCValAssign::LocInfo &LocInfo,
133  ISD::ArgFlagsTy &ArgFlags, CCState &State) {
134  static const MCPhysReg ArgRegs[] = {
135  Hexagon::R0, Hexagon::R1, Hexagon::R2,
136  Hexagon::R3, Hexagon::R4, Hexagon::R5
137  };
138  const unsigned NumArgRegs = array_lengthof(ArgRegs);
139  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
140 
141  // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
142  if (RegNum != NumArgRegs && RegNum % 2 == 1)
143  State.AllocateReg(ArgRegs[RegNum]);
144 
145  // Always return false here, as this function only makes sure that the first
146  // unallocated register has an even register number and does not actually
147  // allocate a register for the current argument.
148  return false;
149 }
150 
151 #include "HexagonGenCallingConv.inc"
152 
153 
154 SDValue
156  const {
157  return SDValue();
158 }
159 
160 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
161 /// by "Src" to address "Dst" of size "Size". Alignment information is
162 /// specified by the specific parameter attribute. The copy will be passed as
163 /// a byval function parameter. Sometimes what we are copying is the end of a
164 /// larger object, the part that does not fit in registers.
166  SDValue Chain, ISD::ArgFlagsTy Flags,
167  SelectionDAG &DAG, const SDLoc &dl) {
168  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
169  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
170  /*isVolatile=*/false, /*AlwaysInline=*/false,
171  /*isTailCall=*/false,
173 }
174 
175 bool
177  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
179  LLVMContext &Context) const {
181  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
182 
184  return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
185  return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
186 }
187 
188 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
189 // passed by value, the function prototype is modified to return void and
190 // the value is stored in memory pointed by a pointer passed by caller.
191 SDValue
193  bool IsVarArg,
195  const SmallVectorImpl<SDValue> &OutVals,
196  const SDLoc &dl, SelectionDAG &DAG) const {
197  // CCValAssign - represent the assignment of the return value to locations.
199 
200  // CCState - Info about the registers and stack slot.
201  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
202  *DAG.getContext());
203 
204  // Analyze return values of ISD::RET
205  if (Subtarget.useHVXOps())
206  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
207  else
208  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
209 
210  SDValue Flag;
211  SmallVector<SDValue, 4> RetOps(1, Chain);
212 
213  // Copy the result values into the output registers.
214  for (unsigned i = 0; i != RVLocs.size(); ++i) {
215  CCValAssign &VA = RVLocs[i];
216 
217  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
218 
219  // Guarantee that all emitted copies are stuck together with flags.
220  Flag = Chain.getValue(1);
221  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
222  }
223 
224  RetOps[0] = Chain; // Update chain.
225 
226  // Add the flag if we have it.
227  if (Flag.getNode())
228  RetOps.push_back(Flag);
229 
230  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
231 }
232 
234  // If either no tail call or told not to tail call at all, don't.
235  auto Attr =
236  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
237  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
238  return false;
239 
240  return true;
241 }
242 
243 unsigned HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
244  SelectionDAG &DAG) const {
245  // Just support r19, the linux kernel uses it.
246  unsigned Reg = StringSwitch<unsigned>(RegName)
247  .Case("r19", Hexagon::R19)
248  .Default(0);
249  if (Reg)
250  return Reg;
251 
252  report_fatal_error("Invalid register name global variable");
253 }
254 
255 /// LowerCallResult - Lower the result values of an ISD::CALL into the
256 /// appropriate copies out of appropriate physical registers. This assumes that
257 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call
258 /// being lowered. Returns a SDNode with the same number of values as the
259 /// ISD::CALL.
261  SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
262  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
264  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
265  // Assign locations to each value returned by this call.
267 
268  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
269  *DAG.getContext());
270 
271  if (Subtarget.useHVXOps())
272  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
273  else
274  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
275 
276  // Copy all of the result registers out of their specified physreg.
277  for (unsigned i = 0; i != RVLocs.size(); ++i) {
278  SDValue RetVal;
279  if (RVLocs[i].getValVT() == MVT::i1) {
280  // Return values of type MVT::i1 require special handling. The reason
281  // is that MVT::i1 is associated with the PredRegs register class, but
282  // values of that type are still returned in R0. Generate an explicit
283  // copy into a predicate register from R0, and treat the value of the
284  // predicate register as the call result.
285  auto &MRI = DAG.getMachineFunction().getRegInfo();
286  SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
287  MVT::i32, Glue);
288  // FR0 = (Value, Chain, Glue)
289  Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
290  SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
291  FR0.getValue(0), FR0.getValue(2));
292  // TPR = (Chain, Glue)
293  // Don't glue this CopyFromReg, because it copies from a virtual
294  // register. If it is glued to the call, InstrEmitter will add it
295  // as an implicit def to the call (EmitMachineNode).
296  RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
297  Glue = TPR.getValue(1);
298  Chain = TPR.getValue(0);
299  } else {
300  RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
301  RVLocs[i].getValVT(), Glue);
302  Glue = RetVal.getValue(2);
303  Chain = RetVal.getValue(1);
304  }
305  InVals.push_back(RetVal.getValue(0));
306  }
307 
308  return Chain;
309 }
310 
311 /// LowerCall - Functions arguments are copied from virtual regs to
312 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
313 SDValue
315  SmallVectorImpl<SDValue> &InVals) const {
316  SelectionDAG &DAG = CLI.DAG;
317  SDLoc &dl = CLI.DL;
319  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
321  SDValue Chain = CLI.Chain;
322  SDValue Callee = CLI.Callee;
323  CallingConv::ID CallConv = CLI.CallConv;
324  bool IsVarArg = CLI.IsVarArg;
325  bool DoesNotReturn = CLI.DoesNotReturn;
326 
327  bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
329  MachineFrameInfo &MFI = MF.getFrameInfo();
330  auto PtrVT = getPointerTy(MF.getDataLayout());
331 
332  unsigned NumParams = CLI.CS.getInstruction()
333  ? CLI.CS.getFunctionType()->getNumParams()
334  : 0;
335  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
336  Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
337 
338  // Analyze operands of the call, assigning locations to each operand.
340  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
341  NumParams);
342 
343  if (Subtarget.useHVXOps())
344  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
345  else
346  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
347 
348  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
349  if (Attr.getValueAsString() == "true")
350  CLI.IsTailCall = false;
351 
352  if (CLI.IsTailCall) {
353  bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
354  CLI.IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
355  IsVarArg, IsStructRet, StructAttrFlag, Outs,
356  OutVals, Ins, DAG);
357  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
358  CCValAssign &VA = ArgLocs[i];
359  if (VA.isMemLoc()) {
360  CLI.IsTailCall = false;
361  break;
362  }
363  }
364  LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
365  : "Argument must be passed on stack. "
366  "Not eligible for Tail Call\n"));
367  }
368  // Get a count of how many bytes are to be pushed on the stack.
369  unsigned NumBytes = CCInfo.getNextStackOffset();
371  SmallVector<SDValue, 8> MemOpChains;
372 
373  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
374  SDValue StackPtr =
375  DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
376 
377  bool NeedsArgAlign = false;
378  unsigned LargestAlignSeen = 0;
379  // Walk the register/memloc assignments, inserting copies/loads.
380  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
381  CCValAssign &VA = ArgLocs[i];
382  SDValue Arg = OutVals[i];
383  ISD::ArgFlagsTy Flags = Outs[i].Flags;
384  // Record if we need > 8 byte alignment on an argument.
385  bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
386  NeedsArgAlign |= ArgAlign;
387 
388  // Promote the value if needed.
389  switch (VA.getLocInfo()) {
390  default:
391  // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
392  llvm_unreachable("Unknown loc info!");
393  case CCValAssign::Full:
394  break;
395  case CCValAssign::BCvt:
396  Arg = DAG.getBitcast(VA.getLocVT(), Arg);
397  break;
398  case CCValAssign::SExt:
399  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
400  break;
401  case CCValAssign::ZExt:
402  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
403  break;
404  case CCValAssign::AExt:
405  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
406  break;
407  }
408 
409  if (VA.isMemLoc()) {
410  unsigned LocMemOffset = VA.getLocMemOffset();
411  SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
412  StackPtr.getValueType());
413  MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
414  if (ArgAlign)
415  LargestAlignSeen = std::max(LargestAlignSeen,
416  VA.getLocVT().getStoreSizeInBits() >> 3);
417  if (Flags.isByVal()) {
418  // The argument is a struct passed by value. According to LLVM, "Arg"
419  // is a pointer.
420  MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
421  Flags, DAG, dl));
422  } else {
424  DAG.getMachineFunction(), LocMemOffset);
425  SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
426  MemOpChains.push_back(S);
427  }
428  continue;
429  }
430 
431  // Arguments that can be passed on register must be kept at RegsToPass
432  // vector.
433  if (VA.isRegLoc())
434  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
435  }
436 
437  if (NeedsArgAlign && Subtarget.hasV60Ops()) {
438  LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
439  unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
440  LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
441  MFI.ensureMaxAlignment(LargestAlignSeen);
442  }
443  // Transform all store nodes into one single node because all store
444  // nodes are independent of each other.
445  if (!MemOpChains.empty())
446  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
447 
448  SDValue Glue;
449  if (!CLI.IsTailCall) {
450  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
451  Glue = Chain.getValue(1);
452  }
453 
454  // Build a sequence of copy-to-reg nodes chained together with token
455  // chain and flag operands which copy the outgoing args into registers.
456  // The Glue is necessary since all emitted instructions must be
457  // stuck together.
458  if (!CLI.IsTailCall) {
459  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
460  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
461  RegsToPass[i].second, Glue);
462  Glue = Chain.getValue(1);
463  }
464  } else {
465  // For tail calls lower the arguments to the 'real' stack slot.
466  //
467  // Force all the incoming stack arguments to be loaded from the stack
468  // before any new outgoing arguments are stored to the stack, because the
469  // outgoing stack slots may alias the incoming argument stack slots, and
470  // the alias isn't otherwise explicit. This is slightly more conservative
471  // than necessary, because it means that each store effectively depends
472  // on every argument instead of just those arguments it would clobber.
473  //
474  // Do not flag preceding copytoreg stuff together with the following stuff.
475  Glue = SDValue();
476  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
477  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
478  RegsToPass[i].second, Glue);
479  Glue = Chain.getValue(1);
480  }
481  Glue = SDValue();
482  }
483 
484  bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
485  unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
486 
487  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
488  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
489  // node so that legalize doesn't hack it.
490  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
491  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
492  } else if (ExternalSymbolSDNode *S =
493  dyn_cast<ExternalSymbolSDNode>(Callee)) {
494  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
495  }
496 
497  // Returns a chain & a flag for retval copy to use.
498  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
500  Ops.push_back(Chain);
501  Ops.push_back(Callee);
502 
503  // Add argument registers to the end of the list so that they are
504  // known live into the call.
505  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
506  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
507  RegsToPass[i].second.getValueType()));
508  }
509 
510  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
511  assert(Mask && "Missing call preserved mask for calling convention");
512  Ops.push_back(DAG.getRegisterMask(Mask));
513 
514  if (Glue.getNode())
515  Ops.push_back(Glue);
516 
517  if (CLI.IsTailCall) {
518  MFI.setHasTailCall();
519  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
520  }
521 
522  // Set this here because we need to know this for "hasFP" in frame lowering.
523  // The target-independent code calls getFrameRegister before setting it, and
524  // getFrameRegister uses hasFP to determine whether the function has FP.
525  MFI.setHasCalls(true);
526 
527  unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
528  Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
529  Glue = Chain.getValue(1);
530 
531  // Create the CALLSEQ_END node.
532  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
533  DAG.getIntPtrConstant(0, dl, true), Glue, dl);
534  Glue = Chain.getValue(1);
535 
536  // Handle result values, copying them out of physregs into vregs that we
537  // return.
538  return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
539  InVals, OutVals, Callee);
540 }
541 
542 /// Returns true by value, base pointer and offset pointer and addressing
543 /// mode by reference if this node can be combined with a load / store to
544 /// form a post-indexed load / store.
547  SelectionDAG &DAG) const {
549  if (!LSN)
550  return false;
551  EVT VT = LSN->getMemoryVT();
552  if (!VT.isSimple())
553  return false;
554  bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
555  VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
556  VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
557  VT == MVT::v4i16 || VT == MVT::v8i8 ||
558  Subtarget.isHVXVectorType(VT.getSimpleVT());
559  if (!IsLegalType)
560  return false;
561 
562  if (Op->getOpcode() != ISD::ADD)
563  return false;
564  Base = Op->getOperand(0);
565  Offset = Op->getOperand(1);
566  if (!isa<ConstantSDNode>(Offset.getNode()))
567  return false;
568  AM = ISD::POST_INC;
569 
570  int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
571  return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
572 }
573 
574 SDValue
577  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
578  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
579  unsigned LR = HRI.getRARegister();
580 
581  if ((Op.getOpcode() != ISD::INLINEASM &&
582  Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
583  return Op;
584 
585  unsigned NumOps = Op.getNumOperands();
586  if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
587  --NumOps; // Ignore the flag operand.
588 
589  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
590  unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
591  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
592  ++i; // Skip the ID value.
593 
594  switch (InlineAsm::getKind(Flags)) {
595  default:
596  llvm_unreachable("Bad flags!");
598  case InlineAsm::Kind_Imm:
599  case InlineAsm::Kind_Mem:
600  i += NumVals;
601  break;
605  for (; NumVals; --NumVals, ++i) {
606  unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
607  if (Reg != LR)
608  continue;
609  HMFI.setHasClobberLR(true);
610  return Op;
611  }
612  break;
613  }
614  }
615  }
616 
617  return Op;
618 }
619 
620 // Need to transform ISD::PREFETCH into something that doesn't inherit
621 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
622 // SDNPMayStore.
624  SelectionDAG &DAG) const {
625  SDValue Chain = Op.getOperand(0);
626  SDValue Addr = Op.getOperand(1);
627  // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
628  // if the "reg" is fed by an "add".
629  SDLoc DL(Op);
630  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
631  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
632 }
633 
634 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
635 // is marked as having side-effects, while the register read on Hexagon does
636 // not have any. TableGen refuses to accept the direct pattern from that node
637 // to the A4_tfrcpp.
639  SelectionDAG &DAG) const {
640  SDValue Chain = Op.getOperand(0);
641  SDLoc dl(Op);
643  return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
644 }
645 
647  SelectionDAG &DAG) const {
648  SDValue Chain = Op.getOperand(0);
649  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
650  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
651  if (IntNo == Intrinsic::hexagon_prefetch) {
652  SDValue Addr = Op.getOperand(2);
653  SDLoc DL(Op);
654  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
655  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
656  }
657  return SDValue();
658 }
659 
660 SDValue
662  SelectionDAG &DAG) const {
663  SDValue Chain = Op.getOperand(0);
664  SDValue Size = Op.getOperand(1);
665  SDValue Align = Op.getOperand(2);
666  SDLoc dl(Op);
667 
669  assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
670 
671  unsigned A = AlignConst->getSExtValue();
672  auto &HFI = *Subtarget.getFrameLowering();
673  // "Zero" means natural stack alignment.
674  if (A == 0)
675  A = HFI.getStackAlignment();
676 
677  LLVM_DEBUG({
678  dbgs () << __func__ << " Align: " << A << " Size: ";
679  Size.getNode()->dump(&DAG);
680  dbgs() << "\n";
681  });
682 
683  SDValue AC = DAG.getConstant(A, dl, MVT::i32);
685  SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
686 
687  DAG.ReplaceAllUsesOfValueWith(Op, AA);
688  return AA;
689 }
690 
692  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
693  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
694  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
696  MachineFrameInfo &MFI = MF.getFrameInfo();
698 
699  // Assign locations to all of the incoming arguments.
701  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
703 
704  if (Subtarget.useHVXOps())
705  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
706  else
707  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
708 
709  // For LLVM, in the case when returning a struct by value (>8byte),
710  // the first argument is a pointer that points to the location on caller's
711  // stack where the return value will be stored. For Hexagon, the location on
712  // caller's stack is passed only when the struct size is smaller than (and
713  // equal to) 8 bytes. If not, no address will be passed into callee and
714  // callee return the result direclty through R0/R1.
715 
716  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
717 
718  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
719  CCValAssign &VA = ArgLocs[i];
720  ISD::ArgFlagsTy Flags = Ins[i].Flags;
721  bool ByVal = Flags.isByVal();
722 
723  // Arguments passed in registers:
724  // 1. 32- and 64-bit values and HVX vectors are passed directly,
725  // 2. Large structs are passed via an address, and the address is
726  // passed in a register.
727  if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
728  llvm_unreachable("ByValSize must be bigger than 8 bytes");
729 
730  bool InReg = VA.isRegLoc() &&
731  (!ByVal || (ByVal && Flags.getByValSize() > 8));
732 
733  if (InReg) {
734  MVT RegVT = VA.getLocVT();
735  if (VA.getLocInfo() == CCValAssign::BCvt)
736  RegVT = VA.getValVT();
737 
738  const TargetRegisterClass *RC = getRegClassFor(RegVT);
739  Register VReg = MRI.createVirtualRegister(RC);
740  SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
741 
742  // Treat values of type MVT::i1 specially: they are passed in
743  // registers of type i32, but they need to remain as values of
744  // type i1 for consistency of the argument lowering.
745  if (VA.getValVT() == MVT::i1) {
746  assert(RegVT.getSizeInBits() <= 32);
747  SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
748  Copy, DAG.getConstant(1, dl, RegVT));
749  Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
750  ISD::SETNE);
751  } else {
752 #ifndef NDEBUG
753  unsigned RegSize = RegVT.getSizeInBits();
754  assert(RegSize == 32 || RegSize == 64 ||
755  Subtarget.isHVXVectorType(RegVT));
756 #endif
757  }
758  InVals.push_back(Copy);
759  MRI.addLiveIn(VA.getLocReg(), VReg);
760  } else {
761  assert(VA.isMemLoc() && "Argument should be passed in memory");
762 
763  // If it's a byval parameter, then we need to compute the
764  // "real" size, not the size of the pointer.
765  unsigned ObjSize = Flags.isByVal()
766  ? Flags.getByValSize()
767  : VA.getLocVT().getStoreSizeInBits() / 8;
768 
769  // Create the frame index object for this incoming parameter.
771  int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
772  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
773 
774  if (Flags.isByVal()) {
775  // If it's a pass-by-value aggregate, then do not dereference the stack
776  // location. Instead, we should generate a reference to the stack
777  // location.
778  InVals.push_back(FIN);
779  } else {
780  SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
782  InVals.push_back(L);
783  }
784  }
785  }
786 
787 
788  if (IsVarArg) {
789  // This will point to the next argument passed via stack.
790  int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
791  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
792  HMFI.setVarArgsFrameIndex(FI);
793  }
794 
795  return Chain;
796 }
797 
798 SDValue
800  // VASTART stores the address of the VarArgsFrameIndex slot into the
801  // memory location argument.
805  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
806  return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
807  MachinePointerInfo(SV));
808 }
809 
811  const SDLoc &dl(Op);
812  SDValue LHS = Op.getOperand(0);
813  SDValue RHS = Op.getOperand(1);
814  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
815  MVT ResTy = ty(Op);
816  MVT OpTy = ty(LHS);
817 
818  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
819  MVT ElemTy = OpTy.getVectorElementType();
820  assert(ElemTy.isScalarInteger());
822  OpTy.getVectorNumElements());
823  return DAG.getSetCC(dl, ResTy,
824  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
825  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
826  }
827 
828  // Treat all other vector types as legal.
829  if (ResTy.isVector())
830  return Op;
831 
832  // Comparisons of short integers should use sign-extend, not zero-extend,
833  // since we can represent small negative values in the compare instructions.
834  // The LLVM default is to use zero-extend arbitrarily in these cases.
835  auto isSExtFree = [this](SDValue N) {
836  switch (N.getOpcode()) {
837  case ISD::TRUNCATE: {
838  // A sign-extend of a truncate of a sign-extend is free.
839  SDValue Op = N.getOperand(0);
840  if (Op.getOpcode() != ISD::AssertSext)
841  return false;
842  EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
843  unsigned ThisBW = ty(N).getSizeInBits();
844  unsigned OrigBW = OrigTy.getSizeInBits();
845  // The type that was sign-extended to get the AssertSext must be
846  // narrower than the type of N (so that N has still the same value
847  // as the original).
848  return ThisBW >= OrigBW;
849  }
850  case ISD::LOAD:
851  // We have sign-extended loads.
852  return true;
853  }
854  return false;
855  };
856 
857  if (OpTy == MVT::i8 || OpTy == MVT::i16) {
859  bool IsNegative = C && C->getAPIntValue().isNegative();
860  if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
861  return DAG.getSetCC(dl, ResTy,
862  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32),
863  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
864  }
865 
866  return SDValue();
867 }
868 
869 SDValue
871  SDValue PredOp = Op.getOperand(0);
872  SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
873  MVT OpTy = ty(Op1);
874  const SDLoc &dl(Op);
875 
876  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
877  MVT ElemTy = OpTy.getVectorElementType();
878  assert(ElemTy.isScalarInteger());
880  OpTy.getVectorNumElements());
881  // Generate (trunc (select (_, sext, sext))).
882  return DAG.getSExtOrTrunc(
883  DAG.getSelect(dl, WideTy, PredOp,
884  DAG.getSExtOrTrunc(Op1, dl, WideTy),
885  DAG.getSExtOrTrunc(Op2, dl, WideTy)),
886  dl, OpTy);
887  }
888 
889  return SDValue();
890 }
891 
892 static Constant *convert_i1_to_i8(const Constant *ConstVal) {
894  const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
895  if (!CV)
896  return nullptr;
897 
898  LLVMContext &Ctx = ConstVal->getContext();
899  IRBuilder<> IRB(Ctx);
900  unsigned NumVectorElements = CV->getNumOperands();
901  assert(isPowerOf2_32(NumVectorElements) &&
902  "conversion only supported for pow2 VectorSize!");
903 
904  for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
905  uint8_t x = 0;
906  for (unsigned j = 0; j < 8; ++j) {
907  uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
908  x |= y << (7 - j);
909  }
910  assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!");
911  NewConst.push_back(IRB.getInt8(x));
912  }
913  return ConstantVector::get(NewConst);
914 }
915 
916 SDValue
918  EVT ValTy = Op.getValueType();
919  ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
920  Constant *CVal = nullptr;
921  bool isVTi1Type = false;
922  if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
923  Type *CValTy = ConstVal->getType();
924  if (CValTy->isVectorTy() &&
925  CValTy->getVectorElementType()->isIntegerTy(1)) {
926  CVal = convert_i1_to_i8(ConstVal);
927  isVTi1Type = (CVal != nullptr);
928  }
929  }
930  unsigned Align = CPN->getAlignment();
931  bool IsPositionIndependent = isPositionIndependent();
932  unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
933 
934  unsigned Offset = 0;
935  SDValue T;
936  if (CPN->isMachineConstantPoolEntry())
937  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
938  TF);
939  else if (isVTi1Type)
940  T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
941  else
942  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset, TF);
943 
944  assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
945  "Inconsistent target flag encountered");
946 
947  if (IsPositionIndependent)
948  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
949  return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
950 }
951 
952 SDValue
954  EVT VT = Op.getValueType();
955  int Idx = cast<JumpTableSDNode>(Op)->getIndex();
956  if (isPositionIndependent()) {
958  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
959  }
960 
961  SDValue T = DAG.getTargetJumpTable(Idx, VT);
962  return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
963 }
964 
965 SDValue
967  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
969  MachineFrameInfo &MFI = MF.getFrameInfo();
970  MFI.setReturnAddressIsTaken(true);
971 
972  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
973  return SDValue();
974 
975  EVT VT = Op.getValueType();
976  SDLoc dl(Op);
977  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
978  if (Depth) {
979  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
980  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
981  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
982  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
984  }
985 
986  // Return LR, which contains the return address. Mark it an implicit live-in.
987  unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
988  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
989 }
990 
991 SDValue
993  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
995  MFI.setFrameAddressIsTaken(true);
996 
997  EVT VT = Op.getValueType();
998  SDLoc dl(Op);
999  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1000  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1001  HRI.getFrameRegister(), VT);
1002  while (Depth--)
1003  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1004  MachinePointerInfo());
1005  return FrameAddr;
1006 }
1007 
1008 SDValue
1010  SDLoc dl(Op);
1011  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1012 }
1013 
1014 SDValue
1016  SDLoc dl(Op);
1017  auto *GAN = cast<GlobalAddressSDNode>(Op);
1018  auto PtrVT = getPointerTy(DAG.getDataLayout());
1019  auto *GV = GAN->getGlobal();
1020  int64_t Offset = GAN->getOffset();
1021 
1022  auto &HLOF = *HTM.getObjFileLowering();
1023  Reloc::Model RM = HTM.getRelocationModel();
1024 
1025  if (RM == Reloc::Static) {
1026  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1027  const GlobalObject *GO = GV->getBaseObject();
1028  if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1029  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1030  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1031  }
1032 
1033  bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1034  if (UsePCRel) {
1035  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1037  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1038  }
1039 
1040  // Use GOT index.
1041  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1042  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1043  SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1044  return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1045 }
1046 
1047 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1048 SDValue
1050  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1051  SDLoc dl(Op);
1052  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1053 
1054  Reloc::Model RM = HTM.getRelocationModel();
1055  if (RM == Reloc::Static) {
1056  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1057  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1058  }
1059 
1060  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1061  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1062 }
1063 
1064 SDValue
1066  const {
1067  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1070  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1071 }
1072 
1073 SDValue
1075  GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1076  unsigned char OperandFlags) const {
1077  MachineFunction &MF = DAG.getMachineFunction();
1078  MachineFrameInfo &MFI = MF.getFrameInfo();
1079  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1080  SDLoc dl(GA);
1081  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1082  GA->getValueType(0),
1083  GA->getOffset(),
1084  OperandFlags);
1085  // Create Operands for the call.The Operands should have the following:
1086  // 1. Chain SDValue
1087  // 2. Callee which in this case is the Global address value.
1088  // 3. Registers live into the call.In this case its R0, as we
1089  // have just one argument to be passed.
1090  // 4. Glue.
1091  // Note: The order is important.
1092 
1093  const auto &HRI = *Subtarget.getRegisterInfo();
1094  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1095  assert(Mask && "Missing call preserved mask for calling convention");
1096  SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1097  DAG.getRegisterMask(Mask), Glue };
1098  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1099 
1100  // Inform MFI that function has calls.
1101  MFI.setAdjustsStack(true);
1102 
1103  Glue = Chain.getValue(1);
1104  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1105 }
1106 
1107 //
1108 // Lower using the intial executable model for TLS addresses
1109 //
1110 SDValue
1112  SelectionDAG &DAG) const {
1113  SDLoc dl(GA);
1114  int64_t Offset = GA->getOffset();
1115  auto PtrVT = getPointerTy(DAG.getDataLayout());
1116 
1117  // Get the thread pointer.
1118  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1119 
1120  bool IsPositionIndependent = isPositionIndependent();
1121  unsigned char TF =
1122  IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1123 
1124  // First generate the TLS symbol address
1125  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1126  Offset, TF);
1127 
1128  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1129 
1130  if (IsPositionIndependent) {
1131  // Generate the GOT pointer in case of position independent code
1132  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1133 
1134  // Add the TLS Symbol address to GOT pointer.This gives
1135  // GOT relative relocation for the symbol.
1136  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1137  }
1138 
1139  // Load the offset value for TLS symbol.This offset is relative to
1140  // thread pointer.
1141  SDValue LoadOffset =
1142  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1143 
1144  // Address of the thread local variable is the add of thread
1145  // pointer and the offset of the variable.
1146  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1147 }
1148 
1149 //
1150 // Lower using the local executable model for TLS addresses
1151 //
1152 SDValue
1154  SelectionDAG &DAG) const {
1155  SDLoc dl(GA);
1156  int64_t Offset = GA->getOffset();
1157  auto PtrVT = getPointerTy(DAG.getDataLayout());
1158 
1159  // Get the thread pointer.
1160  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1161  // Generate the TLS symbol address
1162  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1164  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1165 
1166  // Address of the thread local variable is the add of thread
1167  // pointer and the offset of the variable.
1168  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1169 }
1170 
1171 //
1172 // Lower using the general dynamic model for TLS addresses
1173 //
1174 SDValue
1176  SelectionDAG &DAG) const {
1177  SDLoc dl(GA);
1178  int64_t Offset = GA->getOffset();
1179  auto PtrVT = getPointerTy(DAG.getDataLayout());
1180 
1181  // First generate the TLS symbol address
1182  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1184 
1185  // Then, generate the GOT pointer
1186  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1187 
1188  // Add the TLS symbol and the GOT pointer
1189  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1190  SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1191 
1192  // Copy over the argument to R0
1193  SDValue InFlag;
1194  Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1195  InFlag = Chain.getValue(1);
1196 
1197  unsigned Flags =
1198  static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1201 
1202  return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1203  Hexagon::R0, Flags);
1204 }
1205 
1206 //
1207 // Lower TLS addresses.
1208 //
1209 // For now for dynamic models, we only support the general dynamic model.
1210 //
1211 SDValue
1213  SelectionDAG &DAG) const {
1214  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1215 
1216  switch (HTM.getTLSModel(GA->getGlobal())) {
1219  return LowerToTLSGeneralDynamicModel(GA, DAG);
1220  case TLSModel::InitialExec:
1221  return LowerToTLSInitialExecModel(GA, DAG);
1222  case TLSModel::LocalExec:
1223  return LowerToTLSLocalExecModel(GA, DAG);
1224  }
1225  llvm_unreachable("Bogus TLS model");
1226 }
1227 
1228 //===----------------------------------------------------------------------===//
1229 // TargetLowering Implementation
1230 //===----------------------------------------------------------------------===//
1231 
1233  const HexagonSubtarget &ST)
1234  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1235  Subtarget(ST) {
1236  auto &HRI = *Subtarget.getRegisterInfo();
1237 
1241  setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1244 
1247 
1250  else
1252 
1253  // Limits for inline expansion of memcpy/memmove
1260 
1261  //
1262  // Set up register classes.
1263  //
1264 
1265  addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1266  addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1267  addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1268  addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1269  addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1270  addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1271  addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1272  addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1273  addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1274  addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1275  addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1276 
1277  addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1278  addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1279 
1280  //
1281  // Handling of scalar operations.
1282  //
1283  // All operations default to "legal", except:
1284  // - indexed loads and stores (pre-/post-incremented),
1285  // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1286  // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1287  // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1288  // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1289  // which default to "expand" for at least one type.
1290 
1291  // Misc operations.
1308 
1309  // Custom legalize GlobalAddress nodes into CONST32.
1313 
1314  // Hexagon needs to optimize cases with negative constants.
1319 
1320  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1325 
1329 
1330  if (EmitJumpTables)
1332  else
1335 
1338 
1339  // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
1340  // but they only operate on i64.
1341  for (MVT VT : MVT::integer_valuetypes()) {
1348  }
1351 
1356 
1357  // Popcount can count # of 1s in i64 but returns i32.
1362 
1367 
1372 
1373  for (unsigned IntExpOp :
1378  for (MVT VT : MVT::integer_valuetypes())
1379  setOperationAction(IntExpOp, VT, Expand);
1380  }
1381 
1382  for (unsigned FPExpOp :
1385  for (MVT VT : MVT::fp_valuetypes())
1386  setOperationAction(FPExpOp, VT, Expand);
1387  }
1388 
1389  // No extending loads from i32.
1390  for (MVT VT : MVT::integer_valuetypes()) {
1394  }
1395  // Turn FP truncstore into trunc + store.
1397  // Turn FP extload into load/fpextend.
1398  for (MVT VT : MVT::fp_valuetypes())
1400 
1401  // Expand BR_CC and SELECT_CC for all integer and fp types.
1402  for (MVT VT : MVT::integer_valuetypes()) {
1405  }
1406  for (MVT VT : MVT::fp_valuetypes()) {
1409  }
1411 
1412  //
1413  // Handling of vector operations.
1414  //
1415 
1416  // Set the action for vector operations to "expand", then override it with
1417  // either "custom" or "legal" for specific cases.
1418  static const unsigned VectExpOps[] = {
1419  // Integer arithmetic:
1423  // Logical/bit:
1426  // Floating point arithmetic/math functions:
1433  // Misc:
1435  // Vector:
1440  };
1441 
1442  for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1443  for (unsigned VectExpOp : VectExpOps)
1444  setOperationAction(VectExpOp, VT, Expand);
1445 
1446  // Expand all extending loads and truncating stores:
1447  for (MVT TargetVT : MVT::fixedlen_vector_valuetypes()) {
1448  if (TargetVT == VT)
1449  continue;
1450  setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1451  setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1452  setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1453  setTruncStoreAction(VT, TargetVT, Expand);
1454  }
1455 
1456  // Normalize all inputs to SELECT to be vectors of i32.
1457  if (VT.getVectorElementType() != MVT::i32) {
1458  MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1460  AddPromotedToType(ISD::SELECT, VT, VT32);
1461  }
1465  }
1466 
1467  // Extending loads from (native) vectors of i8 into (native) vectors of i16
1468  // are legal.
1475 
1476  // Types natively supported:
1477  for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1485 
1486  setOperationAction(ISD::ADD, NativeVT, Legal);
1487  setOperationAction(ISD::SUB, NativeVT, Legal);
1488  setOperationAction(ISD::MUL, NativeVT, Legal);
1489  setOperationAction(ISD::AND, NativeVT, Legal);
1490  setOperationAction(ISD::OR, NativeVT, Legal);
1491  setOperationAction(ISD::XOR, NativeVT, Legal);
1492  }
1493 
1494  // Custom lower unaligned loads.
1495  // Also, for both loads and stores, verify the alignment of the address
1496  // in case it is a compile-time constant. This is a usability feature to
1497  // provide a meaningful error message to users.
1502  }
1503 
1505  MVT::v2i32}) {
1513  }
1514 
1515  // Custom-lower bitcasts from i8 to v8i1.
1520  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1521  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1522  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1523 
1524  // V5+.
1529 
1532 
1545 
1546  // Handling of indexed loads/stores: default is "expand".
1547  //
1552  }
1553 
1554  // Subtarget-specific operation actions.
1555  //
1556  if (Subtarget.hasV60Ops()) {
1561  }
1562  if (Subtarget.hasV66Ops()) {
1565  }
1566 
1568 
1569  if (Subtarget.useHVXOps())
1570  initializeHVXLowering();
1571 
1573 
1574  //
1575  // Library calls for unsupported operations
1576  //
1577  bool FastMath = EnableFastMath;
1578 
1579  setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1580  setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1581  setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1582  setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1583  setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1584  setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1585  setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1586  setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1587 
1588  setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1589  setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1590  setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1591  setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1592  setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1593  setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1594 
1595  // This is the only fast library function for sqrtd.
1596  if (FastMath)
1597  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1598 
1599  // Prefix is: nothing for "slow-math",
1600  // "fast2_" for V5+ fast-math double-precision
1601  // (actually, keep fast-math and fast-math2 separate for now)
1602  if (FastMath) {
1603  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1604  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1605  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1606  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1607  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1608  } else {
1609  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1610  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1611  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1612  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1613  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1614  }
1615 
1616  if (FastMath)
1617  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1618  else
1619  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1620 
1621  // These cause problems when the shift amount is non-constant.
1622  setLibcallName(RTLIB::SHL_I128, nullptr);
1623  setLibcallName(RTLIB::SRL_I128, nullptr);
1624  setLibcallName(RTLIB::SRA_I128, nullptr);
1625 }
1626 
1627 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1628  switch ((HexagonISD::NodeType)Opcode) {
1629  case HexagonISD::ADDC: return "HexagonISD::ADDC";
1630  case HexagonISD::SUBC: return "HexagonISD::SUBC";
1631  case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1632  case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1633  case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1634  case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1635  case HexagonISD::CALL: return "HexagonISD::CALL";
1636  case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1637  case HexagonISD::CALLR: return "HexagonISD::CALLR";
1638  case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1639  case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1640  case HexagonISD::CONST32: return "HexagonISD::CONST32";
1641  case HexagonISD::CP: return "HexagonISD::CP";
1642  case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1643  case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1644  case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1645  case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1646  case HexagonISD::INSERT: return "HexagonISD::INSERT";
1647  case HexagonISD::JT: return "HexagonISD::JT";
1648  case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1649  case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1650  case HexagonISD::VASL: return "HexagonISD::VASL";
1651  case HexagonISD::VASR: return "HexagonISD::VASR";
1652  case HexagonISD::VLSR: return "HexagonISD::VLSR";
1653  case HexagonISD::VSPLAT: return "HexagonISD::VSPLAT";
1654  case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1655  case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1656  case HexagonISD::VROR: return "HexagonISD::VROR";
1657  case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1658  case HexagonISD::PTRUE: return "HexagonISD::PTRUE";
1659  case HexagonISD::PFALSE: return "HexagonISD::PFALSE";
1660  case HexagonISD::VZERO: return "HexagonISD::VZERO";
1661  case HexagonISD::VSPLATW: return "HexagonISD::VSPLATW";
1662  case HexagonISD::D2P: return "HexagonISD::D2P";
1663  case HexagonISD::P2D: return "HexagonISD::P2D";
1664  case HexagonISD::V2Q: return "HexagonISD::V2Q";
1665  case HexagonISD::Q2V: return "HexagonISD::Q2V";
1666  case HexagonISD::QCAT: return "HexagonISD::QCAT";
1667  case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1668  case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1669  case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1670  case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1671  case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1672  case HexagonISD::OP_END: break;
1673  }
1674  return nullptr;
1675 }
1676 
1677 void
1678 HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
1679  unsigned NeedAlign) const {
1680  auto *CA = dyn_cast<ConstantSDNode>(Ptr);
1681  if (!CA)
1682  return;
1683  unsigned Addr = CA->getZExtValue();
1684  unsigned HaveAlign = Addr != 0 ? 1u << countTrailingZeros(Addr) : NeedAlign;
1685  if (HaveAlign < NeedAlign) {
1686  std::string ErrMsg;
1687  raw_string_ostream O(ErrMsg);
1688  O << "Misaligned constant address: " << format_hex(Addr, 10)
1689  << " has alignment " << HaveAlign
1690  << ", but the memory access requires " << NeedAlign;
1691  if (DebugLoc DL = dl.getDebugLoc())
1692  DL.print(O << ", at ");
1693  report_fatal_error(O.str());
1694  }
1695 }
1696 
1697 // Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
1698 // intrinsic.
1699 static bool isBrevLdIntrinsic(const Value *Inst) {
1700  unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
1701  return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
1702  ID == Intrinsic::hexagon_L2_loadri_pbr ||
1703  ID == Intrinsic::hexagon_L2_loadrh_pbr ||
1704  ID == Intrinsic::hexagon_L2_loadruh_pbr ||
1705  ID == Intrinsic::hexagon_L2_loadrb_pbr ||
1706  ID == Intrinsic::hexagon_L2_loadrub_pbr);
1707 }
1708 
1709 // Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
1710 // instruction. So far we only handle bitcast, extract value and bit reverse
1711 // load intrinsic instructions. Should we handle CGEP ?
1713  if (Operator::getOpcode(V) == Instruction::ExtractValue ||
1714  Operator::getOpcode(V) == Instruction::BitCast)
1715  V = cast<Operator>(V)->getOperand(0);
1716  else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
1717  V = cast<Instruction>(V)->getOperand(0);
1718  return V;
1719 }
1720 
1721 // Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
1722 // a back edge. If the back edge comes from the intrinsic itself, the incoming
1723 // edge is returned.
1724 static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
1725  const BasicBlock *Parent = PN->getParent();
1726  int Idx = -1;
1727  for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
1728  BasicBlock *Blk = PN->getIncomingBlock(i);
1729  // Determine if the back edge is originated from intrinsic.
1730  if (Blk == Parent) {
1731  Value *BackEdgeVal = PN->getIncomingValue(i);
1732  Value *BaseVal;
1733  // Loop over till we return the same Value or we hit the IntrBaseVal.
1734  do {
1735  BaseVal = BackEdgeVal;
1736  BackEdgeVal = getBrevLdObject(BackEdgeVal);
1737  } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
1738  // If the getBrevLdObject returns IntrBaseVal, we should return the
1739  // incoming edge.
1740  if (IntrBaseVal == BackEdgeVal)
1741  continue;
1742  Idx = i;
1743  break;
1744  } else // Set the node to incoming edge.
1745  Idx = i;
1746  }
1747  assert(Idx >= 0 && "Unexpected index to incoming argument in PHI");
1748  return PN->getIncomingValue(Idx);
1749 }
1750 
1751 // Bit-reverse Load Intrinsic: Figure out the underlying object the base
1752 // pointer points to, for the bit-reverse load intrinsic. Setting this to
1753 // memoperand might help alias analysis to figure out the dependencies.
1755  Value *IntrBaseVal = V;
1756  Value *BaseVal;
1757  // Loop over till we return the same Value, implies we either figure out
1758  // the object or we hit a PHI
1759  do {
1760  BaseVal = V;
1761  V = getBrevLdObject(V);
1762  } while (BaseVal != V);
1763 
1764  // Identify the object from PHINode.
1765  if (const PHINode *PN = dyn_cast<PHINode>(V))
1766  return returnEdge(PN, IntrBaseVal);
1767  // For non PHI nodes, the object is the last value returned by getBrevLdObject
1768  else
1769  return V;
1770 }
1771 
1772 /// Given an intrinsic, checks if on the target the intrinsic will need to map
1773 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1774 /// true and store the intrinsic information into the IntrinsicInfo that was
1775 /// passed to the function.
1777  const CallInst &I,
1778  MachineFunction &MF,
1779  unsigned Intrinsic) const {
1780  switch (Intrinsic) {
1781  case Intrinsic::hexagon_L2_loadrd_pbr:
1782  case Intrinsic::hexagon_L2_loadri_pbr:
1783  case Intrinsic::hexagon_L2_loadrh_pbr:
1784  case Intrinsic::hexagon_L2_loadruh_pbr:
1785  case Intrinsic::hexagon_L2_loadrb_pbr:
1786  case Intrinsic::hexagon_L2_loadrub_pbr: {
1787  Info.opc = ISD::INTRINSIC_W_CHAIN;
1788  auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
1789  auto &Cont = I.getCalledFunction()->getParent()->getContext();
1790  // The intrinsic function call is of the form { ElTy, i8* }
1791  // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
1792  // should be derived from ElTy.
1794  Info.memVT = MVT::getVT(ElTy);
1795  llvm::Value *BasePtrVal = I.getOperand(0);
1796  Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
1797  // The offset value comes through Modifier register. For now, assume the
1798  // offset is 0.
1799  Info.offset = 0;
1800  Info.align =
1801  MaybeAlign(DL.getABITypeAlignment(Info.memVT.getTypeForEVT(Cont)));
1803  return true;
1804  }
1805  case Intrinsic::hexagon_V6_vgathermw:
1806  case Intrinsic::hexagon_V6_vgathermw_128B:
1807  case Intrinsic::hexagon_V6_vgathermh:
1808  case Intrinsic::hexagon_V6_vgathermh_128B:
1809  case Intrinsic::hexagon_V6_vgathermhw:
1810  case Intrinsic::hexagon_V6_vgathermhw_128B:
1811  case Intrinsic::hexagon_V6_vgathermwq:
1812  case Intrinsic::hexagon_V6_vgathermwq_128B:
1813  case Intrinsic::hexagon_V6_vgathermhq:
1814  case Intrinsic::hexagon_V6_vgathermhq_128B:
1815  case Intrinsic::hexagon_V6_vgathermhwq:
1816  case Intrinsic::hexagon_V6_vgathermhwq_128B: {
1817  const Module &M = *I.getParent()->getParent()->getParent();
1818  Info.opc = ISD::INTRINSIC_W_CHAIN;
1819  Type *VecTy = I.getArgOperand(1)->getType();
1820  Info.memVT = MVT::getVT(VecTy);
1821  Info.ptrVal = I.getArgOperand(0);
1822  Info.offset = 0;
1823  Info.align =
1828  return true;
1829  }
1830  default:
1831  break;
1832  }
1833  return false;
1834 }
1835 
1837  return X.getValueType().isScalarInteger(); // 'tstbit'
1838 }
1839 
1841  return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
1842 }
1843 
1845  if (!VT1.isSimple() || !VT2.isSimple())
1846  return false;
1847  return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1848 }
1849 
1851  return isOperationLegalOrCustom(ISD::FMA, VT);
1852 }
1853 
1854 // Should we expand the build vector with shuffles?
1856  unsigned DefinedValues) const {
1857  return false;
1858 }
1859 
1861  EVT VT) const {
1862  return true;
1863 }
1864 
1867  if (VT.getVectorNumElements() == 1 || VT.isScalableVector())
1869 
1870  // Always widen vectors of i1.
1871  MVT ElemTy = VT.getVectorElementType();
1872  if (ElemTy == MVT::i1)
1874 
1875  if (Subtarget.useHVXOps()) {
1876  // If the size of VT is at least half of the vector length,
1877  // widen the vector. Note: the threshold was not selected in
1878  // any scientific way.
1879  ArrayRef<MVT> Tys = Subtarget.getHVXElementTypes();
1880  if (llvm::find(Tys, ElemTy) != Tys.end()) {
1881  unsigned HwWidth = 8*Subtarget.getVectorLength();
1882  unsigned VecWidth = VT.getSizeInBits();
1883  if (VecWidth >= HwWidth/2 && VecWidth < HwWidth)
1885  }
1886  }
1888 }
1889 
1890 std::pair<SDValue, int>
1891 HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
1892  if (Addr.getOpcode() == ISD::ADD) {
1893  SDValue Op1 = Addr.getOperand(1);
1894  if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
1895  return { Addr.getOperand(0), CN->getSExtValue() };
1896  }
1897  return { Addr, 0 };
1898 }
1899 
1900 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
1901 // to select data from, V3 is the permutation.
1902 SDValue
1904  const {
1905  const auto *SVN = cast<ShuffleVectorSDNode>(Op);
1906  ArrayRef<int> AM = SVN->getMask();
1907  assert(AM.size() <= 8 && "Unexpected shuffle mask");
1908  unsigned VecLen = AM.size();
1909 
1910  MVT VecTy = ty(Op);
1911  assert(!Subtarget.isHVXVectorType(VecTy, true) &&
1912  "HVX shuffles should be legal");
1913  assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length");
1914 
1915  SDValue Op0 = Op.getOperand(0);
1916  SDValue Op1 = Op.getOperand(1);
1917  const SDLoc &dl(Op);
1918 
1919  // If the inputs are not the same as the output, bail. This is not an
1920  // error situation, but complicates the handling and the default expansion
1921  // (into BUILD_VECTOR) should be adequate.
1922  if (ty(Op0) != VecTy || ty(Op1) != VecTy)
1923  return SDValue();
1924 
1925  // Normalize the mask so that the first non-negative index comes from
1926  // the first operand.
1927  SmallVector<int,8> Mask(AM.begin(), AM.end());
1928  unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
1929  if (F == AM.size())
1930  return DAG.getUNDEF(VecTy);
1931  if (AM[F] >= int(VecLen)) {
1933  std::swap(Op0, Op1);
1934  }
1935 
1936  // Express the shuffle mask in terms of bytes.
1937  SmallVector<int,8> ByteMask;
1938  unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
1939  for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
1940  int M = Mask[i];
1941  if (M < 0) {
1942  for (unsigned j = 0; j != ElemBytes; ++j)
1943  ByteMask.push_back(-1);
1944  } else {
1945  for (unsigned j = 0; j != ElemBytes; ++j)
1946  ByteMask.push_back(M*ElemBytes + j);
1947  }
1948  }
1949  assert(ByteMask.size() <= 8);
1950 
1951  // All non-undef (non-negative) indexes are well within [0..127], so they
1952  // fit in a single byte. Build two 64-bit words:
1953  // - MaskIdx where each byte is the corresponding index (for non-negative
1954  // indexes), and 0xFF for negative indexes, and
1955  // - MaskUnd that has 0xFF for each negative index.
1956  uint64_t MaskIdx = 0;
1957  uint64_t MaskUnd = 0;
1958  for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
1959  unsigned S = 8*i;
1960  uint64_t M = ByteMask[i] & 0xFF;
1961  if (M == 0xFF)
1962  MaskUnd |= M << S;
1963  MaskIdx |= M << S;
1964  }
1965 
1966  if (ByteMask.size() == 4) {
1967  // Identity.
1968  if (MaskIdx == (0x03020100 | MaskUnd))
1969  return Op0;
1970  // Byte swap.
1971  if (MaskIdx == (0x00010203 | MaskUnd)) {
1972  SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
1973  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
1974  return DAG.getBitcast(VecTy, T1);
1975  }
1976 
1977  // Byte packs.
1978  SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
1979  typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
1980  if (MaskIdx == (0x06040200 | MaskUnd))
1981  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
1982  if (MaskIdx == (0x07050301 | MaskUnd))
1983  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
1984 
1985  SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
1986  typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
1987  if (MaskIdx == (0x02000604 | MaskUnd))
1988  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
1989  if (MaskIdx == (0x03010705 | MaskUnd))
1990  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
1991  }
1992 
1993  if (ByteMask.size() == 8) {
1994  // Identity.
1995  if (MaskIdx == (0x0706050403020100ull | MaskUnd))
1996  return Op0;
1997  // Byte swap.
1998  if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
1999  SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
2000  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
2001  return DAG.getBitcast(VecTy, T1);
2002  }
2003 
2004  // Halfword picks.
2005  if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
2006  return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2007  if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
2008  return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2009  if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
2010  return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2011  if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
2012  return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2013  if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
2014  VectorPair P = opSplit(Op0, dl, DAG);
2015  return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
2016  }
2017 
2018  // Byte packs.
2019  if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2020  return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2021  if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2022  return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2023  }
2024 
2025  return SDValue();
2026 }
2027 
2028 // Create a Hexagon-specific node for shifting a vector by an integer.
2029 SDValue
2030 HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
2031  const {
2032  if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) {
2033  if (SDValue S = BVN->getSplatValue()) {
2034  unsigned NewOpc;
2035  switch (Op.getOpcode()) {
2036  case ISD::SHL:
2037  NewOpc = HexagonISD::VASL;
2038  break;
2039  case ISD::SRA:
2040  NewOpc = HexagonISD::VASR;
2041  break;
2042  case ISD::SRL:
2043  NewOpc = HexagonISD::VLSR;
2044  break;
2045  default:
2046  llvm_unreachable("Unexpected shift opcode");
2047  }
2048  return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), S);
2049  }
2050  }
2051 
2052  return SDValue();
2053 }
2054 
2055 SDValue
2057  return getVectorShiftByInt(Op, DAG);
2058 }
2059 
2060 SDValue
2062  if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
2063  return Op;
2064  return SDValue();
2065 }
2066 
2067 SDValue
2069  MVT ResTy = ty(Op);
2070  SDValue InpV = Op.getOperand(0);
2071  MVT InpTy = ty(InpV);
2072  assert(ResTy.getSizeInBits() == InpTy.getSizeInBits());
2073  const SDLoc &dl(Op);
2074 
2075  // Handle conversion from i8 to v8i1.
2076  if (ResTy == MVT::v8i1) {
2077  SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
2078  SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
2079  return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2080  }
2081 
2082  return SDValue();
2083 }
2084 
2085 bool
2086 HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
2087  MVT VecTy, SelectionDAG &DAG,
2088  MutableArrayRef<ConstantInt*> Consts) const {
2089  MVT ElemTy = VecTy.getVectorElementType();
2090  unsigned ElemWidth = ElemTy.getSizeInBits();
2091  IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
2092  bool AllConst = true;
2093 
2094  for (unsigned i = 0, e = Values.size(); i != e; ++i) {
2095  SDValue V = Values[i];
2096  if (V.isUndef()) {
2097  Consts[i] = ConstantInt::get(IntTy, 0);
2098  continue;
2099  }
2100  // Make sure to always cast to IntTy.
2101  if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2102  const ConstantInt *CI = CN->getConstantIntValue();
2103  Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2104  } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
2105  const ConstantFP *CF = CN->getConstantFPValue();
2106  APInt A = CF->getValueAPF().bitcastToAPInt();
2107  Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
2108  } else {
2109  AllConst = false;
2110  }
2111  }
2112  return AllConst;
2113 }
2114 
2115 SDValue
2116 HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
2117  MVT VecTy, SelectionDAG &DAG) const {
2118  MVT ElemTy = VecTy.getVectorElementType();
2119  assert(VecTy.getVectorNumElements() == Elem.size());
2120 
2121  SmallVector<ConstantInt*,4> Consts(Elem.size());
2122  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2123 
2124  unsigned First, Num = Elem.size();
2125  for (First = 0; First != Num; ++First)
2126  if (!isUndef(Elem[First]))
2127  break;
2128  if (First == Num)
2129  return DAG.getUNDEF(VecTy);
2130 
2131  if (AllConst &&
2132  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2133  return getZero(dl, VecTy, DAG);
2134 
2135  if (ElemTy == MVT::i16) {
2136  assert(Elem.size() == 2);
2137  if (AllConst) {
2138  uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2139  Consts[1]->getZExtValue() << 16;
2140  return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
2141  }
2142  SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
2143  {Elem[1], Elem[0]}, DAG);
2144  return DAG.getBitcast(MVT::v2i16, N);
2145  }
2146 
2147  if (ElemTy == MVT::i8) {
2148  // First try generating a constant.
2149  if (AllConst) {
2150  int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2151  (Consts[1]->getZExtValue() & 0xFF) << 8 |
2152  (Consts[1]->getZExtValue() & 0xFF) << 16 |
2153  Consts[2]->getZExtValue() << 24;
2154  return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2155  }
2156 
2157  // Then try splat.
2158  bool IsSplat = true;
2159  for (unsigned i = 0; i != Num; ++i) {
2160  if (i == First)
2161  continue;
2162  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2163  continue;
2164  IsSplat = false;
2165  break;
2166  }
2167  if (IsSplat) {
2168  // Legalize the operand to VSPLAT.
2169  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2170  return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2171  }
2172 
2173  // Generate
2174  // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
2175  // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
2176  assert(Elem.size() == 4);
2177  SDValue Vs[4];
2178  for (unsigned i = 0; i != 4; ++i) {
2179  Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2180  Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2181  }
2182  SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
2183  SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2184  SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2185  SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2186  SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2187 
2188  SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2189  return DAG.getBitcast(MVT::v4i8, R);
2190  }
2191 
2192 #ifndef NDEBUG
2193  dbgs() << "VecTy: " << EVT(VecTy).getEVTString() << '\n';
2194 #endif
2195  llvm_unreachable("Unexpected vector element type");
2196 }
2197 
2198 SDValue
2199 HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
2200  MVT VecTy, SelectionDAG &DAG) const {
2201  MVT ElemTy = VecTy.getVectorElementType();
2202  assert(VecTy.getVectorNumElements() == Elem.size());
2203 
2204  SmallVector<ConstantInt*,8> Consts(Elem.size());
2205  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2206 
2207  unsigned First, Num = Elem.size();
2208  for (First = 0; First != Num; ++First)
2209  if (!isUndef(Elem[First]))
2210  break;
2211  if (First == Num)
2212  return DAG.getUNDEF(VecTy);
2213 
2214  if (AllConst &&
2215  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2216  return getZero(dl, VecTy, DAG);
2217 
2218  // First try splat if possible.
2219  if (ElemTy == MVT::i16) {
2220  bool IsSplat = true;
2221  for (unsigned i = 0; i != Num; ++i) {
2222  if (i == First)
2223  continue;
2224  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2225  continue;
2226  IsSplat = false;
2227  break;
2228  }
2229  if (IsSplat) {
2230  // Legalize the operand to VSPLAT.
2231  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2232  return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2233  }
2234  }
2235 
2236  // Then try constant.
2237  if (AllConst) {
2238  uint64_t Val = 0;
2239  unsigned W = ElemTy.getSizeInBits();
2240  uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
2241  : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
2242  for (unsigned i = 0; i != Num; ++i)
2243  Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2244  SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2245  return DAG.getBitcast(VecTy, V0);
2246  }
2247 
2248  // Build two 32-bit vectors and concatenate.
2249  MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2250  SDValue L = (ElemTy == MVT::i32)
2251  ? Elem[0]
2252  : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2253  SDValue H = (ElemTy == MVT::i32)
2254  ? Elem[1]
2255  : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
2256  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
2257 }
2258 
2259 SDValue
2260 HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
2261  const SDLoc &dl, MVT ValTy, MVT ResTy,
2262  SelectionDAG &DAG) const {
2263  MVT VecTy = ty(VecV);
2264  assert(!ValTy.isVector() ||
2265  VecTy.getVectorElementType() == ValTy.getVectorElementType());
2266  unsigned VecWidth = VecTy.getSizeInBits();
2267  unsigned ValWidth = ValTy.getSizeInBits();
2268  unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
2269  assert((VecWidth % ElemWidth) == 0);
2270  auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);
2271 
2272  // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2273  // without any coprocessors).
2274  if (ElemWidth == 1) {
2275  assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure");
2276  assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2277  // Check if this is an extract of the lowest bit.
2278  if (IdxN) {
2279  // Extracting the lowest bit is a no-op, but it changes the type,
2280  // so it must be kept as an operation to avoid errors related to
2281  // type mismatches.
2282  if (IdxN->isNullValue() && ValTy.getSizeInBits() == 1)
2283  return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
2284  }
2285 
2286  // If the value extracted is a single bit, use tstbit.
2287  if (ValWidth == 1) {
2288  SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2289  SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
2290  SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2291  return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
2292  }
2293 
2294  // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2295  // a predicate register. The elements of the vector are repeated
2296  // in the register (if necessary) so that the total number is 8.
2297  // The extracted subvector will need to be expanded in such a way.
2298  unsigned Scale = VecWidth / ValWidth;
2299 
2300  // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
2301  // position 0.
2302  assert(ty(IdxV) == MVT::i32);
2303  unsigned VecRep = 8 / VecWidth;
2304  SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2305  DAG.getConstant(8*VecRep, dl, MVT::i32));
2306  SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2307  SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2308  while (Scale > 1) {
2309  // The longest possible subvector is at most 32 bits, so it is always
2310  // contained in the low subregister.
2311  T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
2312  T1 = expandPredicate(T1, dl, DAG);
2313  Scale /= 2;
2314  }
2315 
2316  return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
2317  }
2318 
2319  assert(VecWidth == 32 || VecWidth == 64);
2320 
2321  // Cast everything to scalar integer types.
2322  MVT ScalarTy = tyScalar(VecTy);
2323  VecV = DAG.getBitcast(ScalarTy, VecV);
2324 
2325  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2326  SDValue ExtV;
2327 
2328  if (IdxN) {
2329  unsigned Off = IdxN->getZExtValue() * ElemWidth;
2330  if (VecWidth == 64 && ValWidth == 32) {
2331  assert(Off == 0 || Off == 32);
2332  unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
2333  ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
2334  } else if (Off == 0 && (ValWidth % 8) == 0) {
2335  ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
2336  } else {
2337  SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
2338  // The return type of EXTRACTU must be the same as the type of the
2339  // input vector.
2340  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2341  {VecV, WidthV, OffV});
2342  }
2343  } else {
2344  if (ty(IdxV) != MVT::i32)
2345  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2346  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2347  DAG.getConstant(ElemWidth, dl, MVT::i32));
2348  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2349  {VecV, WidthV, OffV});
2350  }
2351 
2352  // Cast ExtV to the requested result type.
2353  ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
2354  ExtV = DAG.getBitcast(ResTy, ExtV);
2355  return ExtV;
2356 }
2357 
2358 SDValue
2359 HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
2360  const SDLoc &dl, MVT ValTy,
2361  SelectionDAG &DAG) const {
2362  MVT VecTy = ty(VecV);
2363  if (VecTy.getVectorElementType() == MVT::i1) {
2364  MVT ValTy = ty(ValV);
2365  assert(ValTy.getVectorElementType() == MVT::i1);
2366  SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV);
2367  unsigned VecLen = VecTy.getVectorNumElements();
2368  unsigned Scale = VecLen / ValTy.getVectorNumElements();
2369  assert(Scale > 1);
2370 
2371  for (unsigned R = Scale; R > 1; R /= 2) {
2372  ValR = contractPredicate(ValR, dl, DAG);
2373  ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2374  DAG.getUNDEF(MVT::i32), ValR);
2375  }
2376  // The longest possible subvector is at most 32 bits, so it is always
2377  // contained in the low subregister.
2378  ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);
2379 
2380  unsigned ValBytes = 64 / Scale;
2381  SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32);
2382  SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2383  DAG.getConstant(8, dl, MVT::i32));
2384  SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2386  {VecR, ValR, Width, Idx});
2387  return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
2388  }
2389 
2390  unsigned VecWidth = VecTy.getSizeInBits();
2391  unsigned ValWidth = ValTy.getSizeInBits();
2392  assert(VecWidth == 32 || VecWidth == 64);
2393  assert((VecWidth % ValWidth) == 0);
2394 
2395  // Cast everything to scalar integer types.
2396  MVT ScalarTy = MVT::getIntegerVT(VecWidth);
2397  // The actual type of ValV may be different than ValTy (which is related
2398  // to the vector type).
2399  unsigned VW = ty(ValV).getSizeInBits();
2400  ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
2401  VecV = DAG.getBitcast(ScalarTy, VecV);
2402  if (VW != VecWidth)
2403  ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
2404 
2405  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2406  SDValue InsV;
2407 
2408  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
2409  unsigned W = C->getZExtValue() * ValWidth;
2410  SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
2411  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2412  {VecV, ValV, WidthV, OffV});
2413  } else {
2414  if (ty(IdxV) != MVT::i32)
2415  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2416  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2417  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2418  {VecV, ValV, WidthV, OffV});
2419  }
2420 
2421  return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2422 }
2423 
2424 SDValue
2425 HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
2426  SelectionDAG &DAG) const {
2427  assert(ty(Vec32).getSizeInBits() == 32);
2428  if (isUndef(Vec32))
2429  return DAG.getUNDEF(MVT::i64);
2430  return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2431 }
2432 
2433 SDValue
2434 HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
2435  SelectionDAG &DAG) const {
2436  assert(ty(Vec64).getSizeInBits() == 64);
2437  if (isUndef(Vec64))
2438  return DAG.getUNDEF(MVT::i32);
2439  return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2440 }
2441 
2442 SDValue
2443 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
2444  const {
2445  if (Ty.isVector()) {
2446  assert(Ty.isInteger() && "Only integer vectors are supported here");
2447  unsigned W = Ty.getSizeInBits();
2448  if (W <= 64)
2449  return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
2450  return DAG.getNode(HexagonISD::VZERO, dl, Ty);
2451  }
2452 
2453  if (Ty.isInteger())
2454  return DAG.getConstant(0, dl, Ty);
2455  if (Ty.isFloatingPoint())
2456  return DAG.getConstantFP(0.0, dl, Ty);
2457  llvm_unreachable("Invalid type for zero");
2458 }
2459 
2460 SDValue
2462  MVT VecTy = ty(Op);
2463  unsigned BW = VecTy.getSizeInBits();
2464  const SDLoc &dl(Op);
2466  for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
2467  Ops.push_back(Op.getOperand(i));
2468 
2469  if (BW == 32)
2470  return buildVector32(Ops, dl, VecTy, DAG);
2471  if (BW == 64)
2472  return buildVector64(Ops, dl, VecTy, DAG);
2473 
2474  if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2475  // Check if this is a special case or all-0 or all-1.
2476  bool All0 = true, All1 = true;
2477  for (SDValue P : Ops) {
2478  auto *CN = dyn_cast<ConstantSDNode>(P.getNode());
2479  if (CN == nullptr) {
2480  All0 = All1 = false;
2481  break;
2482  }
2483  uint32_t C = CN->getZExtValue();
2484  All0 &= (C == 0);
2485  All1 &= (C == 1);
2486  }
2487  if (All0)
2488  return DAG.getNode(HexagonISD::PFALSE, dl, VecTy);
2489  if (All1)
2490  return DAG.getNode(HexagonISD::PTRUE, dl, VecTy);
2491 
2492  // For each i1 element in the resulting predicate register, put 1
2493  // shifted by the index of the element into a general-purpose register,
2494  // then or them together and transfer it back into a predicate register.
2495  SDValue Rs[8];
2496  SDValue Z = getZero(dl, MVT::i32, DAG);
2497  // Always produce 8 bits, repeat inputs if necessary.
2498  unsigned Rep = 8 / VecTy.getVectorNumElements();
2499  for (unsigned i = 0; i != 8; ++i) {
2500  SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
2501  Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2502  }
2503  for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2504  for (unsigned i = 0, e = A.size()/2; i != e; ++i)
2505  Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2506  }
2507  // Move the value directly to a predicate register.
2508  return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2509  }
2510 
2511  return SDValue();
2512 }
2513 
2514 SDValue
2516  SelectionDAG &DAG) const {
2517  MVT VecTy = ty(Op);
2518  const SDLoc &dl(Op);
2519  if (VecTy.getSizeInBits() == 64) {
2520  assert(Op.getNumOperands() == 2);
2521  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1),
2522  Op.getOperand(0));
2523  }
2524 
2525  MVT ElemTy = VecTy.getVectorElementType();
2526  if (ElemTy == MVT::i1) {
2527  assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2528  MVT OpTy = ty(Op.getOperand(0));
2529  // Scale is how many times the operands need to be contracted to match
2530  // the representation in the target register.
2531  unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
2532  assert(Scale == Op.getNumOperands() && Scale > 1);
2533 
2534  // First, convert all bool vectors to integers, then generate pairwise
2535  // inserts to form values of doubled length. Up until there are only
2536  // two values left to concatenate, all of these values will fit in a
2537  // 32-bit integer, so keep them as i32 to use 32-bit inserts.
2538  SmallVector<SDValue,4> Words[2];
2539  unsigned IdxW = 0;
2540 
2541  for (SDValue P : Op.getNode()->op_values()) {
2542  SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
2543  for (unsigned R = Scale; R > 1; R /= 2) {
2544  W = contractPredicate(W, dl, DAG);
2545  W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2546  DAG.getUNDEF(MVT::i32), W);
2547  }
2548  W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
2549  Words[IdxW].push_back(W);
2550  }
2551 
2552  while (Scale > 2) {
2553  SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
2554  Words[IdxW ^ 1].clear();
2555 
2556  for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
2557  SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
2558  // Insert W1 into W0 right next to the significant bits of W0.
2560  {W0, W1, WidthV, WidthV});
2561  Words[IdxW ^ 1].push_back(T);
2562  }
2563  IdxW ^= 1;
2564  Scale /= 2;
2565  }
2566 
2567  // Another sanity check. At this point there should only be two words
2568  // left, and Scale should be 2.
2569  assert(Scale == 2 && Words[IdxW].size() == 2);
2570 
2572  Words[IdxW][1], Words[IdxW][0]);
2573  return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
2574  }
2575 
2576  return SDValue();
2577 }
2578 
2579 SDValue
2581  SelectionDAG &DAG) const {
2582  SDValue Vec = Op.getOperand(0);
2583  MVT ElemTy = ty(Vec).getVectorElementType();
2584  return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
2585 }
2586 
2587 SDValue
2589  SelectionDAG &DAG) const {
2590  return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
2591  ty(Op), ty(Op), DAG);
2592 }
2593 
2594 SDValue
2596  SelectionDAG &DAG) const {
2597  return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
2598  SDLoc(Op), ty(Op).getVectorElementType(), DAG);
2599 }
2600 
2601 SDValue
2603  SelectionDAG &DAG) const {
2604  SDValue ValV = Op.getOperand(1);
2605  return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
2606  SDLoc(Op), ty(ValV), DAG);
2607 }
2608 
2609 bool
2611  // Assuming the caller does not have either a signext or zeroext modifier, and
2612  // only one value is accepted, any reasonable truncation is allowed.
2613  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2614  return false;
2615 
2616  // FIXME: in principle up to 64-bit could be made safe, but it would be very
2617  // fragile at the moment: any support for multiple value returns would be
2618  // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2619  return Ty1->getPrimitiveSizeInBits() <= 32;
2620 }
2621 
2622 SDValue
2624  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2625  unsigned ClaimAlign = LN->getAlignment();
2626  validateConstPtrAlignment(LN->getBasePtr(), SDLoc(Op), ClaimAlign);
2627  // Call LowerUnalignedLoad for all loads, it recognizes loads that
2628  // don't need extra aligning.
2629  return LowerUnalignedLoad(Op, DAG);
2630 }
2631 
2632 SDValue
2634  StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
2635  unsigned ClaimAlign = SN->getAlignment();
2636  SDValue Ptr = SN->getBasePtr();
2637  const SDLoc &dl(Op);
2638  validateConstPtrAlignment(Ptr, dl, ClaimAlign);
2639 
2640  MVT StoreTy = SN->getMemoryVT().getSimpleVT();
2641  unsigned NeedAlign = Subtarget.getTypeAlignment(StoreTy);
2642  if (ClaimAlign < NeedAlign)
2643  return expandUnalignedStore(SN, DAG);
2644  return Op;
2645 }
2646 
2647 SDValue
2649  const {
2650  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2651  MVT LoadTy = ty(Op);
2652  unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
2653  unsigned HaveAlign = LN->getAlignment();
2654  if (HaveAlign >= NeedAlign)
2655  return Op;
2656 
2657  const SDLoc &dl(Op);
2658  const DataLayout &DL = DAG.getDataLayout();
2659  LLVMContext &Ctx = *DAG.getContext();
2660 
2661  // If the load aligning is disabled or the load can be broken up into two
2662  // smaller legal loads, do the default (target-independent) expansion.
2663  bool DoDefault = false;
2664  // Handle it in the default way if this is an indexed load.
2665  if (!LN->isUnindexed())
2666  DoDefault = true;
2667 
2668  if (!AlignLoads) {
2669  if (allowsMemoryAccess(Ctx, DL, LN->getMemoryVT(), *LN->getMemOperand()))
2670  return Op;
2671  DoDefault = true;
2672  }
2673  if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
2674  // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
2675  MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign)
2676  : MVT::getVectorVT(MVT::i8, HaveAlign);
2677  DoDefault = allowsMemoryAccess(Ctx, DL, PartTy, *LN->getMemOperand());
2678  }
2679  if (DoDefault) {
2680  std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
2681  return DAG.getMergeValues({P.first, P.second}, dl);
2682  }
2683 
2684  // The code below generates two loads, both aligned as NeedAlign, and
2685  // with the distance of NeedAlign between them. For that to cover the
2686  // bits that need to be loaded (and without overlapping), the size of
2687  // the loads should be equal to NeedAlign. This is true for all loadable
2688  // types, but add an assertion in case something changes in the future.
2689  assert(LoadTy.getSizeInBits() == 8*NeedAlign);
2690 
2691  unsigned LoadLen = NeedAlign;
2692  SDValue Base = LN->getBasePtr();
2693  SDValue Chain = LN->getChain();
2694  auto BO = getBaseAndOffset(Base);
2695  unsigned BaseOpc = BO.first.getOpcode();
2696  if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
2697  return Op;
2698 
2699  if (BO.second % LoadLen != 0) {
2700  BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
2701  DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
2702  BO.second -= BO.second % LoadLen;
2703  }
2704  SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
2705  ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
2706  DAG.getConstant(NeedAlign, dl, MVT::i32))
2707  : BO.first;
2708  SDValue Base0 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second, dl);
2709  SDValue Base1 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second+LoadLen, dl);
2710 
2711  MachineMemOperand *WideMMO = nullptr;
2712  if (MachineMemOperand *MMO = LN->getMemOperand()) {
2713  MachineFunction &MF = DAG.getMachineFunction();
2714  WideMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), MMO->getFlags(),
2715  2*LoadLen, LoadLen, MMO->getAAInfo(), MMO->getRanges(),
2716  MMO->getSyncScopeID(), MMO->getOrdering(),
2717  MMO->getFailureOrdering());
2718  }
2719 
2720  SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
2721  SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
2722 
2723  SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
2724  {Load1, Load0, BaseNoOff.getOperand(0)});
2725  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2726  Load0.getValue(1), Load1.getValue(1));
2727  SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
2728  return M;
2729 }
2730 
2731 SDValue
2733  SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
2734  auto *CY = dyn_cast<ConstantSDNode>(Y);
2735  if (!CY)
2736  return SDValue();
2737 
2738  const SDLoc &dl(Op);
2739  SDVTList VTs = Op.getNode()->getVTList();
2740  assert(VTs.NumVTs == 2);
2741  assert(VTs.VTs[1] == MVT::i1);
2742  unsigned Opc = Op.getOpcode();
2743 
2744  if (CY) {
2745  uint32_t VY = CY->getZExtValue();
2746  assert(VY != 0 && "This should have been folded");
2747  // X +/- 1
2748  if (VY != 1)
2749  return SDValue();
2750 
2751  if (Opc == ISD::UADDO) {
2752  SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y});
2753  SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG),
2754  ISD::SETEQ);
2755  return DAG.getMergeValues({Op, Ov}, dl);
2756  }
2757  if (Opc == ISD::USUBO) {
2758  SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
2759  SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op,
2760  DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
2761  return DAG.getMergeValues({Op, Ov}, dl);
2762  }
2763  }
2764 
2765  return SDValue();
2766 }
2767 
2768 SDValue
2770  const SDLoc &dl(Op);
2771  unsigned Opc = Op.getOpcode();
2772  SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
2773 
2774  if (Opc == ISD::ADDCARRY)
2775  return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
2776  { X, Y, C });
2777 
2778  EVT CarryTy = C.getValueType();
2779  SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
2780  { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
2781  SDValue Out[] = { SubC.getValue(0),
2782  DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
2783  return DAG.getMergeValues(Out, dl);
2784 }
2785 
2786 SDValue
2788  SDValue Chain = Op.getOperand(0);
2789  SDValue Offset = Op.getOperand(1);
2790  SDValue Handler = Op.getOperand(2);
2791  SDLoc dl(Op);
2792  auto PtrVT = getPointerTy(DAG.getDataLayout());
2793 
2794  // Mark function as containing a call to EH_RETURN.
2795  HexagonMachineFunctionInfo *FuncInfo =
2797  FuncInfo->setHasEHReturn();
2798 
2799  unsigned OffsetReg = Hexagon::R28;
2800 
2801  SDValue StoreAddr =
2802  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2803  DAG.getIntPtrConstant(4, dl));
2804  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2805  Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2806 
2807  // Not needed we already use it as explict input to EH_RETURN.
2808  // MF.getRegInfo().addLiveOut(OffsetReg);
2809 
2810  return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2811 }
2812 
2813 SDValue
2815  unsigned Opc = Op.getOpcode();
2816 
2817  // Handle INLINEASM first.
2818  if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
2819  return LowerINLINEASM(Op, DAG);
2820 
2821  if (isHvxOperation(Op)) {
2822  // If HVX lowering returns nothing, try the default lowering.
2823  if (SDValue V = LowerHvxOperation(Op, DAG))
2824  return V;
2825  }
2826 
2827  switch (Opc) {
2828  default:
2829 #ifndef NDEBUG
2830  Op.getNode()->dumpr(&DAG);
2831  if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2832  errs() << "Error: check for a non-legal type in this operation\n";
2833 #endif
2834  llvm_unreachable("Should not custom lower this!");
2835  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2836  case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
2837  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
2838  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
2839  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2840  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2841  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2842  case ISD::BITCAST: return LowerBITCAST(Op, DAG);
2843  case ISD::LOAD: return LowerLoad(Op, DAG);
2844  case ISD::STORE: return LowerStore(Op, DAG);
2845  case ISD::UADDO:
2846  case ISD::USUBO: return LowerUAddSubO(Op, DAG);
2847  case ISD::ADDCARRY:
2848  case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
2849  case ISD::SRA:
2850  case ISD::SHL:
2851  case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2852  case ISD::ROTL: return LowerROTL(Op, DAG);
2853  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2854  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2855  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2856  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2857  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2858  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2859  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2860  case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2861  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2862  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2863  case ISD::VASTART: return LowerVASTART(Op, DAG);
2864  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2865  case ISD::SETCC: return LowerSETCC(Op, DAG);
2866  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2867  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2868  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2869  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2870  case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
2871  break;
2872  }
2873 
2874  return SDValue();
2875 }
2876 
2877 void
2880  SelectionDAG &DAG) const {
2881  // We are only custom-lowering stores to verify the alignment of the
2882  // address if it is a compile-time constant. Since a store can be modified
2883  // during type-legalization (the value being stored may need legalization),
2884  // return empty Results here to indicate that we don't really make any
2885  // changes in the custom lowering.
2886  if (N->getOpcode() != ISD::STORE)
2887  return TargetLowering::LowerOperationWrapper(N, Results, DAG);
2888 }
2889 
2890 void
2893  SelectionDAG &DAG) const {
2894  const SDLoc &dl(N);
2895  switch (N->getOpcode()) {
2896  case ISD::SRL:
2897  case ISD::SRA:
2898  case ISD::SHL:
2899  return;
2900  case ISD::BITCAST:
2901  // Handle a bitcast from v8i1 to i8.
2902  if (N->getValueType(0) == MVT::i8) {
2903  SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
2904  N->getOperand(0), DAG);
2905  SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
2906  Results.push_back(T);
2907  }
2908  break;
2909  }
2910 }
2911 
2912 SDValue
2914  const {
2915  SDValue Op(N, 0);
2916  if (isHvxOperation(Op)) {
2917  if (SDValue V = PerformHvxDAGCombine(N, DCI))
2918  return V;
2919  return SDValue();
2920  }
2921 
2922  const SDLoc &dl(Op);
2923  unsigned Opc = Op.getOpcode();
2924 
2925  if (Opc == HexagonISD::P2D) {
2926  SDValue P = Op.getOperand(0);
2927  switch (P.getOpcode()) {
2928  case HexagonISD::PTRUE:
2929  return DCI.DAG.getConstant(-1, dl, ty(Op));
2930  case HexagonISD::PFALSE:
2931  return getZero(dl, ty(Op), DCI.DAG);
2932  default:
2933  break;
2934  }
2935  } else if (Opc == ISD::VSELECT) {
2936  // This is pretty much duplicated in HexagonISelLoweringHVX...
2937  //
2938  // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
2939  SDValue Cond = Op.getOperand(0);
2940  if (Cond->getOpcode() == ISD::XOR) {
2941  SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
2942  if (C1->getOpcode() == HexagonISD::PTRUE) {
2943  SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
2944  Op.getOperand(2), Op.getOperand(1));
2945  return VSel;
2946  }
2947  }
2948  }
2949 
2950  return SDValue();
2951 }
2952 
2953 /// Returns relocation base for the given PIC jumptable.
2954 SDValue
2956  SelectionDAG &DAG) const {
2957  int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2958  EVT VT = Table.getValueType();
2960  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2961 }
2962 
2963 //===----------------------------------------------------------------------===//
2964 // Inline Assembly Support
2965 //===----------------------------------------------------------------------===//
2966 
2969  if (Constraint.size() == 1) {
2970  switch (Constraint[0]) {
2971  case 'q':
2972  case 'v':
2973  if (Subtarget.useHVXOps())
2974  return C_RegisterClass;
2975  break;
2976  case 'a':
2977  return C_RegisterClass;
2978  default:
2979  break;
2980  }
2981  }
2982  return TargetLowering::getConstraintType(Constraint);
2983 }
2984 
2985 std::pair<unsigned, const TargetRegisterClass*>
2987  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
2988 
2989  if (Constraint.size() == 1) {
2990  switch (Constraint[0]) {
2991  case 'r': // R0-R31
2992  switch (VT.SimpleTy) {
2993  default:
2994  return {0u, nullptr};
2995  case MVT::i1:
2996  case MVT::i8:
2997  case MVT::i16:
2998  case MVT::i32:
2999  case MVT::f32:
3000  return {0u, &Hexagon::IntRegsRegClass};
3001  case MVT::i64:
3002  case MVT::f64:
3003  return {0u, &Hexagon::DoubleRegsRegClass};
3004  }
3005  break;
3006  case 'a': // M0-M1
3007  if (VT != MVT::i32)
3008  return {0u, nullptr};
3009  return {0u, &Hexagon::ModRegsRegClass};
3010  case 'q': // q0-q3
3011  switch (VT.getSizeInBits()) {
3012  default:
3013  return {0u, nullptr};
3014  case 512:
3015  case 1024:
3016  return {0u, &Hexagon::HvxQRRegClass};
3017  }
3018  break;
3019  case 'v': // V0-V31
3020  switch (VT.getSizeInBits()) {
3021  default:
3022  return {0u, nullptr};
3023  case 512:
3024  return {0u, &Hexagon::HvxVRRegClass};
3025  case 1024:
3026  if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
3027  return {0u, &Hexagon::HvxVRRegClass};
3028  return {0u, &Hexagon::HvxWRRegClass};
3029  case 2048:
3030  return {0u, &Hexagon::HvxWRRegClass};
3031  }
3032  break;
3033  default:
3034  return {0u, nullptr};
3035  }
3036  }
3037 
3038  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3039 }
3040 
3041 /// isFPImmLegal - Returns true if the target can instruction select the
3042 /// specified FP immediate natively. If false, the legalizer will
3043 /// materialize the FP immediate as a load from a constant pool.
3045  bool ForCodeSize) const {
3046  return true;
3047 }
3048 
3049 /// isLegalAddressingMode - Return true if the addressing mode represented by
3050 /// AM is legal for this target, for a load/store of the specified type.
3052  const AddrMode &AM, Type *Ty,
3053  unsigned AS, Instruction *I) const {
3054  if (Ty->isSized()) {
3055  // When LSR detects uses of the same base address to access different
3056  // types (e.g. unions), it will assume a conservative type for these
3057  // uses:
3058  // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3059  // The type Ty passed here would then be "void". Skip the alignment
3060  // checks, but do not return false right away, since that confuses
3061  // LSR into crashing.
3062  unsigned A = DL.getABITypeAlignment(Ty);
3063  // The base offset must be a multiple of the alignment.
3064  if ((AM.BaseOffs % A) != 0)
3065  return false;
3066  // The shifted offset must fit in 11 bits.
3067  if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
3068  return false;
3069  }
3070 
3071  // No global is ever allowed as a base.
3072  if (AM.BaseGV)
3073  return false;
3074 
3075  int Scale = AM.Scale;
3076  if (Scale < 0)
3077  Scale = -Scale;
3078  switch (Scale) {
3079  case 0: // No scale reg, "r+i", "r", or just "i".
3080  break;
3081  default: // No scaled addressing mode.
3082  return false;
3083  }
3084  return true;
3085 }
3086 
3087 /// Return true if folding a constant offset with the given GlobalAddress is
3088 /// legal. It is frequently not legal in PIC relocation models.
3090  const {
3091  return HTM.getRelocationModel() == Reloc::Static;
3092 }
3093 
3094 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3095 /// icmp immediate, that is the target has icmp instructions which can compare
3096 /// a register against the immediate without having to materialize the
3097 /// immediate into a register.
3099  return Imm >= -512 && Imm <= 511;
3100 }
3101 
3102 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3103 /// for tail call optimization. Targets which want to do tail call
3104 /// optimization should implement this function.
3106  SDValue Callee,
3107  CallingConv::ID CalleeCC,
3108  bool IsVarArg,
3109  bool IsCalleeStructRet,
3110  bool IsCallerStructRet,
3111  const SmallVectorImpl<ISD::OutputArg> &Outs,
3112  const SmallVectorImpl<SDValue> &OutVals,
3114  SelectionDAG& DAG) const {
3115  const Function &CallerF = DAG.getMachineFunction().getFunction();
3116  CallingConv::ID CallerCC = CallerF.getCallingConv();
3117  bool CCMatch = CallerCC == CalleeCC;
3118 
3119  // ***************************************************************************
3120  // Look for obvious safe cases to perform tail call optimization that do not
3121  // require ABI changes.
3122  // ***************************************************************************
3123 
3124  // If this is a tail call via a function pointer, then don't do it!
3125  if (!isa<GlobalAddressSDNode>(Callee) &&
3126  !isa<ExternalSymbolSDNode>(Callee)) {
3127  return false;
3128  }
3129 
3130  // Do not optimize if the calling conventions do not match and the conventions
3131  // used are not C or Fast.
3132  if (!CCMatch) {
3133  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3134  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3135  // If R & E, then ok.
3136  if (!R || !E)
3137  return false;
3138  }
3139 
3140  // Do not tail call optimize vararg calls.
3141  if (IsVarArg)
3142  return false;
3143 
3144  // Also avoid tail call optimization if either caller or callee uses struct
3145  // return semantics.
3146  if (IsCalleeStructRet || IsCallerStructRet)
3147  return false;
3148 
3149  // In addition to the cases above, we also disable Tail Call Optimization if
3150  // the calling convention code that at least one outgoing argument needs to
3151  // go on the stack. We cannot check that here because at this point that
3152  // information is not available.
3153  return true;
3154 }
3155 
3156 /// Returns the target specific optimal type for load and store operations as
3157 /// a result of memset, memcpy, and memmove lowering.
3158 ///
3159 /// If DstAlign is zero that means it's safe to destination alignment can
3160 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3161 /// a need to check it against alignment requirement, probably because the
3162 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3163 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3164 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3165 /// does not need to be loaded. It returns EVT::Other if the type should be
3166 /// determined using generic target-independent logic.
3168  unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3169  bool MemcpyStrSrc, const AttributeList &FuncAttributes) const {
3170 
3171  auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3172  return (GivenA % MinA) == 0;
3173  };
3174 
3175  if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3176  return MVT::i64;
3177  if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3178  return MVT::i32;
3179  if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3180  return MVT::i16;
3181 
3182  return MVT::Other;
3183 }
3184 
3186  EVT VT, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags,
3187  bool *Fast) const {
3188  if (Fast)
3189  *Fast = false;
3190  return Subtarget.isHVXVectorType(VT.getSimpleVT());
3191 }
3192 
3193 std::pair<const TargetRegisterClass*, uint8_t>
3194 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3195  MVT VT) const {
3196  if (Subtarget.isHVXVectorType(VT, true)) {
3197  unsigned BitWidth = VT.getSizeInBits();
3198  unsigned VecWidth = Subtarget.getVectorLength() * 8;
3199 
3200  if (VT.getVectorElementType() == MVT::i1)
3201  return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3202  if (BitWidth == VecWidth)
3203  return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3204  assert(BitWidth == 2 * VecWidth);
3205  return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3206  }
3207 
3209 }
3210 
3212  ISD::LoadExtType ExtTy, EVT NewVT) const {
3213  // TODO: This may be worth removing. Check regression tests for diffs.
3214  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
3215  return false;
3216 
3217  auto *L = cast<LoadSDNode>(Load);
3218  std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3219  // Small-data object, do not shrink.
3220  if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
3221  return false;
3222  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
3223  auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
3224  const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3225  return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3226  }
3227  return true;
3228 }
3229 
3231  AtomicOrdering Ord) const {
3232  BasicBlock *BB = Builder.GetInsertBlock();
3233  Module *M = BB->getParent()->getParent();
3234  auto PT = cast<PointerType>(Addr->getType());
3235  Type *Ty = PT->getElementType();
3236  unsigned SZ = Ty->getPrimitiveSizeInBits();
3237  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3238  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3239  : Intrinsic::hexagon_L4_loadd_locked;
3240  Function *Fn = Intrinsic::getDeclaration(M, IntID);
3241 
3242  PointerType *NewPtrTy
3243  = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
3244  Addr = Builder.CreateBitCast(Addr, NewPtrTy);
3245 
3246  Value *Call = Builder.CreateCall(Fn, Addr, "larx");
3247 
3248  return Builder.CreateBitCast(Call, Ty);
3249 }
3250 
3251 /// Perform a store-conditional operation to Addr. Return the status of the
3252 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3254  Value *Val, Value *Addr, AtomicOrdering Ord) const {
3255  BasicBlock *BB = Builder.GetInsertBlock();
3256  Module *M = BB->getParent()->getParent();
3257  Type *Ty = Val->getType();
3258  unsigned SZ = Ty->getPrimitiveSizeInBits();
3259 
3260  Type *CastTy = Builder.getIntNTy(SZ);
3261  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3262  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3263  : Intrinsic::hexagon_S4_stored_locked;
3264  Function *Fn = Intrinsic::getDeclaration(M, IntID);
3265 
3266  unsigned AS = Addr->getType()->getPointerAddressSpace();
3267  Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
3268  Val = Builder.CreateBitCast(Val, CastTy);
3269 
3270  Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3271  Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3272  Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3273  return Ext;
3274 }
3275 
3278  // Do not expand loads and stores that don't exceed 64 bits.
3279  return LI->getType()->getPrimitiveSizeInBits() > 64
3282 }
3283 
3285  // Do not expand loads and stores that don't exceed 64 bits.
3286  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3287 }
3288 
3291  AtomicCmpXchgInst *AI) const {
3292  const DataLayout &DL = AI->getModule()->getDataLayout();
3293  unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3294  if (Size >= 4 && Size <= 8)
3297 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
bool isMachineConstantPoolEntry() const
bool isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const
Return true if this global value should be placed into small data/bss section.
Type * getVectorElementType() const
Definition: Type.h:371
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
Value * getValueOperand()
Definition: Instructions.h:409
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool isUndef() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
const GlobalValue * getGlobal() const
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1569
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:211
#define R4(n)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:959
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:858
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:389
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:398
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:264
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
An instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:530
HexagonTargetObjectFile * getObjFileLowering() const override
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Definition: Format.h:186
bool isVector() const
Return true if this is a vector value type.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const SDValue & getBasePtr() const
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:145
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:730
SDVTList getVTList() const
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
unsigned getVectorNumElements() const
ArrayRef< MVT > getHVXElementTypes() const
unsigned getStoreSizeInBits() const
Return the number of bits overwritten by a store of the specified value type.
const SDValue & getChain() const
Function Alias Analysis Results
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:733
unsigned getAlignment() const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Hexagon target-specific information for each MachineFunction.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
unsigned second
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1165
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
unsigned const TargetRegisterInfo * TRI
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
A debug info location.
Definition: DebugLoc.h:33
F(f)
Type * getStructElementType(unsigned N) const
Definition: DerivedTypes.h:365
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:972
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:580
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
An instruction for reading from memory.
Definition: Instructions.h:167
SDNode * getNode() const
get the SDNode which holds the desired result
#define R2(n)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Same for subtraction.
Definition: ISDOpcodes.h:253
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:384
unsigned int NumVTs
The address of the GOT.
Definition: ISDOpcodes.h:65
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:812
#define HEXAGON_LRFP_SIZE
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:466
FunctionType * getFunctionType() const
Definition: CallSite.h:328
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isMemLoc() const
SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, const SDLoc &DL)
Returns sum of the base pointer and offset.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:600
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1241
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:487
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:839
void setMinFunctionAlignment(llvm::Align Align)
Set the target&#39;s minimum function alignment.
A description of a memory reference used in the backend.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
static Value * returnEdge(const PHINode *PN, Value *IntrBaseVal)
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Register getFrameRegister(const MachineFunction &MF) const override
Shift and rotation operations.
Definition: ISDOpcodes.h:441
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:263
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:244
Base class for LoadSDNode and StoreSDNode.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:424
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:654
const HexagonRegisterInfo * getRegisterInfo() const override
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:779
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:648
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:473
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:413
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
void setPrefFunctionAlignment(llvm::Align Align)
Set the target&#39;s preferred function alignment.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
zlib style complession
This file implements a class to represent arbitrary precision integral constant values and operations...
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:726
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
InstrTy * getInstruction() const
Definition: CallSite.h:96
int64_t getSExtValue() const
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
static Value * getBrevLdObject(Value *V)
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1964
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1581
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:410
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:509
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:126
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:460
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:137
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:874
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
An instruction for storing to memory.
Definition: Instructions.h:320
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1012
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors...
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1878
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:778
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1057
void ensureMaxAlignment(llvm::Align Align)
Make sure the function is at least Align bytes aligned.
MVT getVectorElementType() const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Class to represent pointers.
Definition: DerivedTypes.h:544
unsigned getByValSize() const
This class is used to represent ISD::STORE nodes.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:555
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:358
The memory access is volatile.
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:363
#define P(N)
const SDValue & getBasePtr() const
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
static bool isBrevLdIntrinsic(const Value *Inst)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:759
iterator_range< value_op_iterator > op_values() const
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:987
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:363
#define H(x, y, z)
Definition: MD5.cpp:57
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:40
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:846
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
#define HEXAGON_GOT_SYM_NAME
static mvt_range fp_valuetypes()
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:798
const APInt & getAPIntValue() const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:114
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:2102
Class to represent integer types.
Definition: DerivedTypes.h:40
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:446
Constant Vector Declarations.
Definition: Constants.h:499
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:750
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1193
IntegerType * getIntNTy(unsigned N)
Fetch the type representing an N-bit integer.
Definition: IRBuilder.h:396
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Extended Value Type.
Definition: ValueTypes.h:33
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1186
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:519
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:686
unsigned first
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:302
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const
void setPrefLoopAlignment(llvm::Align Align)
Set the target&#39;s preferred loop alignment.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
void dump() const
Dump this node, for debugging.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:654
unsigned getNumOperands() const
Definition: User.h:191
CCState - This class holds information needed while lowering arguments and return values...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:638
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
Return true if it is profitable to reduce a load to a smaller type.
static unsigned getIntrinsicID(const SDNode *N)
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1146
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:370
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
This struct is a compact representation of a valid (power of two) or undefined (0) alignment...
Definition: Alignment.h:85
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Module.h This file contains the declarations for the Module class.
const DebugLoc & getDebugLoc() const
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
iterator end() const
Definition: ArrayRef.h:137
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:752
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:444
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Definition: IRBuilder.h:343
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:653
Represents one node in the SelectionDAG.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:691
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static mvt_range integer_valuetypes()
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:163
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:55
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
unsigned getByValAlign() const
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
amdgpu Simplify well known AMD library false FunctionCallee Callee
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:451
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:499
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:502
bool isTailCall() const
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors...
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:343
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::ZeroOrMore, cl::init(8), cl::desc("Max #stores to inline memset"))
Flags
Flags values. These may be or&#39;d together.
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
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