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HexagonMCInstrInfo.cpp
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1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
10 //
11 //===----------------------------------------------------------------------===//
12 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/Support/Casting.h"
28 #include <cassert>
29 #include <cstdint>
30 #include <limits>
31 
32 using namespace llvm;
33 
35  return Register != Hexagon::NoRegister;
36 }
37 
39  MCInst const &Inst)
40  : MCII(MCII), BundleCurrent(Inst.begin() +
41  HexagonMCInstrInfo::bundleInstructionsOffset),
42  BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
43 
45  MCInst const &Inst, std::nullptr_t)
46  : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
47  DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
48 
50  if (DuplexCurrent != DuplexEnd) {
51  ++DuplexCurrent;
52  if (DuplexCurrent == DuplexEnd) {
53  DuplexCurrent = BundleEnd;
54  DuplexEnd = BundleEnd;
55  ++BundleCurrent;
56  }
57  return *this;
58  }
59  ++BundleCurrent;
60  if (BundleCurrent != BundleEnd) {
61  MCInst const &Inst = *BundleCurrent->getInst();
62  if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
63  DuplexCurrent = Inst.begin();
64  DuplexEnd = Inst.end();
65  }
66  }
67  return *this;
68 }
69 
71  if (DuplexCurrent != DuplexEnd)
72  return *DuplexCurrent->getInst();
73  return *BundleCurrent->getInst();
74 }
75 
77  return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
78  DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
79 }
80 
82  MCContext &Context) {
84 }
85 
87  MCInstrInfo const &MCII, MCInst &MCB,
88  MCInst const &MCI) {
90  MCOperand const &exOp =
92 
93  // Create the extender.
94  MCInst *XMCI =
95  new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
96  XMCI->setLoc(MCI.getLoc());
97 
99 }
100 
103  MCInst const &MCI) {
104  assert(isBundle(MCI));
105  return make_range(Hexagon::PacketIterator(MCII, MCI),
106  Hexagon::PacketIterator(MCII, MCI, nullptr));
107 }
108 
111  assert(isBundle(MCI));
112  return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
113 }
114 
117  return (MCI.size() - bundleInstructionsOffset);
118  else
119  return (1);
120 }
121 
123  MCSubtargetInfo const &STI,
124  MCContext &Context, MCInst &MCB,
126  // Check the bundle for errors.
127  bool CheckOk = Check ? Check->check(false) : true;
128  if (!CheckOk)
129  return false;
130  // Examine the packet and convert pairs of instructions to compound
131  // instructions when possible.
133  HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
134  HexagonMCShuffle(Context, false, MCII, STI, MCB);
135  // Examine the packet and convert pairs of instructions to duplex
136  // instructions when possible.
137  MCInst InstBundlePreDuplex = MCInst(MCB);
138  if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
139  SmallVector<DuplexCandidate, 8> possibleDuplexes;
140  possibleDuplexes =
142  HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
143  }
144  // Examines packet and pad the packet, if needed, when an
145  // end-loop is in the bundle.
146  HexagonMCInstrInfo::padEndloop(MCB, Context);
147  // If compounding and duplexing didn't reduce the size below
148  // 4 or less we have a packet that is too big.
150  return false;
151  // Check the bundle for errors.
152  CheckOk = Check ? Check->check(true) : true;
153  if (!CheckOk)
154  return false;
155  HexagonMCShuffle(Context, true, MCII, STI, MCB);
156  return true;
157 }
158 
160  MCInst const &Inst,
161  MCOperand const &MO) {
163  HexagonMCInstrInfo::isExtended(MCII, Inst));
164 
165  MCInst XMI;
166  XMI.setOpcode(Hexagon::A4_ext);
167  if (MO.isImm())
168  XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
169  else if (MO.isExpr())
171  else
172  llvm_unreachable("invalid extendable operand");
173  return XMI;
174 }
175 
177  MCInst const &inst0,
178  MCInst const &inst1) {
179  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
180  MCInst *duplexInst = new (Context) MCInst;
181  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
182 
183  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
184  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
185  duplexInst->addOperand(MCOperand::createInst(SubInst0));
186  duplexInst->addOperand(MCOperand::createInst(SubInst1));
187  return duplexInst;
188 }
189 
191  size_t Index) {
192  assert(Index <= bundleSize(MCB));
193  if (Index == 0)
194  return nullptr;
195  MCInst const *Inst =
196  MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
197  if (isImmext(*Inst))
198  return Inst;
199  return nullptr;
200 }
201 
203  MCInstrInfo const &MCII, MCInst &MCB,
204  MCInst const &MCI) {
205  if (isConstExtended(MCII, MCI))
206  addConstExtender(Context, MCII, MCB, MCI);
207 }
208 
210  MCInst const &MCI) {
211  uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
214 }
215 
217  MCInst const &MCI) {
218  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
219  return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
221 }
222 
224  MCInst const &MCI) {
225  return MCII.get(MCI.getOpcode());
226 }
227 
229  using namespace Hexagon;
230 
231  switch (Reg) {
232  default:
233  llvm_unreachable("unknown duplex register");
234  // Rs Rss
235  case R0:
236  case D0:
237  return 0;
238  case R1:
239  case D1:
240  return 1;
241  case R2:
242  case D2:
243  return 2;
244  case R3:
245  case D3:
246  return 3;
247  case R4:
248  case D8:
249  return 4;
250  case R5:
251  case D9:
252  return 5;
253  case R6:
254  case D10:
255  return 6;
256  case R7:
257  case D11:
258  return 7;
259  case R16:
260  return 8;
261  case R17:
262  return 9;
263  case R18:
264  return 10;
265  case R19:
266  return 11;
267  case R20:
268  return 12;
269  case R21:
270  return 13;
271  case R22:
272  return 14;
273  case R23:
274  return 15;
275  }
276 }
277 
279  const auto &HExpr = cast<HexagonMCExpr>(Expr);
280  assert(HExpr.getExpr());
281  return *HExpr.getExpr();
282 }
283 
285  MCInst const &MCI) {
286  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
288 }
289 
290 MCOperand const &
292  MCInst const &MCI) {
293  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
294  MCOperand const &MO = MCI.getOperand(O);
295 
297  HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
298  (MO.isImm() || MO.isExpr()));
299  return (MO);
300 }
301 
303  MCInst const &MCI) {
304  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
306 }
307 
309  MCInst const &MCI) {
310  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
312 }
313 
315  MCInst const &MCI) {
316  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
318 }
319 
320 /// Return the maximum value of an extendable operand.
322  MCInst const &MCI) {
324  HexagonMCInstrInfo::isExtended(MCII, MCI));
325 
326  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
327  return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
328  return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
329 }
330 
331 /// Return the minimum value of an extendable operand.
333  MCInst const &MCI) {
335  HexagonMCInstrInfo::isExtended(MCII, MCI));
336 
337  if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
338  return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
339  return 0;
340 }
341 
343  MCInst const &MCI) {
344  return MCII.getName(MCI.getOpcode());
345 }
346 
348  MCInst const &MCI) {
349  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
351 }
352 
354  MCInst const &MCI) {
355  if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
356  // VTMP doesn't actually exist in the encodings for these 184
357  // 3 instructions so go ahead and create it here.
358  static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
359  return (MCO);
360  } else {
361  unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
362  MCOperand const &MCO = MCI.getOperand(O);
363 
365  HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
366  MCO.isReg());
367  return (MCO);
368  }
369 }
370 
371 /// Return the new value or the newly produced value.
373  MCInst const &MCI) {
374  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
376 }
377 
378 MCOperand const &
380  MCInst const &MCI) {
381  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
382  MCOperand const &MCO = MCI.getOperand(O);
383 
385  HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
386  MCO.isReg());
387  return (MCO);
388 }
389 
390 /// Return the Hexagon ISA class for the insn.
392  MCInst const &MCI) {
393  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
394  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
395 }
396 
397 /// Return the slots this instruction can execute out of
399  MCSubtargetInfo const &STI,
400  MCInst const &MCI) {
402  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
403  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
404 }
405 
406 /// Return the slots this instruction consumes in addition to
407 /// the slot(s) it can execute out of
408 
410  MCSubtargetInfo const &STI,
411  MCInst const &MCI) {
413  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
414  unsigned Slots = 0;
415 
416  // FirstStage are slots that this instruction can execute in.
417  // FirstStage+1 are slots that are also consumed by this instruction.
418  // For example: vmemu can only execute in slot 0 but also consumes slot 1.
419  for (unsigned Stage = II[SchedClass].FirstStage + 1;
420  Stage < II[SchedClass].LastStage; ++Stage) {
421  unsigned Units = (Stage + HexagonStages)->getUnits();
422  if (Units > HexagonGetLastSlot())
423  break;
424  // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
425  Slots |= Units;
426  }
427 
428  // if 0 is returned, then no additional slots are consumed by this inst.
429  return Slots;
430 }
431 
432 bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
434  return false;
435 
436  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
437  if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
438  return true;
439  }
440 
441  return false;
442 }
443 
445  return extenderForIndex(MCB, Index) != nullptr;
446 }
447 
450  return false;
451 
452  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
453  if (isImmext(*I.getInst()))
454  return true;
455  }
456 
457  return false;
458 }
459 
460 /// Return whether the insn produces a value.
462  MCInst const &MCI) {
463  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
465 }
466 
467 /// Return whether the insn produces a second value.
469  MCInst const &MCI) {
470  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
472 }
473 
475  assert(isBundle(MCB));
476  assert(Index < HEXAGON_PACKET_SIZE);
477  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
478 }
479 
480 /// Return where the instruction is an accumulator.
482  MCInst const &MCI) {
483  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
485 }
486 
488  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
489  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
490  return Result;
491 }
492 
494  MCInst const &MCI) {
495  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
496  return true;
497  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
498  return false;
500  if (isa<HexagonMCExpr>(MO.getExpr()) &&
502  return true;
503  // Branch insns are handled as necessary by relaxation.
504  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
506  HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
509  return false;
510  // Otherwise loop instructions and other CR insts are handled by relaxation
511  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
512  (MCI.getOpcode() != Hexagon::C4_addipc))
513  return false;
514 
515  assert(!MO.isImm());
516  if (isa<HexagonMCExpr>(MO.getExpr()) &&
518  return false;
519  int64_t Value;
520  if (!MO.getExpr()->evaluateAsAbsolute(Value))
521  return true;
522  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
523  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
524  return (MinValue > Value || Value > MaxValue);
525 }
526 
527 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
528  return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
529  !HexagonMCInstrInfo::isPrefix(MCII, MCI);
530 }
531 
532 bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
533  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
535 }
536 
538  MCInst const &MCI) {
539  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
541 }
542 
544  MCInst const &MCI) {
545  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
547 }
548 
550  MCInst const &MCI) {
551  return (getType(MCII, MCI) == HexagonII::TypeCJ);
552 }
553 
554 bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
555  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
557 }
558 
560  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
561  (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
562 }
563 
564 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
566 }
567 
569  MCInst const &MCI) {
570  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
572 }
573 
575  MCInst const &MCI) {
576  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
578 }
579 
580 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
581  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
582  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
583 }
584 
585 bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
586  const uint64_t V = getType(MCII, MCI);
588 }
589 
591  return MCI.getOpcode() == Hexagon::A4_ext;
592 }
593 
595  assert(isBundle(MCI));
596  int64_t Flags = MCI.getOperand(0).getImm();
597  return (Flags & innerLoopMask) != 0;
598 }
599 
601  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
602 }
603 
605  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
606  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
607 }
608 
609 /// Return whether the insn expects newly produced value.
611  MCInst const &MCI) {
612  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
614 }
615 
616 /// Return whether the operand is extendable.
618  MCInst const &MCI, unsigned short O) {
619  return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
620 }
621 
623  assert(isBundle(MCI));
624  int64_t Flags = MCI.getOperand(0).getImm();
625  return (Flags & outerLoopMask) != 0;
626 }
627 
629  MCInst const &MCI) {
630  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
632 }
633 
634 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
636 }
637 
639  MCInst const &MCI) {
640  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
642 }
643 
644 /// Return whether the insn is newly predicated.
646  MCInst const &MCI) {
647  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
649 }
650 
652  MCInst const &MCI) {
653  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
654  return (
656 }
657 
659  return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
660 }
661 
662 /// Return whether the insn can be packaged only with A and X-type insns.
663 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
664  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
666 }
667 
668 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
670  MCInst const &MCI) {
671  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
672  return ((F >> HexagonII::RestrictSlot1AOKPos) &
674 }
675 
677  MCInst const &MCI) {
678  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
679  return ((F >> HexagonII::RestrictNoSlot1StorePos) &
681 }
682 
683 /// Return whether the insn is solo, i.e., cannot be in a packet.
684 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
685  const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
686  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
687 }
688 
690  assert(isBundle(MCI));
691  auto Flags = MCI.getOperand(0).getImm();
692  return (Flags & memReorderDisabledMask) != 0;
693 }
694 
696  switch (MCI.getOpcode()) {
697  default:
698  return false;
699  case Hexagon::SA1_addi:
700  case Hexagon::SA1_addrx:
701  case Hexagon::SA1_addsp:
702  case Hexagon::SA1_and1:
703  case Hexagon::SA1_clrf:
704  case Hexagon::SA1_clrfnew:
705  case Hexagon::SA1_clrt:
706  case Hexagon::SA1_clrtnew:
707  case Hexagon::SA1_cmpeqi:
708  case Hexagon::SA1_combine0i:
709  case Hexagon::SA1_combine1i:
710  case Hexagon::SA1_combine2i:
711  case Hexagon::SA1_combine3i:
712  case Hexagon::SA1_combinerz:
713  case Hexagon::SA1_combinezr:
714  case Hexagon::SA1_dec:
715  case Hexagon::SA1_inc:
716  case Hexagon::SA1_seti:
717  case Hexagon::SA1_setin1:
718  case Hexagon::SA1_sxtb:
719  case Hexagon::SA1_sxth:
720  case Hexagon::SA1_tfr:
721  case Hexagon::SA1_zxtb:
722  case Hexagon::SA1_zxth:
723  case Hexagon::SL1_loadri_io:
724  case Hexagon::SL1_loadrub_io:
725  case Hexagon::SL2_deallocframe:
726  case Hexagon::SL2_jumpr31:
727  case Hexagon::SL2_jumpr31_f:
728  case Hexagon::SL2_jumpr31_fnew:
729  case Hexagon::SL2_jumpr31_t:
730  case Hexagon::SL2_jumpr31_tnew:
731  case Hexagon::SL2_loadrb_io:
732  case Hexagon::SL2_loadrd_sp:
733  case Hexagon::SL2_loadrh_io:
734  case Hexagon::SL2_loadri_sp:
735  case Hexagon::SL2_loadruh_io:
736  case Hexagon::SL2_return:
737  case Hexagon::SL2_return_f:
738  case Hexagon::SL2_return_fnew:
739  case Hexagon::SL2_return_t:
740  case Hexagon::SL2_return_tnew:
741  case Hexagon::SS1_storeb_io:
742  case Hexagon::SS1_storew_io:
743  case Hexagon::SS2_allocframe:
744  case Hexagon::SS2_storebi0:
745  case Hexagon::SS2_storebi1:
746  case Hexagon::SS2_stored_sp:
747  case Hexagon::SS2_storeh_io:
748  case Hexagon::SS2_storew_sp:
749  case Hexagon::SS2_storewi0:
750  case Hexagon::SS2_storewi1:
751  return true;
752  }
753 }
754 
755 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
756  if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
757  (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
758  return true;
759  return false;
760 }
761 
762 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
763  auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
764  << 8;
765  if (MCI.size() <= Index)
766  return Sentinal;
767  MCOperand const &MCO = MCI.getOperand(Index);
768  if (!MCO.isExpr())
769  return Sentinal;
770  int64_t Value;
771  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
772  return Sentinal;
773  return Value;
774 }
775 
776 void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
777  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
778  HExpr.setMustExtend(Val);
779 }
780 
782  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
783  return HExpr.mustExtend();
784 }
785 void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
786  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
787  HExpr.setMustNotExtend(Val);
788 }
790  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
791  return HExpr.mustNotExtend();
792 }
793 void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
794  HexagonMCExpr &HExpr =
795  const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
796  HExpr.setS27_2_reloc(Val);
797 }
799  HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
800  if (!HExpr)
801  return false;
802  return HExpr->s27_2_reloc();
803 }
804 
806  MCInst Nop;
807  Nop.setOpcode(Hexagon::A2_nop);
808  assert(isBundle(MCB));
809  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
813  MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
814 }
815 
818  if (!isPredicated(MCII, MCI))
819  return {0, 0, false};
820  MCInstrDesc const &Desc = getDesc(MCII, MCI);
821  for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
822  if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
823  return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
824  return {0, 0, false};
825 }
826 
828  MCInst const &MCI) {
829  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
831 }
832 
833 /// return true if instruction has hasTmpDst attribute.
834 bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
835  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
837 }
838 
840  DuplexCandidate Candidate) {
841  assert(Candidate.packetIndexI < MCB.size());
842  assert(Candidate.packetIndexJ < MCB.size());
843  assert(isBundle(MCB));
844  MCInst *Duplex =
845  deriveDuplex(Context, Candidate.iClass,
846  *MCB.getOperand(Candidate.packetIndexJ).getInst(),
847  *MCB.getOperand(Candidate.packetIndexI).getInst());
848  assert(Duplex != nullptr);
849  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
850  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
851 }
852 
854  assert(isBundle(MCI));
855  MCOperand &Operand = MCI.getOperand(0);
856  Operand.setImm(Operand.getImm() | innerLoopMask);
857 }
858 
860  assert(isBundle(MCI));
861  MCOperand &Operand = MCI.getOperand(0);
862  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
864 }
865 
867  assert(isBundle(MCI));
868  MCOperand &Operand = MCI.getOperand(0);
869  Operand.setImm(Operand.getImm() | outerLoopMask);
870 }
871 
872 unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
873  unsigned Producer,
874  unsigned Producer2) {
875  // If we're a single vector consumer of a double producer, set subreg bit
876  // based on if we're accessing the lower or upper register component
877  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
878  if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
879  return (Consumer - Hexagon::V0) & 0x1;
880  if (Producer2 != Hexagon::NoRegister)
881  return Consumer == Producer;
882  return 0;
883 }
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
static bool Check(DecodeStatus &Out, DecodeStatus In)
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const & operator*() const
iterator end()
Definition: MCInst.h:194
iterator begin()
Definition: MCInst.h:192
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
bool isImm() const
Definition: MCInst.h:58
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustExtend(bool Val=true)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
#define R4(n)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
return true if instruction has hasTmpDst attribute.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool s27_2_reloc() const
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of...
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
void setInst(const MCInst *Val)
Definition: MCInst.h:110
void setMustNotExtend(bool Val=true)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
bool isIntRegForSubInst(unsigned Reg)
unsigned Reg
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
unsigned HexagonGetLastSlot()
bool isReg() const
Definition: MCInst.h:57
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
F(f)
bool isSubInstruction(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:243
#define R2(n)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:277
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImmext(MCInst const &MCI)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
const FeatureBitset & getFeatureBits() const
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
void erase(iterator I)
Definition: MCInst.h:189
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
bool s27_2_reloc(MCExpr const &Expr)
void padEndloop(MCInst &MCI, MCContext &Context)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
void setMemReorderDisabled(MCInst &MCI)
Context object for machine code objects.
Definition: MCContext.h:62
MCInst const & instruction(MCInst const &MCB, size_t Index)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
const MCInst * getInst() const
Definition: MCInst.h:105
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
void setMustExtend(MCExpr const &Expr, bool Val=true)
const MCExpr * getExpr() const
Definition: MCInst.h:95
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:311
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void setS27_2_reloc(bool Val=true)
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t getImm() const
Definition: MCInst.h:75
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:582
void setImm(int64_t Val)
Definition: MCInst.h:80
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
bool mustExtend(MCExpr const &Expr)
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
int64_t const memReorderDisabledMask
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
cl::opt< bool > HexagonDisableCompound
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
bool operator==(PacketIterator const &Other) const
bool isExpr() const
Definition: MCInst.h:60
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:50
static wasm::ValType getType(const TargetRegisterClass *RC)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
bool mustNotExtend() const
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
void setLoc(SMLoc loc)
Definition: MCInst.h:176
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
size_t const bundleInstructionsOffset
#define R6(n)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
#define HEXAGON_PACKET_INNER_SIZE
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:226
int64_t minConstant(MCInst const &MCI, size_t Index)
A range adaptor for a pair of iterators.
SMLoc getLoc() const
Definition: MCInst.h:177
unsigned const TypeCVI_FIRST
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
bool isMemReorderDisabled(MCInst const &MCI)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned const TypeCVI_LAST
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:143
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
#define HEXAGON_PACKET_OUTER_SIZE
MCExpr const & getExpr(MCExpr const &Expr)
size_t size() const
Definition: MCInst.h:191
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Generic base class for all target subtargets.
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
const InstrStage HexagonStages[]
bool mustExtend() const
uint16_t LastStage
Index of last + 1 stage in itinerary.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
size_t bundleSize(MCInst const &MCI)
bool check(bool FullCheck=true)
bool hasImmExt(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
An itinerary represents the scheduling information for an instruction.
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
#define HEXAGON_PACKET_SIZE
LLVM Value Representation.
Definition: Value.h:72
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
Check for a valid bundle.
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
IRTranslator LLVM IR MI
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getOpcode() const
Definition: MCInst.h:171
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool mustNotExtend(MCExpr const &Expr)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)