LLVM  10.0.0svn
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the InstructionSelector class.
11 //
12 //===----------------------------------------------------------------------===//
22 #include "llvm/MC/MCInstrDesc.h"
23 #include "llvm/Support/Debug.h"
25 #include <cassert>
27 #define DEBUG_TYPE "instructionselector"
29 using namespace llvm;
32  : Renderers(MaxRenderers), MIs() {}
37  MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
39  const RegisterBankInfo &RBI) const {
40  MachineBasicBlock &MBB = *I.getParent();
41  MachineFunction &MF = *MBB.getParent();
44  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC,
45  I.getOperand(OpIdx), OpIdx);
46 }
49  const MachineOperand &MO, int64_t Value,
50  const MachineRegisterInfo &MRI) const {
51  if (MO.isReg() && MO.getReg())
52  if (auto VRegVal = getConstantVRegValWithLookThrough(MO.getReg(), MRI))
53  return VRegVal->Value == Value;
54  return false;
55 }
58  const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
59  if (!Root.isReg())
60  return false;
62  MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
63  if (RootI->getOpcode() != TargetOpcode::G_GEP)
64  return false;
66  MachineOperand &RHS = RootI->getOperand(2);
67  MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
68  if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
69  return false;
71  return true;
72 }
75  MachineInstr &IntoMI) const {
76  // Immediate neighbours are already folded.
77  if (MI.getParent() == IntoMI.getParent() &&
78  std::next(MI.getIterator()) == IntoMI.getIterator())
79  return true;
81  return !MI.mayLoadOrStore() && !MI.mayRaiseFPException() &&
83 }
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Constrain a register operand of an instruction I to a specified register class.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:848
unsigned const TargetRegisterInfo * TRI
Holds all the information related to register banks.
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_GEP with a G_CONSTANT on the right-hand side...
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:858
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
self_iterator getIterator()
Definition: ilist_node.h:81
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:197
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT (LookThroug...
Definition: Utils.cpp:218
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
MachineOperand class - Representation of each machine instruction operand.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:491
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
bool isReg() const
isReg - Tests if this is a MO_Register operand.
LLVM Value Representation.
Definition: Value.h:73
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.