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InstructionSelector.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
17 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/SmallVector.h"
23 #include <bitset>
24 #include <cstddef>
25 #include <cstdint>
26 #include <functional>
27 #include <initializer_list>
28 #include <vector>
29 
30 namespace llvm {
31 
32 class APInt;
33 class APFloat;
34 class GISelKnownBits;
35 class MachineInstr;
36 class MachineInstrBuilder;
37 class MachineFunction;
38 class MachineOperand;
39 class MachineRegisterInfo;
40 class RegisterBankInfo;
41 class TargetInstrInfo;
42 class TargetRegisterClass;
43 class TargetRegisterInfo;
44 
45 /// Container class for CodeGen predicate results.
46 /// This is convenient because std::bitset does not have a constructor
47 /// with an initializer list of set bits.
48 ///
49 /// Each InstructionSelector subclass should define a PredicateBitset class
50 /// with:
51 /// const unsigned MAX_SUBTARGET_PREDICATES = 192;
52 /// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
53 /// and updating the constant to suit the target. Tablegen provides a suitable
54 /// definition for the predicates in use in <Target>GenGlobalISel.inc when
55 /// GET_GLOBALISEL_PREDICATE_BITSET is defined.
56 template <std::size_t MaxPredicates>
57 class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
58 public:
59  // Cannot inherit constructors because it's not supported by VC++..
60  PredicateBitsetImpl() = default;
61 
62  PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
63  : std::bitset<MaxPredicates>(B) {}
64 
65  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
66  for (auto I : Init)
67  std::bitset<MaxPredicates>::set(I);
68  }
69 };
70 
71 enum {
72  /// Begin a try-block to attempt a match and jump to OnFail if it is
73  /// unsuccessful.
74  /// - OnFail - The MatchTable entry at which to resume if the match fails.
75  ///
76  /// FIXME: This ought to take an argument indicating the number of try-blocks
77  /// to exit on failure. It's usually one but the last match attempt of
78  /// a block will need more. The (implemented) alternative is to tack a
79  /// GIM_Reject on the end of each try-block which is simpler but
80  /// requires an extra opcode and iteration in the interpreter on each
81  /// failed match.
83 
84  /// Switch over the opcode on the specified instruction
85  /// - InsnID - Instruction ID
86  /// - LowerBound - numerically minimum opcode supported
87  /// - UpperBound - numerically maximum + 1 opcode supported
88  /// - Default - failure jump target
89  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
91 
92  /// Switch over the LLT on the specified instruction operand
93  /// - InsnID - Instruction ID
94  /// - OpIdx - Operand index
95  /// - LowerBound - numerically minimum Type ID supported
96  /// - UpperBound - numerically maximum + 1 Type ID supported
97  /// - Default - failure jump target
98  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
100 
101  /// Record the specified instruction
102  /// - NewInsnID - Instruction ID to define
103  /// - InsnID - Instruction ID
104  /// - OpIdx - Operand index
106 
107  /// Check the feature bits
108  /// - Expected features
110 
111  /// Check the opcode on the specified instruction
112  /// - InsnID - Instruction ID
113  /// - Expected opcode
115  /// Check the instruction has the right number of operands
116  /// - InsnID - Instruction ID
117  /// - Expected number of operands
119  /// Check an immediate predicate on the specified instruction
120  /// - InsnID - Instruction ID
121  /// - The predicate to test
123  /// Check an immediate predicate on the specified instruction via an APInt.
124  /// - InsnID - Instruction ID
125  /// - The predicate to test
127  /// Check a floating point immediate predicate on the specified instruction.
128  /// - InsnID - Instruction ID
129  /// - The predicate to test
131  /// Check a memory operation has the specified atomic ordering.
132  /// - InsnID - Instruction ID
133  /// - Ordering - The AtomicOrdering value
137  /// Check the size of the memory access for the given machine memory operand.
138  /// - InsnID - Instruction ID
139  /// - MMOIdx - MMO index
140  /// - Size - The size in bytes of the memory access
142 
143  /// Check the address space of the memory access for the given machine memory
144  /// operand.
145  /// - InsnID - Instruction ID
146  /// - MMOIdx - MMO index
147  /// - NumAddrSpace - Number of valid address spaces
148  /// - AddrSpaceN - An allowed space of the memory access
149  /// - AddrSpaceN+1 ...
151 
152  /// Check the minimum alignment of the memory access for the given machine
153  /// memory operand.
154  /// - InsnID - Instruction ID
155  /// - MMOIdx - MMO index
156  /// - MinAlign - Minimum acceptable alignment
158 
159  /// Check the size of the memory access for the given machine memory operand
160  /// against the size of an operand.
161  /// - InsnID - Instruction ID
162  /// - MMOIdx - MMO index
163  /// - OpIdx - The operand index to compare the MMO against
167  /// Check a generic C++ instruction predicate
168  /// - InsnID - Instruction ID
169  /// - PredicateID - The ID of the predicate function to call
171 
172  /// Check the type for the specified operand
173  /// - InsnID - Instruction ID
174  /// - OpIdx - Operand index
175  /// - Expected type
177  /// Check the type of a pointer to any address space.
178  /// - InsnID - Instruction ID
179  /// - OpIdx - Operand index
180  /// - SizeInBits - The size of the pointer value in bits.
182  /// Check the register bank for the specified operand
183  /// - InsnID - Instruction ID
184  /// - OpIdx - Operand index
185  /// - Expected register bank (specified as a register class)
187 
188  /// Check the operand matches a complex predicate
189  /// - InsnID - Instruction ID
190  /// - OpIdx - Operand index
191  /// - RendererID - The renderer to hold the result
192  /// - Complex predicate ID
194 
195  /// Check the operand is a specific integer
196  /// - InsnID - Instruction ID
197  /// - OpIdx - Operand index
198  /// - Expected integer
200  /// Check the operand is a specific literal integer (i.e. MO.isImm() or
201  /// MO.isCImm() is true).
202  /// - InsnID - Instruction ID
203  /// - OpIdx - Operand index
204  /// - Expected integer
206  /// Check the operand is a specific intrinsic ID
207  /// - InsnID - Instruction ID
208  /// - OpIdx - Operand index
209  /// - Expected Intrinsic ID
211 
212  /// Check the operand is a specific predicate
213  /// - InsnID - Instruction ID
214  /// - OpIdx - Operand index
215  /// - Expected predicate
217 
218  /// Check the specified operand is an MBB
219  /// - InsnID - Instruction ID
220  /// - OpIdx - Operand index
222 
223  /// Check if the specified operand is safe to fold into the current
224  /// instruction.
225  /// - InsnID - Instruction ID
227 
228  /// Check the specified operands are identical.
229  /// - InsnID - Instruction ID
230  /// - OpIdx - Operand index
231  /// - OtherInsnID - Other instruction ID
232  /// - OtherOpIdx - Other operand index
234 
235  /// Fail the current try-block, or completely fail to match if there is no
236  /// current try-block.
238 
239  //=== Renderers ===
240 
241  /// Mutate an instruction
242  /// - NewInsnID - Instruction ID to define
243  /// - OldInsnID - Instruction ID to mutate
244  /// - NewOpcode - The new opcode to use
246 
247  /// Build a new instruction
248  /// - InsnID - Instruction ID to define
249  /// - Opcode - The new opcode to use
251 
252  /// Copy an operand to the specified instruction
253  /// - NewInsnID - Instruction ID to modify
254  /// - OldInsnID - Instruction ID to copy from
255  /// - OpIdx - The operand to copy
257 
258  /// Copy an operand to the specified instruction or add a zero register if the
259  /// operand is a zero immediate.
260  /// - NewInsnID - Instruction ID to modify
261  /// - OldInsnID - Instruction ID to copy from
262  /// - OpIdx - The operand to copy
263  /// - ZeroReg - The zero register to use
265  /// Copy an operand to the specified instruction
266  /// - NewInsnID - Instruction ID to modify
267  /// - OldInsnID - Instruction ID to copy from
268  /// - OpIdx - The operand to copy
269  /// - SubRegIdx - The subregister to copy
271 
272  /// Add an implicit register def to the specified instruction
273  /// - InsnID - Instruction ID to modify
274  /// - RegNum - The register to add
276  /// Add an implicit register use to the specified instruction
277  /// - InsnID - Instruction ID to modify
278  /// - RegNum - The register to add
280  /// Add an register to the specified instruction
281  /// - InsnID - Instruction ID to modify
282  /// - RegNum - The register to add
284 
285  /// Add a temporary register to the specified instruction
286  /// - InsnID - Instruction ID to modify
287  /// - TempRegID - The temporary register ID to add
288  /// - TempRegFlags - The register flags to set
290 
291  /// Add an immediate to the specified instruction
292  /// - InsnID - Instruction ID to modify
293  /// - Imm - The immediate to add
295  /// Render complex operands to the specified instruction
296  /// - InsnID - Instruction ID to modify
297  /// - RendererID - The renderer to call
299 
300  /// Render sub-operands of complex operands to the specified instruction
301  /// - InsnID - Instruction ID to modify
302  /// - RendererID - The renderer to call
303  /// - RenderOpID - The suboperand to render.
305  /// Render operands to the specified instruction using a custom function
306  /// - InsnID - Instruction ID to modify
307  /// - OldInsnID - Instruction ID to get the matched operand from
308  /// - RendererFnID - Custom renderer function to call
310 
311  /// Render a G_CONSTANT operator as a sign-extended immediate.
312  /// - NewInsnID - Instruction ID to modify
313  /// - OldInsnID - Instruction ID to copy from
314  /// The operand index is implicitly 1.
316 
317  /// Render a G_FCONSTANT operator as a sign-extended immediate.
318  /// - NewInsnID - Instruction ID to modify
319  /// - OldInsnID - Instruction ID to copy from
320  /// The operand index is implicitly 1.
322 
323  /// Constrain an instruction operand to a register class.
324  /// - InsnID - Instruction ID to modify
325  /// - OpIdx - Operand index
326  /// - RCEnum - Register class enumeration value
328 
329  /// Constrain an instructions operands according to the instruction
330  /// description.
331  /// - InsnID - Instruction ID to modify
333 
334  /// Merge all memory operands into instruction.
335  /// - InsnID - Instruction ID to modify
336  /// - MergeInsnID... - One or more Instruction ID to merge into the result.
337  /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
338  /// merge.
340 
341  /// Erase from parent.
342  /// - InsnID - Instruction ID to erase
344 
345  /// Create a new temporary register that's not constrained.
346  /// - TempRegID - The temporary register ID to initialize.
347  /// - Expected type
349 
350  /// A successful emission
352 
353  /// Increment the rule coverage counter.
354  /// - RuleID - The ID of the rule that was covered.
356 
357  /// Keeping track of the number of the GI opcodes. Must be the last entry.
359 };
360 
361 enum {
362  /// Indicates the end of the variable-length MergeInsnID list in a
363  /// GIR_MergeMemOperands opcode.
365 };
366 
367 /// Provides the logic to select generic machine instructions.
369 public:
370  virtual ~InstructionSelector() = default;
371 
372  /// Select the (possibly generic) instruction \p I to only use target-specific
373  /// opcodes. It is OK to insert multiple instructions, but they cannot be
374  /// generic pre-isel instructions.
375  ///
376  /// \returns whether selection succeeded.
377  /// \pre I.getParent() && I.getParent()->getParent()
378  /// \post
379  /// if returns true:
380  /// for I in all mutated/inserted instructions:
381  /// !isPreISelGenericOpcode(I.getOpcode())
382  virtual bool select(MachineInstr &I) = 0;
383 
384  CodeGenCoverage *CoverageInfo = nullptr;
386  MachineFunction *MF = nullptr;
387 
388  /// Setup per-MF selector state.
389  virtual void setupMF(MachineFunction &mf,
390  GISelKnownBits &KB,
391  CodeGenCoverage &covinfo) {
392  CoverageInfo = &covinfo;
393  KnownBits = &KB;
394  MF = &mf;
395  }
396 
397 protected:
398  using ComplexRendererFns =
402 
403  struct MatcherState {
404  std::vector<ComplexRendererFns::value_type> Renderers;
407 
408  MatcherState(unsigned MaxRenderers);
409  };
410 
411 public:
412  template <class PredicateBitset, class ComplexMatcherMemFn,
413  class CustomRendererFn>
414  struct ISelInfoTy {
415  ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
416  const PredicateBitset *FeatureBitsets,
417  const ComplexMatcherMemFn *ComplexPredicates,
418  const CustomRendererFn *CustomRenderers)
419  : TypeObjects(TypeObjects),
420  FeatureBitsets(FeatureBitsets),
421  ComplexPredicates(ComplexPredicates),
422  CustomRenderers(CustomRenderers) {
423 
424  for (size_t I = 0; I < NumTypeObjects; ++I)
425  TypeIDMap[TypeObjects[I]] = I;
426  }
427  const LLT *TypeObjects;
428  const PredicateBitset *FeatureBitsets;
429  const ComplexMatcherMemFn *ComplexPredicates;
430  const CustomRendererFn *CustomRenderers;
431 
433  };
434 
435 protected:
437 
438  /// Execute a given matcher table and return true if the match was successful
439  /// and false otherwise.
440  template <class TgtInstructionSelector, class PredicateBitset,
441  class ComplexMatcherMemFn, class CustomRendererFn>
442  bool executeMatchTable(
443  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
445  &ISelInfo,
446  const int64_t *MatchTable, const TargetInstrInfo &TII,
448  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
449  CodeGenCoverage &CoverageInfo) const;
450 
451  virtual const int64_t *getMatchTable() const {
452  llvm_unreachable("Should have been overridden by tablegen if used");
453  }
454 
455  virtual bool testImmPredicate_I64(unsigned, int64_t) const {
457  "Subclasses must override this with a tablegen-erated function");
458  }
459  virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
461  "Subclasses must override this with a tablegen-erated function");
462  }
463  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
465  "Subclasses must override this with a tablegen-erated function");
466  }
467  virtual bool testMIPredicate_MI(unsigned, const MachineInstr &) const {
469  "Subclasses must override this with a tablegen-erated function");
470  }
471 
472  /// Constrain a register operand of an instruction \p I to a specified
473  /// register class. This could involve inserting COPYs before (for uses) or
474  /// after (for defs) and may replace the operand of \p I.
475  /// \returns whether operand regclass constraining succeeded.
476  bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx,
477  const TargetRegisterClass &RC,
478  const TargetInstrInfo &TII,
479  const TargetRegisterInfo &TRI,
480  const RegisterBankInfo &RBI) const;
481 
482  bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
483  const MachineRegisterInfo &MRI) const;
484 
485  /// Return true if the specified operand is a G_GEP with a G_CONSTANT on the
486  /// right-hand side. GlobalISel's separation of pointer and integer types
487  /// means that we don't need to worry about G_OR with equivalent semantics.
488  bool isBaseWithConstantOffset(const MachineOperand &Root,
489  const MachineRegisterInfo &MRI) const;
490 
491  /// Return true if MI can obviously be folded into IntoMI.
492  /// MI and IntoMI do not need to be in the same basic blocks, but MI must
493  /// preceed IntoMI.
494  bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
495 };
496 
497 } // end namespace llvm
498 
499 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Constrain an instruction operand to a register class.
virtual void setupMF(MachineFunction &mf, GISelKnownBits &KB, CodeGenCoverage &covinfo)
Setup per-MF selector state.
std::vector< ComplexRendererFns::value_type > Renderers
unsigned const TargetRegisterInfo * TRI
PredicateBitsetImpl(std::initializer_list< unsigned > Init)
Add an implicit register def to the specified instruction.
const ComplexMatcherMemFn * ComplexPredicates
Merge all memory operands into instruction.
Check a memory operation has the specified atomic ordering.
Holds all the information related to register banks.
Definition: BitVector.h:937
virtual const int64_t * getMatchTable() const
const HexagonInstrInfo * TII
Check the specified operands are identical.
Check the specified operand is an MBB.
Check the type of a pointer to any address space.
Render operands to the specified instruction using a custom function.
DenseMap< unsigned, unsigned > TempRegisters
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Add an immediate to the specified instruction.
A successful emission.
Mutate an instruction.
Copy an operand to the specified instruction.
Switch over the LLT on the specified instruction operand.
TargetInstrInfo - Interface to description of machine instruction set.
Add an implicit register use to the specified instruction.
Container class for CodeGen predicate results.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Render sub-operands of complex operands to the specified instruction.
unsigned const MachineRegisterInfo * MRI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &) const
Build a new instruction.
Copy an operand to the specified instruction.
Check the operand is a specific integer.
Check the instruction has the right number of operands.
Check if the specified operand is safe to fold into the current instruction.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Switch over the opcode on the specified instruction.
Check a floating point immediate predicate on the specified instruction.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode...
Check the minimum alignment of the memory access for the given machine memory operand.
Check the opcode on the specified instruction.
Check a generic C++ instruction predicate.
Constrain an instructions operands according to the instruction description.
Render a G_CONSTANT operator as a sign-extended immediate.
Increment the rule coverage counter.
Check the register bank for the specified operand.
Check the type for the specified operand.
MachineOperand class - Representation of each machine instruction operand.
Check the size of the memory access for the given machine memory operand against the size of an opera...
Class for arbitrary precision integers.
Definition: APInt.h:69
Create a new temporary register that&#39;s not constrained.
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Check the feature bits.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects, const PredicateBitset *FeatureBitsets, const ComplexMatcherMemFn *ComplexPredicates, const CustomRendererFn *CustomRenderers)
Representation of each machine instruction.
Definition: MachineInstr.h:64
Render complex operands to the specified instruction.
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Fail the current try-block, or completely fail to match if there is no current try-block.
Check the operand is a specific literal integer (i.e.
Check the size of the memory access for the given machine memory operand.
#define I(x, y, z)
Definition: MD5.cpp:58
Check an immediate predicate on the specified instruction.
Check the operand is a specific predicate.
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Add an register to the specified instruction.
Check the operand matches a complex predicate.
Check the address space of the memory access for the given machine memory operand.
LLVM Value Representation.
Definition: Value.h:73
Record the specified instruction.
Render a G_FCONSTANT operator as a sign-extended immediate.
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Check the operand is a specific intrinsic ID.
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
IRTranslator LLVM IR MI
PredicateBitsetImpl(const std::bitset< MaxPredicates > &B)
Keeping track of the number of the GI opcodes. Must be the last entry.
Add a temporary register to the specified instruction.
Check an immediate predicate on the specified instruction via an APInt.