LLVM  10.0.0svn
LegalizeDAG.cpp
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1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAG::Legalize method.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/SetVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/Metadata.h"
38 #include "llvm/IR/Type.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/Debug.h"
48 #include <algorithm>
49 #include <cassert>
50 #include <cstdint>
51 #include <tuple>
52 #include <utility>
53 
54 using namespace llvm;
55 
56 #define DEBUG_TYPE "legalizedag"
57 
58 namespace {
59 
60 /// Keeps track of state when getting the sign of a floating-point value as an
61 /// integer.
62 struct FloatSignAsInt {
63  EVT FloatVT;
64  SDValue Chain;
65  SDValue FloatPtr;
66  SDValue IntPtr;
67  MachinePointerInfo IntPointerInfo;
68  MachinePointerInfo FloatPointerInfo;
69  SDValue IntValue;
70  APInt SignMask;
71  uint8_t SignBit;
72 };
73 
74 //===----------------------------------------------------------------------===//
75 /// This takes an arbitrary SelectionDAG as input and
76 /// hacks on it until the target machine can handle it. This involves
77 /// eliminating value sizes the machine cannot handle (promoting small sizes to
78 /// large sizes or splitting up large values into small values) as well as
79 /// eliminating operations the machine cannot handle.
80 ///
81 /// This code also does a small amount of optimization and recognition of idioms
82 /// as part of its processing. For example, if a target does not support a
83 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
84 /// will attempt merge setcc and brc instructions into brcc's.
85 class SelectionDAGLegalize {
86  const TargetMachine &TM;
87  const TargetLowering &TLI;
88  SelectionDAG &DAG;
89 
90  /// The set of nodes which have already been legalized. We hold a
91  /// reference to it in order to update as necessary on node deletion.
92  SmallPtrSetImpl<SDNode *> &LegalizedNodes;
93 
94  /// A set of all the nodes updated during legalization.
95  SmallSetVector<SDNode *, 16> *UpdatedNodes;
96 
97  EVT getSetCCResultType(EVT VT) const {
98  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
99  }
100 
101  // Libcall insertion helpers.
102 
103 public:
104  SelectionDAGLegalize(SelectionDAG &DAG,
105  SmallPtrSetImpl<SDNode *> &LegalizedNodes,
106  SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
107  : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
108  LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
109 
110  /// Legalizes the given operation.
111  void LegalizeOp(SDNode *Node);
112 
113 private:
114  SDValue OptimizeFloatStore(StoreSDNode *ST);
115 
116  void LegalizeLoadOps(SDNode *Node);
117  void LegalizeStoreOps(SDNode *Node);
118 
119  /// Some targets cannot handle a variable
120  /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
121  /// is necessary to spill the vector being inserted into to memory, perform
122  /// the insert there, and then read the result back.
123  SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
124  const SDLoc &dl);
125  SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
126  const SDLoc &dl);
127 
128  /// Return a vector shuffle operation which
129  /// performs the same shuffe in terms of order or result bytes, but on a type
130  /// whose vector element type is narrower than the original shuffle type.
131  /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
132  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
133  SDValue N1, SDValue N2,
134  ArrayRef<int> Mask) const;
135 
136  bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
137  bool &NeedInvert, const SDLoc &dl);
138 
139  SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
140 
141  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
142  SDNode *Node, bool isSigned);
143  SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
144  RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
145  RTLIB::Libcall Call_F128,
146  RTLIB::Libcall Call_PPCF128);
147  SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
148  RTLIB::Libcall Call_I8,
149  RTLIB::Libcall Call_I16,
150  RTLIB::Libcall Call_I32,
151  RTLIB::Libcall Call_I64,
152  RTLIB::Libcall Call_I128);
153  SDValue ExpandArgFPLibCall(SDNode *Node,
154  RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
155  RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
156  RTLIB::Libcall Call_PPCF128);
157  void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
158  void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
159 
160  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
161  const SDLoc &dl);
162  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
163  const SDLoc &dl, SDValue ChainIn);
164  SDValue ExpandBUILD_VECTOR(SDNode *Node);
165  SDValue ExpandSPLAT_VECTOR(SDNode *Node);
166  SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
167  void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
168  SmallVectorImpl<SDValue> &Results);
169  void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
170  SDValue Value) const;
171  SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
172  SDValue NewIntValue) const;
173  SDValue ExpandFCOPYSIGN(SDNode *Node) const;
174  SDValue ExpandFABS(SDNode *Node) const;
175  SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
176  const SDLoc &dl);
177  SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
178  const SDLoc &dl);
179  SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
180  const SDLoc &dl);
181 
182  SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
183  SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
184 
185  SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
186  SDValue ExpandInsertToVectorThroughStack(SDValue Op);
187  SDValue ExpandVectorBuildThroughStack(SDNode* Node);
188 
189  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
190  SDValue ExpandConstant(ConstantSDNode *CP);
191 
192  // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
193  bool ExpandNode(SDNode *Node);
194  void ConvertNodeToLibcall(SDNode *Node);
195  void PromoteNode(SDNode *Node);
196 
197 public:
198  // Node replacement helpers
199 
200  void ReplacedNode(SDNode *N) {
201  LegalizedNodes.erase(N);
202  if (UpdatedNodes)
203  UpdatedNodes->insert(N);
204  }
205 
206  void ReplaceNode(SDNode *Old, SDNode *New) {
207  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
208  dbgs() << " with: "; New->dump(&DAG));
209 
210  assert(Old->getNumValues() == New->getNumValues() &&
211  "Replacing one node with another that produces a different number "
212  "of values!");
213  DAG.ReplaceAllUsesWith(Old, New);
214  if (UpdatedNodes)
215  UpdatedNodes->insert(New);
216  ReplacedNode(Old);
217  }
218 
219  void ReplaceNode(SDValue Old, SDValue New) {
220  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
221  dbgs() << " with: "; New->dump(&DAG));
222 
223  DAG.ReplaceAllUsesWith(Old, New);
224  if (UpdatedNodes)
225  UpdatedNodes->insert(New.getNode());
226  ReplacedNode(Old.getNode());
227  }
228 
229  void ReplaceNode(SDNode *Old, const SDValue *New) {
230  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
231 
232  DAG.ReplaceAllUsesWith(Old, New);
233  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
234  LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
235  New[i]->dump(&DAG));
236  if (UpdatedNodes)
237  UpdatedNodes->insert(New[i].getNode());
238  }
239  ReplacedNode(Old);
240  }
241 
242  void ReplaceNodeWithValue(SDValue Old, SDValue New) {
243  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
244  dbgs() << " with: "; New->dump(&DAG));
245 
246  DAG.ReplaceAllUsesOfValueWith(Old, New);
247  if (UpdatedNodes)
248  UpdatedNodes->insert(New.getNode());
249  ReplacedNode(Old.getNode());
250  }
251 };
252 
253 } // end anonymous namespace
254 
255 /// Return a vector shuffle operation which
256 /// performs the same shuffle in terms of order or result bytes, but on a type
257 /// whose vector element type is narrower than the original shuffle type.
258 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
259 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
260  EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
261  ArrayRef<int> Mask) const {
262  unsigned NumMaskElts = VT.getVectorNumElements();
263  unsigned NumDestElts = NVT.getVectorNumElements();
264  unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
265 
266  assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
267 
268  if (NumEltsGrowth == 1)
269  return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
270 
271  SmallVector<int, 8> NewMask;
272  for (unsigned i = 0; i != NumMaskElts; ++i) {
273  int Idx = Mask[i];
274  for (unsigned j = 0; j != NumEltsGrowth; ++j) {
275  if (Idx < 0)
276  NewMask.push_back(-1);
277  else
278  NewMask.push_back(Idx * NumEltsGrowth + j);
279  }
280  }
281  assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
282  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
283  return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
284 }
285 
286 /// Expands the ConstantFP node to an integer constant or
287 /// a load from the constant pool.
288 SDValue
289 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
290  bool Extend = false;
291  SDLoc dl(CFP);
292 
293  // If a FP immediate is precise when represented as a float and if the
294  // target can do an extending load from float to double, we put it into
295  // the constant pool as a float, even if it's is statically typed as a
296  // double. This shrinks FP constants and canonicalizes them for targets where
297  // an FP extending load is the same cost as a normal load (such as on the x87
298  // fp stack or PPC FP unit).
299  EVT VT = CFP->getValueType(0);
300  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
301  if (!UseCP) {
302  assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
303  return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
304  (VT == MVT::f64) ? MVT::i64 : MVT::i32);
305  }
306 
307  APFloat APF = CFP->getValueAPF();
308  EVT OrigVT = VT;
309  EVT SVT = VT;
310 
311  // We don't want to shrink SNaNs. Converting the SNaN back to its real type
312  // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
313  if (!APF.isSignaling()) {
314  while (SVT != MVT::f32 && SVT != MVT::f16) {
315  SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
317  // Only do this if the target has a native EXTLOAD instruction from
318  // smaller type.
319  TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
320  TLI.ShouldShrinkFPConstant(OrigVT)) {
321  Type *SType = SVT.getTypeForEVT(*DAG.getContext());
322  LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
323  VT = SVT;
324  Extend = true;
325  }
326  }
327  }
328 
329  SDValue CPIdx =
330  DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
331  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
332  if (Extend) {
333  SDValue Result = DAG.getExtLoad(
334  ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
335  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
336  Alignment);
337  return Result;
338  }
339  SDValue Result = DAG.getLoad(
340  OrigVT, dl, DAG.getEntryNode(), CPIdx,
341  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
342  return Result;
343 }
344 
345 /// Expands the Constant node to a load from the constant pool.
346 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
347  SDLoc dl(CP);
348  EVT VT = CP->getValueType(0);
349  SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
350  TLI.getPointerTy(DAG.getDataLayout()));
351  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
352  SDValue Result = DAG.getLoad(
353  VT, dl, DAG.getEntryNode(), CPIdx,
354  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
355  return Result;
356 }
357 
358 /// Some target cannot handle a variable insertion index for the
359 /// INSERT_VECTOR_ELT instruction. In this case, it
360 /// is necessary to spill the vector being inserted into to memory, perform
361 /// the insert there, and then read the result back.
362 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
363  SDValue Val,
364  SDValue Idx,
365  const SDLoc &dl) {
366  SDValue Tmp1 = Vec;
367  SDValue Tmp2 = Val;
368  SDValue Tmp3 = Idx;
369 
370  // If the target doesn't support this, we have to spill the input vector
371  // to a temporary stack slot, update the element, then reload it. This is
372  // badness. We could also load the value into a vector register (either
373  // with a "move to register" or "extload into register" instruction, then
374  // permute it into place, if the idx is a constant and if the idx is
375  // supported by the target.
376  EVT VT = Tmp1.getValueType();
377  EVT EltVT = VT.getVectorElementType();
378  SDValue StackPtr = DAG.CreateStackTemporary(VT);
379 
380  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
381 
382  // Store the vector.
383  SDValue Ch = DAG.getStore(
384  DAG.getEntryNode(), dl, Tmp1, StackPtr,
385  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
386 
387  SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
388 
389  // Store the scalar value.
390  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT);
391  // Load the updated vector.
392  return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
393  DAG.getMachineFunction(), SPFI));
394 }
395 
396 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
397  SDValue Idx,
398  const SDLoc &dl) {
399  if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
400  // SCALAR_TO_VECTOR requires that the type of the value being inserted
401  // match the element type of the vector being created, except for
402  // integers in which case the inserted value can be over width.
403  EVT EltVT = Vec.getValueType().getVectorElementType();
404  if (Val.getValueType() == EltVT ||
405  (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
406  SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
407  Vec.getValueType(), Val);
408 
409  unsigned NumElts = Vec.getValueType().getVectorNumElements();
410  // We generate a shuffle of InVec and ScVec, so the shuffle mask
411  // should be 0,1,2,3,4,5... with the appropriate element replaced with
412  // elt 0 of the RHS.
413  SmallVector<int, 8> ShufOps;
414  for (unsigned i = 0; i != NumElts; ++i)
415  ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
416 
417  return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
418  }
419  }
420  return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
421 }
422 
423 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
424  LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
425  // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
426  // FIXME: We shouldn't do this for TargetConstantFP's.
427  // FIXME: move this to the DAG Combiner! Note that we can't regress due
428  // to phase ordering between legalized code and the dag combiner. This
429  // probably means that we need to integrate dag combiner and legalizer
430  // together.
431  // We generally can't do this one for long doubles.
432  SDValue Chain = ST->getChain();
433  SDValue Ptr = ST->getBasePtr();
434  unsigned Alignment = ST->getAlignment();
435  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
436  AAMDNodes AAInfo = ST->getAAInfo();
437  SDLoc dl(ST);
438  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
439  if (CFP->getValueType(0) == MVT::f32 &&
440  TLI.isTypeLegal(MVT::i32)) {
441  SDValue Con = DAG.getConstant(CFP->getValueAPF().
442  bitcastToAPInt().zextOrTrunc(32),
443  SDLoc(CFP), MVT::i32);
444  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), Alignment,
445  MMOFlags, AAInfo);
446  }
447 
448  if (CFP->getValueType(0) == MVT::f64) {
449  // If this target supports 64-bit registers, do a single 64-bit store.
450  if (TLI.isTypeLegal(MVT::i64)) {
451  SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
452  zextOrTrunc(64), SDLoc(CFP), MVT::i64);
453  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
454  Alignment, MMOFlags, AAInfo);
455  }
456 
457  if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
458  // Otherwise, if the target supports 32-bit registers, use 2 32-bit
459  // stores. If the target supports neither 32- nor 64-bits, this
460  // xform is certainly not worth it.
461  const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
462  SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
463  SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
464  if (DAG.getDataLayout().isBigEndian())
465  std::swap(Lo, Hi);
466 
467  Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
468  MMOFlags, AAInfo);
469  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
470  DAG.getConstant(4, dl, Ptr.getValueType()));
471  Hi = DAG.getStore(Chain, dl, Hi, Ptr,
472  ST->getPointerInfo().getWithOffset(4),
473  MinAlign(Alignment, 4U), MMOFlags, AAInfo);
474 
475  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
476  }
477  }
478  }
479  return SDValue(nullptr, 0);
480 }
481 
482 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
483  StoreSDNode *ST = cast<StoreSDNode>(Node);
484  SDValue Chain = ST->getChain();
485  SDValue Ptr = ST->getBasePtr();
486  SDLoc dl(Node);
487 
488  unsigned Alignment = ST->getAlignment();
489  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
490  AAMDNodes AAInfo = ST->getAAInfo();
491 
492  if (!ST->isTruncatingStore()) {
493  LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
494  if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
495  ReplaceNode(ST, OptStore);
496  return;
497  }
498 
499  SDValue Value = ST->getValue();
500  MVT VT = Value.getSimpleValueType();
501  switch (TLI.getOperationAction(ISD::STORE, VT)) {
502  default: llvm_unreachable("This action is not supported yet!");
503  case TargetLowering::Legal: {
504  // If this is an unaligned store and the target doesn't support it,
505  // expand it.
506  EVT MemVT = ST->getMemoryVT();
507  const DataLayout &DL = DAG.getDataLayout();
508  if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
509  *ST->getMemOperand())) {
510  LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
511  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
512  ReplaceNode(SDValue(ST, 0), Result);
513  } else
514  LLVM_DEBUG(dbgs() << "Legal store\n");
515  break;
516  }
517  case TargetLowering::Custom: {
518  LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
519  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
520  if (Res && Res != SDValue(Node, 0))
521  ReplaceNode(SDValue(Node, 0), Res);
522  return;
523  }
525  MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
526  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
527  "Can only promote stores to same size type");
528  Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
529  SDValue Result =
530  DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
531  Alignment, MMOFlags, AAInfo);
532  ReplaceNode(SDValue(Node, 0), Result);
533  break;
534  }
535  }
536  return;
537  }
538 
539  LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
540  SDValue Value = ST->getValue();
541  EVT StVT = ST->getMemoryVT();
542  unsigned StWidth = StVT.getSizeInBits();
543  auto &DL = DAG.getDataLayout();
544 
545  if (StWidth != StVT.getStoreSizeInBits()) {
546  // Promote to a byte-sized store with upper bits zero if not
547  // storing an integral number of bytes. For example, promote
548  // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
549  EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
550  StVT.getStoreSizeInBits());
551  Value = DAG.getZeroExtendInReg(Value, dl, StVT);
552  SDValue Result =
553  DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
554  Alignment, MMOFlags, AAInfo);
555  ReplaceNode(SDValue(Node, 0), Result);
556  } else if (StWidth & (StWidth - 1)) {
557  // If not storing a power-of-2 number of bits, expand as two stores.
558  assert(!StVT.isVector() && "Unsupported truncstore!");
559  unsigned LogStWidth = Log2_32(StWidth);
560  assert(LogStWidth < 32);
561  unsigned RoundWidth = 1 << LogStWidth;
562  assert(RoundWidth < StWidth);
563  unsigned ExtraWidth = StWidth - RoundWidth;
564  assert(ExtraWidth < RoundWidth);
565  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
566  "Store size not an integral number of bytes!");
567  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
568  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
569  SDValue Lo, Hi;
570  unsigned IncrementSize;
571 
572  if (DL.isLittleEndian()) {
573  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
574  // Store the bottom RoundWidth bits.
575  Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
576  RoundVT, Alignment, MMOFlags, AAInfo);
577 
578  // Store the remaining ExtraWidth bits.
579  IncrementSize = RoundWidth / 8;
580  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
581  DAG.getConstant(IncrementSize, dl,
582  Ptr.getValueType()));
583  Hi = DAG.getNode(
584  ISD::SRL, dl, Value.getValueType(), Value,
585  DAG.getConstant(RoundWidth, dl,
586  TLI.getShiftAmountTy(Value.getValueType(), DL)));
587  Hi = DAG.getTruncStore(
588  Chain, dl, Hi, Ptr,
589  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
590  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
591  } else {
592  // Big endian - avoid unaligned stores.
593  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
594  // Store the top RoundWidth bits.
595  Hi = DAG.getNode(
596  ISD::SRL, dl, Value.getValueType(), Value,
597  DAG.getConstant(ExtraWidth, dl,
598  TLI.getShiftAmountTy(Value.getValueType(), DL)));
599  Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
600  RoundVT, Alignment, MMOFlags, AAInfo);
601 
602  // Store the remaining ExtraWidth bits.
603  IncrementSize = RoundWidth / 8;
604  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
605  DAG.getConstant(IncrementSize, dl,
606  Ptr.getValueType()));
607  Lo = DAG.getTruncStore(
608  Chain, dl, Value, Ptr,
609  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
610  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
611  }
612 
613  // The order of the stores doesn't matter.
614  SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
615  ReplaceNode(SDValue(Node, 0), Result);
616  } else {
617  switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
618  default: llvm_unreachable("This action is not supported yet!");
619  case TargetLowering::Legal: {
620  EVT MemVT = ST->getMemoryVT();
621  // If this is an unaligned store and the target doesn't support it,
622  // expand it.
623  if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
624  *ST->getMemOperand())) {
625  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
626  ReplaceNode(SDValue(ST, 0), Result);
627  }
628  break;
629  }
630  case TargetLowering::Custom: {
631  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
632  if (Res && Res != SDValue(Node, 0))
633  ReplaceNode(SDValue(Node, 0), Res);
634  return;
635  }
637  assert(!StVT.isVector() &&
638  "Vector Stores are handled in LegalizeVectorOps");
639 
640  SDValue Result;
641 
642  // TRUNCSTORE:i16 i32 -> STORE i16
643  if (TLI.isTypeLegal(StVT)) {
644  Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
645  Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
646  Alignment, MMOFlags, AAInfo);
647  } else {
648  // The in-memory type isn't legal. Truncate to the type it would promote
649  // to, and then do a truncstore.
650  Value = DAG.getNode(ISD::TRUNCATE, dl,
651  TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
652  Value);
653  Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
654  StVT, Alignment, MMOFlags, AAInfo);
655  }
656 
657  ReplaceNode(SDValue(Node, 0), Result);
658  break;
659  }
660  }
661 }
662 
663 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
664  LoadSDNode *LD = cast<LoadSDNode>(Node);
665  SDValue Chain = LD->getChain(); // The chain.
666  SDValue Ptr = LD->getBasePtr(); // The base pointer.
667  SDValue Value; // The value returned by the load op.
668  SDLoc dl(Node);
669 
671  if (ExtType == ISD::NON_EXTLOAD) {
672  LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
673  MVT VT = Node->getSimpleValueType(0);
674  SDValue RVal = SDValue(Node, 0);
675  SDValue RChain = SDValue(Node, 1);
676 
677  switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
678  default: llvm_unreachable("This action is not supported yet!");
679  case TargetLowering::Legal: {
680  EVT MemVT = LD->getMemoryVT();
681  const DataLayout &DL = DAG.getDataLayout();
682  // If this is an unaligned load and the target doesn't support it,
683  // expand it.
684  if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
685  *LD->getMemOperand())) {
686  std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
687  }
688  break;
689  }
691  if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
692  RVal = Res;
693  RChain = Res.getValue(1);
694  }
695  break;
696 
698  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
699  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
700  "Can only promote loads to same size type");
701 
702  SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
703  RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
704  RChain = Res.getValue(1);
705  break;
706  }
707  }
708  if (RChain.getNode() != Node) {
709  assert(RVal.getNode() != Node && "Load must be completely replaced");
710  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
711  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
712  if (UpdatedNodes) {
713  UpdatedNodes->insert(RVal.getNode());
714  UpdatedNodes->insert(RChain.getNode());
715  }
716  ReplacedNode(Node);
717  }
718  return;
719  }
720 
721  LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
722  EVT SrcVT = LD->getMemoryVT();
723  unsigned SrcWidth = SrcVT.getSizeInBits();
724  unsigned Alignment = LD->getAlignment();
725  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
726  AAMDNodes AAInfo = LD->getAAInfo();
727 
728  if (SrcWidth != SrcVT.getStoreSizeInBits() &&
729  // Some targets pretend to have an i1 loading operation, and actually
730  // load an i8. This trick is correct for ZEXTLOAD because the top 7
731  // bits are guaranteed to be zero; it helps the optimizers understand
732  // that these bits are zero. It is also useful for EXTLOAD, since it
733  // tells the optimizers that those bits are undefined. It would be
734  // nice to have an effective generic way of getting these benefits...
735  // Until such a way is found, don't insist on promoting i1 here.
736  (SrcVT != MVT::i1 ||
737  TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
739  // Promote to a byte-sized load if not loading an integral number of
740  // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
741  unsigned NewWidth = SrcVT.getStoreSizeInBits();
742  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
743  SDValue Ch;
744 
745  // The extra bits are guaranteed to be zero, since we stored them that
746  // way. A zext load from NVT thus automatically gives zext from SrcVT.
747 
748  ISD::LoadExtType NewExtType =
750 
751  SDValue Result =
752  DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Chain, Ptr,
753  LD->getPointerInfo(), NVT, Alignment, MMOFlags, AAInfo);
754 
755  Ch = Result.getValue(1); // The chain.
756 
757  if (ExtType == ISD::SEXTLOAD)
758  // Having the top bits zero doesn't help when sign extending.
759  Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
760  Result.getValueType(),
761  Result, DAG.getValueType(SrcVT));
762  else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
763  // All the top bits are guaranteed to be zero - inform the optimizers.
764  Result = DAG.getNode(ISD::AssertZext, dl,
765  Result.getValueType(), Result,
766  DAG.getValueType(SrcVT));
767 
768  Value = Result;
769  Chain = Ch;
770  } else if (SrcWidth & (SrcWidth - 1)) {
771  // If not loading a power-of-2 number of bits, expand as two loads.
772  assert(!SrcVT.isVector() && "Unsupported extload!");
773  unsigned LogSrcWidth = Log2_32(SrcWidth);
774  assert(LogSrcWidth < 32);
775  unsigned RoundWidth = 1 << LogSrcWidth;
776  assert(RoundWidth < SrcWidth);
777  unsigned ExtraWidth = SrcWidth - RoundWidth;
778  assert(ExtraWidth < RoundWidth);
779  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
780  "Load size not an integral number of bytes!");
781  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
782  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
783  SDValue Lo, Hi, Ch;
784  unsigned IncrementSize;
785  auto &DL = DAG.getDataLayout();
786 
787  if (DL.isLittleEndian()) {
788  // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
789  // Load the bottom RoundWidth bits.
790  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
791  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
792  AAInfo);
793 
794  // Load the remaining ExtraWidth bits.
795  IncrementSize = RoundWidth / 8;
796  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
797  DAG.getConstant(IncrementSize, dl,
798  Ptr.getValueType()));
799  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
800  LD->getPointerInfo().getWithOffset(IncrementSize),
801  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
802  AAInfo);
803 
804  // Build a factor node to remember that this load is independent of
805  // the other one.
806  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
807  Hi.getValue(1));
808 
809  // Move the top bits to the right place.
810  Hi = DAG.getNode(
811  ISD::SHL, dl, Hi.getValueType(), Hi,
812  DAG.getConstant(RoundWidth, dl,
813  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
814 
815  // Join the hi and lo parts.
816  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
817  } else {
818  // Big endian - avoid unaligned loads.
819  // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
820  // Load the top RoundWidth bits.
821  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
822  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
823  AAInfo);
824 
825  // Load the remaining ExtraWidth bits.
826  IncrementSize = RoundWidth / 8;
827  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
828  DAG.getConstant(IncrementSize, dl,
829  Ptr.getValueType()));
830  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
831  LD->getPointerInfo().getWithOffset(IncrementSize),
832  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
833  AAInfo);
834 
835  // Build a factor node to remember that this load is independent of
836  // the other one.
837  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
838  Hi.getValue(1));
839 
840  // Move the top bits to the right place.
841  Hi = DAG.getNode(
842  ISD::SHL, dl, Hi.getValueType(), Hi,
843  DAG.getConstant(ExtraWidth, dl,
844  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
845 
846  // Join the hi and lo parts.
847  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
848  }
849 
850  Chain = Ch;
851  } else {
852  bool isCustom = false;
853  switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
854  SrcVT.getSimpleVT())) {
855  default: llvm_unreachable("This action is not supported yet!");
857  isCustom = true;
860  Value = SDValue(Node, 0);
861  Chain = SDValue(Node, 1);
862 
863  if (isCustom) {
864  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
865  Value = Res;
866  Chain = Res.getValue(1);
867  }
868  } else {
869  // If this is an unaligned load and the target doesn't support it,
870  // expand it.
871  EVT MemVT = LD->getMemoryVT();
872  const DataLayout &DL = DAG.getDataLayout();
873  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT,
874  *LD->getMemOperand())) {
875  std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
876  }
877  }
878  break;
879 
880  case TargetLowering::Expand: {
881  EVT DestVT = Node->getValueType(0);
882  if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
883  // If the source type is not legal, see if there is a legal extload to
884  // an intermediate type that we can then extend further.
885  EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
886  if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
887  TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
888  // If we are loading a legal type, this is a non-extload followed by a
889  // full extend.
890  ISD::LoadExtType MidExtType =
891  (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
892 
893  SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
894  SrcVT, LD->getMemOperand());
895  unsigned ExtendOp =
897  Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
898  Chain = Load.getValue(1);
899  break;
900  }
901 
902  // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
903  // normal undefined upper bits behavior to allow using an in-reg extend
904  // with the illegal FP type, so load as an integer and do the
905  // from-integer conversion.
906  if (SrcVT.getScalarType() == MVT::f16) {
907  EVT ISrcVT = SrcVT.changeTypeToInteger();
908  EVT IDestVT = DestVT.changeTypeToInteger();
909  EVT ILoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
910 
911  SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, ILoadVT, Chain,
912  Ptr, ISrcVT, LD->getMemOperand());
913  Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
914  Chain = Result.getValue(1);
915  break;
916  }
917  }
918 
919  assert(!SrcVT.isVector() &&
920  "Vector Loads are handled in LegalizeVectorOps");
921 
922  // FIXME: This does not work for vectors on most targets. Sign-
923  // and zero-extend operations are currently folded into extending
924  // loads, whether they are legal or not, and then we end up here
925  // without any support for legalizing them.
926  assert(ExtType != ISD::EXTLOAD &&
927  "EXTLOAD should always be supported!");
928  // Turn the unsupported load into an EXTLOAD followed by an
929  // explicit zero/sign extend inreg.
930  SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
931  Node->getValueType(0),
932  Chain, Ptr, SrcVT,
933  LD->getMemOperand());
934  SDValue ValRes;
935  if (ExtType == ISD::SEXTLOAD)
936  ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
937  Result.getValueType(),
938  Result, DAG.getValueType(SrcVT));
939  else
940  ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
941  Value = ValRes;
942  Chain = Result.getValue(1);
943  break;
944  }
945  }
946  }
947 
948  // Since loads produce two values, make sure to remember that we legalized
949  // both of them.
950  if (Chain.getNode() != Node) {
951  assert(Value.getNode() != Node && "Load must be completely replaced");
952  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
953  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
954  if (UpdatedNodes) {
955  UpdatedNodes->insert(Value.getNode());
956  UpdatedNodes->insert(Chain.getNode());
957  }
958  ReplacedNode(Node);
959  }
960 }
961 
962 /// Return a legal replacement for the given operation, with all legal operands.
963 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
964  LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
965 
966  // Allow illegal target nodes and illegal registers.
967  if (Node->getOpcode() == ISD::TargetConstant ||
968  Node->getOpcode() == ISD::Register)
969  return;
970 
971 #ifndef NDEBUG
972  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
973  assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
975  "Unexpected illegal type!");
976 
977  for (const SDValue &Op : Node->op_values())
978  assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
980  Op.getOpcode() == ISD::TargetConstant ||
981  Op.getOpcode() == ISD::Register) &&
982  "Unexpected illegal type!");
983 #endif
984 
985  // Figure out the correct action; the way to query this varies by opcode
987  bool SimpleFinishLegalizing = true;
988  switch (Node->getOpcode()) {
991  case ISD::INTRINSIC_VOID:
992  case ISD::STACKSAVE:
993  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
994  break;
996  Action = TLI.getOperationAction(Node->getOpcode(),
997  Node->getValueType(0));
998  break;
999  case ISD::VAARG:
1000  Action = TLI.getOperationAction(Node->getOpcode(),
1001  Node->getValueType(0));
1002  if (Action != TargetLowering::Promote)
1003  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1004  break;
1005  case ISD::FP_TO_FP16:
1006  case ISD::SINT_TO_FP:
1007  case ISD::UINT_TO_FP:
1009  case ISD::LROUND:
1010  case ISD::LLROUND:
1011  case ISD::LRINT:
1012  case ISD::LLRINT:
1013  Action = TLI.getOperationAction(Node->getOpcode(),
1014  Node->getOperand(0).getValueType());
1015  break;
1016  case ISD::SIGN_EXTEND_INREG: {
1017  EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1018  Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1019  break;
1020  }
1021  case ISD::ATOMIC_STORE:
1022  Action = TLI.getOperationAction(Node->getOpcode(),
1023  Node->getOperand(2).getValueType());
1024  break;
1025  case ISD::SELECT_CC:
1026  case ISD::SETCC:
1027  case ISD::BR_CC: {
1028  unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1029  Node->getOpcode() == ISD::SETCC ? 2 : 1;
1030  unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1031  MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1032  ISD::CondCode CCCode =
1033  cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1034  Action = TLI.getCondCodeAction(CCCode, OpVT);
1035  if (Action == TargetLowering::Legal) {
1036  if (Node->getOpcode() == ISD::SELECT_CC)
1037  Action = TLI.getOperationAction(Node->getOpcode(),
1038  Node->getValueType(0));
1039  else
1040  Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1041  }
1042  break;
1043  }
1044  case ISD::LOAD:
1045  case ISD::STORE:
1046  // FIXME: Model these properly. LOAD and STORE are complicated, and
1047  // STORE expects the unlegalized operand in some cases.
1048  SimpleFinishLegalizing = false;
1049  break;
1050  case ISD::CALLSEQ_START:
1051  case ISD::CALLSEQ_END:
1052  // FIXME: This shouldn't be necessary. These nodes have special properties
1053  // dealing with the recursive nature of legalization. Removing this
1054  // special case should be done as part of making LegalizeDAG non-recursive.
1055  SimpleFinishLegalizing = false;
1056  break;
1057  case ISD::EXTRACT_ELEMENT:
1058  case ISD::FLT_ROUNDS_:
1059  case ISD::MERGE_VALUES:
1060  case ISD::EH_RETURN:
1062  case ISD::EH_DWARF_CFA:
1063  case ISD::EH_SJLJ_SETJMP:
1064  case ISD::EH_SJLJ_LONGJMP:
1066  // These operations lie about being legal: when they claim to be legal,
1067  // they should actually be expanded.
1068  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1069  if (Action == TargetLowering::Legal)
1070  Action = TargetLowering::Expand;
1071  break;
1072  case ISD::INIT_TRAMPOLINE:
1074  case ISD::FRAMEADDR:
1075  case ISD::RETURNADDR:
1076  case ISD::ADDROFRETURNADDR:
1077  case ISD::SPONENTRY:
1078  // These operations lie about being legal: when they claim to be legal,
1079  // they should actually be custom-lowered.
1080  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1081  if (Action == TargetLowering::Legal)
1082  Action = TargetLowering::Custom;
1083  break;
1084  case ISD::READCYCLECOUNTER:
1085  // READCYCLECOUNTER returns an i64, even if type legalization might have
1086  // expanded that to several smaller types.
1087  Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1088  break;
1089  case ISD::READ_REGISTER:
1090  case ISD::WRITE_REGISTER:
1091  // Named register is legal in the DAG, but blocked by register name
1092  // selection if not implemented by target (to chose the correct register)
1093  // They'll be converted to Copy(To/From)Reg.
1094  Action = TargetLowering::Legal;
1095  break;
1096  case ISD::DEBUGTRAP:
1097  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1098  if (Action == TargetLowering::Expand) {
1099  // replace ISD::DEBUGTRAP with ISD::TRAP
1100  SDValue NewVal;
1101  NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1102  Node->getOperand(0));
1103  ReplaceNode(Node, NewVal.getNode());
1104  LegalizeOp(NewVal.getNode());
1105  return;
1106  }
1107  break;
1108  case ISD::STRICT_LRINT:
1109  case ISD::STRICT_LLRINT:
1110  case ISD::STRICT_LROUND:
1111  case ISD::STRICT_LLROUND:
1112  // These pseudo-ops are the same as the other STRICT_ ops except
1113  // they are registered with setOperationAction() using the input type
1114  // instead of the output type.
1115  Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
1116  Node->getOperand(1).getValueType());
1117  break;
1118  case ISD::SADDSAT:
1119  case ISD::UADDSAT:
1120  case ISD::SSUBSAT:
1121  case ISD::USUBSAT: {
1122  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1123  break;
1124  }
1125  case ISD::SMULFIX:
1126  case ISD::SMULFIXSAT:
1127  case ISD::UMULFIX:
1128  case ISD::UMULFIXSAT: {
1129  unsigned Scale = Node->getConstantOperandVal(2);
1130  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
1131  Node->getValueType(0), Scale);
1132  break;
1133  }
1134  case ISD::MSCATTER:
1135  Action = TLI.getOperationAction(Node->getOpcode(),
1136  cast<MaskedScatterSDNode>(Node)->getValue().getValueType());
1137  break;
1138  case ISD::MSTORE:
1139  Action = TLI.getOperationAction(Node->getOpcode(),
1140  cast<MaskedStoreSDNode>(Node)->getValue().getValueType());
1141  break;
1142  case ISD::VECREDUCE_FADD:
1143  case ISD::VECREDUCE_FMUL:
1144  case ISD::VECREDUCE_ADD:
1145  case ISD::VECREDUCE_MUL:
1146  case ISD::VECREDUCE_AND:
1147  case ISD::VECREDUCE_OR:
1148  case ISD::VECREDUCE_XOR:
1149  case ISD::VECREDUCE_SMAX:
1150  case ISD::VECREDUCE_SMIN:
1151  case ISD::VECREDUCE_UMAX:
1152  case ISD::VECREDUCE_UMIN:
1153  case ISD::VECREDUCE_FMAX:
1154  case ISD::VECREDUCE_FMIN:
1155  Action = TLI.getOperationAction(
1156  Node->getOpcode(), Node->getOperand(0).getValueType());
1157  break;
1158  default:
1159  if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1160  Action = TargetLowering::Legal;
1161  } else {
1162  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1163  }
1164  break;
1165  }
1166 
1167  if (SimpleFinishLegalizing) {
1168  SDNode *NewNode = Node;
1169  switch (Node->getOpcode()) {
1170  default: break;
1171  case ISD::SHL:
1172  case ISD::SRL:
1173  case ISD::SRA:
1174  case ISD::ROTL:
1175  case ISD::ROTR: {
1176  // Legalizing shifts/rotates requires adjusting the shift amount
1177  // to the appropriate width.
1178  SDValue Op0 = Node->getOperand(0);
1179  SDValue Op1 = Node->getOperand(1);
1180  if (!Op1.getValueType().isVector()) {
1181  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1182  // The getShiftAmountOperand() may create a new operand node or
1183  // return the existing one. If new operand is created we need
1184  // to update the parent node.
1185  // Do not try to legalize SAO here! It will be automatically legalized
1186  // in the next round.
1187  if (SAO != Op1)
1188  NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1189  }
1190  }
1191  break;
1192  case ISD::FSHL:
1193  case ISD::FSHR:
1194  case ISD::SRL_PARTS:
1195  case ISD::SRA_PARTS:
1196  case ISD::SHL_PARTS: {
1197  // Legalizing shifts/rotates requires adjusting the shift amount
1198  // to the appropriate width.
1199  SDValue Op0 = Node->getOperand(0);
1200  SDValue Op1 = Node->getOperand(1);
1201  SDValue Op2 = Node->getOperand(2);
1202  if (!Op2.getValueType().isVector()) {
1203  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1204  // The getShiftAmountOperand() may create a new operand node or
1205  // return the existing one. If new operand is created we need
1206  // to update the parent node.
1207  if (SAO != Op2)
1208  NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1209  }
1210  break;
1211  }
1212  }
1213 
1214  if (NewNode != Node) {
1215  ReplaceNode(Node, NewNode);
1216  Node = NewNode;
1217  }
1218  switch (Action) {
1219  case TargetLowering::Legal:
1220  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1221  return;
1223  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1224  // FIXME: The handling for custom lowering with multiple results is
1225  // a complete mess.
1226  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1227  if (!(Res.getNode() != Node || Res.getResNo() != 0))
1228  return;
1229 
1230  if (Node->getNumValues() == 1) {
1231  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1232  // We can just directly replace this node with the lowered value.
1233  ReplaceNode(SDValue(Node, 0), Res);
1234  return;
1235  }
1236 
1237  SmallVector<SDValue, 8> ResultVals;
1238  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1239  ResultVals.push_back(Res.getValue(i));
1240  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1241  ReplaceNode(Node, ResultVals.data());
1242  return;
1243  }
1244  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1247  if (ExpandNode(Node))
1248  return;
1251  ConvertNodeToLibcall(Node);
1252  return;
1254  PromoteNode(Node);
1255  return;
1256  }
1257  }
1258 
1259  switch (Node->getOpcode()) {
1260  default:
1261 #ifndef NDEBUG
1262  dbgs() << "NODE: ";
1263  Node->dump( &DAG);
1264  dbgs() << "\n";
1265 #endif
1266  llvm_unreachable("Do not know how to legalize this operator!");
1267 
1268  case ISD::CALLSEQ_START:
1269  case ISD::CALLSEQ_END:
1270  break;
1271  case ISD::LOAD:
1272  return LegalizeLoadOps(Node);
1273  case ISD::STORE:
1274  return LegalizeStoreOps(Node);
1275  }
1276 }
1277 
1278 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1279  SDValue Vec = Op.getOperand(0);
1280  SDValue Idx = Op.getOperand(1);
1281  SDLoc dl(Op);
1282 
1283  // Before we generate a new store to a temporary stack slot, see if there is
1284  // already one that we can use. There often is because when we scalarize
1285  // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1286  // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1287  // the vector. If all are expanded here, we don't want one store per vector
1288  // element.
1289 
1290  // Caches for hasPredecessorHelper
1293  Visited.insert(Op.getNode());
1294  Worklist.push_back(Idx.getNode());
1295  SDValue StackPtr, Ch;
1296  for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1297  UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1298  SDNode *User = *UI;
1299  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1300  if (ST->isIndexed() || ST->isTruncatingStore() ||
1301  ST->getValue() != Vec)
1302  continue;
1303 
1304  // Make sure that nothing else could have stored into the destination of
1305  // this store.
1306  if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1307  continue;
1308 
1309  // If the index is dependent on the store we will introduce a cycle when
1310  // creating the load (the load uses the index, and by replacing the chain
1311  // we will make the index dependent on the load). Also, the store might be
1312  // dependent on the extractelement and introduce a cycle when creating
1313  // the load.
1314  if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
1315  ST->hasPredecessor(Op.getNode()))
1316  continue;
1317 
1318  StackPtr = ST->getBasePtr();
1319  Ch = SDValue(ST, 0);
1320  break;
1321  }
1322  }
1323 
1324  EVT VecVT = Vec.getValueType();
1325 
1326  if (!Ch.getNode()) {
1327  // Store the value to a temporary stack slot, then LOAD the returned part.
1328  StackPtr = DAG.CreateStackTemporary(VecVT);
1329  Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1330  MachinePointerInfo());
1331  }
1332 
1333  StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1334 
1335  SDValue NewLoad;
1336 
1337  if (Op.getValueType().isVector())
1338  NewLoad =
1339  DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, MachinePointerInfo());
1340  else
1341  NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1343  VecVT.getVectorElementType());
1344 
1345  // Replace the chain going out of the store, by the one out of the load.
1346  DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1347 
1348  // We introduced a cycle though, so update the loads operands, making sure
1349  // to use the original store's chain as an incoming chain.
1350  SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1351  NewLoad->op_end());
1352  NewLoadOperands[0] = Ch;
1353  NewLoad =
1354  SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1355  return NewLoad;
1356 }
1357 
1358 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1359  assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1360 
1361  SDValue Vec = Op.getOperand(0);
1362  SDValue Part = Op.getOperand(1);
1363  SDValue Idx = Op.getOperand(2);
1364  SDLoc dl(Op);
1365 
1366  // Store the value to a temporary stack slot, then LOAD the returned part.
1367  EVT VecVT = Vec.getValueType();
1368  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1369  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1370  MachinePointerInfo PtrInfo =
1371  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1372 
1373  // First store the whole vector.
1374  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1375 
1376  // Then store the inserted part.
1377  SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1378 
1379  // Store the subvector.
1380  Ch = DAG.getStore(Ch, dl, Part, SubStackPtr, MachinePointerInfo());
1381 
1382  // Finally, load the updated vector.
1383  return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1384 }
1385 
1386 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1387  // We can't handle this case efficiently. Allocate a sufficiently
1388  // aligned object on the stack, store each element into it, then load
1389  // the result as a vector.
1390  // Create the stack frame object.
1391  EVT VT = Node->getValueType(0);
1392  EVT EltVT = VT.getVectorElementType();
1393  SDLoc dl(Node);
1394  SDValue FIPtr = DAG.CreateStackTemporary(VT);
1395  int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1396  MachinePointerInfo PtrInfo =
1397  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1398 
1399  // Emit a store of each element to the stack slot.
1400  SmallVector<SDValue, 8> Stores;
1401  unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1402  assert(TypeByteSize > 0 && "Vector element type too small for stack store!");
1403  // Store (in the right endianness) the elements to memory.
1404  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1405  // Ignore undef elements.
1406  if (Node->getOperand(i).isUndef()) continue;
1407 
1408  unsigned Offset = TypeByteSize*i;
1409 
1410  SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1411  Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1412 
1413  // If the destination vector element type is narrower than the source
1414  // element type, only store the bits necessary.
1415  if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1416  Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1417  Node->getOperand(i), Idx,
1418  PtrInfo.getWithOffset(Offset), EltVT));
1419  } else
1420  Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1421  Idx, PtrInfo.getWithOffset(Offset)));
1422  }
1423 
1424  SDValue StoreChain;
1425  if (!Stores.empty()) // Not all undef elements?
1426  StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1427  else
1428  StoreChain = DAG.getEntryNode();
1429 
1430  // Result is a load from the stack slot.
1431  return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1432 }
1433 
1434 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1435 /// containing the sign bit if the target has no integer value capable of
1436 /// holding all bits of the floating-point value.
1437 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1438  const SDLoc &DL,
1439  SDValue Value) const {
1440  EVT FloatVT = Value.getValueType();
1441  unsigned NumBits = FloatVT.getSizeInBits();
1442  State.FloatVT = FloatVT;
1443  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1444  // Convert to an integer of the same size.
1445  if (TLI.isTypeLegal(IVT)) {
1446  State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1447  State.SignMask = APInt::getSignMask(NumBits);
1448  State.SignBit = NumBits - 1;
1449  return;
1450  }
1451 
1452  auto &DataLayout = DAG.getDataLayout();
1453  // Store the float to memory, then load the sign part out as an integer.
1454  MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1455  // First create a temporary that is aligned for both the load and store.
1456  SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1457  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1458  // Then store the float to it.
1459  State.FloatPtr = StackPtr;
1460  MachineFunction &MF = DAG.getMachineFunction();
1461  State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1462  State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1463  State.FloatPointerInfo);
1464 
1465  SDValue IntPtr;
1466  if (DataLayout.isBigEndian()) {
1467  assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1468  // Load out a legal integer with the same sign bit as the float.
1469  IntPtr = StackPtr;
1470  State.IntPointerInfo = State.FloatPointerInfo;
1471  } else {
1472  // Advance the pointer so that the loaded byte will contain the sign bit.
1473  unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1474  IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1475  DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1476  State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1477  ByteOffset);
1478  }
1479 
1480  State.IntPtr = IntPtr;
1481  State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1482  State.IntPointerInfo, MVT::i8);
1483  State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1484  State.SignBit = 7;
1485 }
1486 
1487 /// Replace the integer value produced by getSignAsIntValue() with a new value
1488 /// and cast the result back to a floating-point type.
1489 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1490  const SDLoc &DL,
1491  SDValue NewIntValue) const {
1492  if (!State.Chain)
1493  return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1494 
1495  // Override the part containing the sign bit in the value stored on the stack.
1496  SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1497  State.IntPointerInfo, MVT::i8);
1498  return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1499  State.FloatPointerInfo);
1500 }
1501 
1502 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1503  SDLoc DL(Node);
1504  SDValue Mag = Node->getOperand(0);
1505  SDValue Sign = Node->getOperand(1);
1506 
1507  // Get sign bit into an integer value.
1508  FloatSignAsInt SignAsInt;
1509  getSignAsIntValue(SignAsInt, DL, Sign);
1510 
1511  EVT IntVT = SignAsInt.IntValue.getValueType();
1512  SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1513  SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1514  SignMask);
1515 
1516  // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1517  EVT FloatVT = Mag.getValueType();
1518  if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1519  TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1520  SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1521  SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1522  SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1523  DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1524  return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1525  }
1526 
1527  // Transform Mag value to integer, and clear the sign bit.
1528  FloatSignAsInt MagAsInt;
1529  getSignAsIntValue(MagAsInt, DL, Mag);
1530  EVT MagVT = MagAsInt.IntValue.getValueType();
1531  SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1532  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1533  ClearSignMask);
1534 
1535  // Get the signbit at the right position for MagAsInt.
1536  int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1537  EVT ShiftVT = IntVT;
1538  if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1539  SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1540  ShiftVT = MagVT;
1541  }
1542  if (ShiftAmount > 0) {
1543  SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1544  SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst);
1545  } else if (ShiftAmount < 0) {
1546  SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
1547  SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
1548  }
1549  if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1550  SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1551  }
1552 
1553  // Store the part with the modified sign and convert back to float.
1554  SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1555  return modifySignAsInt(MagAsInt, DL, CopiedSign);
1556 }
1557 
1558 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1559  SDLoc DL(Node);
1560  SDValue Value = Node->getOperand(0);
1561 
1562  // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1563  EVT FloatVT = Value.getValueType();
1564  if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1565  SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1566  return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1567  }
1568 
1569  // Transform value to integer, clear the sign bit and transform back.
1570  FloatSignAsInt ValueAsInt;
1571  getSignAsIntValue(ValueAsInt, DL, Value);
1572  EVT IntVT = ValueAsInt.IntValue.getValueType();
1573  SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1574  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1575  ClearSignMask);
1576  return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1577 }
1578 
1579 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1581  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1582  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1583  " not tell us which reg is the stack pointer!");
1584  SDLoc dl(Node);
1585  EVT VT = Node->getValueType(0);
1586  SDValue Tmp1 = SDValue(Node, 0);
1587  SDValue Tmp2 = SDValue(Node, 1);
1588  SDValue Tmp3 = Node->getOperand(2);
1589  SDValue Chain = Tmp1.getOperand(0);
1590 
1591  // Chain the dynamic stack allocation so that it doesn't modify the stack
1592  // pointer when other instructions are using the stack.
1593  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1594 
1595  SDValue Size = Tmp2.getOperand(1);
1596  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1597  Chain = SP.getValue(1);
1598  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1599  unsigned StackAlign =
1600  DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1601  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1602  if (Align > StackAlign)
1603  Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1604  DAG.getConstant(-(uint64_t)Align, dl, VT));
1605  Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1606 
1607  Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1608  DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1609 
1610  Results.push_back(Tmp1);
1611  Results.push_back(Tmp2);
1612 }
1613 
1614 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1615 /// target.
1616 ///
1617 /// If the SETCC has been legalized using AND / OR, then the legalized node
1618 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1619 /// will be set to false.
1620 ///
1621 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1622 /// then the values of LHS and RHS will be swapped, CC will be set to the
1623 /// new condition, and NeedInvert will be set to false.
1624 ///
1625 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1626 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1627 /// will be set to true. The caller must invert the result of the SETCC with
1628 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1629 /// of a true/false result.
1630 ///
1631 /// \returns true if the SetCC has been legalized, false if it hasn't.
1632 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1633  SDValue &RHS, SDValue &CC,
1634  bool &NeedInvert,
1635  const SDLoc &dl) {
1636  MVT OpVT = LHS.getSimpleValueType();
1637  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1638  NeedInvert = false;
1639  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1640  default: llvm_unreachable("Unknown condition code action!");
1641  case TargetLowering::Legal:
1642  // Nothing to do.
1643  break;
1644  case TargetLowering::Expand: {
1646  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1647  std::swap(LHS, RHS);
1648  CC = DAG.getCondCode(InvCC);
1649  return true;
1650  }
1651  // Swapping operands didn't work. Try inverting the condition.
1652  bool NeedSwap = false;
1653  InvCC = getSetCCInverse(CCCode, OpVT.isInteger());
1654  if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1655  // If inverting the condition is not enough, try swapping operands
1656  // on top of it.
1657  InvCC = ISD::getSetCCSwappedOperands(InvCC);
1658  NeedSwap = true;
1659  }
1660  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1661  CC = DAG.getCondCode(InvCC);
1662  NeedInvert = true;
1663  if (NeedSwap)
1664  std::swap(LHS, RHS);
1665  return true;
1666  }
1667 
1669  unsigned Opc = 0;
1670  switch (CCCode) {
1671  default: llvm_unreachable("Don't know how to expand this condition!");
1672  case ISD::SETO:
1673  assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
1674  && "If SETO is expanded, SETOEQ must be legal!");
1675  CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1676  case ISD::SETUO:
1677  assert(TLI.isCondCodeLegal(ISD::SETUNE, OpVT)
1678  && "If SETUO is expanded, SETUNE must be legal!");
1679  CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1680  case ISD::SETOEQ:
1681  case ISD::SETOGT:
1682  case ISD::SETOGE:
1683  case ISD::SETOLT:
1684  case ISD::SETOLE:
1685  case ISD::SETONE:
1686  case ISD::SETUEQ:
1687  case ISD::SETUNE:
1688  case ISD::SETUGT:
1689  case ISD::SETUGE:
1690  case ISD::SETULT:
1691  case ISD::SETULE:
1692  // If we are floating point, assign and break, otherwise fall through.
1693  if (!OpVT.isInteger()) {
1694  // We can use the 4th bit to tell if we are the unordered
1695  // or ordered version of the opcode.
1696  CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1697  Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1698  CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1699  break;
1700  }
1701  // Fallthrough if we are unsigned integer.
1703  case ISD::SETLE:
1704  case ISD::SETGT:
1705  case ISD::SETGE:
1706  case ISD::SETLT:
1707  case ISD::SETNE:
1708  case ISD::SETEQ:
1709  // If all combinations of inverting the condition and swapping operands
1710  // didn't work then we have no means to expand the condition.
1711  llvm_unreachable("Don't know how to expand this condition!");
1712  }
1713 
1714  SDValue SetCC1, SetCC2;
1715  if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1716  // If we aren't the ordered or unorder operation,
1717  // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1718  SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1719  SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1720  } else {
1721  // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1722  SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1723  SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1724  }
1725  LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1726  RHS = SDValue();
1727  CC = SDValue();
1728  return true;
1729  }
1730  }
1731  return false;
1732 }
1733 
1734 /// Emit a store/load combination to the stack. This stores
1735 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1736 /// a load from the stack slot to DestVT, extending it if needed.
1737 /// The resultant code need not be legal.
1738 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1739  EVT DestVT, const SDLoc &dl) {
1740  return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode());
1741 }
1742 
1743 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1744  EVT DestVT, const SDLoc &dl,
1745  SDValue Chain) {
1746  // Create the stack frame object.
1747  unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1748  SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1749  SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1750 
1751  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1752  int SPFI = StackPtrFI->getIndex();
1753  MachinePointerInfo PtrInfo =
1754  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1755 
1756  unsigned SrcSize = SrcOp.getValueSizeInBits();
1757  unsigned SlotSize = SlotVT.getSizeInBits();
1758  unsigned DestSize = DestVT.getSizeInBits();
1759  Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1760  unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1761 
1762  // Emit a store to the stack slot. Use a truncstore if the input value is
1763  // later than DestVT.
1764  SDValue Store;
1765 
1766  if (SrcSize > SlotSize)
1767  Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo,
1768  SlotVT, SrcAlign);
1769  else {
1770  assert(SrcSize == SlotSize && "Invalid store");
1771  Store =
1772  DAG.getStore(Chain, dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1773  }
1774 
1775  // Result is a load from the stack slot.
1776  if (SlotSize == DestSize)
1777  return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1778 
1779  assert(SlotSize < DestSize && "Unknown extension!");
1780  return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1781  DestAlign);
1782 }
1783 
1784 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1785  SDLoc dl(Node);
1786  // Create a vector sized/aligned stack slot, store the value to element #0,
1787  // then load the whole vector back out.
1788  SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1789 
1790  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1791  int SPFI = StackPtrFI->getIndex();
1792 
1793  SDValue Ch = DAG.getTruncStore(
1794  DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1795  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1796  Node->getValueType(0).getVectorElementType());
1797  return DAG.getLoad(
1798  Node->getValueType(0), dl, Ch, StackPtr,
1799  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1800 }
1801 
1802 static bool
1804  const TargetLowering &TLI, SDValue &Res) {
1805  unsigned NumElems = Node->getNumOperands();
1806  SDLoc dl(Node);
1807  EVT VT = Node->getValueType(0);
1808 
1809  // Try to group the scalars into pairs, shuffle the pairs together, then
1810  // shuffle the pairs of pairs together, etc. until the vector has
1811  // been built. This will work only if all of the necessary shuffle masks
1812  // are legal.
1813 
1814  // We do this in two phases; first to check the legality of the shuffles,
1815  // and next, assuming that all shuffles are legal, to create the new nodes.
1816  for (int Phase = 0; Phase < 2; ++Phase) {
1818  NewIntermedVals;
1819  for (unsigned i = 0; i < NumElems; ++i) {
1820  SDValue V = Node->getOperand(i);
1821  if (V.isUndef())
1822  continue;
1823 
1824  SDValue Vec;
1825  if (Phase)
1826  Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1827  IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1828  }
1829 
1830  while (IntermedVals.size() > 2) {
1831  NewIntermedVals.clear();
1832  for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1833  // This vector and the next vector are shuffled together (simply to
1834  // append the one to the other).
1835  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1836 
1837  SmallVector<int, 16> FinalIndices;
1838  FinalIndices.reserve(IntermedVals[i].second.size() +
1839  IntermedVals[i+1].second.size());
1840 
1841  int k = 0;
1842  for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1843  ++j, ++k) {
1844  ShuffleVec[k] = j;
1845  FinalIndices.push_back(IntermedVals[i].second[j]);
1846  }
1847  for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1848  ++j, ++k) {
1849  ShuffleVec[k] = NumElems + j;
1850  FinalIndices.push_back(IntermedVals[i+1].second[j]);
1851  }
1852 
1853  SDValue Shuffle;
1854  if (Phase)
1855  Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1856  IntermedVals[i+1].first,
1857  ShuffleVec);
1858  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1859  return false;
1860  NewIntermedVals.push_back(
1861  std::make_pair(Shuffle, std::move(FinalIndices)));
1862  }
1863 
1864  // If we had an odd number of defined values, then append the last
1865  // element to the array of new vectors.
1866  if ((IntermedVals.size() & 1) != 0)
1867  NewIntermedVals.push_back(IntermedVals.back());
1868 
1869  IntermedVals.swap(NewIntermedVals);
1870  }
1871 
1872  assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1873  "Invalid number of intermediate vectors");
1874  SDValue Vec1 = IntermedVals[0].first;
1875  SDValue Vec2;
1876  if (IntermedVals.size() > 1)
1877  Vec2 = IntermedVals[1].first;
1878  else if (Phase)
1879  Vec2 = DAG.getUNDEF(VT);
1880 
1881  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1882  for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1883  ShuffleVec[IntermedVals[0].second[i]] = i;
1884  for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1885  ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1886 
1887  if (Phase)
1888  Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1889  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1890  return false;
1891  }
1892 
1893  return true;
1894 }
1895 
1896 /// Expand a BUILD_VECTOR node on targets that don't
1897 /// support the operation, but do support the resultant vector type.
1898 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1899  unsigned NumElems = Node->getNumOperands();
1900  SDValue Value1, Value2;
1901  SDLoc dl(Node);
1902  EVT VT = Node->getValueType(0);
1903  EVT OpVT = Node->getOperand(0).getValueType();
1904  EVT EltVT = VT.getVectorElementType();
1905 
1906  // If the only non-undef value is the low element, turn this into a
1907  // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1908  bool isOnlyLowElement = true;
1909  bool MoreThanTwoValues = false;
1910  bool isConstant = true;
1911  for (unsigned i = 0; i < NumElems; ++i) {
1912  SDValue V = Node->getOperand(i);
1913  if (V.isUndef())
1914  continue;
1915  if (i > 0)
1916  isOnlyLowElement = false;
1917  if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1918  isConstant = false;
1919 
1920  if (!Value1.getNode()) {
1921  Value1 = V;
1922  } else if (!Value2.getNode()) {
1923  if (V != Value1)
1924  Value2 = V;
1925  } else if (V != Value1 && V != Value2) {
1926  MoreThanTwoValues = true;
1927  }
1928  }
1929 
1930  if (!Value1.getNode())
1931  return DAG.getUNDEF(VT);
1932 
1933  if (isOnlyLowElement)
1934  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1935 
1936  // If all elements are constants, create a load from the constant pool.
1937  if (isConstant) {
1939  for (unsigned i = 0, e = NumElems; i != e; ++i) {
1940  if (ConstantFPSDNode *V =
1941  dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1942  CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1943  } else if (ConstantSDNode *V =
1944  dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1945  if (OpVT==EltVT)
1946  CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1947  else {
1948  // If OpVT and EltVT don't match, EltVT is not legal and the
1949  // element values have been promoted/truncated earlier. Undo this;
1950  // we don't want a v16i8 to become a v16i32 for example.
1951  const ConstantInt *CI = V->getConstantIntValue();
1952  CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1953  CI->getZExtValue()));
1954  }
1955  } else {
1956  assert(Node->getOperand(i).isUndef());
1957  Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1958  CV.push_back(UndefValue::get(OpNTy));
1959  }
1960  }
1961  Constant *CP = ConstantVector::get(CV);
1962  SDValue CPIdx =
1963  DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1964  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1965  return DAG.getLoad(
1966  VT, dl, DAG.getEntryNode(), CPIdx,
1967  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1968  Alignment);
1969  }
1970 
1971  SmallSet<SDValue, 16> DefinedValues;
1972  for (unsigned i = 0; i < NumElems; ++i) {
1973  if (Node->getOperand(i).isUndef())
1974  continue;
1975  DefinedValues.insert(Node->getOperand(i));
1976  }
1977 
1978  if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1979  if (!MoreThanTwoValues) {
1980  SmallVector<int, 8> ShuffleVec(NumElems, -1);
1981  for (unsigned i = 0; i < NumElems; ++i) {
1982  SDValue V = Node->getOperand(i);
1983  if (V.isUndef())
1984  continue;
1985  ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1986  }
1987  if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1988  // Get the splatted value into the low element of a vector register.
1989  SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1990  SDValue Vec2;
1991  if (Value2.getNode())
1992  Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1993  else
1994  Vec2 = DAG.getUNDEF(VT);
1995 
1996  // Return shuffle(LowValVec, undef, <0,0,0,0>)
1997  return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1998  }
1999  } else {
2000  SDValue Res;
2001  if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2002  return Res;
2003  }
2004  }
2005 
2006  // Otherwise, we can't handle this case efficiently.
2007  return ExpandVectorBuildThroughStack(Node);
2008 }
2009 
2010 SDValue SelectionDAGLegalize::ExpandSPLAT_VECTOR(SDNode *Node) {
2011  SDLoc DL(Node);
2012  EVT VT = Node->getValueType(0);
2013  SDValue SplatVal = Node->getOperand(0);
2014 
2015  return DAG.getSplatBuildVector(VT, DL, SplatVal);
2016 }
2017 
2018 // Expand a node into a call to a libcall. If the result value
2019 // does not fit into a register, return the lo part and set the hi part to the
2020 // by-reg argument. If it does fit into a single register, return the result
2021 // and leave the Hi part unset.
2022 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2023  bool isSigned) {
2025  TargetLowering::ArgListEntry Entry;
2026  for (const SDValue &Op : Node->op_values()) {
2027  EVT ArgVT = Op.getValueType();
2028  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2029  Entry.Node = Op;
2030  Entry.Ty = ArgTy;
2031  Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2032  Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2033  Args.push_back(Entry);
2034  }
2035  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2036  TLI.getPointerTy(DAG.getDataLayout()));
2037 
2038  EVT RetVT = Node->getValueType(0);
2039  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2040 
2041  // By default, the input chain to this libcall is the entry node of the
2042  // function. If the libcall is going to be emitted as a tail call then
2043  // TLI.isUsedByReturnOnly will change it to the right chain if the return
2044  // node which is being folded has a non-entry input chain.
2045  SDValue InChain = DAG.getEntryNode();
2046 
2047  // isTailCall may be true since the callee does not reference caller stack
2048  // frame. Check if it's in the right position and that the return types match.
2049  SDValue TCChain = InChain;
2050  const Function &F = DAG.getMachineFunction().getFunction();
2051  bool isTailCall =
2052  TLI.isInTailCallPosition(DAG, Node, TCChain) &&
2053  (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2054  if (isTailCall)
2055  InChain = TCChain;
2056 
2058  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2059  CLI.setDebugLoc(SDLoc(Node))
2060  .setChain(InChain)
2061  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2062  std::move(Args))
2063  .setTailCall(isTailCall)
2064  .setSExtResult(signExtend)
2065  .setZExtResult(!signExtend)
2067 
2068  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2069 
2070  if (!CallInfo.second.getNode()) {
2071  LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump(&DAG));
2072  // It's a tailcall, return the chain (which is the DAG root).
2073  return DAG.getRoot();
2074  }
2075 
2076  LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump(&DAG));
2077  return CallInfo.first;
2078 }
2079 
2080 // Expand a node into a call to a libcall. Similar to
2081 // ExpandLibCall except that the first operand is the in-chain.
2082 std::pair<SDValue, SDValue>
2083 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2084  SDNode *Node,
2085  bool isSigned) {
2086  SDValue InChain = Node->getOperand(0);
2087 
2089  TargetLowering::ArgListEntry Entry;
2090  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2091  EVT ArgVT = Node->getOperand(i).getValueType();
2092  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2093  Entry.Node = Node->getOperand(i);
2094  Entry.Ty = ArgTy;
2095  Entry.IsSExt = isSigned;
2096  Entry.IsZExt = !isSigned;
2097  Args.push_back(Entry);
2098  }
2099  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2100  TLI.getPointerTy(DAG.getDataLayout()));
2101 
2102  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2103 
2105  CLI.setDebugLoc(SDLoc(Node))
2106  .setChain(InChain)
2107  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2108  std::move(Args))
2109  .setSExtResult(isSigned)
2110  .setZExtResult(!isSigned);
2111 
2112  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2113 
2114  return CallInfo;
2115 }
2116 
2117 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2118  RTLIB::Libcall Call_F32,
2119  RTLIB::Libcall Call_F64,
2120  RTLIB::Libcall Call_F80,
2121  RTLIB::Libcall Call_F128,
2122  RTLIB::Libcall Call_PPCF128) {
2123  if (Node->isStrictFPOpcode())
2124  Node = DAG.mutateStrictFPToFP(Node);
2125 
2126  RTLIB::Libcall LC;
2127  switch (Node->getSimpleValueType(0).SimpleTy) {
2128  default: llvm_unreachable("Unexpected request for libcall!");
2129  case MVT::f32: LC = Call_F32; break;
2130  case MVT::f64: LC = Call_F64; break;
2131  case MVT::f80: LC = Call_F80; break;
2132  case MVT::f128: LC = Call_F128; break;
2133  case MVT::ppcf128: LC = Call_PPCF128; break;
2134  }
2135  return ExpandLibCall(LC, Node, false);
2136 }
2137 
2138 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2139  RTLIB::Libcall Call_I8,
2140  RTLIB::Libcall Call_I16,
2141  RTLIB::Libcall Call_I32,
2142  RTLIB::Libcall Call_I64,
2143  RTLIB::Libcall Call_I128) {
2144  RTLIB::Libcall LC;
2145  switch (Node->getSimpleValueType(0).SimpleTy) {
2146  default: llvm_unreachable("Unexpected request for libcall!");
2147  case MVT::i8: LC = Call_I8; break;
2148  case MVT::i16: LC = Call_I16; break;
2149  case MVT::i32: LC = Call_I32; break;
2150  case MVT::i64: LC = Call_I64; break;
2151  case MVT::i128: LC = Call_I128; break;
2152  }
2153  return ExpandLibCall(LC, Node, isSigned);
2154 }
2155 
2156 /// Expand the node to a libcall based on first argument type (for instance
2157 /// lround and its variant).
2158 SDValue SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
2159  RTLIB::Libcall Call_F32,
2160  RTLIB::Libcall Call_F64,
2161  RTLIB::Libcall Call_F80,
2162  RTLIB::Libcall Call_F128,
2163  RTLIB::Libcall Call_PPCF128) {
2164  if (Node->isStrictFPOpcode())
2165  Node = DAG.mutateStrictFPToFP(Node);
2166 
2167  RTLIB::Libcall LC;
2168  switch (Node->getOperand(0).getValueType().getSimpleVT().SimpleTy) {
2169  default: llvm_unreachable("Unexpected request for libcall!");
2170  case MVT::f32: LC = Call_F32; break;
2171  case MVT::f64: LC = Call_F64; break;
2172  case MVT::f80: LC = Call_F80; break;
2173  case MVT::f128: LC = Call_F128; break;
2174  case MVT::ppcf128: LC = Call_PPCF128; break;
2175  }
2176 
2177  return ExpandLibCall(LC, Node, false);
2178 }
2179 
2180 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2181 void
2182 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2183  SmallVectorImpl<SDValue> &Results) {
2184  unsigned Opcode = Node->getOpcode();
2185  bool isSigned = Opcode == ISD::SDIVREM;
2186 
2187  RTLIB::Libcall LC;
2188  switch (Node->getSimpleValueType(0).SimpleTy) {
2189  default: llvm_unreachable("Unexpected request for libcall!");
2190  case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2191  case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2192  case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2193  case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2194  case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2195  }
2196 
2197  // The input chain to this libcall is the entry node of the function.
2198  // Legalizing the call will automatically add the previous call to the
2199  // dependence.
2200  SDValue InChain = DAG.getEntryNode();
2201 
2202  EVT RetVT = Node->getValueType(0);
2203  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2204 
2206  TargetLowering::ArgListEntry Entry;
2207  for (const SDValue &Op : Node->op_values()) {
2208  EVT ArgVT = Op.getValueType();
2209  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2210  Entry.Node = Op;
2211  Entry.Ty = ArgTy;
2212  Entry.IsSExt = isSigned;
2213  Entry.IsZExt = !isSigned;
2214  Args.push_back(Entry);
2215  }
2216 
2217  // Also pass the return address of the remainder.
2218  SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2219  Entry.Node = FIPtr;
2220  Entry.Ty = RetTy->getPointerTo();
2221  Entry.IsSExt = isSigned;
2222  Entry.IsZExt = !isSigned;
2223  Args.push_back(Entry);
2224 
2225  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2226  TLI.getPointerTy(DAG.getDataLayout()));
2227 
2228  SDLoc dl(Node);
2230  CLI.setDebugLoc(dl)
2231  .setChain(InChain)
2232  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2233  std::move(Args))
2234  .setSExtResult(isSigned)
2235  .setZExtResult(!isSigned);
2236 
2237  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2238 
2239  // Remainder is loaded back from the stack frame.
2240  SDValue Rem =
2241  DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2242  Results.push_back(CallInfo.first);
2243  Results.push_back(Rem);
2244 }
2245 
2246 /// Return true if sincos libcall is available.
2247 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2248  RTLIB::Libcall LC;
2249  switch (Node->getSimpleValueType(0).SimpleTy) {
2250  default: llvm_unreachable("Unexpected request for libcall!");
2251  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2252  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2253  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2254  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2255  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2256  }
2257  return TLI.getLibcallName(LC) != nullptr;
2258 }
2259 
2260 /// Only issue sincos libcall if both sin and cos are needed.
2261 static bool useSinCos(SDNode *Node) {
2262  unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2263  ? ISD::FCOS : ISD::FSIN;
2264 
2265  SDValue Op0 = Node->getOperand(0);
2266  for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2267  UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2268  SDNode *User = *UI;
2269  if (User == Node)
2270  continue;
2271  // The other user might have been turned into sincos already.
2272  if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2273  return true;
2274  }
2275  return false;
2276 }
2277 
2278 /// Issue libcalls to sincos to compute sin / cos pairs.
2279 void
2280 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2281  SmallVectorImpl<SDValue> &Results) {
2282  RTLIB::Libcall LC;
2283  switch (Node->getSimpleValueType(0).SimpleTy) {
2284  default: llvm_unreachable("Unexpected request for libcall!");
2285  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2286  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2287  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2288  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2289  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2290  }
2291 
2292  // The input chain to this libcall is the entry node of the function.
2293  // Legalizing the call will automatically add the previous call to the
2294  // dependence.
2295  SDValue InChain = DAG.getEntryNode();
2296 
2297  EVT RetVT = Node->getValueType(0);
2298  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2299 
2301  TargetLowering::ArgListEntry Entry;
2302 
2303  // Pass the argument.
2304  Entry.Node = Node->getOperand(0);
2305  Entry.Ty = RetTy;
2306  Entry.IsSExt = false;
2307  Entry.IsZExt = false;
2308  Args.push_back(Entry);
2309 
2310  // Pass the return address of sin.
2311  SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2312  Entry.Node = SinPtr;
2313  Entry.Ty = RetTy->getPointerTo();
2314  Entry.IsSExt = false;
2315  Entry.IsZExt = false;
2316  Args.push_back(Entry);
2317 
2318  // Also pass the return address of the cos.
2319  SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2320  Entry.Node = CosPtr;
2321  Entry.Ty = RetTy->getPointerTo();
2322  Entry.IsSExt = false;
2323  Entry.IsZExt = false;
2324  Args.push_back(Entry);
2325 
2326  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2327  TLI.getPointerTy(DAG.getDataLayout()));
2328 
2329  SDLoc dl(Node);
2331  CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2332  TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee,
2333  std::move(Args));
2334 
2335  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2336 
2337  Results.push_back(
2338  DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2339  Results.push_back(
2340  DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2341 }
2342 
2343 /// This function is responsible for legalizing a
2344 /// INT_TO_FP operation of the specified operand when the target requests that
2345 /// we expand it. At this point, we know that the result and operand types are
2346 /// legal for the target.
2347 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
2348  EVT DestVT,
2349  const SDLoc &dl) {
2350  EVT SrcVT = Op0.getValueType();
2351 
2352  // TODO: Should any fast-math-flags be set for the created nodes?
2353  LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2354  if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2355  LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2356  "expansion\n");
2357 
2358  // Get the stack frame index of a 8 byte buffer.
2359  SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2360 
2361  // word offset constant for Hi/Lo address computation
2362  SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2363  StackSlot.getValueType());
2364  // set up Hi and Lo (into buffer) address based on endian
2365  SDValue Hi = StackSlot;
2366  SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2367  StackSlot, WordOff);
2368  if (DAG.getDataLayout().isLittleEndian())
2369  std::swap(Hi, Lo);
2370 
2371  // if signed map to unsigned space
2372  SDValue Op0Mapped;
2373  if (isSigned) {
2374  // constant used to invert sign bit (signed to unsigned mapping)
2375  SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2376  Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2377  } else {
2378  Op0Mapped = Op0;
2379  }
2380  // store the lo of the constructed double - based on integer input
2381  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo,
2382  MachinePointerInfo());
2383  // initial hi portion of constructed double
2384  SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2385  // store the hi of the constructed double - biased exponent
2386  SDValue Store2 =
2387  DAG.getStore(Store1, dl, InitialHi, Hi, MachinePointerInfo());
2388  // load the constructed double
2389  SDValue Load =
2390  DAG.getLoad(MVT::f64, dl, Store2, StackSlot, MachinePointerInfo());
2391  // FP constant to bias correct the final result
2392  SDValue Bias = DAG.getConstantFP(isSigned ?
2393  BitsToDouble(0x4330000080000000ULL) :
2394  BitsToDouble(0x4330000000000000ULL),
2395  dl, MVT::f64);
2396  // subtract the bias
2397  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2398  // final result
2399  SDValue Result = DAG.getFPExtendOrRound(Sub, dl, DestVT);
2400  return Result;
2401  }
2402  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2403  // Code below here assumes !isSigned without checking again.
2404 
2405  SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2406 
2407  SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
2408  DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2409  SDValue Zero = DAG.getIntPtrConstant(0, dl),
2410  Four = DAG.getIntPtrConstant(4, dl);
2411  SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2412  SignSet, Four, Zero);
2413 
2414  // If the sign bit of the integer is set, the large number will be treated
2415  // as a negative number. To counteract this, the dynamic code adds an
2416  // offset depending on the data type.
2417  uint64_t FF;
2418  switch (SrcVT.getSimpleVT().SimpleTy) {
2419  default: llvm_unreachable("Unsupported integer type!");
2420  case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2421  case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2422  case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2423  case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2424  }
2425  if (DAG.getDataLayout().isLittleEndian())
2426  FF <<= 32;
2427  Constant *FudgeFactor = ConstantInt::get(
2428  Type::getInt64Ty(*DAG.getContext()), FF);
2429 
2430  SDValue CPIdx =
2431  DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2432  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2433  CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2434  Alignment = std::min(Alignment, 4u);
2435  SDValue FudgeInReg;
2436  if (DestVT == MVT::f32)
2437  FudgeInReg = DAG.getLoad(
2438  MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2439  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2440  Alignment);
2441  else {
2442  SDValue Load = DAG.getExtLoad(
2443  ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2444  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2445  Alignment);
2446  HandleSDNode Handle(Load);
2447  LegalizeOp(Load.getNode());
2448  FudgeInReg = Handle.getValue();
2449  }
2450 
2451  return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2452 }
2453 
2454 /// This function is responsible for legalizing a
2455 /// *INT_TO_FP operation of the specified operand when the target requests that
2456 /// we promote it. At this point, we know that the result and operand types are
2457 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2458 /// operation that takes a larger input.
2459 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
2460  bool isSigned,
2461  const SDLoc &dl) {
2462  // First step, figure out the appropriate *INT_TO_FP operation to use.
2463  EVT NewInTy = LegalOp.getValueType();
2464 
2465  unsigned OpToUse = 0;
2466 
2467  // Scan for the appropriate larger type to use.
2468  while (true) {
2469  NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2470  assert(NewInTy.isInteger() && "Ran out of possibilities!");
2471 
2472  // If the target supports SINT_TO_FP of this type, use it.
2473  if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2474  OpToUse = ISD::SINT_TO_FP;
2475  break;
2476  }
2477  if (isSigned) continue;
2478 
2479  // If the target supports UINT_TO_FP of this type, use it.
2480  if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2481  OpToUse = ISD::UINT_TO_FP;
2482  break;
2483  }
2484 
2485  // Otherwise, try a larger type.
2486  }
2487 
2488  // Okay, we found the operation and type to use. Zero extend our input to the
2489  // desired type then run the operation on it.
2490  return DAG.getNode(OpToUse, dl, DestVT,
2491  DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2492  dl, NewInTy, LegalOp));
2493 }
2494 
2495 /// This function is responsible for legalizing a
2496 /// FP_TO_*INT operation of the specified operand when the target requests that
2497 /// we promote it. At this point, we know that the result and operand types are
2498 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2499 /// operation that returns a larger result.
2500 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
2501  bool isSigned,
2502  const SDLoc &dl) {
2503  // First step, figure out the appropriate FP_TO*INT operation to use.
2504  EVT NewOutTy = DestVT;
2505 
2506  unsigned OpToUse = 0;
2507 
2508  // Scan for the appropriate larger type to use.
2509  while (true) {
2510  NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2511  assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2512 
2513  // A larger signed type can hold all unsigned values of the requested type,
2514  // so using FP_TO_SINT is valid
2515  if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2516  OpToUse = ISD::FP_TO_SINT;
2517  break;
2518  }
2519 
2520  // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2521  if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2522  OpToUse = ISD::FP_TO_UINT;
2523  break;
2524  }
2525 
2526  // Otherwise, try a larger type.
2527  }
2528 
2529  // Okay, we found the operation and type to use.
2530  SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2531 
2532  // Truncate the result of the extended FP_TO_*INT operation to the desired
2533  // size.
2534  return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2535 }
2536 
2537 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2538 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
2539  EVT VT = Op.getValueType();
2540  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2541  unsigned Sz = VT.getScalarSizeInBits();
2542 
2543  SDValue Tmp, Tmp2, Tmp3;
2544 
2545  // If we can, perform BSWAP first and then the mask+swap the i4, then i2
2546  // and finally the i1 pairs.
2547  // TODO: We can easily support i4/i2 legal types if any target ever does.
2548  if (Sz >= 8 && isPowerOf2_32(Sz)) {
2549  // Create the masks - repeating the pattern every byte.
2550  APInt MaskHi4 = APInt::getSplat(Sz, APInt(8, 0xF0));
2551  APInt MaskHi2 = APInt::getSplat(Sz, APInt(8, 0xCC));
2552  APInt MaskHi1 = APInt::getSplat(Sz, APInt(8, 0xAA));
2553  APInt MaskLo4 = APInt::getSplat(Sz, APInt(8, 0x0F));
2554  APInt MaskLo2 = APInt::getSplat(Sz, APInt(8, 0x33));
2555  APInt MaskLo1 = APInt::getSplat(Sz, APInt(8, 0x55));
2556 
2557  // BSWAP if the type is wider than a single byte.
2558  Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2559 
2560  // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4)
2561  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2562  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2563  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT));
2564  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT));
2565  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2566 
2567  // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2)
2568  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2569  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2570  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT));
2571  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT));
2572  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2573 
2574  // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
2575  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2576  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2577  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT));
2578  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT));
2579  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2580  return Tmp;
2581  }
2582 
2583  Tmp = DAG.getConstant(0, dl, VT);
2584  for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2585  if (I < J)
2586  Tmp2 =
2587  DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2588  else
2589  Tmp2 =
2590  DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2591 
2592  APInt Shift(Sz, 1);
2593  Shift <<= J;
2594  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2595  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2596  }
2597 
2598  return Tmp;
2599 }
2600 
2601 /// Open code the operations for BSWAP of the specified operation.
2602 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
2603  EVT VT = Op.getValueType();
2604  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2605  SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2606  switch (VT.getSimpleVT().getScalarType().SimpleTy) {
2607  default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2608  case MVT::i16:
2609  // Use a rotate by 8. This can be further expanded if necessary.
2610  return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2611  case MVT::i32:
2612  Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2613  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2614  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2615  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2616  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2617  DAG.getConstant(0xFF0000, dl, VT));
2618  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2619  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2620  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2621  return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2622  case MVT::i64:
2623  Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2624  Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2625  Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2626  Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2627  Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2628  Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2629  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2630  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2631  Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2632  DAG.getConstant(255ULL<<48, dl, VT));
2633  Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2634  DAG.getConstant(255ULL<<40, dl, VT));
2635  Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2636  DAG.getConstant(255ULL<<32, dl, VT));
2637  Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2638  DAG.getConstant(255ULL<<24, dl, VT));
2639  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2640  DAG.getConstant(255ULL<<16, dl, VT));
2641  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2642  DAG.getConstant(255ULL<<8 , dl, VT));
2643  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2644  Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2645  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2646  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2647  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2648  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2649  return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2650  }
2651 }
2652 
2653 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2654  LLVM_DEBUG(dbgs() << "Trying to expand node\n");
2656  SDLoc dl(Node);
2657  SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2658  bool NeedInvert;
2659  switch (Node->getOpcode()) {
2660  case ISD::ABS:
2661  if (TLI.expandABS(Node, Tmp1, DAG))
2662  Results.push_back(Tmp1);
2663  break;
2664  case ISD::CTPOP:
2665  if (TLI.expandCTPOP(Node, Tmp1, DAG))
2666  Results.push_back(Tmp1);
2667  break;
2668  case ISD::CTLZ:
2669  case ISD::CTLZ_ZERO_UNDEF:
2670  if (TLI.expandCTLZ(Node, Tmp1, DAG))
2671  Results.push_back(Tmp1);
2672  break;
2673  case ISD::CTTZ:
2674  case ISD::CTTZ_ZERO_UNDEF:
2675  if (TLI.expandCTTZ(Node, Tmp1, DAG))
2676  Results.push_back(Tmp1);
2677  break;
2678  case ISD::BITREVERSE:
2679  Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
2680  break;
2681  case ISD::BSWAP:
2682  Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2683  break;
2684  case ISD::FRAMEADDR:
2685  case ISD::RETURNADDR:
2687  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2688  break;
2689  case ISD::EH_DWARF_CFA: {
2690  SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2691  TLI.getPointerTy(DAG.getDataLayout()));
2692  SDValue Offset = DAG.getNode(ISD::ADD, dl,
2693  CfaArg.getValueType(),
2694  DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2695  CfaArg.getValueType()),
2696  CfaArg);
2697  SDValue FA = DAG.getNode(
2698  ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2699  DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2700  Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2701  FA, Offset));
2702  break;
2703  }
2704  case ISD::FLT_ROUNDS_:
2705  Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2706  break;
2707  case ISD::EH_RETURN:
2708  case ISD::EH_LABEL:
2709  case ISD::PREFETCH:
2710  case ISD::VAEND:
2711  case ISD::EH_SJLJ_LONGJMP:
2712  // If the target didn't expand these, there's nothing to do, so just
2713  // preserve the chain and be done.
2714  Results.push_back(Node->getOperand(0));
2715  break;
2716  case ISD::READCYCLECOUNTER:
2717  // If the target didn't expand this, just return 'zero' and preserve the
2718  // chain.
2719  Results.append(Node->getNumValues() - 1,
2720  DAG.getConstant(0, dl, Node->getValueType(0)));
2721  Results.push_back(Node->getOperand(0));
2722  break;
2723  case ISD::EH_SJLJ_SETJMP:
2724  // If the target didn't expand this, just return 'zero' and preserve the
2725  // chain.
2726  Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2727  Results.push_back(Node->getOperand(0));
2728  break;
2729  case ISD::ATOMIC_LOAD: {
2730  // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2731  SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2732  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2733  SDValue Swap = DAG.getAtomicCmpSwap(
2734  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2735  Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2736  cast<AtomicSDNode>(Node)->getMemOperand());
2737  Results.push_back(Swap.getValue(0));
2738  Results.push_back(Swap.getValue(1));
2739  break;
2740  }
2741  case ISD::ATOMIC_STORE: {
2742  // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2743  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2744  cast<AtomicSDNode>(Node)->getMemoryVT(),
2745  Node->getOperand(0),
2746  Node->getOperand(1), Node->getOperand(2),
2747  cast<AtomicSDNode>(Node)->getMemOperand());
2748  Results.push_back(Swap.getValue(1));
2749  break;
2750  }
2752  // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2753  // splits out the success value as a comparison. Expanding the resulting
2754  // ATOMIC_CMP_SWAP will produce a libcall.
2755  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2756  SDValue Res = DAG.getAtomicCmpSwap(
2757  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2758  Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2759  Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2760 
2761  SDValue ExtRes = Res;
2762  SDValue LHS = Res;
2763  SDValue RHS = Node->getOperand(1);
2764 
2765  EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2766  EVT OuterType = Node->getValueType(0);
2767  switch (TLI.getExtendForAtomicOps()) {
2768  case ISD::SIGN_EXTEND:
2769  LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2770  DAG.getValueType(AtomicType));
2771  RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2772  Node->getOperand(2), DAG.getValueType(AtomicType));
2773  ExtRes = LHS;
2774  break;
2775  case ISD::ZERO_EXTEND:
2776  LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2777  DAG.getValueType(AtomicType));
2778  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2779  ExtRes = LHS;
2780  break;
2781  case ISD::ANY_EXTEND:
2782  LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2783  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2784  break;
2785  default:
2786  llvm_unreachable("Invalid atomic op extension");
2787  }
2788 
2789  SDValue Success =
2790  DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2791 
2792  Results.push_back(ExtRes.getValue(0));
2793  Results.push_back(Success);
2794  Results.push_back(Res.getValue(1));
2795  break;
2796  }
2798  ExpandDYNAMIC_STACKALLOC(Node, Results);
2799  break;
2800  case ISD::MERGE_VALUES:
2801  for (unsigned i = 0; i < Node->getNumValues(); i++)
2802  Results.push_back(Node->getOperand(i));
2803  break;
2804  case ISD::UNDEF: {
2805  EVT VT = Node->getValueType(0);
2806  if (VT.isInteger())
2807  Results.push_back(DAG.getConstant(0, dl, VT));
2808  else {
2809  assert(VT.isFloatingPoint() && "Unknown value type!");
2810  Results.push_back(DAG.getConstantFP(0, dl, VT));
2811  }
2812  break;
2813  }
2814  case ISD::STRICT_FP_ROUND:
2815  // This expansion does not honor the "strict" properties anyway,
2816  // so prefer falling back to the non-strict operation if legal.
2817  if (TLI.getStrictFPOperationAction(Node->getOpcode(),
2818  Node->getValueType(0))
2820  break;
2821  Tmp1 = EmitStackConvert(Node->getOperand(1),
2822  Node->getValueType(0),
2823  Node->getValueType(0), dl, Node->getOperand(0));
2824  ReplaceNode(Node, Tmp1.getNode());
2825  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_ROUND node\n");
2826  return true;
2827  case ISD::FP_ROUND:
2828  case ISD::BITCAST:
2829  Tmp1 = EmitStackConvert(Node->getOperand(0),
2830  Node->getValueType(0),
2831  Node->getValueType(0), dl);
2832  Results.push_back(Tmp1);
2833  break;
2834  case ISD::STRICT_FP_EXTEND:
2835  // This expansion does not honor the "strict" properties anyway,
2836  // so prefer falling back to the non-strict operation if legal.
2837  if (TLI.getStrictFPOperationAction(Node->getOpcode(),
2838  Node->getValueType(0))
2840  break;
2841  Tmp1 = EmitStackConvert(Node->getOperand(1),
2842  Node->getOperand(1).getValueType(),
2843  Node->getValueType(0), dl, Node->getOperand(0));
2844  ReplaceNode(Node, Tmp1.getNode());
2845  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_EXTEND node\n");
2846  return true;
2847  case ISD::FP_EXTEND:
2848  Tmp1 = EmitStackConvert(Node->getOperand(0),
2849  Node->getOperand(0).getValueType(),
2850  Node->getValueType(0), dl);
2851  Results.push_back(Tmp1);
2852  break;
2853  case ISD::SIGN_EXTEND_INREG: {
2854  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2855  EVT VT = Node->getValueType(0);
2856 
2857  // An in-register sign-extend of a boolean is a negation:
2858  // 'true' (1) sign-extended is -1.
2859  // 'false' (0) sign-extended is 0.
2860  // However, we must mask the high bits of the source operand because the
2861  // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2862 
2863  // TODO: Do this for vectors too?
2864  if (ExtraVT.getSizeInBits() == 1) {
2865  SDValue One = DAG.getConstant(1, dl, VT);
2866  SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2867  SDValue Zero = DAG.getConstant(0, dl, VT);
2868  SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2869  Results.push_back(Neg);
2870  break;
2871  }
2872 
2873  // NOTE: we could fall back on load/store here too for targets without
2874  // SRA. However, it is doubtful that any exist.
2875  EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2876  unsigned BitsDiff = VT.getScalarSizeInBits() -
2877  ExtraVT.getScalarSizeInBits();
2878  SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2879  Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2880  Node->getOperand(0), ShiftCst);
2881  Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2882  Results.push_back(Tmp1);
2883  break;
2884  }
2885  case ISD::UINT_TO_FP:
2886  if (TLI.expandUINT_TO_FP(Node, Tmp1, DAG)) {
2887  Results.push_back(Tmp1);
2888  break;
2889  }
2891  case ISD::SINT_TO_FP:
2892  Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2893  Node->getOperand(0), Node->getValueType(0), dl);
2894  Results.push_back(Tmp1);
2895  break;
2896  case ISD::FP_TO_SINT:
2897  if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
2898  Results.push_back(Tmp1);
2899  break;
2901  if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG)) {
2902  ReplaceNode(Node, Tmp1.getNode());
2903  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_SINT node\n");
2904  return true;
2905  }
2906  break;
2907  case ISD::FP_TO_UINT:
2908  if (TLI.expandFP_TO_UINT(Node, Tmp1, Tmp2, DAG))
2909  Results.push_back(Tmp1);
2910  break;
2912  if (TLI.expandFP_TO_UINT(Node, Tmp1, Tmp2, DAG)) {
2913  // Relink the chain.
2914  DAG.ReplaceAllUsesOfValueWith(SDValue(Node,1), Tmp2);
2915  // Replace the new UINT result.
2916  ReplaceNodeWithValue(SDValue(Node, 0), Tmp1);
2917  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_UINT node\n");
2918  return true;
2919  }
2920  break;
2921  case ISD::VAARG:
2922  Results.push_back(DAG.expandVAArg(Node));
2923  Results.push_back(Results[0].getValue(1));
2924  break;
2925  case ISD::VACOPY:
2926  Results.push_back(DAG.expandVACopy(Node));
2927  break;
2929  if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2930  // This must be an access of the only element. Return it.
2931  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2932  Node->getOperand(0));
2933  else
2934  Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2935  Results.push_back(Tmp1);
2936  break;
2938  Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2939  break;
2940  case ISD::INSERT_SUBVECTOR:
2941  Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2942  break;
2943  case ISD::CONCAT_VECTORS:
2944  Results.push_back(ExpandVectorBuildThroughStack(Node));
2945  break;
2946  case ISD::SCALAR_TO_VECTOR:
2947  Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2948  break;
2950  Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2951  Node->getOperand(1),
2952  Node->getOperand(2), dl));
2953  break;
2954  case ISD::VECTOR_SHUFFLE: {
2955  SmallVector<int, 32> NewMask;
2956  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2957 
2958  EVT VT = Node->getValueType(0);
2959  EVT EltVT = VT.getVectorElementType();
2960  SDValue Op0 = Node->getOperand(0);
2961  SDValue Op1 = Node->getOperand(1);
2962  if (!TLI.isTypeLegal(EltVT)) {
2963  EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2964 
2965  // BUILD_VECTOR operands are allowed to be wider than the element type.
2966  // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
2967  // it.
2968  if (NewEltVT.bitsLT(EltVT)) {
2969  // Convert shuffle node.
2970  // If original node was v4i64 and the new EltVT is i32,
2971  // cast operands to v8i32 and re-build the mask.
2972 
2973  // Calculate new VT, the size of the new VT should be equal to original.
2974  EVT NewVT =
2975  EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2976  VT.getSizeInBits() / NewEltVT.getSizeInBits());
2977  assert(NewVT.bitsEq(VT));
2978 
2979  // cast operands to new VT
2980  Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2981  Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2982 
2983  // Convert the shuffle mask
2984  unsigned int factor =
2986 
2987  // EltVT gets smaller
2988  assert(factor > 0);
2989 
2990  for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2991  if (Mask[i] < 0) {
2992  for (unsigned fi = 0; fi < factor; ++fi)
2993  NewMask.push_back(Mask[i]);
2994  }
2995  else {
2996  for (unsigned fi = 0; fi < factor; ++fi)
2997  NewMask.push_back(Mask[i]*factor+fi);
2998  }
2999  }
3000  Mask = NewMask;
3001  VT = NewVT;
3002  }
3003  EltVT = NewEltVT;
3004  }
3005  unsigned NumElems = VT.getVectorNumElements();
3007  for (unsigned i = 0; i != NumElems; ++i) {
3008  if (Mask[i] < 0) {
3009  Ops.push_back(DAG.getUNDEF(EltVT));
3010  continue;
3011  }
3012  unsigned Idx = Mask[i];
3013  if (Idx < NumElems)
3014  Ops.push_back(DAG.getNode(
3015  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3016  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3017  else
3018  Ops.push_back(DAG.getNode(
3019  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3020  DAG.getConstant(Idx - NumElems, dl,
3021  TLI.getVectorIdxTy(DAG.getDataLayout()))));
3022  }
3023 
3024  Tmp1 = DAG.getBuildVector(VT, dl, Ops);
3025  // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3026  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3027  Results.push_back(Tmp1);
3028  break;
3029  }
3030  case ISD::EXTRACT_ELEMENT: {
3031  EVT OpTy = Node->getOperand(0).getValueType();
3032  if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3033  // 1 -> Hi
3034  Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3035  DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3036  TLI.getShiftAmountTy(
3037  Node->getOperand(0).getValueType(),
3038  DAG.getDataLayout())));
3039  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3040  } else {
3041  // 0 -> Lo
3042  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3043  Node->getOperand(0));
3044  }
3045  Results.push_back(Tmp1);
3046  break;
3047  }
3048  case ISD::STACKSAVE:
3049  // Expand to CopyFromReg if the target set
3050  // StackPointerRegisterToSaveRestore.
3051  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3052  Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3053  Node->getValueType(0)));
3054  Results.push_back(Results[0].getValue(1));
3055  } else {
3056  Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3057  Results.push_back(Node->getOperand(0));
3058  }
3059  break;
3060  case ISD::STACKRESTORE:
3061  // Expand to CopyToReg if the target set
3062  // StackPointerRegisterToSaveRestore.
3063  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3064  Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3065  Node->getOperand(1)));
3066  } else {
3067  Results.push_back(Node->getOperand(0));
3068  }
3069  break;
3071  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3072  Results.push_back(Results[0].getValue(0));
3073  break;
3074  case ISD::FCOPYSIGN:
3075  Results.push_back(ExpandFCOPYSIGN(Node));
3076  break;
3077  case ISD::FNEG:
3078  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3079  Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3080  // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3081  Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3082  Node->getOperand(0));
3083  Results.push_back(Tmp1);
3084  break;
3085  case ISD::FABS:
3086  Results.push_back(ExpandFABS(Node));
3087  break;
3088  case ISD::SMIN:
3089  case ISD::SMAX:
3090  case ISD::UMIN:
3091  case ISD::UMAX: {
3092  // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3093  ISD::CondCode Pred;
3094  switch (Node->getOpcode()) {
3095  default: llvm_unreachable("How did we get here?");
3096  case ISD::SMAX: Pred = ISD::SETGT; break;
3097  case ISD::SMIN: Pred = ISD::SETLT; break;
3098  case ISD::UMAX: Pred = ISD::SETUGT; break;
3099  case ISD::UMIN: Pred = ISD::SETULT; break;
3100  }
3101  Tmp1 = Node->getOperand(0);
3102  Tmp2 = Node->getOperand(1);
3103  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3104  Results.push_back(Tmp1);
3105  break;
3106  }
3107  case ISD::FMINNUM:
3108  case ISD::FMAXNUM: {
3109  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Node, DAG))
3110  Results.push_back(Expanded);
3111  break;
3112  }
3113  case ISD::FSIN:
3114  case ISD::FCOS: {
3115  EVT VT = Node->getValueType(0);
3116  // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3117  // fcos which share the same operand and both are used.
3118  if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3119  isSinCosLibcallAvailable(Node, TLI))
3120  && useSinCos(Node)) {
3121  SDVTList VTs = DAG.getVTList(VT, VT);
3122  Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3123  if (Node->getOpcode() == ISD::FCOS)
3124  Tmp1 = Tmp1.getValue(1);
3125  Results.push_back(Tmp1);
3126  }
3127  break;
3128  }
3129  case ISD::FMAD:
3130  llvm_unreachable("Illegal fmad should never be formed");
3131 
3132  case ISD::FP16_TO_FP:
3133  if (Node->getValueType(0) != MVT::f32) {
3134  // We can extend to types bigger than f32 in two steps without changing
3135  // the result. Since "f16 -> f32" is much more commonly available, give
3136  // CodeGen the option of emitting that before resorting to a libcall.
3137  SDValue Res =
3138  DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3139  Results.push_back(
3140  DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3141  }
3142  break;
3143  case ISD::FP_TO_FP16:
3144  LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3145  if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3146  SDValue Op = Node->getOperand(0);
3147  MVT SVT = Op.getSimpleValueType();
3148  if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3149  TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3150  // Under fastmath, we can expand this node into a fround followed by
3151  // a float-half conversion.
3152  SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3153  DAG.getIntPtrConstant(0, dl));
3154  Results.push_back(
3155  DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3156  }
3157  }
3158  break;
3159  case ISD::ConstantFP: {
3160  ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3161  // Check to see if this FP immediate is already legal.
3162  // If this is a legal constant, turn it into a TargetConstantFP node.
3163  if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0),
3164  DAG.getMachineFunction().getFunction().hasOptSize()))
3165  Results.push_back(ExpandConstantFP(CFP, true));
3166  break;
3167  }
3168  case ISD::Constant: {
3169  ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3170  Results.push_back(ExpandConstant(CP));
3171  break;
3172  }
3173  case ISD::FSUB: {
3174  EVT VT = Node->getValueType(0);
3175  if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3176  TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3177  const SDNodeFlags Flags = Node->getFlags();
3178  Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3179  Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3180  Results.push_back(Tmp1);
3181  }
3182  break;
3183  }
3184  case ISD::SUB: {
3185  EVT VT = Node->getValueType(0);
3186  assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3187  TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3188  "Don't know how to expand this subtraction!");
3189  Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3190  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3191  VT));
3192  Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3193  Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3194  break;
3195  }
3196  case ISD::UREM:
3197  case ISD::SREM: {
3198  EVT VT = Node->getValueType(0);
3199  bool isSigned = Node->getOpcode() == ISD::SREM;
3200  unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3201  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3202  Tmp2 = Node->getOperand(0);
3203  Tmp3 = Node->getOperand(1);
3204  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3205  SDVTList VTs = DAG.getVTList(VT, VT);
3206  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3207  Results.push_back(Tmp1);
3208  } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3209  // X % Y -> X-X/Y*Y
3210  Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3211  Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3212  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3213  Results.push_back(Tmp1);
3214  }
3215  break;
3216  }
3217  case ISD::UDIV:
3218  case ISD::SDIV: {
3219  bool isSigned = Node->getOpcode() == ISD::SDIV;
3220  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3221  EVT VT = Node->getValueType(0);
3222  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3223  SDVTList VTs = DAG.getVTList(VT, VT);
3224  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3225  Node->getOperand(1));
3226  Results.push_back(Tmp1);
3227  }
3228  break;
3229  }
3230  case ISD::MULHU:
3231  case ISD::MULHS: {
3232  unsigned ExpandOpcode =
3234  EVT VT = Node->getValueType(0);
3235  SDVTList VTs = DAG.getVTList(VT, VT);
3236 
3237  Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3238  Node->getOperand(1));
3239  Results.push_back(Tmp1.getValue(1));
3240  break;
3241  }
3242  case ISD::UMUL_LOHI:
3243  case ISD::SMUL_LOHI: {
3244  SDValue LHS = Node->getOperand(0);
3245  SDValue RHS = Node->getOperand(1);
3246  MVT VT = LHS.getSimpleValueType();
3247  unsigned MULHOpcode =
3249 
3250  if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3251  Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3252  Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3253  break;
3254  }
3255 
3256  SmallVector<SDValue, 4> Halves;
3257  EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3258  assert(TLI.isTypeLegal(HalfType));
3259  if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3260  HalfType, DAG,
3262  for (unsigned i = 0; i < 2; ++i) {
3263  SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3264  SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3265  SDValue Shift = DAG.getConstant(
3266  HalfType.getScalarSizeInBits(), dl,
3267  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3268  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3269  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3270  }
3271  break;
3272  }
3273  break;
3274  }
3275  case ISD::MUL: {
3276  EVT VT = Node->getValueType(0);
3277  SDVTList VTs = DAG.getVTList(VT, VT);
3278  // See if multiply or divide can be lowered using two-result operations.
3279  // We just need the low half of the multiply; try both the signed
3280  // and unsigned forms. If the target supports both SMUL_LOHI and
3281  // UMUL_LOHI, form a preference by checking which forms of plain
3282  // MULH it supports.
3283  bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3284  bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3285  bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3286  bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3287  unsigned OpToUse = 0;
3288  if (HasSMUL_LOHI && !HasMULHS) {
3289  OpToUse = ISD::SMUL_LOHI;
3290  } else if (HasUMUL_LOHI && !HasMULHU) {
3291  OpToUse = ISD::UMUL_LOHI;
3292  } else if (HasSMUL_LOHI) {
3293  OpToUse = ISD::SMUL_LOHI;
3294  } else if (HasUMUL_LOHI) {
3295  OpToUse = ISD::UMUL_LOHI;
3296  }
3297  if (OpToUse) {
3298  Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3299  Node->getOperand(1)));
3300  break;
3301  }
3302 
3303  SDValue Lo, Hi;
3304  EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3305  if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3306  TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3307  TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3308  TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3309  TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3311  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3312  Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3313  SDValue Shift =
3314  DAG.getConstant(HalfType.getSizeInBits(), dl,
3315  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3316  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3317  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3318  }
3319  break;
3320  }
3321  case ISD::FSHL:
3322  case ISD::FSHR:
3323  if (TLI.expandFunnelShift(Node, Tmp1, DAG))
3324  Results.push_back(Tmp1);
3325  break;
3326  case ISD::ROTL:
3327  case ISD::ROTR:
3328  if (TLI.expandROT(Node, Tmp1, DAG))
3329  Results.push_back(Tmp1);
3330  break;
3331  case ISD::SADDSAT:
3332  case ISD::UADDSAT:
3333  case ISD::SSUBSAT:
3334  case ISD::USUBSAT:
3335  Results.push_back(TLI.expandAddSubSat(Node, DAG));
3336  break;
3337  case ISD::SMULFIX:
3338  case ISD::SMULFIXSAT:
3339  case ISD::UMULFIX:
3340  case ISD::UMULFIXSAT:
3341  Results.push_back(TLI.expandFixedPointMul(Node, DAG));
3342  break;
3343  case ISD::ADDCARRY:
3344  case ISD::SUBCARRY: {
3345  SDValue LHS = Node->getOperand(0);
3346  SDValue RHS = Node->getOperand(1);
3347  SDValue Carry = Node->getOperand(2);
3348 
3349  bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;
3350 
3351  // Initial add of the 2 operands.
3352  unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
3353  EVT VT = LHS.getValueType();
3354  SDValue Sum = DAG.getNode(Op, dl, VT, LHS, RHS);
3355 
3356  // Initial check for overflow.
3357  EVT CarryType = Node->getValueType(1);
3358  EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3359  ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3360  SDValue Overflow = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3361 
3362  // Add of the sum and the carry.
3363  SDValue CarryExt =
3364  DAG.getZeroExtendInReg(DAG.getZExtOrTrunc(Carry, dl, VT), dl, MVT::i1);
3365  SDValue Sum2 = DAG.getNode(Op, dl, VT, Sum, CarryExt);
3366 
3367  // Second check for overflow. If we are adding, we can only overflow if the
3368  // initial sum is all 1s ang the carry is set, resulting in a new sum of 0.
3369  // If we are subtracting, we can only overflow if the initial sum is 0 and
3370  // the carry is set, resulting in a new sum of all 1s.
3371  SDValue Zero = DAG.getConstant(0, dl, VT);
3372  SDValue Overflow2 =
3373  IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ)
3374  : DAG.getSetCC(dl, SetCCType, Sum, Zero, ISD::SETEQ);
3375  Overflow2 = DAG.getNode(ISD::AND, dl, SetCCType, Overflow2,
3376  DAG.getZExtOrTrunc(Carry, dl, SetCCType));
3377 
3378  SDValue ResultCarry =
3379  DAG.getNode(ISD::OR, dl, SetCCType, Overflow, Overflow2);
3380 
3381  Results.push_back(Sum2);
3382  Results.push_back(DAG.getBoolExtOrTrunc(ResultCarry, dl, CarryType, VT));
3383  break;
3384  }
3385  case ISD::SADDO:
3386  case ISD::SSUBO: {
3387  SDValue Result, Overflow;
3388  TLI.expandSADDSUBO(Node, Result, Overflow, DAG);
3389  Results.push_back(Result);
3390  Results.push_back(Overflow);
3391  break;
3392  }
3393  case ISD::UADDO:
3394  case ISD::USUBO: {
3395  SDValue Result, Overflow;
3396  TLI.expandUADDSUBO(Node, Result, Overflow, DAG);
3397  Results.push_back(Result);
3398  Results.push_back(Overflow);
3399  break;
3400  }
3401  case ISD::UMULO:
3402  case ISD::SMULO: {
3403  SDValue Result, Overflow;
3404  if (TLI.expandMULO(Node, Result, Overflow, DAG)) {
3405  Results.push_back(Result);
3406  Results.push_back(Overflow);
3407  }
3408  break;
3409  }
3410  case ISD::BUILD_PAIR: {
3411  EVT PairTy = Node->getValueType(0);
3412  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3413  Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3414  Tmp2 = DAG.getNode(
3415  ISD::SHL, dl, PairTy, Tmp2,
3416  DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3417  TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3418  Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3419  break;
3420  }
3421  case ISD::SELECT:
3422  Tmp1 = Node->getOperand(0);
3423  Tmp2 = Node->getOperand(1);
3424  Tmp3 = Node->getOperand(2);
3425  if (Tmp1.getOpcode() == ISD::SETCC) {
3426  Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3427  Tmp2, Tmp3,
3428  cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3429  } else {
3430  Tmp1 = DAG.getSelectCC(dl, Tmp1,
3431  DAG.getConstant(0, dl, Tmp1.getValueType()),
3432  Tmp2, Tmp3, ISD::SETNE);
3433  }
3434  Tmp1->setFlags(Node->getFlags());
3435  Results.push_back(Tmp1);
3436  break;
3437  case ISD::BR_JT: {
3438  SDValue Chain = Node->getOperand(0);
3439  SDValue Table = Node->getOperand(1);
3440  SDValue Index = Node->getOperand(2);
3441 
3442  const DataLayout &TD = DAG.getDataLayout();
3443  EVT PTy = TLI.getPointerTy(TD);
3444 
3445  unsigned EntrySize =
3446  DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3447 
3448  // For power-of-two jumptable entry sizes convert multiplication to a shift.
3449  // This transformation needs to be done here since otherwise the MIPS
3450  // backend will end up emitting a three instruction multiply sequence
3451  // instead of a single shift and MSP430 will call a runtime function.
3452  if (llvm::isPowerOf2_32(EntrySize))
3453  Index = DAG.getNode(
3454  ISD::SHL, dl, Index.getValueType(), Index,
3455  DAG.getConstant(llvm::Log2_32(EntrySize), dl, Index.getValueType()));
3456  else
3457  Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3458  DAG.getConstant(EntrySize, dl, Index.getValueType()));
3459  SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3460  Index, Table);
3461 
3462  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3463  SDValue LD = DAG.getExtLoad(
3464  ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3465  MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3466  Addr = LD;
3467  if (TLI.isJumpTableRelative()) {
3468  // For PIC, the sequence is:
3469  // BRIND(load(Jumptable + index) + RelocBase)
3470  // RelocBase can be JumpTable, GOT or some sort of global base.
3471  Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3472  TLI.getPICJumpTableRelocBase(Table, DAG));
3473  }
3474 
3475  Tmp1 = TLI.expandIndirectJTBranch(dl, LD.getValue(1), Addr, DAG);
3476  Results.push_back(Tmp1);
3477  break;
3478  }
3479  case ISD::BRCOND:
3480  // Expand brcond's setcc into its constituent parts and create a BR_CC
3481  // Node.
3482  Tmp1 = Node->getOperand(0);
3483  Tmp2 = Node->getOperand(1);
3484  if (Tmp2.getOpcode() == ISD::SETCC) {
3485  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3486  Tmp1, Tmp2.getOperand(2),
3487  Tmp2.getOperand(0), Tmp2.getOperand(1),
3488  Node->getOperand(2));
3489  } else {
3490  // We test only the i1 bit. Skip the AND if UNDEF or another AND.
3491  if (Tmp2.isUndef() ||
3492  (Tmp2.getOpcode() == ISD::AND &&
3493  isa<ConstantSDNode>(Tmp2.getOperand(1)) &&
3494  cast<ConstantSDNode>(Tmp2.getOperand(1))->getZExtValue() == 1))
3495  Tmp3 = Tmp2;
3496  else
3497  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3498  DAG.getConstant(1, dl, Tmp2.getValueType()));
3499  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3500  DAG.getCondCode(ISD::SETNE), Tmp3,
3501  DAG.getConstant(0, dl, Tmp3.getValueType()),
3502  Node->getOperand(2));
3503  }
3504  Results.push_back(Tmp1);
3505  break;
3506  case ISD::SETCC: {
3507  Tmp1 = Node->getOperand(0);
3508  Tmp2 = Node->getOperand(1);
3509  Tmp3 = Node->getOperand(2);
3510  bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3511  Tmp3, NeedInvert, dl);
3512 
3513  if (Legalized) {
3514  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3515  // condition code, create a new SETCC node.
3516  if (Tmp3.getNode())
3517  Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3518  Tmp1, Tmp2, Tmp3, Node->getFlags());
3519 
3520  // If we expanded the SETCC by inverting the condition code, then wrap
3521  // the existing SETCC in a NOT to restore the intended condition.
3522  if (NeedInvert)
3523  Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3524 
3525  Results.push_back(Tmp1);
3526  break;
3527  }
3528 
3529  // Otherwise, SETCC for the given comparison type must be completely
3530  // illegal; expand it into a SELECT_CC.
3531  EVT VT = Node->getValueType(0);
3532  int TrueValue;
3533  switch (TLI.getBooleanContents(Tmp1.getValueType())) {
3536  TrueValue = 1;
3537  break;
3539  TrueValue = -1;
3540  break;
3541  }
3542  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3543  DAG.getConstant(TrueValue, dl, VT),
3544  DAG.getConstant(0, dl, VT),
3545  Tmp3);
3546  Tmp1->setFlags(Node->getFlags());
3547  Results.push_back(Tmp1);
3548  break;
3549  }
3550  case ISD::SELECT_CC: {
3551  Tmp1 = Node->getOperand(0); // LHS
3552  Tmp2 = Node->getOperand(1); // RHS
3553  Tmp3 = Node->getOperand(2); // True
3554  Tmp4 = Node->getOperand(3); // False
3555  EVT VT = Node->getValueType(0);
3556  SDValue CC = Node->getOperand(4);
3557  ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3558 
3559  if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) {
3560  // If the condition code is legal, then we need to expand this
3561  // node using SETCC and SELECT.
3562  EVT CmpVT = Tmp1.getValueType();
3563  assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3564  "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3565  "expanded.");
3566  EVT CCVT = getSetCCResultType(CmpVT);
3567  SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags());
3568  Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3569  break;
3570  }
3571 
3572  // SELECT_CC is legal, so the condition code must not be.
3573  bool Legalized = false;
3574  // Try to legalize by inverting the condition. This is for targets that
3575  // might support an ordered version of a condition, but not the unordered
3576  // version (or vice versa).
3577  ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3578  Tmp1.getValueType().isInteger());
3579  if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
3580  // Use the new condition code and swap true and false
3581  Legalized = true;
3582  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3583  Tmp1->setFlags(Node->getFlags());
3584  } else {
3585  // If The inverse is not legal, then try to swap the arguments using
3586  // the inverse condition code.
3587  ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3588  if (TLI.isCondCodeLegalOrCustom(SwapInvCC, Tmp1.getSimpleValueType())) {
3589  // The swapped inverse condition is legal, so swap true and false,
3590  // lhs and rhs.
3591  Legalized = true;
3592  Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3593  Tmp1->setFlags(Node->getFlags());
3594  }
3595  }
3596 
3597  if (!Legalized) {
3598  Legalized = LegalizeSetCCCondCode(
3599  getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3600  dl);
3601 
3602  assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3603 
3604  // If we expanded the SETCC by inverting the condition code, then swap
3605  // the True/False operands to match.
3606  if (NeedInvert)
3607  std::swap(Tmp3, Tmp4);
3608 
3609  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3610  // condition code, create a new SELECT_CC node.
3611  if (CC.getNode()) {
3612  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3613  Tmp1, Tmp2, Tmp3, Tmp4, CC);
3614  } else {
3615  Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3616  CC = DAG.getCondCode(ISD::SETNE);
3617  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3618  Tmp2, Tmp3, Tmp4, CC);
3619  }
3620  Tmp1->setFlags(Node->getFlags());
3621  }
3622  Results.push_back(Tmp1);
3623  break;
3624  }
3625  case ISD::BR_CC: {
3626  Tmp1 = Node->getOperand(0); // Chain
3627  Tmp2 = Node->getOperand(2); // LHS
3628  Tmp3 = Node->getOperand(3); // RHS
3629  Tmp4 = Node->getOperand(1); // CC
3630 
3631  bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3632  Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3633  (void)Legalized;
3634  assert(Legalized && "Can't legalize BR_CC with legal condition!");
3635 
3636  assert(!NeedInvert && "Don't know how to invert BR_CC!");
3637 
3638  // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3639  // node.
3640  if (Tmp4.getNode()) {
3641  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3642  Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3643  } else {
3644  Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3645  Tmp4 = DAG.getCondCode(ISD::SETNE);
3646  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3647  Tmp2, Tmp3, Node->getOperand(4));
3648  }
3649  Results.push_back(Tmp1);
3650  break;
3651  }
3652  case ISD::BUILD_VECTOR:
3653  Results.push_back(ExpandBUILD_VECTOR(Node));
3654  break;
3655  case ISD::SPLAT_VECTOR:
3656  Results.push_back(ExpandSPLAT_VECTOR(Node));
3657  break;
3658  case ISD::SRA:
3659  case ISD::SRL:
3660  case ISD::SHL: {
3661  // Scalarize vector SRA/SRL/SHL.
3662  EVT VT = Node->getValueType(0);
3663  assert(VT.isVector() && "Unable to legalize non-vector shift");
3664  assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3665  unsigned NumElem = VT.getVectorNumElements();
3666 
3667  SmallVector<SDValue, 8> Scalars;
3668  for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3669  SDValue Ex = DAG.getNode(
3670  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3671  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3672  SDValue Sh = DAG.getNode(
3673  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3674  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3675  Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3676  VT.getScalarType(), Ex, Sh));
3677  }
3678 
3679  SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
3680  ReplaceNode(SDValue(Node, 0), Result);
3681  break;
3682  }
3683  case ISD::VECREDUCE_FADD:
3684  case ISD::VECREDUCE_FMUL:
3685  case ISD::VECREDUCE_ADD:
3686  case ISD::VECREDUCE_MUL:
3687  case ISD::VECREDUCE_AND:
3688  case ISD::VECREDUCE_OR:
3689  case ISD::VECREDUCE_XOR:
3690  case ISD::VECREDUCE_SMAX:
3691  case ISD::VECREDUCE_SMIN:
3692  case ISD::VECREDUCE_UMAX:
3693  case ISD::VECREDUCE_UMIN:
3694  case ISD::VECREDUCE_FMAX:
3695  case ISD::VECREDUCE_FMIN:
3696  Results.push_back(TLI.expandVecReduce(Node, DAG));
3697  break;
3699  case ISD::GlobalAddress:
3700  case ISD::GlobalTLSAddress:
3701  case ISD::ExternalSymbol:
3702  case ISD::ConstantPool:
3703  case ISD::JumpTable:
3706  case ISD::INTRINSIC_VOID:
3707  // FIXME: Custom lowering for these operations shouldn't return null!
3708  break;
3709  }
3710 
3711  if (Results.empty() && Node->isStrictFPOpcode()) {
3712  // FIXME: We were asked to expand a strict floating-point operation,
3713  // but there is currently no expansion implemented that would preserve
3714  // the "strict" properties. For now, we just fall back to the non-strict
3715  // version if that is legal on the target. The actual mutation of the
3716  // operation will happen in SelectionDAGISel::DoInstructionSelection.
3717  switch (Node->getOpcode()) {
3718  default:
3719  if (TLI.getStrictFPOperationAction(Node->getOpcode(),
3720  Node->getValueType(0))
3722  return true;
3723  break;
3724  case ISD::STRICT_LRINT:
3725  case ISD::STRICT_LLRINT:
3726  case ISD::STRICT_LROUND:
3727  case ISD::STRICT_LLROUND:
3728  // These are registered by the operand type instead of the value
3729  // type. Reflect that here.
3730  if (TLI.getStrictFPOperationAction(Node->getOpcode(),
3731  Node->getOperand(1).getValueType())
3733  return true;
3734  break;
3735  }
3736  }
3737 
3738  // Replace the original node with the legalized result.
3739  if (Results.empty()) {
3740  LLVM_DEBUG(dbgs() << "Cannot expand node\n");
3741  return false;
3742  }
3743 
3744  LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
3745  ReplaceNode(Node, Results.data());
3746  return true;
3747 }
3748 
3749 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3750  LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
3752  SDLoc dl(Node);
3753  // FIXME: Check flags on the node to see if we can use a finite call.
3754  bool CanUseFiniteLibCall = TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath;
3755  unsigned Opc = Node->getOpcode();
3756  switch (Opc) {
3757  case ISD::ATOMIC_FENCE: {
3758  // If the target didn't lower this, lower it to '__sync_synchronize()' call
3759  // FIXME: handle "fence singlethread" more efficiently.
3761 
3763  CLI.setDebugLoc(dl)
3764  .setChain(Node->getOperand(0))
3765  .setLibCallee(
3766  CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3767  DAG.getExternalSymbol("__sync_synchronize",
3768  TLI.getPointerTy(DAG.getDataLayout())),
3769  std::move(Args));
3770 
3771  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3772 
3773  Results.push_back(CallResult.second);
3774  break;
3775  }
3776  // By default, atomic intrinsics are marked Legal and lowered. Targets
3777  // which don't support them directly, however, may want libcalls, in which
3778  // case they mark them Expand, and we get here.
3779  case ISD::ATOMIC_SWAP:
3780  case ISD::ATOMIC_LOAD_ADD:
3781  case ISD::ATOMIC_LOAD_SUB:
3782  case ISD::ATOMIC_LOAD_AND:
3783  case ISD::ATOMIC_LOAD_CLR:
3784  case ISD::ATOMIC_LOAD_OR:
3785  case ISD::ATOMIC_LOAD_XOR:
3786  case ISD::ATOMIC_LOAD_NAND:
3787  case ISD::ATOMIC_LOAD_MIN:
3788  case ISD::ATOMIC_LOAD_MAX:
3789  case ISD::ATOMIC_LOAD_UMIN:
3790  case ISD::ATOMIC_LOAD_UMAX:
3791  case ISD::ATOMIC_CMP_SWAP: {
3792  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3793  RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
3794  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3795 
3796  std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3797  Results.push_back(Tmp.first);
3798  Results.push_back(Tmp.second);
3799  break;
3800  }
3801  case ISD::TRAP: {
3802  // If this operation is not supported, lower it to 'abort()' call
3805  CLI.setDebugLoc(dl)
3806  .setChain(Node->getOperand(0))
3807  .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3808  DAG.getExternalSymbol(
3809  "abort", TLI.getPointerTy(DAG.getDataLayout())),
3810  std::move(Args));
3811  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3812 
3813  Results.push_back(CallResult.second);
3814  break;
3815  }
3816  case ISD::FMINNUM:
3817  case ISD::STRICT_FMINNUM:
3818  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3819  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3820  RTLIB::FMIN_PPCF128));
3821  break;
3822  case ISD::FMAXNUM:
3823  case ISD::STRICT_FMAXNUM:
3824  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3825  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3826  RTLIB::FMAX_PPCF128));
3827  break;
3828  case ISD::FSQRT:
3829  case ISD::STRICT_FSQRT:
3830  Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3831  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3832  RTLIB::SQRT_PPCF128));
3833  break;
3834  case ISD::FCBRT:
3835  Results.push_back(ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
3836  RTLIB::CBRT_F80, RTLIB::CBRT_F128,
3837  RTLIB::CBRT_PPCF128));
3838  break;
3839  case ISD::FSIN:
3840  case ISD::STRICT_FSIN:
3841  Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3842  RTLIB::SIN_F80, RTLIB::SIN_F128,
3843  RTLIB::SIN_PPCF128));
3844  break;
3845  case ISD::FCOS:
3846  case ISD::STRICT_FCOS:
3847  Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3848  RTLIB::COS_F80, RTLIB::COS_F128,
3849  RTLIB::COS_PPCF128));
3850  break;
3851  case ISD::FSINCOS:
3852  // Expand into sincos libcall.
3853  ExpandSinCosLibCall(Node, Results);
3854  break;
3855  case ISD::FLOG:
3856  case ISD::STRICT_FLOG:
3857  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log_finite))
3858  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_FINITE_F32,
3859  RTLIB::LOG_FINITE_F64,
3860  RTLIB::LOG_FINITE_F80,
3861  RTLIB::LOG_FINITE_F128,
3862  RTLIB::LOG_FINITE_PPCF128));
3863  else
3864  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3865  RTLIB::LOG_F80, RTLIB::LOG_F128,
3866  RTLIB::LOG_PPCF128));
3867  break;
3868  case ISD::FLOG2:
3869  case ISD::STRICT_FLOG2:
3870  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log2_finite))
3871  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_FINITE_F32,
3872  RTLIB::LOG2_FINITE_F64,
3873  RTLIB::LOG2_FINITE_F80,
3874  RTLIB::LOG2_FINITE_F128,
3875  RTLIB::LOG2_FINITE_PPCF128));
3876  else
3877  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3878  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3879  RTLIB::LOG2_PPCF128));
3880  break;
3881  case ISD::FLOG10:
3882  case ISD::STRICT_FLOG10:
3883  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log10_finite))
3884  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_FINITE_F32,
3885  RTLIB::LOG10_FINITE_F64,
3886  RTLIB::LOG10_FINITE_F80,
3887  RTLIB::LOG10_FINITE_F128,
3888  RTLIB::LOG10_FINITE_PPCF128));
3889  else
3890  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3891  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3892  RTLIB::LOG10_PPCF128));
3893  break;
3894  case ISD::FEXP:
3895  case ISD::STRICT_FEXP:
3896  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp_finite))
3897  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_FINITE_F32,
3898  RTLIB::EXP_FINITE_F64,
3899  RTLIB::EXP_FINITE_F80,
3900  RTLIB::EXP_FINITE_F128,
3901  RTLIB::EXP_FINITE_PPCF128));
3902  else
3903  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3904  RTLIB::EXP_F80, RTLIB::EXP_F128,
3905  RTLIB::EXP_PPCF128));
3906  break;
3907  case ISD::FEXP2:
3908  case ISD::STRICT_FEXP2:
3909  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp2_finite))
3910  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_FINITE_F32,
3911  RTLIB::EXP2_FINITE_F64,
3912  RTLIB::EXP2_FINITE_F80,
3913  RTLIB::EXP2_FINITE_F128,
3914  RTLIB::EXP2_FINITE_PPCF128));
3915  else
3916  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3917  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3918  RTLIB::EXP2_PPCF128));
3919  break;
3920  case ISD::FTRUNC:
3921  case ISD::STRICT_FTRUNC:
3922  Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3923  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3924  RTLIB::TRUNC_PPCF128));
3925  break;
3926  case ISD::FFLOOR:
3927  case ISD::STRICT_FFLOOR:
3928  Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3929  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3930  RTLIB::FLOOR_PPCF128));
3931  break;
3932  case ISD::FCEIL:
3933  case ISD::STRICT_FCEIL:
3934  Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3935  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3936  RTLIB::CEIL_PPCF128));
3937  break;
3938  case ISD::FRINT:
3939  case ISD::STRICT_FRINT:
3940  Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3941  RTLIB::RINT_F80, RTLIB::RINT_F128,
3942  RTLIB::RINT_PPCF128));
3943  break;
3944  case ISD::FNEARBYINT:
3946  Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3947  RTLIB::NEARBYINT_F64,
3948  RTLIB::NEARBYINT_F80,
3949  RTLIB::NEARBYINT_F128,
3950  RTLIB::NEARBYINT_PPCF128));
3951  break;
3952  case ISD::FROUND:
3953  case ISD::STRICT_FROUND:
3954  Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3955  RTLIB::ROUND_F64,
3956  RTLIB::ROUND_F80,
3957  RTLIB::ROUND_F128,
3958  RTLIB::ROUND_PPCF128));
3959  break;
3960  case ISD::FPOWI:
3961  case ISD::STRICT_FPOWI:
3962  Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3963  RTLIB::POWI_F80, RTLIB::POWI_F128,
3964  RTLIB::POWI_PPCF128));
3965  break;
3966  case ISD::FPOW:
3967  case ISD::STRICT_FPOW:
3968  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_pow_finite))
3969  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_FINITE_F32,
3970  RTLIB::POW_FINITE_F64,
3971  RTLIB::POW_FINITE_F80,
3972  RTLIB::POW_FINITE_F128,
3973  RTLIB::POW_FINITE_PPCF128));
3974  else
3975  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3976  RTLIB::POW_F80, RTLIB::POW_F128,
3977  RTLIB::POW_PPCF128));
3978  break;
3979  case ISD::LROUND:
3980  case ISD::STRICT_LROUND:
3981  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LROUND_F32,
3982  RTLIB::LROUND_F64, RTLIB::LROUND_F80,
3983  RTLIB::LROUND_F128,
3984  RTLIB::LROUND_PPCF128));
3985  break;
3986  case ISD::LLROUND:
3987  case ISD::STRICT_LLROUND:
3988  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LLROUND_F32,
3989  RTLIB::LLROUND_F64, RTLIB::LLROUND_F80,
3990  RTLIB::LLROUND_F128,
3991  RTLIB::LLROUND_PPCF128));
3992  break;
3993  case ISD::LRINT:
3994  case ISD::STRICT_LRINT:
3995  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LRINT_F32,
3996  RTLIB::LRINT_F64, RTLIB::LRINT_F80,
3997  RTLIB::LRINT_F128,
3998  RTLIB::LRINT_PPCF128));
3999  break;
4000  case ISD::LLRINT:
4001  case ISD::STRICT_LLRINT:
4002  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LLRINT_F32,
4003  RTLIB::LLRINT_F64, RTLIB::LLRINT_F80,
4004  RTLIB::LLRINT_F128,
4005  RTLIB::LLRINT_PPCF128));
4006  break;
4007  case ISD::FDIV:
4008  Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
4009  RTLIB::DIV_F80, RTLIB::DIV_F128,
4010  RTLIB::DIV_PPCF128));
4011  break;
4012  case ISD::FREM:
4013  case ISD::STRICT_FREM:
4014  Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
4015  RTLIB::REM_F80, RTLIB::REM_F128,
4016  RTLIB::REM_PPCF128));
4017  break;
4018  case ISD::FMA:
4019  case ISD::STRICT_FMA:
4020  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4021  RTLIB::FMA_F80, RTLIB::FMA_F128,
4022  RTLIB::FMA_PPCF128));
4023  break;
4024  case ISD::FADD:
4025  Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4026  RTLIB::ADD_F80, RTLIB::ADD_F128,
4027  RTLIB::ADD_PPCF128));
4028  break;
4029  case ISD::FMUL:
4030  Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4031  RTLIB::MUL_F80, RTLIB::MUL_F128,
4032  RTLIB::MUL_PPCF128));
4033  break;
4034  case ISD::FP16_TO_FP:
4035  if (Node->getValueType(0) == MVT::f32) {
4036  Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4037  }
4038  break;
4039  case ISD::FP_TO_FP16: {
4040  RTLIB::Libcall LC =
4042  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4043  Results.push_back(ExpandLibCall(LC, Node, false));
4044  break;
4045  }
4046  case ISD::FSUB:
4047  Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4048  RTLIB::SUB_F80, RTLIB::SUB_F128,
4049  RTLIB::SUB_PPCF128));
4050  break;
4051  case ISD::SREM:
4052  Results.push_back(ExpandIntLibCall(Node, true,
4053  RTLIB::SREM_I8,
4054  RTLIB::SREM_I16, RTLIB::SREM_I32,
4055  RTLIB::SREM_I64, RTLIB::SREM_I128));
4056  break;
4057  case ISD::UREM:
4058  Results.push_back(ExpandIntLibCall(Node, false,
4059  RTLIB::UREM_I8,
4060  RTLIB::UREM_I16, RTLIB::UREM_I32,
4061  RTLIB::UREM_I64, RTLIB::UREM_I128));
4062  break;
4063  case ISD::SDIV:
4064  Results.push_back(ExpandIntLibCall(Node, true,
4065  RTLIB::SDIV_I8,
4066  RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4067  RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4068  break;
4069  case ISD::UDIV:
4070  Results.push_back(ExpandIntLibCall(Node, false,
4071  RTLIB::UDIV_I8,
4072  RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4073  RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4074  break;
4075  case ISD::SDIVREM:
4076  case ISD::UDIVREM:
4077  // Expand into divrem libcall
4078  ExpandDivRemLibCall(Node, Results);
4079  break;
4080  case ISD::MUL:
4081  Results.push_back(ExpandIntLibCall(Node, false,
4082  RTLIB::MUL_I8,
4083  RTLIB::MUL_I16, RTLIB::MUL_I32,
4084  RTLIB::MUL_I64, RTLIB::MUL_I128));
4085  break;
4086  case ISD::CTLZ_ZERO_UNDEF:
4087  switch (Node->getSimpleValueType(0).SimpleTy) {
4088  default:
4089  llvm_unreachable("LibCall explicitly requested, but not available");
4090  case MVT::i32:
4091  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false));
4092  break;
4093  case MVT::i64:
4094  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false));
4095  break;
4096  case MVT::i128:
4097  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false));
4098  break;
4099  }
4100  break;
4101  }
4102 
4103  // Replace the original node with the legalized result.
4104  if (!Results.empty()) {
4105  LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
4106  ReplaceNode(Node, Results.data());
4107  } else
4108  LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
4109 }
4110 
4111 // Determine the vector type to use in place of an original scalar element when
4112 // promoting equally sized vectors.
4114  MVT EltVT, MVT NewEltVT) {
4115  unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4116  MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4117  assert(TLI.isTypeLegal(MidVT) && "unexpected");
4118  return MidVT;
4119 }
4120 
4121 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4122  LLVM_DEBUG(dbgs() << "Trying to promote node\n");
4124  MVT OVT = Node->getSimpleValueType(0);
4125  if (Node->getOpcode() == ISD::UINT_TO_FP ||
4126  Node->getOpcode() == ISD::SINT_TO_FP ||
4127  Node->getOpcode() == ISD::SETCC ||
4128  Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4129  Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4130  OVT = Node->getOperand(0).getSimpleValueType();
4131  }
4132  if (Node->getOpcode() == ISD::BR_CC)
4133  OVT = Node->getOperand(2).getSimpleValueType();
4134  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4135  SDLoc dl(Node);
4136  SDValue Tmp1, Tmp2, Tmp3;
4137  switch (Node->getOpcode()) {
4138  case ISD::CTTZ:
4139  case ISD::CTTZ_ZERO_UNDEF:
4140  case ISD::CTLZ:
4141  case ISD::CTLZ_ZERO_UNDEF:
4142  case ISD::CTPOP:
4143  // Zero extend the argument.
4144  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4145  if (Node->getOpcode() == ISD::CTTZ) {
4146  // The count is the same in the promoted type except if the original
4147  // value was zero. This can be handled by setting the bit just off
4148  // the top of the original type.
4149  auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
4150  OVT.getSizeInBits());
4151  Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4152  DAG.getConstant(TopBit, dl, NVT));
4153  }
4154  // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4155  // already the correct result.
4156  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4157  if (Node->getOpcode() == ISD::CTLZ ||
4158  Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4159  // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4160  Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4161  DAG.getConstant(NVT.getSizeInBits() -
4162  OVT.getSizeInBits(), dl, NVT));
4163  }
4164  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4165  break;
4166  case ISD::BITREVERSE:
4167  case ISD::BSWAP: {
4168  unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4169  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4170  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4171  Tmp1 = DAG.getNode(
4172  ISD::SRL, dl, NVT, Tmp1,
4173  DAG.getConstant(DiffBits, dl,
4174  TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4175 
4176  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4177  break;
4178  }
4179  case ISD::FP_TO_UINT:
4180  case ISD::FP_TO_SINT:
4181  Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4182  Node->getOpcode() == ISD::FP_TO_SINT, dl);
4183  Results.push_back(Tmp1);
4184  break;
4185  case ISD::UINT_TO_FP:
4186  case ISD::SINT_TO_FP:
4187  Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4188  Node->getOpcode() == ISD::SINT_TO_FP, dl);
4189  Results.push_back(Tmp1);
4190  break;
4191  case ISD::VAARG: {
4192  SDValue Chain = Node->getOperand(0); // Get the chain.
4193  SDValue Ptr = Node->getOperand(1); // Get the pointer.
4194 
4195  unsigned TruncOp;
4196  if (OVT.isVector()) {
4197  TruncOp = ISD::BITCAST;
4198  } else {
4199  assert(OVT.isInteger()
4200  && "VAARG promotion is supported only for vectors or integer types");
4201  TruncOp = ISD::TRUNCATE;
4202  }
4203 
4204  // Perform the larger operation, then convert back
4205  Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4206  Node->getConstantOperandVal(3));
4207  Chain = Tmp1.getValue(1);
4208 
4209  Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4210 
4211  // Modified the chain result - switch anything that used the old chain to
4212  // use the new one.
4213  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4214  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4215  if (UpdatedNodes) {
4216  UpdatedNodes->insert(Tmp2.getNode());
4217  UpdatedNodes->insert(Chain.getNode());
4218  }
4219  ReplacedNode(Node);
4220  break;
4221  }
4222  case ISD::MUL:
4223  case ISD::SDIV:
4224  case ISD::SREM:
4225  case ISD::UDIV:
4226  case ISD::UREM:
4227  case ISD::AND:
4228  case ISD::OR:
4229  case ISD::XOR: {
4230  unsigned ExtOp, TruncOp;
4231  if (OVT.isVector()) {
4232  ExtOp = ISD::BITCAST;
4233  TruncOp = ISD::BITCAST;
4234  } else {
4235  assert(OVT.isInteger() && "Cannot promote logic operation");
4236 
4237  switch (Node->getOpcode()) {
4238  default:
4239  ExtOp = ISD::ANY_EXTEND;
4240  break;
4241  case ISD::SDIV:
4242  case ISD::SREM:
4243  ExtOp = ISD::SIGN_EXTEND;
4244  break;
4245  case ISD::UDIV:
4246  case ISD::UREM:
4247  ExtOp = ISD::ZERO_EXTEND;
4248  break;
4249  }
4250  TruncOp = ISD::TRUNCATE;
4251  }
4252  // Promote each of the values to the new type.
4253  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4254  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4255  // Perform the larger operation, then convert back
4256  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4257  Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4258  break;
4259  }
4260  case ISD::UMUL_LOHI:
4261  case ISD::SMUL_LOHI: {
4262  // Promote to a multiply in a wider integer type.
4263  unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4264  : ISD::SIGN_EXTEND;
4265  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4266  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4267  Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4268 
4269  auto &DL = DAG.getDataLayout();
4270  unsigned OriginalSize = OVT.getScalarSizeInBits();
4271  Tmp2 = DAG.getNode(
4272  ISD::SRL, dl, NVT, Tmp1,
4273  DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4274  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4275  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4276  break;
4277  }
4278  case ISD::SELECT: {
4279  unsigned ExtOp, TruncOp;
4280  if (Node->getValueType(0).isVector() ||
4281  Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4282  ExtOp = ISD::BITCAST;
4283  TruncOp = ISD::BITCAST;
4284  } else if (Node->getValueType(0).isInteger()) {
4285  ExtOp = ISD::ANY_EXTEND;
4286  TruncOp = ISD::TRUNCATE;
4287  } else {
4288  ExtOp = ISD::FP_EXTEND;
4289  TruncOp = ISD::FP_ROUND;
4290  }
4291  Tmp1 = Node->getOperand(0);
4292  // Promote each of the values to the new type.
4293  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4294  Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4295  // Perform the larger operation, then round down.
4296  Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4297  Tmp1->setFlags(Node->getFlags());
4298  if (TruncOp != ISD::FP_ROUND)
4299  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4300  else
4301  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4302  DAG.getIntPtrConstant(0, dl));
4303  Results.push_back(Tmp1);
4304  break;
4305  }
4306  case ISD::VECTOR_SHUFFLE: {
4307  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4308 
4309  // Cast the two input vectors.
4310  Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4311  Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4312 
4313  // Convert the shuffle mask to the right # elements.
4314  Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4315  Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4316  Results.push_back(Tmp1);
4317  break;
4318  }
4319  case ISD::SETCC: {
4320  unsigned ExtOp = ISD::FP_EXTEND;
4321  if (NVT.isInteger()) {
4322  ISD::CondCode CCCode =
4323  cast<CondCodeSDNode>(Node->getOperand(2))->get();
4325  }
4326  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4327  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4328  Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1,
4329  Tmp2, Node->getOperand(2), Node->getFlags()));
4330  break;
4331  }
4332  case ISD::BR_CC: {
4333  unsigned ExtOp = ISD::FP_EXTEND;
4334  if (NVT.isInteger()) {
4335  ISD::CondCode CCCode =
4336  cast<CondCodeSDNode>(Node->getOperand(1))->get();
4338  }
4339  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4340  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4341  Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4342  Node->getOperand(0), Node->getOperand(1),
4343  Tmp1, Tmp2, Node->getOperand(4)));
4344  break;
4345  }
4346  case ISD::FADD:
4347  case ISD::FSUB:
4348  case ISD::FMUL:
4349  case ISD::FDIV:
4350  case ISD::FREM:
4351  case ISD::FMINNUM:
4352  case ISD::FMAXNUM:
4353  case ISD::FPOW:
4354  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4355  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4356  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4357  Node->getFlags());
4358  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4359  Tmp3, DAG.getIntPtrConstant(0, dl)));
4360  break;
4361  case ISD::FMA:
4362  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4363  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4364  Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4365  Results.push_back(
4366  DAG.getNode(ISD::FP_ROUND, dl, OVT,
4367  DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4368  DAG.getIntPtrConstant(0, dl)));
4369  break;
4370  case ISD::FCOPYSIGN:
4371  case ISD::FPOWI: {
4372  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4373  Tmp2 = Node->getOperand(1);
4374  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4375 
4376  // fcopysign doesn't change anything but the sign bit, so
4377  // (fp_round (fcopysign (fpext a), b))
4378  // is as precise as
4379  // (fp_round (fpext a))
4380  // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4381  const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4382  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4383  Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4384  break;
4385  }
4386  case ISD::FFLOOR:
4387  case ISD::FCEIL:
4388  case ISD::FRINT:
4389  case ISD::FNEARBYINT:
4390  case ISD::FROUND:
4391  case ISD::FTRUNC:
4392  case ISD::FNEG:
4393  case ISD::FSQRT:
4394  case ISD::FSIN:
4395  case ISD::FCOS:
4396  case ISD::FLOG:
4397  case ISD::FLOG2:
4398  case ISD::FLOG10:
4399  case ISD::FABS:
4400  case ISD::FEXP:
4401  case ISD::FEXP2:
4402  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4403  Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4404  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4405  Tmp2, DAG.getIntPtrConstant(0, dl)));
4406  break;
4407  case ISD::BUILD_VECTOR: {
4408  MVT EltVT = OVT.getVectorElementType();
4409  MVT NewEltVT = NVT.getVectorElementType();
4410 
4411  // Handle bitcasts to a different vector type with the same total bit size
4412  //
4413  // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4414  // =>
4415  // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4416 
4417  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4418  "Invalid promote type for build_vector");
4419  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4420 
4421  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4422 
4423  SmallVector<SDValue, 8> NewOps;
4424  for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4425  SDValue Op = Node->getOperand(I);
4426  NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4427  }
4428 
4429  SDLoc SL(Node);
4430  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4431  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4432  Results.push_back(CvtVec);
4433  break;
4434  }
4435  case ISD::EXTRACT_VECTOR_ELT: {
4436  MVT EltVT = OVT.getVectorElementType();
4437  MVT NewEltVT = NVT.getVectorElementType();
4438 
4439  // Handle bitcasts to a different vector type with the same total bit size.
4440  //
4441  // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4442  // =>
4443  // v4i32:castx = bitcast x:v2i64
4444  //
4445  // i64 = bitcast
4446  // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4447  // (i32 (extract_vector_elt castx, (2 * y + 1)))
4448  //
4449 
4450  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4451  "Invalid promote type for extract_vector_elt");
4452  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4453 
4454  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4455  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4456 
4457  SDValue Idx = Node->getOperand(1);
4458  EVT IdxVT = Idx.getValueType();
4459  SDLoc SL(Node);
4460  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4461  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4462 
4463  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4464 
4465  SmallVector<SDValue, 8> NewOps;
4466  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4467  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4468  SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4469 
4470  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4471  CastVec, TmpIdx);
4472  NewOps.push_back(Elt);
4473  }
4474 
4475  SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4476  Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4477  break;
4478  }
4479  case ISD::INSERT_VECTOR_ELT: {
4480  MVT EltVT = OVT.getVectorElementType();
4481  MVT NewEltVT = NVT.getVectorElementType();
4482 
4483  // Handle bitcasts to a different vector type with the same total bit size
4484  //
4485  // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4486  // =>
4487  // v4i32:castx = bitcast x:v2i64
4488  // v2i32:casty = bitcast y:i64
4489  //
4490  // v2i64 = bitcast
4491  // (v4i32 insert_vector_elt
4492  // (v4i32 insert_vector_elt v4i32:castx,
4493  // (extract_vector_elt casty, 0), 2 * z),
4494  // (extract_vector_elt casty, 1), (2 * z + 1))
4495 
4496  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4497  "Invalid promote type for insert_vector_elt");
4498  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4499 
4500  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4501  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4502 
4503  SDValue Val = Node->getOperand(1);
4504  SDValue Idx = Node->getOperand(2);
4505  EVT IdxVT = Idx.getValueType();
4506  SDLoc SL(Node);
4507 
4508  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4509  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4510 
4511  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4512  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4513 
4514  SDValue NewVec = CastVec;
4515  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4516  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4517  SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4518 
4519  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4520  CastVal, IdxOffset);
4521 
4522  NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4523  NewVec, Elt, InEltIdx);
4524  }
4525 
4526  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4527  break;
4528  }
4529  case ISD::SCALAR_TO_VECTOR: {
4530  MVT EltVT = OVT.getVectorElementType();
4531  MVT NewEltVT = NVT.getVectorElementType();
4532 
4533  // Handle bitcasts to different vector type with the same total bit size.
4534  //
4535  // e.g. v2i64 = scalar_to_vector x:i64
4536  // =>
4537  // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4538  //
4539 
4540  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4541  SDValue Val = Node->getOperand(0);
4542  SDLoc SL(Node);
4543 
4544  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4545  SDValue Undef = DAG.getUNDEF(MidVT);
4546 
4547  SmallVector<SDValue, 8> NewElts;
4548  NewElts.push_back(CastVal);
4549  for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4550  NewElts.push_back(Undef);
4551 
4552  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4553  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4554  Results.push_back(CvtVec);
4555  break;
4556  }
4557  case ISD::ATOMIC_SWAP: {
4558  AtomicSDNode *AM = cast<AtomicSDNode>(Node);
4559  SDLoc SL(Node);
4560  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
4561  assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
4562  "unexpected promotion type");
4563  assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
4564  "unexpected atomic_swap with illegal type");
4565 
4566  SDValue NewAtomic
4567  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, NVT,
4568  DAG.getVTList(NVT, MVT::Other),
4569  { AM->getChain(), AM->getBasePtr(), CastVal },
4570  AM->getMemOperand());
4571  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
4572  Results.push_back(NewAtomic.getValue(1));
4573  break;
4574  }
4575  }
4576 
4577  // Replace the original node with the legalized result.
4578  if (!Results.empty()) {
4579  LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
4580  ReplaceNode(Node, Results.data());
4581  } else
4582  LLVM_DEBUG(dbgs() << "Could not promote node\n");
4583 }
4584 
4585 /// This is the entry point for the file.
4587  AssignTopologicalOrder();
4588 
4589  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4590  // Use a delete listener to remove nodes which were deleted during
4591  // legalization from LegalizeNodes. This is needed to handle the situation
4592  // where a new node is allocated by the object pool to the same address of a
4593  // previously deleted node.
4594  DAGNodeDeletedListener DeleteListener(
4595  *this,
4596  [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(N); });
4597 
4598  SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4599 
4600  // Visit all the nodes. We start in topological order, so that we see
4601  // nodes with their original operands intact. Legalization can produce
4602  // new nodes which may themselves need to be legalized. Iterate until all
4603  // nodes have been legalized.
4604  while (true) {
4605  bool AnyLegalized = false;
4606  for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4607  --NI;
4608 
4609  SDNode *N = &*NI;
4610  if (N->use_empty() && N != getRoot().getNode()) {
4611  ++NI;
4612  DeleteNode(N);
4613  continue;
4614  }
4615 
4616  if (LegalizedNodes.insert(N).second) {
4617  AnyLegalized = true;
4618  Legalizer.LegalizeOp(N);
4619 
4620  if (N->use_empty() && N != getRoot().getNode()) {
4621  ++NI;
4622  DeleteNode(N);
4623  }
4624  }
4625  }
4626  if (!AnyLegalized)
4627  break;
4628 
4629  }
4630 
4631  // Remove dead nodes now.
4632  RemoveDeadNodes();
4633 }
4634 
4636  SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4637  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4638  SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4639 
4640  // Directly insert the node in question, and legalize it. This will recurse
4641  // as needed through operands.
4642  LegalizedNodes.insert(N);
4643  Legalizer.LegalizeOp(N);
4644 
4645  return LegalizedNodes.count(N);
4646 }
bool LegalizeOp(SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target ...
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:803
static Constant * getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced=false)
Definition: Constants.cpp:1710
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:603
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:577
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:921
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:630
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isInteger() const
Return true if this is an integer or a vector integer type.
void setFlags(SDNodeFlags NewFlags)
static bool isConstant(const MachineInstr &MI)
bool isUndef() const
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:390
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:686
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:399
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
const SDValue & getVal() const
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
bool isVector() const
Return true if this is a vector value type.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void push_back(const T &Elt)
Definition: SmallVector.h:211
const SDValue & getValue() const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:738
SDVTList getVTList() const
This file contains the declarations for metadata subclasses.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
const SDValue & getBasePtr() const
unsigned getVectorNumElements() const
const SDValue & getChain() const
Function Alias Analysis Results
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:414
static MVT getPromotedVectorElementType(const TargetLowering &TLI, MVT EltVT, MVT NewEltVT)
unsigned getAlignment() const
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:841
unsigned second
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:865
static uint32_t Concat[]
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:181
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:423
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Same for subtraction.
Definition: ISDOpcodes.h:253
void reserve(size_type N)
Definition: SmallVector.h:369
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:385
The address of the GOT.
Definition: ISDOpcodes.h:65
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:820
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:474
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
const ConstantFP * getConstantFPValue() const
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isTruncatingStore() const
Return true if the op does a truncation before store.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode *> &Visited, SmallVectorImpl< const SDNode *> &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
Definition: ISDOpcodes.h:113
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:495
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Shift and rotation operations.
Definition: ISDOpcodes.h:449
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:264
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:432
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:659
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
op_iterator op_end() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
Definition: ISDOpcodes.h:585
SimpleValueType SimpleTy
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence, and carry arbitrary information that target might want to know.
Definition: ISDOpcodes.h:752
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA)...
Definition: ISDOpcodes.h:95
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:849
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:417
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
This is an SDNode representing atomic operations.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:734
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:90
unsigned getSizeInBits() const
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:517
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here...
Definition: ISDOpcodes.h:117
falkor hwpf fix Falkor HW Prefetch Fix Late Phase
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:418
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200