LLVM  9.0.0svn
LegalizeDAG.cpp
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1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SelectionDAG::Legalize method.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/Metadata.h"
38 #include "llvm/IR/Type.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/Debug.h"
48 #include <algorithm>
49 #include <cassert>
50 #include <cstdint>
51 #include <tuple>
52 #include <utility>
53 
54 using namespace llvm;
55 
56 #define DEBUG_TYPE "legalizedag"
57 
58 namespace {
59 
60 /// Keeps track of state when getting the sign of a floating-point value as an
61 /// integer.
62 struct FloatSignAsInt {
63  EVT FloatVT;
64  SDValue Chain;
65  SDValue FloatPtr;
66  SDValue IntPtr;
67  MachinePointerInfo IntPointerInfo;
68  MachinePointerInfo FloatPointerInfo;
69  SDValue IntValue;
70  APInt SignMask;
71  uint8_t SignBit;
72 };
73 
74 //===----------------------------------------------------------------------===//
75 /// This takes an arbitrary SelectionDAG as input and
76 /// hacks on it until the target machine can handle it. This involves
77 /// eliminating value sizes the machine cannot handle (promoting small sizes to
78 /// large sizes or splitting up large values into small values) as well as
79 /// eliminating operations the machine cannot handle.
80 ///
81 /// This code also does a small amount of optimization and recognition of idioms
82 /// as part of its processing. For example, if a target does not support a
83 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
84 /// will attempt merge setcc and brc instructions into brcc's.
85 class SelectionDAGLegalize {
86  const TargetMachine &TM;
87  const TargetLowering &TLI;
88  SelectionDAG &DAG;
89 
90  /// The set of nodes which have already been legalized. We hold a
91  /// reference to it in order to update as necessary on node deletion.
92  SmallPtrSetImpl<SDNode *> &LegalizedNodes;
93 
94  /// A set of all the nodes updated during legalization.
95  SmallSetVector<SDNode *, 16> *UpdatedNodes;
96 
97  EVT getSetCCResultType(EVT VT) const {
98  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
99  }
100 
101  // Libcall insertion helpers.
102 
103 public:
104  SelectionDAGLegalize(SelectionDAG &DAG,
105  SmallPtrSetImpl<SDNode *> &LegalizedNodes,
106  SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
107  : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
108  LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
109 
110  /// Legalizes the given operation.
111  void LegalizeOp(SDNode *Node);
112 
113 private:
114  SDValue OptimizeFloatStore(StoreSDNode *ST);
115 
116  void LegalizeLoadOps(SDNode *Node);
117  void LegalizeStoreOps(SDNode *Node);
118 
119  /// Some targets cannot handle a variable
120  /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
121  /// is necessary to spill the vector being inserted into to memory, perform
122  /// the insert there, and then read the result back.
123  SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
124  const SDLoc &dl);
125  SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
126  const SDLoc &dl);
127 
128  /// Return a vector shuffle operation which
129  /// performs the same shuffe in terms of order or result bytes, but on a type
130  /// whose vector element type is narrower than the original shuffle type.
131  /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
132  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
133  SDValue N1, SDValue N2,
134  ArrayRef<int> Mask) const;
135 
136  bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
137  bool &NeedInvert, const SDLoc &dl);
138 
139  SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
140  SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
141  unsigned NumOps, bool isSigned, const SDLoc &dl);
142 
143  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
144  SDNode *Node, bool isSigned);
145  SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
146  RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
147  RTLIB::Libcall Call_F128,
148  RTLIB::Libcall Call_PPCF128);
149  SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
150  RTLIB::Libcall Call_I8,
151  RTLIB::Libcall Call_I16,
152  RTLIB::Libcall Call_I32,
153  RTLIB::Libcall Call_I64,
154  RTLIB::Libcall Call_I128);
155  void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
156  void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
157 
158  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
159  const SDLoc &dl);
160  SDValue ExpandBUILD_VECTOR(SDNode *Node);
161  SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
162  void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
163  SmallVectorImpl<SDValue> &Results);
164  void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
165  SDValue Value) const;
166  SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
167  SDValue NewIntValue) const;
168  SDValue ExpandFCOPYSIGN(SDNode *Node) const;
169  SDValue ExpandFABS(SDNode *Node) const;
170  SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
171  const SDLoc &dl);
172  SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
173  const SDLoc &dl);
174  SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
175  const SDLoc &dl);
176 
177  SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
178  SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
179 
180  SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
181  SDValue ExpandInsertToVectorThroughStack(SDValue Op);
182  SDValue ExpandVectorBuildThroughStack(SDNode* Node);
183 
184  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
185  SDValue ExpandConstant(ConstantSDNode *CP);
186 
187  // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
188  bool ExpandNode(SDNode *Node);
189  void ConvertNodeToLibcall(SDNode *Node);
190  void PromoteNode(SDNode *Node);
191 
192 public:
193  // Node replacement helpers
194 
195  void ReplacedNode(SDNode *N) {
196  LegalizedNodes.erase(N);
197  if (UpdatedNodes)
198  UpdatedNodes->insert(N);
199  }
200 
201  void ReplaceNode(SDNode *Old, SDNode *New) {
202  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
203  dbgs() << " with: "; New->dump(&DAG));
204 
205  assert(Old->getNumValues() == New->getNumValues() &&
206  "Replacing one node with another that produces a different number "
207  "of values!");
208  DAG.ReplaceAllUsesWith(Old, New);
209  if (UpdatedNodes)
210  UpdatedNodes->insert(New);
211  ReplacedNode(Old);
212  }
213 
214  void ReplaceNode(SDValue Old, SDValue New) {
215  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
216  dbgs() << " with: "; New->dump(&DAG));
217 
218  DAG.ReplaceAllUsesWith(Old, New);
219  if (UpdatedNodes)
220  UpdatedNodes->insert(New.getNode());
221  ReplacedNode(Old.getNode());
222  }
223 
224  void ReplaceNode(SDNode *Old, const SDValue *New) {
225  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
226 
227  DAG.ReplaceAllUsesWith(Old, New);
228  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
229  LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
230  New[i]->dump(&DAG));
231  if (UpdatedNodes)
232  UpdatedNodes->insert(New[i].getNode());
233  }
234  ReplacedNode(Old);
235  }
236 };
237 
238 } // end anonymous namespace
239 
240 /// Return a vector shuffle operation which
241 /// performs the same shuffle in terms of order or result bytes, but on a type
242 /// whose vector element type is narrower than the original shuffle type.
243 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
244 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
245  EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
246  ArrayRef<int> Mask) const {
247  unsigned NumMaskElts = VT.getVectorNumElements();
248  unsigned NumDestElts = NVT.getVectorNumElements();
249  unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
250 
251  assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
252 
253  if (NumEltsGrowth == 1)
254  return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
255 
256  SmallVector<int, 8> NewMask;
257  for (unsigned i = 0; i != NumMaskElts; ++i) {
258  int Idx = Mask[i];
259  for (unsigned j = 0; j != NumEltsGrowth; ++j) {
260  if (Idx < 0)
261  NewMask.push_back(-1);
262  else
263  NewMask.push_back(Idx * NumEltsGrowth + j);
264  }
265  }
266  assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
267  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
268  return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
269 }
270 
271 /// Expands the ConstantFP node to an integer constant or
272 /// a load from the constant pool.
273 SDValue
274 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
275  bool Extend = false;
276  SDLoc dl(CFP);
277 
278  // If a FP immediate is precise when represented as a float and if the
279  // target can do an extending load from float to double, we put it into
280  // the constant pool as a float, even if it's is statically typed as a
281  // double. This shrinks FP constants and canonicalizes them for targets where
282  // an FP extending load is the same cost as a normal load (such as on the x87
283  // fp stack or PPC FP unit).
284  EVT VT = CFP->getValueType(0);
285  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
286  if (!UseCP) {
287  assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
288  return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
289  (VT == MVT::f64) ? MVT::i64 : MVT::i32);
290  }
291 
292  APFloat APF = CFP->getValueAPF();
293  EVT OrigVT = VT;
294  EVT SVT = VT;
295 
296  // We don't want to shrink SNaNs. Converting the SNaN back to its real type
297  // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
298  if (!APF.isSignaling()) {
299  while (SVT != MVT::f32 && SVT != MVT::f16) {
300  SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
302  // Only do this if the target has a native EXTLOAD instruction from
303  // smaller type.
304  TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
305  TLI.ShouldShrinkFPConstant(OrigVT)) {
306  Type *SType = SVT.getTypeForEVT(*DAG.getContext());
307  LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
308  VT = SVT;
309  Extend = true;
310  }
311  }
312  }
313 
314  SDValue CPIdx =
315  DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
316  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
317  if (Extend) {
318  SDValue Result = DAG.getExtLoad(
319  ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
320  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
321  Alignment);
322  return Result;
323  }
324  SDValue Result = DAG.getLoad(
325  OrigVT, dl, DAG.getEntryNode(), CPIdx,
326  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
327  return Result;
328 }
329 
330 /// Expands the Constant node to a load from the constant pool.
331 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
332  SDLoc dl(CP);
333  EVT VT = CP->getValueType(0);
334  SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
335  TLI.getPointerTy(DAG.getDataLayout()));
336  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
337  SDValue Result = DAG.getLoad(
338  VT, dl, DAG.getEntryNode(), CPIdx,
339  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
340  return Result;
341 }
342 
343 /// Some target cannot handle a variable insertion index for the
344 /// INSERT_VECTOR_ELT instruction. In this case, it
345 /// is necessary to spill the vector being inserted into to memory, perform
346 /// the insert there, and then read the result back.
347 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
348  SDValue Val,
349  SDValue Idx,
350  const SDLoc &dl) {
351  SDValue Tmp1 = Vec;
352  SDValue Tmp2 = Val;
353  SDValue Tmp3 = Idx;
354 
355  // If the target doesn't support this, we have to spill the input vector
356  // to a temporary stack slot, update the element, then reload it. This is
357  // badness. We could also load the value into a vector register (either
358  // with a "move to register" or "extload into register" instruction, then
359  // permute it into place, if the idx is a constant and if the idx is
360  // supported by the target.
361  EVT VT = Tmp1.getValueType();
362  EVT EltVT = VT.getVectorElementType();
363  SDValue StackPtr = DAG.CreateStackTemporary(VT);
364 
365  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
366 
367  // Store the vector.
368  SDValue Ch = DAG.getStore(
369  DAG.getEntryNode(), dl, Tmp1, StackPtr,
370  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
371 
372  SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
373 
374  // Store the scalar value.
375  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT);
376  // Load the updated vector.
377  return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
378  DAG.getMachineFunction(), SPFI));
379 }
380 
381 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
382  SDValue Idx,
383  const SDLoc &dl) {
384  if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
385  // SCALAR_TO_VECTOR requires that the type of the value being inserted
386  // match the element type of the vector being created, except for
387  // integers in which case the inserted value can be over width.
388  EVT EltVT = Vec.getValueType().getVectorElementType();
389  if (Val.getValueType() == EltVT ||
390  (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
391  SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
392  Vec.getValueType(), Val);
393 
394  unsigned NumElts = Vec.getValueType().getVectorNumElements();
395  // We generate a shuffle of InVec and ScVec, so the shuffle mask
396  // should be 0,1,2,3,4,5... with the appropriate element replaced with
397  // elt 0 of the RHS.
398  SmallVector<int, 8> ShufOps;
399  for (unsigned i = 0; i != NumElts; ++i)
400  ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
401 
402  return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
403  }
404  }
405  return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
406 }
407 
408 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
409  LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
410  // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
411  // FIXME: We shouldn't do this for TargetConstantFP's.
412  // FIXME: move this to the DAG Combiner! Note that we can't regress due
413  // to phase ordering between legalized code and the dag combiner. This
414  // probably means that we need to integrate dag combiner and legalizer
415  // together.
416  // We generally can't do this one for long doubles.
417  SDValue Chain = ST->getChain();
418  SDValue Ptr = ST->getBasePtr();
419  unsigned Alignment = ST->getAlignment();
420  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
421  AAMDNodes AAInfo = ST->getAAInfo();
422  SDLoc dl(ST);
423  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
424  if (CFP->getValueType(0) == MVT::f32 &&
425  TLI.isTypeLegal(MVT::i32)) {
426  SDValue Con = DAG.getConstant(CFP->getValueAPF().
427  bitcastToAPInt().zextOrTrunc(32),
428  SDLoc(CFP), MVT::i32);
429  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), Alignment,
430  MMOFlags, AAInfo);
431  }
432 
433  if (CFP->getValueType(0) == MVT::f64) {
434  // If this target supports 64-bit registers, do a single 64-bit store.
435  if (TLI.isTypeLegal(MVT::i64)) {
436  SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
437  zextOrTrunc(64), SDLoc(CFP), MVT::i64);
438  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
439  Alignment, MMOFlags, AAInfo);
440  }
441 
442  if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
443  // Otherwise, if the target supports 32-bit registers, use 2 32-bit
444  // stores. If the target supports neither 32- nor 64-bits, this
445  // xform is certainly not worth it.
446  const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
447  SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
448  SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
449  if (DAG.getDataLayout().isBigEndian())
450  std::swap(Lo, Hi);
451 
452  Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
453  MMOFlags, AAInfo);
454  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
455  DAG.getConstant(4, dl, Ptr.getValueType()));
456  Hi = DAG.getStore(Chain, dl, Hi, Ptr,
457  ST->getPointerInfo().getWithOffset(4),
458  MinAlign(Alignment, 4U), MMOFlags, AAInfo);
459 
460  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
461  }
462  }
463  }
464  return SDValue(nullptr, 0);
465 }
466 
467 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
468  StoreSDNode *ST = cast<StoreSDNode>(Node);
469  SDValue Chain = ST->getChain();
470  SDValue Ptr = ST->getBasePtr();
471  SDLoc dl(Node);
472 
473  unsigned Alignment = ST->getAlignment();
474  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
475  AAMDNodes AAInfo = ST->getAAInfo();
476 
477  if (!ST->isTruncatingStore()) {
478  LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
479  if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
480  ReplaceNode(ST, OptStore);
481  return;
482  }
483 
484  SDValue Value = ST->getValue();
485  MVT VT = Value.getSimpleValueType();
486  switch (TLI.getOperationAction(ISD::STORE, VT)) {
487  default: llvm_unreachable("This action is not supported yet!");
488  case TargetLowering::Legal: {
489  // If this is an unaligned store and the target doesn't support it,
490  // expand it.
491  EVT MemVT = ST->getMemoryVT();
492  unsigned AS = ST->getAddressSpace();
493  unsigned Align = ST->getAlignment();
494  const DataLayout &DL = DAG.getDataLayout();
495  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
496  LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
497  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
498  ReplaceNode(SDValue(ST, 0), Result);
499  } else
500  LLVM_DEBUG(dbgs() << "Legal store\n");
501  break;
502  }
503  case TargetLowering::Custom: {
504  LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
505  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
506  if (Res && Res != SDValue(Node, 0))
507  ReplaceNode(SDValue(Node, 0), Res);
508  return;
509  }
511  MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
512  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
513  "Can only promote stores to same size type");
514  Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
515  SDValue Result =
516  DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
517  Alignment, MMOFlags, AAInfo);
518  ReplaceNode(SDValue(Node, 0), Result);
519  break;
520  }
521  }
522  return;
523  }
524 
525  LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
526  SDValue Value = ST->getValue();
527  EVT StVT = ST->getMemoryVT();
528  unsigned StWidth = StVT.getSizeInBits();
529  auto &DL = DAG.getDataLayout();
530 
531  if (StWidth != StVT.getStoreSizeInBits()) {
532  // Promote to a byte-sized store with upper bits zero if not
533  // storing an integral number of bytes. For example, promote
534  // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
535  EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
536  StVT.getStoreSizeInBits());
537  Value = DAG.getZeroExtendInReg(Value, dl, StVT);
538  SDValue Result =
539  DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
540  Alignment, MMOFlags, AAInfo);
541  ReplaceNode(SDValue(Node, 0), Result);
542  } else if (StWidth & (StWidth - 1)) {
543  // If not storing a power-of-2 number of bits, expand as two stores.
544  assert(!StVT.isVector() && "Unsupported truncstore!");
545  unsigned RoundWidth = 1 << Log2_32(StWidth);
546  assert(RoundWidth < StWidth);
547  unsigned ExtraWidth = StWidth - RoundWidth;
548  assert(ExtraWidth < RoundWidth);
549  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
550  "Store size not an integral number of bytes!");
551  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
552  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
553  SDValue Lo, Hi;
554  unsigned IncrementSize;
555 
556  if (DL.isLittleEndian()) {
557  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
558  // Store the bottom RoundWidth bits.
559  Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
560  RoundVT, Alignment, MMOFlags, AAInfo);
561 
562  // Store the remaining ExtraWidth bits.
563  IncrementSize = RoundWidth / 8;
564  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
565  DAG.getConstant(IncrementSize, dl,
566  Ptr.getValueType()));
567  Hi = DAG.getNode(
568  ISD::SRL, dl, Value.getValueType(), Value,
569  DAG.getConstant(RoundWidth, dl,
570  TLI.getShiftAmountTy(Value.getValueType(), DL)));
571  Hi = DAG.getTruncStore(
572  Chain, dl, Hi, Ptr,
573  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
574  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
575  } else {
576  // Big endian - avoid unaligned stores.
577  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
578  // Store the top RoundWidth bits.
579  Hi = DAG.getNode(
580  ISD::SRL, dl, Value.getValueType(), Value,
581  DAG.getConstant(ExtraWidth, dl,
582  TLI.getShiftAmountTy(Value.getValueType(), DL)));
583  Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
584  RoundVT, Alignment, MMOFlags, AAInfo);
585 
586  // Store the remaining ExtraWidth bits.
587  IncrementSize = RoundWidth / 8;
588  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
589  DAG.getConstant(IncrementSize, dl,
590  Ptr.getValueType()));
591  Lo = DAG.getTruncStore(
592  Chain, dl, Value, Ptr,
593  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
594  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
595  }
596 
597  // The order of the stores doesn't matter.
598  SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
599  ReplaceNode(SDValue(Node, 0), Result);
600  } else {
601  switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
602  default: llvm_unreachable("This action is not supported yet!");
603  case TargetLowering::Legal: {
604  EVT MemVT = ST->getMemoryVT();
605  unsigned AS = ST->getAddressSpace();
606  unsigned Align = ST->getAlignment();
607  // If this is an unaligned store and the target doesn't support it,
608  // expand it.
609  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
610  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
611  ReplaceNode(SDValue(ST, 0), Result);
612  }
613  break;
614  }
615  case TargetLowering::Custom: {
616  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
617  if (Res && Res != SDValue(Node, 0))
618  ReplaceNode(SDValue(Node, 0), Res);
619  return;
620  }
622  assert(!StVT.isVector() &&
623  "Vector Stores are handled in LegalizeVectorOps");
624 
625  SDValue Result;
626 
627  // TRUNCSTORE:i16 i32 -> STORE i16
628  if (TLI.isTypeLegal(StVT)) {
629  Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
630  Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
631  Alignment, MMOFlags, AAInfo);
632  } else {
633  // The in-memory type isn't legal. Truncate to the type it would promote
634  // to, and then do a truncstore.
635  Value = DAG.getNode(ISD::TRUNCATE, dl,
636  TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
637  Value);
638  Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
639  StVT, Alignment, MMOFlags, AAInfo);
640  }
641 
642  ReplaceNode(SDValue(Node, 0), Result);
643  break;
644  }
645  }
646 }
647 
648 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
649  LoadSDNode *LD = cast<LoadSDNode>(Node);
650  SDValue Chain = LD->getChain(); // The chain.
651  SDValue Ptr = LD->getBasePtr(); // The base pointer.
652  SDValue Value; // The value returned by the load op.
653  SDLoc dl(Node);
654 
656  if (ExtType == ISD::NON_EXTLOAD) {
657  LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
658  MVT VT = Node->getSimpleValueType(0);
659  SDValue RVal = SDValue(Node, 0);
660  SDValue RChain = SDValue(Node, 1);
661 
662  switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
663  default: llvm_unreachable("This action is not supported yet!");
664  case TargetLowering::Legal: {
665  EVT MemVT = LD->getMemoryVT();
666  unsigned AS = LD->getAddressSpace();
667  unsigned Align = LD->getAlignment();
668  const DataLayout &DL = DAG.getDataLayout();
669  // If this is an unaligned load and the target doesn't support it,
670  // expand it.
671  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
672  std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
673  }
674  break;
675  }
677  if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
678  RVal = Res;
679  RChain = Res.getValue(1);
680  }
681  break;
682 
684  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
685  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
686  "Can only promote loads to same size type");
687 
688  SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
689  RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
690  RChain = Res.getValue(1);
691  break;
692  }
693  }
694  if (RChain.getNode() != Node) {
695  assert(RVal.getNode() != Node && "Load must be completely replaced");
696  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
697  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
698  if (UpdatedNodes) {
699  UpdatedNodes->insert(RVal.getNode());
700  UpdatedNodes->insert(RChain.getNode());
701  }
702  ReplacedNode(Node);
703  }
704  return;
705  }
706 
707  LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
708  EVT SrcVT = LD->getMemoryVT();
709  unsigned SrcWidth = SrcVT.getSizeInBits();
710  unsigned Alignment = LD->getAlignment();
711  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
712  AAMDNodes AAInfo = LD->getAAInfo();
713 
714  if (SrcWidth != SrcVT.getStoreSizeInBits() &&
715  // Some targets pretend to have an i1 loading operation, and actually
716  // load an i8. This trick is correct for ZEXTLOAD because the top 7
717  // bits are guaranteed to be zero; it helps the optimizers understand
718  // that these bits are zero. It is also useful for EXTLOAD, since it
719  // tells the optimizers that those bits are undefined. It would be
720  // nice to have an effective generic way of getting these benefits...
721  // Until such a way is found, don't insist on promoting i1 here.
722  (SrcVT != MVT::i1 ||
723  TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
725  // Promote to a byte-sized load if not loading an integral number of
726  // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
727  unsigned NewWidth = SrcVT.getStoreSizeInBits();
728  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
729  SDValue Ch;
730 
731  // The extra bits are guaranteed to be zero, since we stored them that
732  // way. A zext load from NVT thus automatically gives zext from SrcVT.
733 
734  ISD::LoadExtType NewExtType =
736 
737  SDValue Result =
738  DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Chain, Ptr,
739  LD->getPointerInfo(), NVT, Alignment, MMOFlags, AAInfo);
740 
741  Ch = Result.getValue(1); // The chain.
742 
743  if (ExtType == ISD::SEXTLOAD)
744  // Having the top bits zero doesn't help when sign extending.
745  Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
746  Result.getValueType(),
747  Result, DAG.getValueType(SrcVT));
748  else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
749  // All the top bits are guaranteed to be zero - inform the optimizers.
750  Result = DAG.getNode(ISD::AssertZext, dl,
751  Result.getValueType(), Result,
752  DAG.getValueType(SrcVT));
753 
754  Value = Result;
755  Chain = Ch;
756  } else if (SrcWidth & (SrcWidth - 1)) {
757  // If not loading a power-of-2 number of bits, expand as two loads.
758  assert(!SrcVT.isVector() && "Unsupported extload!");
759  unsigned RoundWidth = 1 << Log2_32(SrcWidth);
760  assert(RoundWidth < SrcWidth);
761  unsigned ExtraWidth = SrcWidth - RoundWidth;
762  assert(ExtraWidth < RoundWidth);
763  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
764  "Load size not an integral number of bytes!");
765  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
766  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
767  SDValue Lo, Hi, Ch;
768  unsigned IncrementSize;
769  auto &DL = DAG.getDataLayout();
770 
771  if (DL.isLittleEndian()) {
772  // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
773  // Load the bottom RoundWidth bits.
774  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
775  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
776  AAInfo);
777 
778  // Load the remaining ExtraWidth bits.
779  IncrementSize = RoundWidth / 8;
780  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
781  DAG.getConstant(IncrementSize, dl,
782  Ptr.getValueType()));
783  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
784  LD->getPointerInfo().getWithOffset(IncrementSize),
785  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
786  AAInfo);
787 
788  // Build a factor node to remember that this load is independent of
789  // the other one.
790  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
791  Hi.getValue(1));
792 
793  // Move the top bits to the right place.
794  Hi = DAG.getNode(
795  ISD::SHL, dl, Hi.getValueType(), Hi,
796  DAG.getConstant(RoundWidth, dl,
797  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
798 
799  // Join the hi and lo parts.
800  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
801  } else {
802  // Big endian - avoid unaligned loads.
803  // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
804  // Load the top RoundWidth bits.
805  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
806  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
807  AAInfo);
808 
809  // Load the remaining ExtraWidth bits.
810  IncrementSize = RoundWidth / 8;
811  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
812  DAG.getConstant(IncrementSize, dl,
813  Ptr.getValueType()));
814  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
815  LD->getPointerInfo().getWithOffset(IncrementSize),
816  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
817  AAInfo);
818 
819  // Build a factor node to remember that this load is independent of
820  // the other one.
821  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
822  Hi.getValue(1));
823 
824  // Move the top bits to the right place.
825  Hi = DAG.getNode(
826  ISD::SHL, dl, Hi.getValueType(), Hi,
827  DAG.getConstant(ExtraWidth, dl,
828  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
829 
830  // Join the hi and lo parts.
831  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
832  }
833 
834  Chain = Ch;
835  } else {
836  bool isCustom = false;
837  switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
838  SrcVT.getSimpleVT())) {
839  default: llvm_unreachable("This action is not supported yet!");
841  isCustom = true;
844  Value = SDValue(Node, 0);
845  Chain = SDValue(Node, 1);
846 
847  if (isCustom) {
848  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
849  Value = Res;
850  Chain = Res.getValue(1);
851  }
852  } else {
853  // If this is an unaligned load and the target doesn't support it,
854  // expand it.
855  EVT MemVT = LD->getMemoryVT();
856  unsigned AS = LD->getAddressSpace();
857  unsigned Align = LD->getAlignment();
858  const DataLayout &DL = DAG.getDataLayout();
859  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
860  std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
861  }
862  }
863  break;
864 
865  case TargetLowering::Expand: {
866  EVT DestVT = Node->getValueType(0);
867  if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
868  // If the source type is not legal, see if there is a legal extload to
869  // an intermediate type that we can then extend further.
870  EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
871  if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
872  TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
873  // If we are loading a legal type, this is a non-extload followed by a
874  // full extend.
875  ISD::LoadExtType MidExtType =
876  (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
877 
878  SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
879  SrcVT, LD->getMemOperand());
880  unsigned ExtendOp =
882  Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
883  Chain = Load.getValue(1);
884  break;
885  }
886 
887  // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
888  // normal undefined upper bits behavior to allow using an in-reg extend
889  // with the illegal FP type, so load as an integer and do the
890  // from-integer conversion.
891  if (SrcVT.getScalarType() == MVT::f16) {
892  EVT ISrcVT = SrcVT.changeTypeToInteger();
893  EVT IDestVT = DestVT.changeTypeToInteger();
894  EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
895 
896  SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
897  Chain, Ptr, ISrcVT,
898  LD->getMemOperand());
899  Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
900  Chain = Result.getValue(1);
901  break;
902  }
903  }
904 
905  assert(!SrcVT.isVector() &&
906  "Vector Loads are handled in LegalizeVectorOps");
907 
908  // FIXME: This does not work for vectors on most targets. Sign-
909  // and zero-extend operations are currently folded into extending
910  // loads, whether they are legal or not, and then we end up here
911  // without any support for legalizing them.
912  assert(ExtType != ISD::EXTLOAD &&
913  "EXTLOAD should always be supported!");
914  // Turn the unsupported load into an EXTLOAD followed by an
915  // explicit zero/sign extend inreg.
916  SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
917  Node->getValueType(0),
918  Chain, Ptr, SrcVT,
919  LD->getMemOperand());
920  SDValue ValRes;
921  if (ExtType == ISD::SEXTLOAD)
922  ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
923  Result.getValueType(),
924  Result, DAG.getValueType(SrcVT));
925  else
926  ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
927  Value = ValRes;
928  Chain = Result.getValue(1);
929  break;
930  }
931  }
932  }
933 
934  // Since loads produce two values, make sure to remember that we legalized
935  // both of them.
936  if (Chain.getNode() != Node) {
937  assert(Value.getNode() != Node && "Load must be completely replaced");
938  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
939  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
940  if (UpdatedNodes) {
941  UpdatedNodes->insert(Value.getNode());
942  UpdatedNodes->insert(Chain.getNode());
943  }
944  ReplacedNode(Node);
945  }
946 }
947 
948 /// Return a legal replacement for the given operation, with all legal operands.
949 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
950  LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
951 
952  // Allow illegal target nodes and illegal registers.
953  if (Node->getOpcode() == ISD::TargetConstant ||
954  Node->getOpcode() == ISD::Register)
955  return;
956 
957 #ifndef NDEBUG
958  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
959  assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
961  TLI.isTypeLegal(Node->getValueType(i))) &&
962  "Unexpected illegal type!");
963 
964  for (const SDValue &Op : Node->op_values())
965  assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
967  TLI.isTypeLegal(Op.getValueType()) ||
968  Op.getOpcode() == ISD::TargetConstant ||
969  Op.getOpcode() == ISD::Register) &&
970  "Unexpected illegal type!");
971 #endif
972 
973  // Figure out the correct action; the way to query this varies by opcode
975  bool SimpleFinishLegalizing = true;
976  switch (Node->getOpcode()) {
979  case ISD::INTRINSIC_VOID:
980  case ISD::STACKSAVE:
981  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
982  break;
984  Action = TLI.getOperationAction(Node->getOpcode(),
985  Node->getValueType(0));
986  break;
987  case ISD::VAARG:
988  Action = TLI.getOperationAction(Node->getOpcode(),
989  Node->getValueType(0));
990  if (Action != TargetLowering::Promote)
991  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
992  break;
993  case ISD::FP_TO_FP16:
994  case ISD::SINT_TO_FP:
995  case ISD::UINT_TO_FP:
997  Action = TLI.getOperationAction(Node->getOpcode(),
998  Node->getOperand(0).getValueType());
999  break;
1000  case ISD::FP_ROUND_INREG:
1001  case ISD::SIGN_EXTEND_INREG: {
1002  EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1003  Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1004  break;
1005  }
1006  case ISD::ATOMIC_STORE:
1007  Action = TLI.getOperationAction(Node->getOpcode(),
1008  Node->getOperand(2).getValueType());
1009  break;
1010  case ISD::SELECT_CC:
1011  case ISD::SETCC:
1012  case ISD::BR_CC: {
1013  unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1014  Node->getOpcode() == ISD::SETCC ? 2 : 1;
1015  unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1016  MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1017  ISD::CondCode CCCode =
1018  cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1019  Action = TLI.getCondCodeAction(CCCode, OpVT);
1020  if (Action == TargetLowering::Legal) {
1021  if (Node->getOpcode() == ISD::SELECT_CC)
1022  Action = TLI.getOperationAction(Node->getOpcode(),
1023  Node->getValueType(0));
1024  else
1025  Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1026  }
1027  break;
1028  }
1029  case ISD::LOAD:
1030  case ISD::STORE:
1031  // FIXME: Model these properly. LOAD and STORE are complicated, and
1032  // STORE expects the unlegalized operand in some cases.
1033  SimpleFinishLegalizing = false;
1034  break;
1035  case ISD::CALLSEQ_START:
1036  case ISD::CALLSEQ_END:
1037  // FIXME: This shouldn't be necessary. These nodes have special properties
1038  // dealing with the recursive nature of legalization. Removing this
1039  // special case should be done as part of making LegalizeDAG non-recursive.
1040  SimpleFinishLegalizing = false;
1041  break;
1042  case ISD::EXTRACT_ELEMENT:
1043  case ISD::FLT_ROUNDS_:
1044  case ISD::MERGE_VALUES:
1045  case ISD::EH_RETURN:
1047  case ISD::EH_DWARF_CFA:
1048  case ISD::EH_SJLJ_SETJMP:
1049  case ISD::EH_SJLJ_LONGJMP:
1051  // These operations lie about being legal: when they claim to be legal,
1052  // they should actually be expanded.
1053  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1054  if (Action == TargetLowering::Legal)
1055  Action = TargetLowering::Expand;
1056  break;
1057  case ISD::INIT_TRAMPOLINE:
1059  case ISD::FRAMEADDR:
1060  case ISD::RETURNADDR:
1061  case ISD::ADDROFRETURNADDR:
1062  case ISD::SPONENTRY:
1063  // These operations lie about being legal: when they claim to be legal,
1064  // they should actually be custom-lowered.
1065  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1066  if (Action == TargetLowering::Legal)
1067  Action = TargetLowering::Custom;
1068  break;
1069  case ISD::READCYCLECOUNTER:
1070  // READCYCLECOUNTER returns an i64, even if type legalization might have
1071  // expanded that to several smaller types.
1072  Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1073  break;
1074  case ISD::READ_REGISTER:
1075  case ISD::WRITE_REGISTER:
1076  // Named register is legal in the DAG, but blocked by register name
1077  // selection if not implemented by target (to chose the correct register)
1078  // They'll be converted to Copy(To/From)Reg.
1079  Action = TargetLowering::Legal;
1080  break;
1081  case ISD::DEBUGTRAP:
1082  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1083  if (Action == TargetLowering::Expand) {
1084  // replace ISD::DEBUGTRAP with ISD::TRAP
1085  SDValue NewVal;
1086  NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1087  Node->getOperand(0));
1088  ReplaceNode(Node, NewVal.getNode());
1089  LegalizeOp(NewVal.getNode());
1090  return;
1091  }
1092  break;
1093  case ISD::STRICT_FADD:
1094  case ISD::STRICT_FSUB:
1095  case ISD::STRICT_FMUL:
1096  case ISD::STRICT_FDIV:
1097  case ISD::STRICT_FREM:
1098  case ISD::STRICT_FSQRT:
1099  case ISD::STRICT_FMA:
1100  case ISD::STRICT_FPOW:
1101  case ISD::STRICT_FPOWI:
1102  case ISD::STRICT_FSIN:
1103  case ISD::STRICT_FCOS:
1104  case ISD::STRICT_FEXP:
1105  case ISD::STRICT_FEXP2:
1106  case ISD::STRICT_FLOG:
1107  case ISD::STRICT_FLOG10:
1108  case ISD::STRICT_FLOG2:
1109  case ISD::STRICT_FRINT:
1111  case ISD::STRICT_FMAXNUM:
1112  case ISD::STRICT_FMINNUM:
1113  case ISD::STRICT_FCEIL:
1114  case ISD::STRICT_FFLOOR:
1115  case ISD::STRICT_FROUND:
1116  case ISD::STRICT_FTRUNC:
1117  // These pseudo-ops get legalized as if they were their non-strict
1118  // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
1119  // is also legal, but if ISD::FSQRT requires expansion then so does
1120  // ISD::STRICT_FSQRT.
1121  Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
1122  Node->getValueType(0));
1123  break;
1124  case ISD::SADDSAT:
1125  case ISD::UADDSAT:
1126  case ISD::SSUBSAT:
1127  case ISD::USUBSAT: {
1128  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1129  break;
1130  }
1131  case ISD::SMULFIX: {
1132  unsigned Scale = Node->getConstantOperandVal(2);
1133  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
1134  Node->getValueType(0), Scale);
1135  break;
1136  }
1137  case ISD::MSCATTER:
1138  Action = TLI.getOperationAction(Node->getOpcode(),
1139  cast<MaskedScatterSDNode>(Node)->getValue().getValueType());
1140  break;
1141  case ISD::MSTORE:
1142  Action = TLI.getOperationAction(Node->getOpcode(),
1143  cast<MaskedStoreSDNode>(Node)->getValue().getValueType());
1144  break;
1145  default:
1146  if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1147  Action = TargetLowering::Legal;
1148  } else {
1149  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1150  }
1151  break;
1152  }
1153 
1154  if (SimpleFinishLegalizing) {
1155  SDNode *NewNode = Node;
1156  switch (Node->getOpcode()) {
1157  default: break;
1158  case ISD::SHL:
1159  case ISD::SRL:
1160  case ISD::SRA:
1161  case ISD::ROTL:
1162  case ISD::ROTR: {
1163  // Legalizing shifts/rotates requires adjusting the shift amount
1164  // to the appropriate width.
1165  SDValue Op0 = Node->getOperand(0);
1166  SDValue Op1 = Node->getOperand(1);
1167  if (!Op1.getValueType().isVector()) {
1168  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1169  // The getShiftAmountOperand() may create a new operand node or
1170  // return the existing one. If new operand is created we need
1171  // to update the parent node.
1172  // Do not try to legalize SAO here! It will be automatically legalized
1173  // in the next round.
1174  if (SAO != Op1)
1175  NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1176  }
1177  }
1178  break;
1179  case ISD::FSHL:
1180  case ISD::FSHR:
1181  case ISD::SRL_PARTS:
1182  case ISD::SRA_PARTS:
1183  case ISD::SHL_PARTS: {
1184  // Legalizing shifts/rotates requires adjusting the shift amount
1185  // to the appropriate width.
1186  SDValue Op0 = Node->getOperand(0);
1187  SDValue Op1 = Node->getOperand(1);
1188  SDValue Op2 = Node->getOperand(2);
1189  if (!Op2.getValueType().isVector()) {
1190  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1191  // The getShiftAmountOperand() may create a new operand node or
1192  // return the existing one. If new operand is created we need
1193  // to update the parent node.
1194  if (SAO != Op2)
1195  NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1196  }
1197  break;
1198  }
1199  }
1200 
1201  if (NewNode != Node) {
1202  ReplaceNode(Node, NewNode);
1203  Node = NewNode;
1204  }
1205  switch (Action) {
1206  case TargetLowering::Legal:
1207  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1208  return;
1210  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1211  // FIXME: The handling for custom lowering with multiple results is
1212  // a complete mess.
1213  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1214  if (!(Res.getNode() != Node || Res.getResNo() != 0))
1215  return;
1216 
1217  if (Node->getNumValues() == 1) {
1218  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1219  // We can just directly replace this node with the lowered value.
1220  ReplaceNode(SDValue(Node, 0), Res);
1221  return;
1222  }
1223 
1224  SmallVector<SDValue, 8> ResultVals;
1225  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1226  ResultVals.push_back(Res.getValue(i));
1227  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1228  ReplaceNode(Node, ResultVals.data());
1229  return;
1230  }
1231  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1234  if (ExpandNode(Node))
1235  return;
1238  ConvertNodeToLibcall(Node);
1239  return;
1241  PromoteNode(Node);
1242  return;
1243  }
1244  }
1245 
1246  switch (Node->getOpcode()) {
1247  default:
1248 #ifndef NDEBUG
1249  dbgs() << "NODE: ";
1250  Node->dump( &DAG);
1251  dbgs() << "\n";
1252 #endif
1253  llvm_unreachable("Do not know how to legalize this operator!");
1254 
1255  case ISD::CALLSEQ_START:
1256  case ISD::CALLSEQ_END:
1257  break;
1258  case ISD::LOAD:
1259  return LegalizeLoadOps(Node);
1260  case ISD::STORE:
1261  return LegalizeStoreOps(Node);
1262  }
1263 }
1264 
1265 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1266  SDValue Vec = Op.getOperand(0);
1267  SDValue Idx = Op.getOperand(1);
1268  SDLoc dl(Op);
1269 
1270  // Before we generate a new store to a temporary stack slot, see if there is
1271  // already one that we can use. There often is because when we scalarize
1272  // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1273  // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1274  // the vector. If all are expanded here, we don't want one store per vector
1275  // element.
1276 
1277  // Caches for hasPredecessorHelper
1280  Visited.insert(Op.getNode());
1281  Worklist.push_back(Idx.getNode());
1282  SDValue StackPtr, Ch;
1283  for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1284  UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1285  SDNode *User = *UI;
1286  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1287  if (ST->isIndexed() || ST->isTruncatingStore() ||
1288  ST->getValue() != Vec)
1289  continue;
1290 
1291  // Make sure that nothing else could have stored into the destination of
1292  // this store.
1293  if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1294  continue;
1295 
1296  // If the index is dependent on the store we will introduce a cycle when
1297  // creating the load (the load uses the index, and by replacing the chain
1298  // we will make the index dependent on the load). Also, the store might be
1299  // dependent on the extractelement and introduce a cycle when creating
1300  // the load.
1301  if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
1302  ST->hasPredecessor(Op.getNode()))
1303  continue;
1304 
1305  StackPtr = ST->getBasePtr();
1306  Ch = SDValue(ST, 0);
1307  break;
1308  }
1309  }
1310 
1311  EVT VecVT = Vec.getValueType();
1312 
1313  if (!Ch.getNode()) {
1314  // Store the value to a temporary stack slot, then LOAD the returned part.
1315  StackPtr = DAG.CreateStackTemporary(VecVT);
1316  Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1317  MachinePointerInfo());
1318  }
1319 
1320  StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1321 
1322  SDValue NewLoad;
1323 
1324  if (Op.getValueType().isVector())
1325  NewLoad =
1326  DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, MachinePointerInfo());
1327  else
1328  NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1330  VecVT.getVectorElementType());
1331 
1332  // Replace the chain going out of the store, by the one out of the load.
1333  DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1334 
1335  // We introduced a cycle though, so update the loads operands, making sure
1336  // to use the original store's chain as an incoming chain.
1337  SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1338  NewLoad->op_end());
1339  NewLoadOperands[0] = Ch;
1340  NewLoad =
1341  SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1342  return NewLoad;
1343 }
1344 
1345 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1346  assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1347 
1348  SDValue Vec = Op.getOperand(0);
1349  SDValue Part = Op.getOperand(1);
1350  SDValue Idx = Op.getOperand(2);
1351  SDLoc dl(Op);
1352 
1353  // Store the value to a temporary stack slot, then LOAD the returned part.
1354  EVT VecVT = Vec.getValueType();
1355  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1356  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1357  MachinePointerInfo PtrInfo =
1358  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1359 
1360  // First store the whole vector.
1361  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1362 
1363  // Then store the inserted part.
1364  SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1365 
1366  // Store the subvector.
1367  Ch = DAG.getStore(Ch, dl, Part, SubStackPtr, MachinePointerInfo());
1368 
1369  // Finally, load the updated vector.
1370  return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1371 }
1372 
1373 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1374  // We can't handle this case efficiently. Allocate a sufficiently
1375  // aligned object on the stack, store each element into it, then load
1376  // the result as a vector.
1377  // Create the stack frame object.
1378  EVT VT = Node->getValueType(0);
1379  EVT EltVT = VT.getVectorElementType();
1380  SDLoc dl(Node);
1381  SDValue FIPtr = DAG.CreateStackTemporary(VT);
1382  int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1383  MachinePointerInfo PtrInfo =
1384  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1385 
1386  // Emit a store of each element to the stack slot.
1387  SmallVector<SDValue, 8> Stores;
1388  unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1389  // Store (in the right endianness) the elements to memory.
1390  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1391  // Ignore undef elements.
1392  if (Node->getOperand(i).isUndef()) continue;
1393 
1394  unsigned Offset = TypeByteSize*i;
1395 
1396  SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1397  Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1398 
1399  // If the destination vector element type is narrower than the source
1400  // element type, only store the bits necessary.
1401  if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1402  Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1403  Node->getOperand(i), Idx,
1404  PtrInfo.getWithOffset(Offset), EltVT));
1405  } else
1406  Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1407  Idx, PtrInfo.getWithOffset(Offset)));
1408  }
1409 
1410  SDValue StoreChain;
1411  if (!Stores.empty()) // Not all undef elements?
1412  StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1413  else
1414  StoreChain = DAG.getEntryNode();
1415 
1416  // Result is a load from the stack slot.
1417  return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1418 }
1419 
1420 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1421 /// containing the sign bit if the target has no integer value capable of
1422 /// holding all bits of the floating-point value.
1423 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1424  const SDLoc &DL,
1425  SDValue Value) const {
1426  EVT FloatVT = Value.getValueType();
1427  unsigned NumBits = FloatVT.getSizeInBits();
1428  State.FloatVT = FloatVT;
1429  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1430  // Convert to an integer of the same size.
1431  if (TLI.isTypeLegal(IVT)) {
1432  State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1433  State.SignMask = APInt::getSignMask(NumBits);
1434  State.SignBit = NumBits - 1;
1435  return;
1436  }
1437 
1438  auto &DataLayout = DAG.getDataLayout();
1439  // Store the float to memory, then load the sign part out as an integer.
1440  MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1441  // First create a temporary that is aligned for both the load and store.
1442  SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1443  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1444  // Then store the float to it.
1445  State.FloatPtr = StackPtr;
1446  MachineFunction &MF = DAG.getMachineFunction();
1447  State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1448  State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1449  State.FloatPointerInfo);
1450 
1451  SDValue IntPtr;
1452  if (DataLayout.isBigEndian()) {
1453  assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1454  // Load out a legal integer with the same sign bit as the float.
1455  IntPtr = StackPtr;
1456  State.IntPointerInfo = State.FloatPointerInfo;
1457  } else {
1458  // Advance the pointer so that the loaded byte will contain the sign bit.
1459  unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1460  IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1461  DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1462  State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1463  ByteOffset);
1464  }
1465 
1466  State.IntPtr = IntPtr;
1467  State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1468  State.IntPointerInfo, MVT::i8);
1469  State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1470  State.SignBit = 7;
1471 }
1472 
1473 /// Replace the integer value produced by getSignAsIntValue() with a new value
1474 /// and cast the result back to a floating-point type.
1475 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1476  const SDLoc &DL,
1477  SDValue NewIntValue) const {
1478  if (!State.Chain)
1479  return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1480 
1481  // Override the part containing the sign bit in the value stored on the stack.
1482  SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1483  State.IntPointerInfo, MVT::i8);
1484  return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1485  State.FloatPointerInfo);
1486 }
1487 
1488 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1489  SDLoc DL(Node);
1490  SDValue Mag = Node->getOperand(0);
1491  SDValue Sign = Node->getOperand(1);
1492 
1493  // Get sign bit into an integer value.
1494  FloatSignAsInt SignAsInt;
1495  getSignAsIntValue(SignAsInt, DL, Sign);
1496 
1497  EVT IntVT = SignAsInt.IntValue.getValueType();
1498  SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1499  SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1500  SignMask);
1501 
1502  // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1503  EVT FloatVT = Mag.getValueType();
1504  if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1505  TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1506  SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1507  SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1508  SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1509  DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1510  return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1511  }
1512 
1513  // Transform Mag value to integer, and clear the sign bit.
1514  FloatSignAsInt MagAsInt;
1515  getSignAsIntValue(MagAsInt, DL, Mag);
1516  EVT MagVT = MagAsInt.IntValue.getValueType();
1517  SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1518  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1519  ClearSignMask);
1520 
1521  // Get the signbit at the right position for MagAsInt.
1522  int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1523  EVT ShiftVT = IntVT;
1524  if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1525  SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1526  ShiftVT = MagVT;
1527  }
1528  if (ShiftAmount > 0) {
1529  SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1530  SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst);
1531  } else if (ShiftAmount < 0) {
1532  SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
1533  SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
1534  }
1535  if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1536  SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1537  }
1538 
1539  // Store the part with the modified sign and convert back to float.
1540  SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1541  return modifySignAsInt(MagAsInt, DL, CopiedSign);
1542 }
1543 
1544 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1545  SDLoc DL(Node);
1546  SDValue Value = Node->getOperand(0);
1547 
1548  // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1549  EVT FloatVT = Value.getValueType();
1550  if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1551  SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1552  return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1553  }
1554 
1555  // Transform value to integer, clear the sign bit and transform back.
1556  FloatSignAsInt ValueAsInt;
1557  getSignAsIntValue(ValueAsInt, DL, Value);
1558  EVT IntVT = ValueAsInt.IntValue.getValueType();
1559  SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1560  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1561  ClearSignMask);
1562  return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1563 }
1564 
1565 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1567  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1568  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1569  " not tell us which reg is the stack pointer!");
1570  SDLoc dl(Node);
1571  EVT VT = Node->getValueType(0);
1572  SDValue Tmp1 = SDValue(Node, 0);
1573  SDValue Tmp2 = SDValue(Node, 1);
1574  SDValue Tmp3 = Node->getOperand(2);
1575  SDValue Chain = Tmp1.getOperand(0);
1576 
1577  // Chain the dynamic stack allocation so that it doesn't modify the stack
1578  // pointer when other instructions are using the stack.
1579  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1580 
1581  SDValue Size = Tmp2.getOperand(1);
1582  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1583  Chain = SP.getValue(1);
1584  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1585  unsigned StackAlign =
1586  DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1587  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1588  if (Align > StackAlign)
1589  Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1590  DAG.getConstant(-(uint64_t)Align, dl, VT));
1591  Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1592 
1593  Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1594  DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1595 
1596  Results.push_back(Tmp1);
1597  Results.push_back(Tmp2);
1598 }
1599 
1600 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1601 /// target.
1602 ///
1603 /// If the SETCC has been legalized using AND / OR, then the legalized node
1604 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1605 /// will be set to false.
1606 ///
1607 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1608 /// then the values of LHS and RHS will be swapped, CC will be set to the
1609 /// new condition, and NeedInvert will be set to false.
1610 ///
1611 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1612 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1613 /// will be set to true. The caller must invert the result of the SETCC with
1614 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1615 /// of a true/false result.
1616 ///
1617 /// \returns true if the SetCC has been legalized, false if it hasn't.
1618 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1619  SDValue &RHS, SDValue &CC,
1620  bool &NeedInvert,
1621  const SDLoc &dl) {
1622  MVT OpVT = LHS.getSimpleValueType();
1623  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1624  NeedInvert = false;
1625  bool NeedSwap = false;
1626  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1627  default: llvm_unreachable("Unknown condition code action!");
1628  case TargetLowering::Legal:
1629  // Nothing to do.
1630  break;
1631  case TargetLowering::Expand: {
1633  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1634  std::swap(LHS, RHS);
1635  CC = DAG.getCondCode(InvCC);
1636  return true;
1637  }
1638  // Swapping operands didn't work. Try inverting the condition.
1639  InvCC = getSetCCInverse(CCCode, OpVT.isInteger());
1640  if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1641  // If inverting the condition is not enough, try swapping operands
1642  // on top of it.
1643  InvCC = ISD::getSetCCSwappedOperands(InvCC);
1644  NeedSwap = true;
1645  }
1646  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1647  CC = DAG.getCondCode(InvCC);
1648  NeedInvert = true;
1649  if (NeedSwap)
1650  std::swap(LHS, RHS);
1651  return true;
1652  }
1653 
1655  unsigned Opc = 0;
1656  switch (CCCode) {
1657  default: llvm_unreachable("Don't know how to expand this condition!");
1658  case ISD::SETO:
1659  assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
1660  && "If SETO is expanded, SETOEQ must be legal!");
1661  CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1662  case ISD::SETUO:
1663  assert(TLI.isCondCodeLegal(ISD::SETUNE, OpVT)
1664  && "If SETUO is expanded, SETUNE must be legal!");
1665  CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1666  case ISD::SETOEQ:
1667  case ISD::SETOGT:
1668  case ISD::SETOGE:
1669  case ISD::SETOLT:
1670  case ISD::SETOLE:
1671  case ISD::SETONE:
1672  case ISD::SETUEQ:
1673  case ISD::SETUNE:
1674  case ISD::SETUGT:
1675  case ISD::SETUGE:
1676  case ISD::SETULT:
1677  case ISD::SETULE:
1678  // If we are floating point, assign and break, otherwise fall through.
1679  if (!OpVT.isInteger()) {
1680  // We can use the 4th bit to tell if we are the unordered
1681  // or ordered version of the opcode.
1682  CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1683  Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1684  CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1685  break;
1686  }
1687  // Fallthrough if we are unsigned integer.
1689  case ISD::SETLE:
1690  case ISD::SETGT:
1691  case ISD::SETGE:
1692  case ISD::SETLT:
1693  case ISD::SETNE:
1694  case ISD::SETEQ:
1695  // If all combinations of inverting the condition and swapping operands
1696  // didn't work then we have no means to expand the condition.
1697  llvm_unreachable("Don't know how to expand this condition!");
1698  }
1699 
1700  SDValue SetCC1, SetCC2;
1701  if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1702  // If we aren't the ordered or unorder operation,
1703  // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1704  SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1705  SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1706  } else {
1707  // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1708  SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1709  SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1710  }
1711  LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1712  RHS = SDValue();
1713  CC = SDValue();
1714  return true;
1715  }
1716  }
1717  return false;
1718 }
1719 
1720 /// Emit a store/load combination to the stack. This stores
1721 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1722 /// a load from the stack slot to DestVT, extending it if needed.
1723 /// The resultant code need not be legal.
1724 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1725  EVT DestVT, const SDLoc &dl) {
1726  // Create the stack frame object.
1727  unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1728  SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1729  SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1730 
1731  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1732  int SPFI = StackPtrFI->getIndex();
1733  MachinePointerInfo PtrInfo =
1734  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1735 
1736  unsigned SrcSize = SrcOp.getValueSizeInBits();
1737  unsigned SlotSize = SlotVT.getSizeInBits();
1738  unsigned DestSize = DestVT.getSizeInBits();
1739  Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1740  unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1741 
1742  // Emit a store to the stack slot. Use a truncstore if the input value is
1743  // later than DestVT.
1744  SDValue Store;
1745 
1746  if (SrcSize > SlotSize)
1747  Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, PtrInfo,
1748  SlotVT, SrcAlign);
1749  else {
1750  assert(SrcSize == SlotSize && "Invalid store");
1751  Store =
1752  DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1753  }
1754 
1755  // Result is a load from the stack slot.
1756  if (SlotSize == DestSize)
1757  return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1758 
1759  assert(SlotSize < DestSize && "Unknown extension!");
1760  return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1761  DestAlign);
1762 }
1763 
1764 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1765  SDLoc dl(Node);
1766  // Create a vector sized/aligned stack slot, store the value to element #0,
1767  // then load the whole vector back out.
1768  SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1769 
1770  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1771  int SPFI = StackPtrFI->getIndex();
1772 
1773  SDValue Ch = DAG.getTruncStore(
1774  DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1775  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1776  Node->getValueType(0).getVectorElementType());
1777  return DAG.getLoad(
1778  Node->getValueType(0), dl, Ch, StackPtr,
1779  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1780 }
1781 
1782 static bool
1784  const TargetLowering &TLI, SDValue &Res) {
1785  unsigned NumElems = Node->getNumOperands();
1786  SDLoc dl(Node);
1787  EVT VT = Node->getValueType(0);
1788 
1789  // Try to group the scalars into pairs, shuffle the pairs together, then
1790  // shuffle the pairs of pairs together, etc. until the vector has
1791  // been built. This will work only if all of the necessary shuffle masks
1792  // are legal.
1793 
1794  // We do this in two phases; first to check the legality of the shuffles,
1795  // and next, assuming that all shuffles are legal, to create the new nodes.
1796  for (int Phase = 0; Phase < 2; ++Phase) {
1798  NewIntermedVals;
1799  for (unsigned i = 0; i < NumElems; ++i) {
1800  SDValue V = Node->getOperand(i);
1801  if (V.isUndef())
1802  continue;
1803 
1804  SDValue Vec;
1805  if (Phase)
1806  Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1807  IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1808  }
1809 
1810  while (IntermedVals.size() > 2) {
1811  NewIntermedVals.clear();
1812  for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1813  // This vector and the next vector are shuffled together (simply to
1814  // append the one to the other).
1815  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1816 
1817  SmallVector<int, 16> FinalIndices;
1818  FinalIndices.reserve(IntermedVals[i].second.size() +
1819  IntermedVals[i+1].second.size());
1820 
1821  int k = 0;
1822  for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1823  ++j, ++k) {
1824  ShuffleVec[k] = j;
1825  FinalIndices.push_back(IntermedVals[i].second[j]);
1826  }
1827  for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1828  ++j, ++k) {
1829  ShuffleVec[k] = NumElems + j;
1830  FinalIndices.push_back(IntermedVals[i+1].second[j]);
1831  }
1832 
1833  SDValue Shuffle;
1834  if (Phase)
1835  Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1836  IntermedVals[i+1].first,
1837  ShuffleVec);
1838  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1839  return false;
1840  NewIntermedVals.push_back(
1841  std::make_pair(Shuffle, std::move(FinalIndices)));
1842  }
1843 
1844  // If we had an odd number of defined values, then append the last
1845  // element to the array of new vectors.
1846  if ((IntermedVals.size() & 1) != 0)
1847  NewIntermedVals.push_back(IntermedVals.back());
1848 
1849  IntermedVals.swap(NewIntermedVals);
1850  }
1851 
1852  assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1853  "Invalid number of intermediate vectors");
1854  SDValue Vec1 = IntermedVals[0].first;
1855  SDValue Vec2;
1856  if (IntermedVals.size() > 1)
1857  Vec2 = IntermedVals[1].first;
1858  else if (Phase)
1859  Vec2 = DAG.getUNDEF(VT);
1860 
1861  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1862  for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1863  ShuffleVec[IntermedVals[0].second[i]] = i;
1864  for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1865  ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1866 
1867  if (Phase)
1868  Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1869  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1870  return false;
1871  }
1872 
1873  return true;
1874 }
1875 
1876 /// Expand a BUILD_VECTOR node on targets that don't
1877 /// support the operation, but do support the resultant vector type.
1878 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1879  unsigned NumElems = Node->getNumOperands();
1880  SDValue Value1, Value2;
1881  SDLoc dl(Node);
1882  EVT VT = Node->getValueType(0);
1883  EVT OpVT = Node->getOperand(0).getValueType();
1884  EVT EltVT = VT.getVectorElementType();
1885 
1886  // If the only non-undef value is the low element, turn this into a
1887  // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1888  bool isOnlyLowElement = true;
1889  bool MoreThanTwoValues = false;
1890  bool isConstant = true;
1891  for (unsigned i = 0; i < NumElems; ++i) {
1892  SDValue V = Node->getOperand(i);
1893  if (V.isUndef())
1894  continue;
1895  if (i > 0)
1896  isOnlyLowElement = false;
1897  if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1898  isConstant = false;
1899 
1900  if (!Value1.getNode()) {
1901  Value1 = V;
1902  } else if (!Value2.getNode()) {
1903  if (V != Value1)
1904  Value2 = V;
1905  } else if (V != Value1 && V != Value2) {
1906  MoreThanTwoValues = true;
1907  }
1908  }
1909 
1910  if (!Value1.getNode())
1911  return DAG.getUNDEF(VT);
1912 
1913  if (isOnlyLowElement)
1914  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1915 
1916  // If all elements are constants, create a load from the constant pool.
1917  if (isConstant) {
1919  for (unsigned i = 0, e = NumElems; i != e; ++i) {
1920  if (ConstantFPSDNode *V =
1921  dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1922  CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1923  } else if (ConstantSDNode *V =
1924  dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1925  if (OpVT==EltVT)
1926  CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1927  else {
1928  // If OpVT and EltVT don't match, EltVT is not legal and the
1929  // element values have been promoted/truncated earlier. Undo this;
1930  // we don't want a v16i8 to become a v16i32 for example.
1931  const ConstantInt *CI = V->getConstantIntValue();
1932  CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1933  CI->getZExtValue()));
1934  }
1935  } else {
1936  assert(Node->getOperand(i).isUndef());
1937  Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1938  CV.push_back(UndefValue::get(OpNTy));
1939  }
1940  }
1941  Constant *CP = ConstantVector::get(CV);
1942  SDValue CPIdx =
1943  DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1944  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1945  return DAG.getLoad(
1946  VT, dl, DAG.getEntryNode(), CPIdx,
1947  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1948  Alignment);
1949  }
1950 
1951  SmallSet<SDValue, 16> DefinedValues;
1952  for (unsigned i = 0; i < NumElems; ++i) {
1953  if (Node->getOperand(i).isUndef())
1954  continue;
1955  DefinedValues.insert(Node->getOperand(i));
1956  }
1957 
1958  if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1959  if (!MoreThanTwoValues) {
1960  SmallVector<int, 8> ShuffleVec(NumElems, -1);
1961  for (unsigned i = 0; i < NumElems; ++i) {
1962  SDValue V = Node->getOperand(i);
1963  if (V.isUndef())
1964  continue;
1965  ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1966  }
1967  if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1968  // Get the splatted value into the low element of a vector register.
1969  SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1970  SDValue Vec2;
1971  if (Value2.getNode())
1972  Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1973  else
1974  Vec2 = DAG.getUNDEF(VT);
1975 
1976  // Return shuffle(LowValVec, undef, <0,0,0,0>)
1977  return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1978  }
1979  } else {
1980  SDValue Res;
1981  if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
1982  return Res;
1983  }
1984  }
1985 
1986  // Otherwise, we can't handle this case efficiently.
1987  return ExpandVectorBuildThroughStack(Node);
1988 }
1989 
1990 // Expand a node into a call to a libcall. If the result value
1991 // does not fit into a register, return the lo part and set the hi part to the
1992 // by-reg argument. If it does fit into a single register, return the result
1993 // and leave the Hi part unset.
1994 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1995  bool isSigned) {
1997  TargetLowering::ArgListEntry Entry;
1998  for (const SDValue &Op : Node->op_values()) {
1999  EVT ArgVT = Op.getValueType();
2000  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2001  Entry.Node = Op;
2002  Entry.Ty = ArgTy;
2003  Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2004  Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2005  Args.push_back(Entry);
2006  }
2007  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2008  TLI.getPointerTy(DAG.getDataLayout()));
2009 
2010  EVT RetVT = Node->getValueType(0);
2011  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2012 
2013  // By default, the input chain to this libcall is the entry node of the
2014  // function. If the libcall is going to be emitted as a tail call then
2015  // TLI.isUsedByReturnOnly will change it to the right chain if the return
2016  // node which is being folded has a non-entry input chain.
2017  SDValue InChain = DAG.getEntryNode();
2018 
2019  // isTailCall may be true since the callee does not reference caller stack
2020  // frame. Check if it's in the right position and that the return types match.
2021  SDValue TCChain = InChain;
2022  const Function &F = DAG.getMachineFunction().getFunction();
2023  bool isTailCall =
2024  TLI.isInTailCallPosition(DAG, Node, TCChain) &&
2025  (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2026  if (isTailCall)
2027  InChain = TCChain;
2028 
2030  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2031  CLI.setDebugLoc(SDLoc(Node))
2032  .setChain(InChain)
2033  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2034  std::move(Args))
2035  .setTailCall(isTailCall)
2036  .setSExtResult(signExtend)
2037  .setZExtResult(!signExtend)
2039 
2040  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2041 
2042  if (!CallInfo.second.getNode()) {
2043  LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump());
2044  // It's a tailcall, return the chain (which is the DAG root).
2045  return DAG.getRoot();
2046  }
2047 
2048  LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump());
2049  return CallInfo.first;
2050 }
2051 
2052 /// Generate a libcall taking the given operands as arguments
2053 /// and returning a result of type RetVT.
2054 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2055  const SDValue *Ops, unsigned NumOps,
2056  bool isSigned, const SDLoc &dl) {
2058  Args.reserve(NumOps);
2059 
2060  TargetLowering::ArgListEntry Entry;
2061  for (unsigned i = 0; i != NumOps; ++i) {
2062  Entry.Node = Ops[i];
2063  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2064  Entry.IsSExt = isSigned;
2065  Entry.IsZExt = !isSigned;
2066  Args.push_back(Entry);
2067  }
2068  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2069  TLI.getPointerTy(DAG.getDataLayout()));
2070 
2071  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2072 
2074  CLI.setDebugLoc(dl)
2075  .setChain(DAG.getEntryNode())
2076  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2077  std::move(Args))
2078  .setSExtResult(isSigned)
2079  .setZExtResult(!isSigned)
2081 
2082  std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2083 
2084  return CallInfo.first;
2085 }
2086 
2087 // Expand a node into a call to a libcall. Similar to
2088 // ExpandLibCall except that the first operand is the in-chain.
2089 std::pair<SDValue, SDValue>
2090 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2091  SDNode *Node,
2092  bool isSigned) {
2093  SDValue InChain = Node->getOperand(0);
2094 
2096  TargetLowering::ArgListEntry Entry;
2097  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2098  EVT ArgVT = Node->getOperand(i).getValueType();
2099  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2100  Entry.Node = Node->getOperand(i);
2101  Entry.Ty = ArgTy;
2102  Entry.IsSExt = isSigned;
2103  Entry.IsZExt = !isSigned;
2104  Args.push_back(Entry);
2105  }
2106  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2107  TLI.getPointerTy(DAG.getDataLayout()));
2108 
2109  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2110 
2112  CLI.setDebugLoc(SDLoc(Node))
2113  .setChain(InChain)
2114  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2115  std::move(Args))
2116  .setSExtResult(isSigned)
2117  .setZExtResult(!isSigned);
2118 
2119  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2120 
2121  return CallInfo;
2122 }
2123 
2124 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2125  RTLIB::Libcall Call_F32,
2126  RTLIB::Libcall Call_F64,
2127  RTLIB::Libcall Call_F80,
2128  RTLIB::Libcall Call_F128,
2129  RTLIB::Libcall Call_PPCF128) {
2130  if (Node->isStrictFPOpcode())
2131  Node = DAG.mutateStrictFPToFP(Node);
2132 
2133  RTLIB::Libcall LC;
2134  switch (Node->getSimpleValueType(0).SimpleTy) {
2135  default: llvm_unreachable("Unexpected request for libcall!");
2136  case MVT::f32: LC = Call_F32; break;
2137  case MVT::f64: LC = Call_F64; break;
2138  case MVT::f80: LC = Call_F80; break;
2139  case MVT::f128: LC = Call_F128; break;
2140  case MVT::ppcf128: LC = Call_PPCF128; break;
2141  }
2142  return ExpandLibCall(LC, Node, false);
2143 }
2144 
2145 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2146  RTLIB::Libcall Call_I8,
2147  RTLIB::Libcall Call_I16,
2148  RTLIB::Libcall Call_I32,
2149  RTLIB::Libcall Call_I64,
2150  RTLIB::Libcall Call_I128) {
2151  RTLIB::Libcall LC;
2152  switch (Node->getSimpleValueType(0).SimpleTy) {
2153  default: llvm_unreachable("Unexpected request for libcall!");
2154  case MVT::i8: LC = Call_I8; break;
2155  case MVT::i16: LC = Call_I16; break;
2156  case MVT::i32: LC = Call_I32; break;
2157  case MVT::i64: LC = Call_I64; break;
2158  case MVT::i128: LC = Call_I128; break;
2159  }
2160  return ExpandLibCall(LC, Node, isSigned);
2161 }
2162 
2163 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2164 void
2165 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2166  SmallVectorImpl<SDValue> &Results) {
2167  unsigned Opcode = Node->getOpcode();
2168  bool isSigned = Opcode == ISD::SDIVREM;
2169 
2170  RTLIB::Libcall LC;
2171  switch (Node->getSimpleValueType(0).SimpleTy) {
2172  default: llvm_unreachable("Unexpected request for libcall!");
2173  case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2174  case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2175  case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2176  case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2177  case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2178  }
2179 
2180  // The input chain to this libcall is the entry node of the function.
2181  // Legalizing the call will automatically add the previous call to the
2182  // dependence.
2183  SDValue InChain = DAG.getEntryNode();
2184 
2185  EVT RetVT = Node->getValueType(0);
2186  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2187 
2189  TargetLowering::ArgListEntry Entry;
2190  for (const SDValue &Op : Node->op_values()) {
2191  EVT ArgVT = Op.getValueType();
2192  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2193  Entry.Node = Op;
2194  Entry.Ty = ArgTy;
2195  Entry.IsSExt = isSigned;
2196  Entry.IsZExt = !isSigned;
2197  Args.push_back(Entry);
2198  }
2199 
2200  // Also pass the return address of the remainder.
2201  SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2202  Entry.Node = FIPtr;
2203  Entry.Ty = RetTy->getPointerTo();
2204  Entry.IsSExt = isSigned;
2205  Entry.IsZExt = !isSigned;
2206  Args.push_back(Entry);
2207 
2208  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2209  TLI.getPointerTy(DAG.getDataLayout()));
2210 
2211  SDLoc dl(Node);
2213  CLI.setDebugLoc(dl)
2214  .setChain(InChain)
2215  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2216  std::move(Args))
2217  .setSExtResult(isSigned)
2218  .setZExtResult(!isSigned);
2219 
2220  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2221 
2222  // Remainder is loaded back from the stack frame.
2223  SDValue Rem =
2224  DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2225  Results.push_back(CallInfo.first);
2226  Results.push_back(Rem);
2227 }
2228 
2229 /// Return true if sincos libcall is available.
2230 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2231  RTLIB::Libcall LC;
2232  switch (Node->getSimpleValueType(0).SimpleTy) {
2233  default: llvm_unreachable("Unexpected request for libcall!");
2234  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2235  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2236  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2237  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2238  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2239  }
2240  return TLI.getLibcallName(LC) != nullptr;
2241 }
2242 
2243 /// Only issue sincos libcall if both sin and cos are needed.
2244 static bool useSinCos(SDNode *Node) {
2245  unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2246  ? ISD::FCOS : ISD::FSIN;
2247 
2248  SDValue Op0 = Node->getOperand(0);
2249  for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2250  UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2251  SDNode *User = *UI;
2252  if (User == Node)
2253  continue;
2254  // The other user might have been turned into sincos already.
2255  if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2256  return true;
2257  }
2258  return false;
2259 }
2260 
2261 /// Issue libcalls to sincos to compute sin / cos pairs.
2262 void
2263 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2264  SmallVectorImpl<SDValue> &Results) {
2265  RTLIB::Libcall LC;
2266  switch (Node->getSimpleValueType(0).SimpleTy) {
2267  default: llvm_unreachable("Unexpected request for libcall!");
2268  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2269  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2270  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2271  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2272  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2273  }
2274 
2275  // The input chain to this libcall is the entry node of the function.
2276  // Legalizing the call will automatically add the previous call to the
2277  // dependence.
2278  SDValue InChain = DAG.getEntryNode();
2279 
2280  EVT RetVT = Node->getValueType(0);
2281  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2282 
2284  TargetLowering::ArgListEntry Entry;
2285 
2286  // Pass the argument.
2287  Entry.Node = Node->getOperand(0);
2288  Entry.Ty = RetTy;
2289  Entry.IsSExt = false;
2290  Entry.IsZExt = false;
2291  Args.push_back(Entry);
2292 
2293  // Pass the return address of sin.
2294  SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2295  Entry.Node = SinPtr;
2296  Entry.Ty = RetTy->getPointerTo();
2297  Entry.IsSExt = false;
2298  Entry.IsZExt = false;
2299  Args.push_back(Entry);
2300 
2301  // Also pass the return address of the cos.
2302  SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2303  Entry.Node = CosPtr;
2304  Entry.Ty = RetTy->getPointerTo();
2305  Entry.IsSExt = false;
2306  Entry.IsZExt = false;
2307  Args.push_back(Entry);
2308 
2309  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2310  TLI.getPointerTy(DAG.getDataLayout()));
2311 
2312  SDLoc dl(Node);
2314  CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2315  TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee,
2316  std::move(Args));
2317 
2318  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2319 
2320  Results.push_back(
2321  DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2322  Results.push_back(
2323  DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2324 }
2325 
2326 /// This function is responsible for legalizing a
2327 /// INT_TO_FP operation of the specified operand when the target requests that
2328 /// we expand it. At this point, we know that the result and operand types are
2329 /// legal for the target.
2330 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
2331  EVT DestVT,
2332  const SDLoc &dl) {
2333  EVT SrcVT = Op0.getValueType();
2334 
2335  // TODO: Should any fast-math-flags be set for the created nodes?
2336  LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2337  if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2338  LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2339  "expansion\n");
2340 
2341  // Get the stack frame index of a 8 byte buffer.
2342  SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2343 
2344  // word offset constant for Hi/Lo address computation
2345  SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2346  StackSlot.getValueType());
2347  // set up Hi and Lo (into buffer) address based on endian
2348  SDValue Hi = StackSlot;
2349  SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2350  StackSlot, WordOff);
2351  if (DAG.getDataLayout().isLittleEndian())
2352  std::swap(Hi, Lo);
2353 
2354  // if signed map to unsigned space
2355  SDValue Op0Mapped;
2356  if (isSigned) {
2357  // constant used to invert sign bit (signed to unsigned mapping)
2358  SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2359  Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2360  } else {
2361  Op0Mapped = Op0;
2362  }
2363  // store the lo of the constructed double - based on integer input
2364  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo,
2365  MachinePointerInfo());
2366  // initial hi portion of constructed double
2367  SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2368  // store the hi of the constructed double - biased exponent
2369  SDValue Store2 =
2370  DAG.getStore(Store1, dl, InitialHi, Hi, MachinePointerInfo());
2371  // load the constructed double
2372  SDValue Load =
2373  DAG.getLoad(MVT::f64, dl, Store2, StackSlot, MachinePointerInfo());
2374  // FP constant to bias correct the final result
2375  SDValue Bias = DAG.getConstantFP(isSigned ?
2376  BitsToDouble(0x4330000080000000ULL) :
2377  BitsToDouble(0x4330000000000000ULL),
2378  dl, MVT::f64);
2379  // subtract the bias
2380  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2381  // final result
2382  SDValue Result = DAG.getFPExtendOrRound(Sub, dl, DestVT);
2383  return Result;
2384  }
2385  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2386  // Code below here assumes !isSigned without checking again.
2387 
2388  SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2389 
2390  SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
2391  DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2392  SDValue Zero = DAG.getIntPtrConstant(0, dl),
2393  Four = DAG.getIntPtrConstant(4, dl);
2394  SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2395  SignSet, Four, Zero);
2396 
2397  // If the sign bit of the integer is set, the large number will be treated
2398  // as a negative number. To counteract this, the dynamic code adds an
2399  // offset depending on the data type.
2400  uint64_t FF;
2401  switch (SrcVT.getSimpleVT().SimpleTy) {
2402  default: llvm_unreachable("Unsupported integer type!");
2403  case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2404  case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2405  case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2406  case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2407  }
2408  if (DAG.getDataLayout().isLittleEndian())
2409  FF <<= 32;
2410  Constant *FudgeFactor = ConstantInt::get(
2411  Type::getInt64Ty(*DAG.getContext()), FF);
2412 
2413  SDValue CPIdx =
2414  DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2415  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2416  CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2417  Alignment = std::min(Alignment, 4u);
2418  SDValue FudgeInReg;
2419  if (DestVT == MVT::f32)
2420  FudgeInReg = DAG.getLoad(
2421  MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2422  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2423  Alignment);
2424  else {
2425  SDValue Load = DAG.getExtLoad(
2426  ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2427  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2428  Alignment);
2429  HandleSDNode Handle(Load);
2430  LegalizeOp(Load.getNode());
2431  FudgeInReg = Handle.getValue();
2432  }
2433 
2434  return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2435 }
2436 
2437 /// This function is responsible for legalizing a
2438 /// *INT_TO_FP operation of the specified operand when the target requests that
2439 /// we promote it. At this point, we know that the result and operand types are
2440 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2441 /// operation that takes a larger input.
2442 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
2443  bool isSigned,
2444  const SDLoc &dl) {
2445  // First step, figure out the appropriate *INT_TO_FP operation to use.
2446  EVT NewInTy = LegalOp.getValueType();
2447 
2448  unsigned OpToUse = 0;
2449 
2450  // Scan for the appropriate larger type to use.
2451  while (true) {
2452  NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2453  assert(NewInTy.isInteger() && "Ran out of possibilities!");
2454 
2455  // If the target supports SINT_TO_FP of this type, use it.
2456  if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2457  OpToUse = ISD::SINT_TO_FP;
2458  break;
2459  }
2460  if (isSigned) continue;
2461 
2462  // If the target supports UINT_TO_FP of this type, use it.
2463  if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2464  OpToUse = ISD::UINT_TO_FP;
2465  break;
2466  }
2467 
2468  // Otherwise, try a larger type.
2469  }
2470 
2471  // Okay, we found the operation and type to use. Zero extend our input to the
2472  // desired type then run the operation on it.
2473  return DAG.getNode(OpToUse, dl, DestVT,
2474  DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2475  dl, NewInTy, LegalOp));
2476 }
2477 
2478 /// This function is responsible for legalizing a
2479 /// FP_TO_*INT operation of the specified operand when the target requests that
2480 /// we promote it. At this point, we know that the result and operand types are
2481 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2482 /// operation that returns a larger result.
2483 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
2484  bool isSigned,
2485  const SDLoc &dl) {
2486  // First step, figure out the appropriate FP_TO*INT operation to use.
2487  EVT NewOutTy = DestVT;
2488 
2489  unsigned OpToUse = 0;
2490 
2491  // Scan for the appropriate larger type to use.
2492  while (true) {
2493  NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2494  assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2495 
2496  // A larger signed type can hold all unsigned values of the requested type,
2497  // so using FP_TO_SINT is valid
2498  if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2499  OpToUse = ISD::FP_TO_SINT;
2500  break;
2501  }
2502 
2503  // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2504  if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2505  OpToUse = ISD::FP_TO_UINT;
2506  break;
2507  }
2508 
2509  // Otherwise, try a larger type.
2510  }
2511 
2512  // Okay, we found the operation and type to use.
2513  SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2514 
2515  // Truncate the result of the extended FP_TO_*INT operation to the desired
2516  // size.
2517  return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2518 }
2519 
2520 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2521 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
2522  EVT VT = Op.getValueType();
2523  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2524  unsigned Sz = VT.getScalarSizeInBits();
2525 
2526  SDValue Tmp, Tmp2, Tmp3;
2527 
2528  // If we can, perform BSWAP first and then the mask+swap the i4, then i2
2529  // and finally the i1 pairs.
2530  // TODO: We can easily support i4/i2 legal types if any target ever does.
2531  if (Sz >= 8 && isPowerOf2_32(Sz)) {
2532  // Create the masks - repeating the pattern every byte.
2533  APInt MaskHi4(Sz, 0), MaskHi2(Sz, 0), MaskHi1(Sz, 0);
2534  APInt MaskLo4(Sz, 0), MaskLo2(Sz, 0), MaskLo1(Sz, 0);
2535  for (unsigned J = 0; J != Sz; J += 8) {
2536  MaskHi4 = MaskHi4 | (0xF0ull << J);
2537  MaskLo4 = MaskLo4 | (0x0Full << J);
2538  MaskHi2 = MaskHi2 | (0xCCull << J);
2539  MaskLo2 = MaskLo2 | (0x33ull << J);
2540  MaskHi1 = MaskHi1 | (0xAAull << J);
2541  MaskLo1 = MaskLo1 | (0x55ull << J);
2542  }
2543 
2544  // BSWAP if the type is wider than a single byte.
2545  Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2546 
2547  // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4)
2548  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2549  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2550  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT));
2551  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT));
2552  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2553 
2554  // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2)
2555  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2556  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2557  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT));
2558  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT));
2559  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2560 
2561  // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
2562  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2563  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2564  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT));
2565  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT));
2566  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2567  return Tmp;
2568  }
2569 
2570  Tmp = DAG.getConstant(0, dl, VT);
2571  for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2572  if (I < J)
2573  Tmp2 =
2574  DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2575  else
2576  Tmp2 =
2577  DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2578 
2579  APInt Shift(Sz, 1);
2580  Shift <<= J;
2581  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2582  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2583  }
2584 
2585  return Tmp;
2586 }
2587 
2588 /// Open code the operations for BSWAP of the specified operation.
2589 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
2590  EVT VT = Op.getValueType();
2591  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2592  SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2593  switch (VT.getSimpleVT().getScalarType().SimpleTy) {
2594  default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2595  case MVT::i16:
2596  Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2597  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2598  return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2599  case MVT::i32:
2600  Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2601  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2602  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2603  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2604  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2605  DAG.getConstant(0xFF0000, dl, VT));
2606  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2607  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2608  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2609  return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2610  case MVT::i64:
2611  Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2612  Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2613  Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2614  Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2615  Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2616  Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2617  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2618  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2619  Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2620  DAG.getConstant(255ULL<<48, dl, VT));
2621  Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2622  DAG.getConstant(255ULL<<40, dl, VT));
2623  Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2624  DAG.getConstant(255ULL<<32, dl, VT));
2625  Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2626  DAG.getConstant(255ULL<<24, dl, VT));
2627  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2628  DAG.getConstant(255ULL<<16, dl, VT));
2629  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2630  DAG.getConstant(255ULL<<8 , dl, VT));
2631  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2632  Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2633  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2634  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2635  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2636  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2637  return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2638  }
2639 }
2640 
2641 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2642  LLVM_DEBUG(dbgs() << "Trying to expand node\n");
2644  SDLoc dl(Node);
2645  SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2646  bool NeedInvert;
2647  switch (Node->getOpcode()) {
2648  case ISD::ABS:
2649  if (TLI.expandABS(Node, Tmp1, DAG))
2650  Results.push_back(Tmp1);
2651  break;
2652  case ISD::CTPOP:
2653  if (TLI.expandCTPOP(Node, Tmp1, DAG))
2654  Results.push_back(Tmp1);
2655  break;
2656  case ISD::CTLZ:
2657  case ISD::CTLZ_ZERO_UNDEF:
2658  if (TLI.expandCTLZ(Node, Tmp1, DAG))
2659  Results.push_back(Tmp1);
2660  break;
2661  case ISD::CTTZ:
2662  case ISD::CTTZ_ZERO_UNDEF:
2663  if (TLI.expandCTTZ(Node, Tmp1, DAG))
2664  Results.push_back(Tmp1);
2665  break;
2666  case ISD::BITREVERSE:
2667  Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
2668  break;
2669  case ISD::BSWAP:
2670  Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2671  break;
2672  case ISD::FRAMEADDR:
2673  case ISD::RETURNADDR:
2675  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2676  break;
2677  case ISD::EH_DWARF_CFA: {
2678  SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2679  TLI.getPointerTy(DAG.getDataLayout()));
2680  SDValue Offset = DAG.getNode(ISD::ADD, dl,
2681  CfaArg.getValueType(),
2682  DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2683  CfaArg.getValueType()),
2684  CfaArg);
2685  SDValue FA = DAG.getNode(
2686  ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2687  DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2688  Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2689  FA, Offset));
2690  break;
2691  }
2692  case ISD::FLT_ROUNDS_:
2693  Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2694  break;
2695  case ISD::EH_RETURN:
2696  case ISD::EH_LABEL:
2697  case ISD::PREFETCH:
2698  case ISD::VAEND:
2699  case ISD::EH_SJLJ_LONGJMP:
2700  // If the target didn't expand these, there's nothing to do, so just
2701  // preserve the chain and be done.
2702  Results.push_back(Node->getOperand(0));
2703  break;
2704  case ISD::READCYCLECOUNTER:
2705  // If the target didn't expand this, just return 'zero' and preserve the
2706  // chain.
2707  Results.append(Node->getNumValues() - 1,
2708  DAG.getConstant(0, dl, Node->getValueType(0)));
2709  Results.push_back(Node->getOperand(0));
2710  break;
2711  case ISD::EH_SJLJ_SETJMP:
2712  // If the target didn't expand this, just return 'zero' and preserve the
2713  // chain.
2714  Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2715  Results.push_back(Node->getOperand(0));
2716  break;
2717  case ISD::ATOMIC_LOAD: {
2718  // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2719  SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2720  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2721  SDValue Swap = DAG.getAtomicCmpSwap(
2722  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2723  Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2724  cast<AtomicSDNode>(Node)->getMemOperand());
2725  Results.push_back(Swap.getValue(0));
2726  Results.push_back(Swap.getValue(1));
2727  break;
2728  }
2729  case ISD::ATOMIC_STORE: {
2730  // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2731  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2732  cast<AtomicSDNode>(Node)->getMemoryVT(),
2733  Node->getOperand(0),
2734  Node->getOperand(1), Node->getOperand(2),
2735  cast<AtomicSDNode>(Node)->getMemOperand());
2736  Results.push_back(Swap.getValue(1));
2737  break;
2738  }
2740  // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2741  // splits out the success value as a comparison. Expanding the resulting
2742  // ATOMIC_CMP_SWAP will produce a libcall.
2743  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2744  SDValue Res = DAG.getAtomicCmpSwap(
2745  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2746  Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2747  Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2748 
2749  SDValue ExtRes = Res;
2750  SDValue LHS = Res;
2751  SDValue RHS = Node->getOperand(1);
2752 
2753  EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2754  EVT OuterType = Node->getValueType(0);
2755  switch (TLI.getExtendForAtomicOps()) {
2756  case ISD::SIGN_EXTEND:
2757  LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2758  DAG.getValueType(AtomicType));
2759  RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2760  Node->getOperand(2), DAG.getValueType(AtomicType));
2761  ExtRes = LHS;
2762  break;
2763  case ISD::ZERO_EXTEND:
2764  LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2765  DAG.getValueType(AtomicType));
2766  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2767  ExtRes = LHS;
2768  break;
2769  case ISD::ANY_EXTEND:
2770  LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2771  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2772  break;
2773  default:
2774  llvm_unreachable("Invalid atomic op extension");
2775  }
2776 
2777  SDValue Success =
2778  DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2779 
2780  Results.push_back(ExtRes.getValue(0));
2781  Results.push_back(Success);
2782  Results.push_back(Res.getValue(1));
2783  break;
2784  }
2786  ExpandDYNAMIC_STACKALLOC(Node, Results);
2787  break;
2788  case ISD::MERGE_VALUES:
2789  for (unsigned i = 0; i < Node->getNumValues(); i++)
2790  Results.push_back(Node->getOperand(i));
2791  break;
2792  case ISD::UNDEF: {
2793  EVT VT = Node->getValueType(0);
2794  if (VT.isInteger())
2795  Results.push_back(DAG.getConstant(0, dl, VT));
2796  else {
2797  assert(VT.isFloatingPoint() && "Unknown value type!");
2798  Results.push_back(DAG.getConstantFP(0, dl, VT));
2799  }
2800  break;
2801  }
2802  case ISD::FP_ROUND:
2803  case ISD::BITCAST:
2804  Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2805  Node->getValueType(0), dl);
2806  Results.push_back(Tmp1);
2807  break;
2808  case ISD::FP_EXTEND:
2809  Tmp1 = EmitStackConvert(Node->getOperand(0),
2810  Node->getOperand(0).getValueType(),
2811  Node->getValueType(0), dl);
2812  Results.push_back(Tmp1);
2813  break;
2814  case ISD::SIGN_EXTEND_INREG: {
2815  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2816  EVT VT = Node->getValueType(0);
2817 
2818  // An in-register sign-extend of a boolean is a negation:
2819  // 'true' (1) sign-extended is -1.
2820  // 'false' (0) sign-extended is 0.
2821  // However, we must mask the high bits of the source operand because the
2822  // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2823 
2824  // TODO: Do this for vectors too?
2825  if (ExtraVT.getSizeInBits() == 1) {
2826  SDValue One = DAG.getConstant(1, dl, VT);
2827  SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2828  SDValue Zero = DAG.getConstant(0, dl, VT);
2829  SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2830  Results.push_back(Neg);
2831  break;
2832  }
2833 
2834  // NOTE: we could fall back on load/store here too for targets without
2835  // SRA. However, it is doubtful that any exist.
2836  EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2837  unsigned BitsDiff = VT.getScalarSizeInBits() -
2838  ExtraVT.getScalarSizeInBits();
2839  SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2840  Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2841  Node->getOperand(0), ShiftCst);
2842  Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2843  Results.push_back(Tmp1);
2844  break;
2845  }
2846  case ISD::FP_ROUND_INREG: {
2847  // The only way we can lower this is to turn it into a TRUNCSTORE,
2848  // EXTLOAD pair, targeting a temporary location (a stack slot).
2849 
2850  // NOTE: there is a choice here between constantly creating new stack
2851  // slots and always reusing the same one. We currently always create
2852  // new ones, as reuse may inhibit scheduling.
2853  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2854  Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2855  Node->getValueType(0), dl);
2856  Results.push_back(Tmp1);
2857  break;
2858  }
2859  case ISD::UINT_TO_FP:
2860  if (TLI.expandUINT_TO_FP(Node, Tmp1, DAG)) {
2861  Results.push_back(Tmp1);
2862  break;
2863  }
2865  case ISD::SINT_TO_FP:
2866  Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2867  Node->getOperand(0), Node->getValueType(0), dl);
2868  Results.push_back(Tmp1);
2869  break;
2870  case ISD::FP_TO_SINT:
2871  if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
2872  Results.push_back(Tmp1);
2873  break;
2874  case ISD::FP_TO_UINT:
2875  if (TLI.expandFP_TO_UINT(Node, Tmp1, DAG))
2876  Results.push_back(Tmp1);
2877  break;
2878  case ISD::VAARG:
2879  Results.push_back(DAG.expandVAArg(Node));
2880  Results.push_back(Results[0].getValue(1));
2881  break;
2882  case ISD::VACOPY:
2883  Results.push_back(DAG.expandVACopy(Node));
2884  break;
2886  if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2887  // This must be an access of the only element. Return it.
2888  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2889  Node->getOperand(0));
2890  else
2891  Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2892  Results.push_back(Tmp1);
2893  break;
2895  Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2896  break;
2897  case ISD::INSERT_SUBVECTOR:
2898  Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2899  break;
2900  case ISD::CONCAT_VECTORS:
2901  Results.push_back(ExpandVectorBuildThroughStack(Node));
2902  break;
2903  case ISD::SCALAR_TO_VECTOR:
2904  Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2905  break;
2907  Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2908  Node->getOperand(1),
2909  Node->getOperand(2), dl));
2910  break;
2911  case ISD::VECTOR_SHUFFLE: {
2912  SmallVector<int, 32> NewMask;
2913  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2914 
2915  EVT VT = Node->getValueType(0);
2916  EVT EltVT = VT.getVectorElementType();
2917  SDValue Op0 = Node->getOperand(0);
2918  SDValue Op1 = Node->getOperand(1);
2919  if (!TLI.isTypeLegal(EltVT)) {
2920  EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2921 
2922  // BUILD_VECTOR operands are allowed to be wider than the element type.
2923  // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
2924  // it.
2925  if (NewEltVT.bitsLT(EltVT)) {
2926  // Convert shuffle node.
2927  // If original node was v4i64 and the new EltVT is i32,
2928  // cast operands to v8i32 and re-build the mask.
2929 
2930  // Calculate new VT, the size of the new VT should be equal to original.
2931  EVT NewVT =
2932  EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2933  VT.getSizeInBits() / NewEltVT.getSizeInBits());
2934  assert(NewVT.bitsEq(VT));
2935 
2936  // cast operands to new VT
2937  Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2938  Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2939 
2940  // Convert the shuffle mask
2941  unsigned int factor =
2943 
2944  // EltVT gets smaller
2945  assert(factor > 0);
2946 
2947  for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2948  if (Mask[i] < 0) {
2949  for (unsigned fi = 0; fi < factor; ++fi)
2950  NewMask.push_back(Mask[i]);
2951  }
2952  else {
2953  for (unsigned fi = 0; fi < factor; ++fi)
2954  NewMask.push_back(Mask[i]*factor+fi);
2955  }
2956  }
2957  Mask = NewMask;
2958  VT = NewVT;
2959  }
2960  EltVT = NewEltVT;
2961  }
2962  unsigned NumElems = VT.getVectorNumElements();
2964  for (unsigned i = 0; i != NumElems; ++i) {
2965  if (Mask[i] < 0) {
2966  Ops.push_back(DAG.getUNDEF(EltVT));
2967  continue;
2968  }
2969  unsigned Idx = Mask[i];
2970  if (Idx < NumElems)
2971  Ops.push_back(DAG.getNode(
2972  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
2973  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
2974  else
2975  Ops.push_back(DAG.getNode(
2976  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
2977  DAG.getConstant(Idx - NumElems, dl,
2978  TLI.getVectorIdxTy(DAG.getDataLayout()))));
2979  }
2980 
2981  Tmp1 = DAG.getBuildVector(VT, dl, Ops);
2982  // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
2983  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
2984  Results.push_back(Tmp1);
2985  break;
2986  }
2987  case ISD::EXTRACT_ELEMENT: {
2988  EVT OpTy = Node->getOperand(0).getValueType();
2989  if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2990  // 1 -> Hi
2991  Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2992  DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
2993  TLI.getShiftAmountTy(
2994  Node->getOperand(0).getValueType(),
2995  DAG.getDataLayout())));
2996  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2997  } else {
2998  // 0 -> Lo
2999  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3000  Node->getOperand(0));
3001  }
3002  Results.push_back(Tmp1);
3003  break;
3004  }
3005  case ISD::STACKSAVE:
3006  // Expand to CopyFromReg if the target set
3007  // StackPointerRegisterToSaveRestore.
3008  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3009  Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3010  Node->getValueType(0)));
3011  Results.push_back(Results[0].getValue(1));
3012  } else {
3013  Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3014  Results.push_back(Node->getOperand(0));
3015  }
3016  break;
3017  case ISD::STACKRESTORE:
3018  // Expand to CopyToReg if the target set
3019  // StackPointerRegisterToSaveRestore.
3020  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3021  Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3022  Node->getOperand(1)));
3023  } else {
3024  Results.push_back(Node->getOperand(0));
3025  }
3026  break;
3028  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3029  Results.push_back(Results[0].getValue(0));
3030  break;
3031  case ISD::FCOPYSIGN:
3032  Results.push_back(ExpandFCOPYSIGN(Node));
3033  break;
3034  case ISD::FNEG:
3035  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3036  Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3037  // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3038  Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3039  Node->getOperand(0));
3040  Results.push_back(Tmp1);
3041  break;
3042  case ISD::FABS:
3043  Results.push_back(ExpandFABS(Node));
3044  break;
3045  case ISD::SMIN:
3046  case ISD::SMAX:
3047  case ISD::UMIN:
3048  case ISD::UMAX: {
3049  // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3050  ISD::CondCode Pred;
3051  switch (Node->getOpcode()) {
3052  default: llvm_unreachable("How did we get here?");
3053  case ISD::SMAX: Pred = ISD::SETGT; break;
3054  case ISD::SMIN: Pred = ISD::SETLT; break;
3055  case ISD::UMAX: Pred = ISD::SETUGT; break;
3056  case ISD::UMIN: Pred = ISD::SETULT; break;
3057  }
3058  Tmp1 = Node->getOperand(0);
3059  Tmp2 = Node->getOperand(1);
3060  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3061  Results.push_back(Tmp1);
3062  break;
3063  }
3064  case ISD::FMINNUM:
3065  case ISD::FMAXNUM: {
3066  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Node, DAG))
3067  Results.push_back(Expanded);
3068  break;
3069  }
3070  case ISD::FSIN:
3071  case ISD::FCOS: {
3072  EVT VT = Node->getValueType(0);
3073  // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3074  // fcos which share the same operand and both are used.
3075  if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3076  isSinCosLibcallAvailable(Node, TLI))
3077  && useSinCos(Node)) {
3078  SDVTList VTs = DAG.getVTList(VT, VT);
3079  Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3080  if (Node->getOpcode() == ISD::FCOS)
3081  Tmp1 = Tmp1.getValue(1);
3082  Results.push_back(Tmp1);
3083  }
3084  break;
3085  }
3086  case ISD::FMAD:
3087  llvm_unreachable("Illegal fmad should never be formed");
3088 
3089  case ISD::FP16_TO_FP:
3090  if (Node->getValueType(0) != MVT::f32) {
3091  // We can extend to types bigger than f32 in two steps without changing
3092  // the result. Since "f16 -> f32" is much more commonly available, give
3093  // CodeGen the option of emitting that before resorting to a libcall.
3094  SDValue Res =
3095  DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3096  Results.push_back(
3097  DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3098  }
3099  break;
3100  case ISD::FP_TO_FP16:
3101  LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3102  if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3103  SDValue Op = Node->getOperand(0);
3104  MVT SVT = Op.getSimpleValueType();
3105  if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3106  TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3107  // Under fastmath, we can expand this node into a fround followed by
3108  // a float-half conversion.
3109  SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3110  DAG.getIntPtrConstant(0, dl));
3111  Results.push_back(
3112  DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3113  }
3114  }
3115  break;
3116  case ISD::ConstantFP: {
3117  ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3118  // Check to see if this FP immediate is already legal.
3119  // If this is a legal constant, turn it into a TargetConstantFP node.
3120  if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3121  Results.push_back(ExpandConstantFP(CFP, true));
3122  break;
3123  }
3124  case ISD::Constant: {
3125  ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3126  Results.push_back(ExpandConstant(CP));
3127  break;
3128  }
3129  case ISD::FSUB: {
3130  EVT VT = Node->getValueType(0);
3131  if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3132  TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3133  const SDNodeFlags Flags = Node->getFlags();
3134  Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3135  Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3136  Results.push_back(Tmp1);
3137  }
3138  break;
3139  }
3140  case ISD::SUB: {
3141  EVT VT = Node->getValueType(0);
3142  assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3143  TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3144  "Don't know how to expand this subtraction!");
3145  Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3146  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3147  VT));
3148  Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3149  Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3150  break;
3151  }
3152  case ISD::UREM:
3153  case ISD::SREM: {
3154  EVT VT = Node->getValueType(0);
3155  bool isSigned = Node->getOpcode() == ISD::SREM;
3156  unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3157  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3158  Tmp2 = Node->getOperand(0);
3159  Tmp3 = Node->getOperand(1);
3160  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3161  SDVTList VTs = DAG.getVTList(VT, VT);
3162  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3163  Results.push_back(Tmp1);
3164  } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3165  // X % Y -> X-X/Y*Y
3166  Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3167  Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3168  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3169  Results.push_back(Tmp1);
3170  }
3171  break;
3172  }
3173  case ISD::UDIV:
3174  case ISD::SDIV: {
3175  bool isSigned = Node->getOpcode() == ISD::SDIV;
3176  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3177  EVT VT = Node->getValueType(0);
3178  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3179  SDVTList VTs = DAG.getVTList(VT, VT);
3180  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3181  Node->getOperand(1));
3182  Results.push_back(Tmp1);
3183  }
3184  break;
3185  }
3186  case ISD::MULHU:
3187  case ISD::MULHS: {
3188  unsigned ExpandOpcode =
3190  EVT VT = Node->getValueType(0);
3191  SDVTList VTs = DAG.getVTList(VT, VT);
3192 
3193  Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3194  Node->getOperand(1));
3195  Results.push_back(Tmp1.getValue(1));
3196  break;
3197  }
3198  case ISD::UMUL_LOHI:
3199  case ISD::SMUL_LOHI: {
3200  SDValue LHS = Node->getOperand(0);
3201  SDValue RHS = Node->getOperand(1);
3202  MVT VT = LHS.getSimpleValueType();
3203  unsigned MULHOpcode =
3205 
3206  if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3207  Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3208  Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3209  break;
3210  }
3211 
3212  SmallVector<SDValue, 4> Halves;
3213  EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3214  assert(TLI.isTypeLegal(HalfType));
3215  if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3216  HalfType, DAG,
3218  for (unsigned i = 0; i < 2; ++i) {
3219  SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3220  SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3221  SDValue Shift = DAG.getConstant(
3222  HalfType.getScalarSizeInBits(), dl,
3223  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3224  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3225  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3226  }
3227  break;
3228  }
3229  break;
3230  }
3231  case ISD::MUL: {
3232  EVT VT = Node->getValueType(0);
3233  SDVTList VTs = DAG.getVTList(VT, VT);
3234  // See if multiply or divide can be lowered using two-result operations.
3235  // We just need the low half of the multiply; try both the signed
3236  // and unsigned forms. If the target supports both SMUL_LOHI and
3237  // UMUL_LOHI, form a preference by checking which forms of plain
3238  // MULH it supports.
3239  bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3240  bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3241  bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3242  bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3243  unsigned OpToUse = 0;
3244  if (HasSMUL_LOHI && !HasMULHS) {
3245  OpToUse = ISD::SMUL_LOHI;
3246  } else if (HasUMUL_LOHI && !HasMULHU) {
3247  OpToUse = ISD::UMUL_LOHI;
3248  } else if (HasSMUL_LOHI) {
3249  OpToUse = ISD::SMUL_LOHI;
3250  } else if (HasUMUL_LOHI) {
3251  OpToUse = ISD::UMUL_LOHI;
3252  }
3253  if (OpToUse) {
3254  Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3255  Node->getOperand(1)));
3256  break;
3257  }
3258 
3259  SDValue Lo, Hi;
3260  EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3261  if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3262  TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3263  TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3264  TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3265  TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3267  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3268  Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3269  SDValue Shift =
3270  DAG.getConstant(HalfType.getSizeInBits(), dl,
3271  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3272  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3273  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3274  }
3275  break;
3276  }
3277  case ISD::FSHL:
3278  case ISD::FSHR:
3279  if (TLI.expandFunnelShift(Node, Tmp1, DAG))
3280  Results.push_back(Tmp1);
3281  break;
3282  case ISD::ROTL:
3283  case ISD::ROTR:
3284  if (TLI.expandROT(Node, Tmp1, DAG))
3285  Results.push_back(Tmp1);
3286  break;
3287  case ISD::SADDSAT:
3288  case ISD::UADDSAT:
3289  case ISD::SSUBSAT:
3290  case ISD::USUBSAT:
3291  Results.push_back(TLI.expandAddSubSat(Node, DAG));
3292  break;
3293  case ISD::SMULFIX:
3294  Results.push_back(TLI.getExpandedFixedPointMultiplication(Node, DAG));
3295  break;
3296  case ISD::SADDO:
3297  case ISD::SSUBO: {
3298  SDValue LHS = Node->getOperand(0);
3299  SDValue RHS = Node->getOperand(1);
3300  SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3301  ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3302  LHS, RHS);
3303  Results.push_back(Sum);
3304  EVT ResultType = Node->getValueType(1);
3305  EVT OType = getSetCCResultType(Node->getValueType(0));
3306 
3307  SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3308 
3309  // LHSSign -> LHS >= 0
3310  // RHSSign -> RHS >= 0
3311  // SumSign -> Sum >= 0
3312  //
3313  // Add:
3314  // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3315  // Sub:
3316  // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3317  SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3318  SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3319  SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3320  Node->getOpcode() == ISD::SADDO ?
3322 
3323  SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3324  SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3325 
3326  SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3327  Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3328  break;
3329  }
3330  case ISD::UADDO:
3331  case ISD::USUBO: {
3332  SDValue LHS = Node->getOperand(0);
3333  SDValue RHS = Node->getOperand(1);
3334  bool IsAdd = Node->getOpcode() == ISD::UADDO;
3335  // If ADD/SUBCARRY is legal, use that instead.
3336  unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;
3337  if (TLI.isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) {
3338  SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1));
3339  SDValue NodeCarry = DAG.getNode(OpcCarry, dl, Node->getVTList(),
3340  { LHS, RHS, CarryIn });
3341  Results.push_back(SDValue(NodeCarry.getNode(), 0));
3342  Results.push_back(SDValue(NodeCarry.getNode(), 1));
3343  break;
3344  }
3345 
3346  SDValue Sum = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
3347  LHS.getValueType(), LHS, RHS);
3348  Results.push_back(Sum);
3349 
3350  EVT ResultType = Node->getValueType(1);
3351  EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3352  ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3353  SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3354 
3355  Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3356  break;
3357  }
3358  case ISD::UMULO:
3359  case ISD::SMULO: {
3360  EVT VT = Node->getValueType(0);
3361  EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3362  SDValue LHS = Node->getOperand(0);
3363  SDValue RHS = Node->getOperand(1);
3364  SDValue BottomHalf;
3365  SDValue TopHalf;
3366  static const unsigned Ops[2][3] =
3369  bool isSigned = Node->getOpcode() == ISD::SMULO;
3370  if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3371  BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3372  TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3373  } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3374  BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3375  RHS);
3376  TopHalf = BottomHalf.getValue(1);
3377  } else if (TLI.isTypeLegal(WideVT)) {
3378  LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3379  RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3380  Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3381  BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3382  DAG.getIntPtrConstant(0, dl));
3383  TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3384  DAG.getIntPtrConstant(1, dl));
3385  } else {
3386  // We can fall back to a libcall with an illegal type for the MUL if we
3387  // have a libcall big enough.
3388  // Also, we can fall back to a division in some cases, but that's a big
3389  // performance hit in the general case.
3390  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3391  if (WideVT == MVT::i16)
3392  LC = RTLIB::MUL_I16;
3393  else if (WideVT == MVT::i32)
3394  LC = RTLIB::MUL_I32;
3395  else if (WideVT == MVT::i64)
3396  LC = RTLIB::MUL_I64;
3397  else if (WideVT == MVT::i128)
3398  LC = RTLIB::MUL_I128;
3399  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3400 
3401  SDValue HiLHS;
3402  SDValue HiRHS;
3403  if (isSigned) {
3404  // The high part is obtained by SRA'ing all but one of the bits of low
3405  // part.
3406  unsigned LoSize = VT.getSizeInBits();
3407  HiLHS =
3408  DAG.getNode(ISD::SRA, dl, VT, LHS,
3409  DAG.getConstant(LoSize - 1, dl,
3410  TLI.getPointerTy(DAG.getDataLayout())));
3411  HiRHS =
3412  DAG.getNode(ISD::SRA, dl, VT, RHS,
3413  DAG.getConstant(LoSize - 1, dl,
3414  TLI.getPointerTy(DAG.getDataLayout())));
3415  } else {
3416  HiLHS = DAG.getConstant(0, dl, VT);
3417  HiRHS = DAG.getConstant(0, dl, VT);
3418  }
3419 
3420  // Here we're passing the 2 arguments explicitly as 4 arguments that are
3421  // pre-lowered to the correct types. This all depends upon WideVT not
3422  // being a legal type for the architecture and thus has to be split to
3423  // two arguments.
3424  SDValue Ret;
3425  if(DAG.getDataLayout().isLittleEndian()) {
3426  // Halves of WideVT are packed into registers in different order
3427  // depending on platform endianness. This is usually handled by
3428  // the C calling convention, but we can't defer to it in
3429  // the legalizer.
3430  SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3431  Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3432  } else {
3433  SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
3434  Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3435  }
3436  assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
3437  "Ret value is a collection of constituent nodes holding result.");
3438  BottomHalf = Ret.getOperand(0);
3439  TopHalf = Ret.getOperand(1);
3440  }
3441 
3442  if (isSigned) {
3443  Tmp1 = DAG.getConstant(
3444  VT.getSizeInBits() - 1, dl,
3445  TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3446  Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3447  TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3448  ISD::SETNE);
3449  } else {
3450  TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3451  DAG.getConstant(0, dl, VT), ISD::SETNE);
3452  }
3453 
3454  // Truncate the result if SetCC returns a larger type than needed.
3455  EVT RType = Node->getValueType(1);
3456  if (RType.getSizeInBits() < TopHalf.getValueSizeInBits())
3457  TopHalf = DAG.getNode(ISD::TRUNCATE, dl, RType, TopHalf);
3458 
3459  assert(RType.getSizeInBits() == TopHalf.getValueSizeInBits() &&
3460  "Unexpected result type for S/UMULO legalization");
3461 
3462  Results.push_back(BottomHalf);
3463  Results.push_back(TopHalf);
3464  break;
3465  }
3466  case ISD::BUILD_PAIR: {
3467  EVT PairTy = Node->getValueType(0);
3468  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3469  Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3470  Tmp2 = DAG.getNode(
3471  ISD::SHL, dl, PairTy, Tmp2,
3472  DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3473  TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3474  Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3475  break;
3476  }
3477  case ISD::SELECT:
3478  Tmp1 = Node->getOperand(0);
3479  Tmp2 = Node->getOperand(1);
3480  Tmp3 = Node->getOperand(2);
3481  if (Tmp1.getOpcode() == ISD::SETCC) {
3482  Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3483  Tmp2, Tmp3,
3484  cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3485  } else {
3486  Tmp1 = DAG.getSelectCC(dl, Tmp1,
3487  DAG.getConstant(0, dl, Tmp1.getValueType()),
3488  Tmp2, Tmp3, ISD::SETNE);
3489  }
3490  Results.push_back(Tmp1);
3491  break;
3492  case ISD::BR_JT: {
3493  SDValue Chain = Node->getOperand(0);
3494  SDValue Table = Node->getOperand(1);
3495  SDValue Index = Node->getOperand(2);
3496 
3497  const DataLayout &TD = DAG.getDataLayout();
3498  EVT PTy = TLI.getPointerTy(TD);
3499 
3500  unsigned EntrySize =
3501  DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3502 
3503  // For power-of-two jumptable entry sizes convert multiplication to a shift.
3504  // This transformation needs to be done here since otherwise the MIPS
3505  // backend will end up emitting a three instruction multiply sequence
3506  // instead of a single shift and MSP430 will call a runtime function.
3507  if (llvm::isPowerOf2_32(EntrySize))
3508  Index = DAG.getNode(
3509  ISD::SHL, dl, Index.getValueType(), Index,
3510  DAG.getConstant(llvm::Log2_32(EntrySize), dl, Index.getValueType()));
3511  else
3512  Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3513  DAG.getConstant(EntrySize, dl, Index.getValueType()));
3514  SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3515  Index, Table);
3516 
3517  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3518  SDValue LD = DAG.getExtLoad(
3519  ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3520  MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3521  Addr = LD;
3522  if (TLI.isJumpTableRelative()) {
3523  // For PIC, the sequence is:
3524  // BRIND(load(Jumptable + index) + RelocBase)
3525  // RelocBase can be JumpTable, GOT or some sort of global base.
3526  Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3527  TLI.getPICJumpTableRelocBase(Table, DAG));
3528  }
3529 
3530  Tmp1 = TLI.expandIndirectJTBranch(dl, LD.getValue(1), Addr, DAG);
3531  Results.push_back(Tmp1);
3532  break;
3533  }
3534  case ISD::BRCOND:
3535  // Expand brcond's setcc into its constituent parts and create a BR_CC
3536  // Node.
3537  Tmp1 = Node->getOperand(0);
3538  Tmp2 = Node->getOperand(1);
3539  if (Tmp2.getOpcode() == ISD::SETCC) {
3540  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3541  Tmp1, Tmp2.getOperand(2),
3542  Tmp2.getOperand(0), Tmp2.getOperand(1),
3543  Node->getOperand(2));
3544  } else {
3545  // We test only the i1 bit. Skip the AND if UNDEF or another AND.
3546  if (Tmp2.isUndef() ||
3547  (Tmp2.getOpcode() == ISD::AND &&
3548  isa<ConstantSDNode>(Tmp2.getOperand(1)) &&
3549  cast<ConstantSDNode>(Tmp2.getOperand(1))->getZExtValue() == 1))
3550  Tmp3 = Tmp2;
3551  else
3552  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3553  DAG.getConstant(1, dl, Tmp2.getValueType()));
3554  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3555  DAG.getCondCode(ISD::SETNE), Tmp3,
3556  DAG.getConstant(0, dl, Tmp3.getValueType()),
3557  Node->getOperand(2));
3558  }
3559  Results.push_back(Tmp1);
3560  break;
3561  case ISD::SETCC: {
3562  Tmp1 = Node->getOperand(0);
3563  Tmp2 = Node->getOperand(1);
3564  Tmp3 = Node->getOperand(2);
3565  bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3566  Tmp3, NeedInvert, dl);
3567 
3568  if (Legalized) {
3569  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3570  // condition code, create a new SETCC node.
3571  if (Tmp3.getNode())
3572  Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3573  Tmp1, Tmp2, Tmp3);
3574 
3575  // If we expanded the SETCC by inverting the condition code, then wrap
3576  // the existing SETCC in a NOT to restore the intended condition.
3577  if (NeedInvert)
3578  Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3579 
3580  Results.push_back(Tmp1);
3581  break;
3582  }
3583 
3584  // Otherwise, SETCC for the given comparison type must be completely
3585  // illegal; expand it into a SELECT_CC.
3586  EVT VT = Node->getValueType(0);
3587  int TrueValue;
3588  switch (TLI.getBooleanContents(Tmp1.getValueType())) {
3591  TrueValue = 1;
3592  break;
3594  TrueValue = -1;
3595  break;
3596  }
3597  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3598  DAG.getConstant(TrueValue, dl, VT),
3599  DAG.getConstant(0, dl, VT),
3600  Tmp3);
3601  Results.push_back(Tmp1);
3602  break;
3603  }
3604  case ISD::SELECT_CC: {
3605  Tmp1 = Node->getOperand(0); // LHS
3606  Tmp2 = Node->getOperand(1); // RHS
3607  Tmp3 = Node->getOperand(2); // True
3608  Tmp4 = Node->getOperand(3); // False
3609  EVT VT = Node->getValueType(0);
3610  SDValue CC = Node->getOperand(4);
3611  ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3612 
3613  if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) {
3614  // If the condition code is legal, then we need to expand this
3615  // node using SETCC and SELECT.
3616  EVT CmpVT = Tmp1.getValueType();
3617  assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3618  "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3619  "expanded.");
3620  EVT CCVT =
3621  TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3622  SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3623  Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3624  break;
3625  }
3626 
3627  // SELECT_CC is legal, so the condition code must not be.
3628  bool Legalized = false;
3629  // Try to legalize by inverting the condition. This is for targets that
3630  // might support an ordered version of a condition, but not the unordered
3631  // version (or vice versa).
3632  ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3633  Tmp1.getValueType().isInteger());
3634  if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
3635  // Use the new condition code and swap true and false
3636  Legalized = true;
3637  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3638  } else {
3639  // If The inverse is not legal, then try to swap the arguments using
3640  // the inverse condition code.
3641  ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3642  if (TLI.isCondCodeLegalOrCustom(SwapInvCC, Tmp1.getSimpleValueType())) {
3643  // The swapped inverse condition is legal, so swap true and false,
3644  // lhs and rhs.
3645  Legalized = true;
3646  Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3647  }
3648  }
3649 
3650  if (!Legalized) {
3651  Legalized = LegalizeSetCCCondCode(
3652  getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3653  dl);
3654 
3655  assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3656 
3657  // If we expanded the SETCC by inverting the condition code, then swap
3658  // the True/False operands to match.
3659  if (NeedInvert)
3660  std::swap(Tmp3, Tmp4);
3661 
3662  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3663  // condition code, create a new SELECT_CC node.
3664  if (CC.getNode()) {
3665  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3666  Tmp1, Tmp2, Tmp3, Tmp4, CC);
3667  } else {
3668  Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3669  CC = DAG.getCondCode(ISD::SETNE);
3670  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3671  Tmp2, Tmp3, Tmp4, CC);
3672  }
3673  }
3674  Results.push_back(Tmp1);
3675  break;
3676  }
3677  case ISD::BR_CC: {
3678  Tmp1 = Node->getOperand(0); // Chain
3679  Tmp2 = Node->getOperand(2); // LHS
3680  Tmp3 = Node->getOperand(3); // RHS
3681  Tmp4 = Node->getOperand(1); // CC
3682 
3683  bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3684  Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3685  (void)Legalized;
3686  assert(Legalized && "Can't legalize BR_CC with legal condition!");
3687 
3688  assert(!NeedInvert && "Don't know how to invert BR_CC!");
3689 
3690  // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3691  // node.
3692  if (Tmp4.getNode()) {
3693  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3694  Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3695  } else {
3696  Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3697  Tmp4 = DAG.getCondCode(ISD::SETNE);
3698  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3699  Tmp2, Tmp3, Node->getOperand(4));
3700  }
3701  Results.push_back(Tmp1);
3702  break;
3703  }
3704  case ISD::BUILD_VECTOR:
3705  Results.push_back(ExpandBUILD_VECTOR(Node));
3706  break;
3707  case ISD::SRA:
3708  case ISD::SRL:
3709  case ISD::SHL: {
3710  // Scalarize vector SRA/SRL/SHL.
3711  EVT VT = Node->getValueType(0);
3712  assert(VT.isVector() && "Unable to legalize non-vector shift");
3713  assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3714  unsigned NumElem = VT.getVectorNumElements();
3715 
3716  SmallVector<SDValue, 8> Scalars;
3717  for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3718  SDValue Ex = DAG.getNode(
3719  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3720  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3721  SDValue Sh = DAG.getNode(
3722  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3723  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3724  Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3725  VT.getScalarType(), Ex, Sh));
3726  }
3727 
3728  SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
3729  ReplaceNode(SDValue(Node, 0), Result);
3730  break;
3731  }
3733  case ISD::GlobalAddress:
3734  case ISD::GlobalTLSAddress:
3735  case ISD::ExternalSymbol:
3736  case ISD::ConstantPool:
3737  case ISD::JumpTable:
3740  case ISD::INTRINSIC_VOID:
3741  // FIXME: Custom lowering for these operations shouldn't return null!
3742  break;
3743  }
3744 
3745  // Replace the original node with the legalized result.
3746  if (Results.empty()) {
3747  LLVM_DEBUG(dbgs() << "Cannot expand node\n");
3748  return false;
3749  }
3750 
3751  LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
3752  ReplaceNode(Node, Results.data());
3753  return true;
3754 }
3755 
3756 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3757  LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
3759  SDLoc dl(Node);
3760  // FIXME: Check flags on the node to see if we can use a finite call.
3761  bool CanUseFiniteLibCall = TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath;
3762  unsigned Opc = Node->getOpcode();
3763  switch (Opc) {
3764  case ISD::ATOMIC_FENCE: {
3765  // If the target didn't lower this, lower it to '__sync_synchronize()' call
3766  // FIXME: handle "fence singlethread" more efficiently.
3768 
3770  CLI.setDebugLoc(dl)
3771  .setChain(Node->getOperand(0))
3772  .setLibCallee(
3773  CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3774  DAG.getExternalSymbol("__sync_synchronize",
3775  TLI.getPointerTy(DAG.getDataLayout())),
3776  std::move(Args));
3777 
3778  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3779 
3780  Results.push_back(CallResult.second);
3781  break;
3782  }
3783  // By default, atomic intrinsics are marked Legal and lowered. Targets
3784  // which don't support them directly, however, may want libcalls, in which
3785  // case they mark them Expand, and we get here.
3786  case ISD::ATOMIC_SWAP:
3787  case ISD::ATOMIC_LOAD_ADD:
3788  case ISD::ATOMIC_LOAD_SUB:
3789  case ISD::ATOMIC_LOAD_AND:
3790  case ISD::ATOMIC_LOAD_CLR:
3791  case ISD::ATOMIC_LOAD_OR:
3792  case ISD::ATOMIC_LOAD_XOR:
3793  case ISD::ATOMIC_LOAD_NAND:
3794  case ISD::ATOMIC_LOAD_MIN:
3795  case ISD::ATOMIC_LOAD_MAX:
3796  case ISD::ATOMIC_LOAD_UMIN:
3797  case ISD::ATOMIC_LOAD_UMAX:
3798  case ISD::ATOMIC_CMP_SWAP: {
3799  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3800  RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
3801  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3802 
3803  std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3804  Results.push_back(Tmp.first);
3805  Results.push_back(Tmp.second);
3806  break;
3807  }
3808  case ISD::TRAP: {
3809  // If this operation is not supported, lower it to 'abort()' call
3812  CLI.setDebugLoc(dl)
3813  .setChain(Node->getOperand(0))
3814  .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3815  DAG.getExternalSymbol(
3816  "abort", TLI.getPointerTy(DAG.getDataLayout())),
3817  std::move(Args));
3818  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3819 
3820  Results.push_back(CallResult.second);
3821  break;
3822  }
3823  case ISD::FMINNUM:
3824  case ISD::STRICT_FMINNUM:
3825  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3826  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3827  RTLIB::FMIN_PPCF128));
3828  break;
3829  case ISD::FMAXNUM:
3830  case ISD::STRICT_FMAXNUM:
3831  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3832  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3833  RTLIB::FMAX_PPCF128));
3834  break;
3835  case ISD::FSQRT:
3836  case ISD::STRICT_FSQRT:
3837  Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3838  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3839  RTLIB::SQRT_PPCF128));
3840  break;
3841  case ISD::FCBRT:
3842  Results.push_back(ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
3843  RTLIB::CBRT_F80, RTLIB::CBRT_F128,
3844  RTLIB::CBRT_PPCF128));
3845  break;
3846  case ISD::FSIN:
3847  case ISD::STRICT_FSIN:
3848  Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3849  RTLIB::SIN_F80, RTLIB::SIN_F128,
3850  RTLIB::SIN_PPCF128));
3851  break;
3852  case ISD::FCOS:
3853  case ISD::STRICT_FCOS:
3854  Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3855  RTLIB::COS_F80, RTLIB::COS_F128,
3856  RTLIB::COS_PPCF128));
3857  break;
3858  case ISD::FSINCOS:
3859  // Expand into sincos libcall.
3860  ExpandSinCosLibCall(Node, Results);
3861  break;
3862  case ISD::FLOG:
3863  case ISD::STRICT_FLOG:
3864  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log_finite))
3865  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_FINITE_F32,
3866  RTLIB::LOG_FINITE_F64,
3867  RTLIB::LOG_FINITE_F80,
3868  RTLIB::LOG_FINITE_F128,
3869  RTLIB::LOG_FINITE_PPCF128));
3870  else
3871  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3872  RTLIB::LOG_F80, RTLIB::LOG_F128,
3873  RTLIB::LOG_PPCF128));
3874  break;
3875  case ISD::FLOG2:
3876  case ISD::STRICT_FLOG2:
3877  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log2_finite))
3878  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_FINITE_F32,
3879  RTLIB::LOG2_FINITE_F64,
3880  RTLIB::LOG2_FINITE_F80,
3881  RTLIB::LOG2_FINITE_F128,
3882  RTLIB::LOG2_FINITE_PPCF128));
3883  else
3884  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3885  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3886  RTLIB::LOG2_PPCF128));
3887  break;
3888  case ISD::FLOG10:
3889  case ISD::STRICT_FLOG10:
3890  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log10_finite))
3891  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_FINITE_F32,
3892  RTLIB::LOG10_FINITE_F64,
3893  RTLIB::LOG10_FINITE_F80,
3894  RTLIB::LOG10_FINITE_F128,
3895  RTLIB::LOG10_FINITE_PPCF128));
3896  else
3897  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3898  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3899  RTLIB::LOG10_PPCF128));
3900  break;
3901  case ISD::FEXP:
3902  case ISD::STRICT_FEXP:
3903  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp_finite))
3904  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_FINITE_F32,
3905  RTLIB::EXP_FINITE_F64,
3906  RTLIB::EXP_FINITE_F80,
3907  RTLIB::EXP_FINITE_F128,
3908  RTLIB::EXP_FINITE_PPCF128));
3909  else
3910  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3911  RTLIB::EXP_F80, RTLIB::EXP_F128,
3912  RTLIB::EXP_PPCF128));
3913  break;
3914  case ISD::FEXP2:
3915  case ISD::STRICT_FEXP2:
3916  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp2_finite))
3917  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_FINITE_F32,
3918  RTLIB::EXP2_FINITE_F64,
3919  RTLIB::EXP2_FINITE_F80,
3920  RTLIB::EXP2_FINITE_F128,
3921  RTLIB::EXP2_FINITE_PPCF128));
3922  else
3923  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3924  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3925  RTLIB::EXP2_PPCF128));
3926  break;
3927  case ISD::FTRUNC:
3928  case ISD::STRICT_FTRUNC:
3929  Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3930  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3931  RTLIB::TRUNC_PPCF128));
3932  break;
3933  case ISD::FFLOOR:
3934  case ISD::STRICT_FFLOOR:
3935  Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3936  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3937  RTLIB::FLOOR_PPCF128));
3938  break;
3939  case ISD::FCEIL:
3940  case ISD::STRICT_FCEIL:
3941  Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3942  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3943  RTLIB::CEIL_PPCF128));
3944  break;
3945  case ISD::FRINT:
3946  case ISD::STRICT_FRINT:
3947  Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3948  RTLIB::RINT_F80, RTLIB::RINT_F128,
3949  RTLIB::RINT_PPCF128));
3950  break;
3951  case ISD::FNEARBYINT:
3953  Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3954  RTLIB::NEARBYINT_F64,
3955  RTLIB::NEARBYINT_F80,
3956  RTLIB::NEARBYINT_F128,
3957  RTLIB::NEARBYINT_PPCF128));
3958  break;
3959  case ISD::FROUND:
3960  case ISD::STRICT_FROUND:
3961  Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3962  RTLIB::ROUND_F64,
3963  RTLIB::ROUND_F80,
3964  RTLIB::ROUND_F128,
3965  RTLIB::ROUND_PPCF128));
3966  break;
3967  case ISD::FPOWI:
3968  case ISD::STRICT_FPOWI:
3969  Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3970  RTLIB::POWI_F80, RTLIB::POWI_F128,
3971  RTLIB::POWI_PPCF128));
3972  break;
3973  case ISD::FPOW:
3974  case ISD::STRICT_FPOW:
3975  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_pow_finite))
3976  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_FINITE_F32,
3977  RTLIB::POW_FINITE_F64,
3978  RTLIB::POW_FINITE_F80,
3979  RTLIB::POW_FINITE_F128,
3980  RTLIB::POW_FINITE_PPCF128));
3981  else
3982  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3983  RTLIB::POW_F80, RTLIB::POW_F128,
3984  RTLIB::POW_PPCF128));
3985  break;
3986  case ISD::FDIV:
3987  Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3988  RTLIB::DIV_F80, RTLIB::DIV_F128,
3989  RTLIB::DIV_PPCF128));
3990  break;
3991  case ISD::FREM:
3992  case ISD::STRICT_FREM:
3993  Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3994  RTLIB::REM_F80, RTLIB::REM_F128,
3995  RTLIB::REM_PPCF128));
3996  break;
3997  case ISD::FMA:
3998  case ISD::STRICT_FMA:
3999  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4000  RTLIB::FMA_F80, RTLIB::FMA_F128,
4001  RTLIB::FMA_PPCF128));
4002  break;
4003  case ISD::FADD:
4004  Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4005  RTLIB::ADD_F80, RTLIB::ADD_F128,
4006  RTLIB::ADD_PPCF128));
4007  break;
4008  case ISD::FMUL:
4009  Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4010  RTLIB::MUL_F80, RTLIB::MUL_F128,
4011  RTLIB::MUL_PPCF128));
4012  break;
4013  case ISD::FP16_TO_FP:
4014  if (Node->getValueType(0) == MVT::f32) {
4015  Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4016  }
4017  break;
4018  case ISD::FP_TO_FP16: {
4019  RTLIB::Libcall LC =
4021  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4022  Results.push_back(ExpandLibCall(LC, Node, false));
4023  break;
4024  }
4025  case ISD::FSUB:
4026  Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4027  RTLIB::SUB_F80, RTLIB::SUB_F128,
4028  RTLIB::SUB_PPCF128));
4029  break;
4030  case ISD::SREM:
4031  Results.push_back(ExpandIntLibCall(Node, true,
4032  RTLIB::SREM_I8,
4033  RTLIB::SREM_I16, RTLIB::SREM_I32,
4034  RTLIB::SREM_I64, RTLIB::SREM_I128));
4035  break;
4036  case ISD::UREM:
4037  Results.push_back(ExpandIntLibCall(Node, false,
4038  RTLIB::UREM_I8,
4039  RTLIB::UREM_I16, RTLIB::UREM_I32,
4040  RTLIB::UREM_I64, RTLIB::UREM_I128));
4041  break;
4042  case ISD::SDIV:
4043  Results.push_back(ExpandIntLibCall(Node, true,
4044  RTLIB::SDIV_I8,
4045  RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4046  RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4047  break;
4048  case ISD::UDIV:
4049  Results.push_back(ExpandIntLibCall(Node, false,
4050  RTLIB::UDIV_I8,
4051  RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4052  RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4053  break;
4054  case ISD::SDIVREM:
4055  case ISD::UDIVREM:
4056  // Expand into divrem libcall
4057  ExpandDivRemLibCall(Node, Results);
4058  break;
4059  case ISD::MUL:
4060  Results.push_back(ExpandIntLibCall(Node, false,
4061  RTLIB::MUL_I8,
4062  RTLIB::MUL_I16, RTLIB::MUL_I32,
4063  RTLIB::MUL_I64, RTLIB::MUL_I128));
4064  break;
4065  case ISD::CTLZ_ZERO_UNDEF:
4066  switch (Node->getSimpleValueType(0).SimpleTy) {
4067  default:
4068  llvm_unreachable("LibCall explicitly requested, but not available");
4069  case MVT::i32:
4070  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false));
4071  break;
4072  case MVT::i64:
4073  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false));
4074  break;
4075  case MVT::i128:
4076  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false));
4077  break;
4078  }
4079  break;
4080  }
4081 
4082  // Replace the original node with the legalized result.
4083  if (!Results.empty()) {
4084  LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
4085  ReplaceNode(Node, Results.data());
4086  } else
4087  LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
4088 }
4089 
4090 // Determine the vector type to use in place of an original scalar element when
4091 // promoting equally sized vectors.
4093  MVT EltVT, MVT NewEltVT) {
4094  unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4095  MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4096  assert(TLI.isTypeLegal(MidVT) && "unexpected");
4097  return MidVT;
4098 }
4099 
4100 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4101  LLVM_DEBUG(dbgs() << "Trying to promote node\n");
4103  MVT OVT = Node->getSimpleValueType(0);
4104  if (Node->getOpcode() == ISD::UINT_TO_FP ||
4105  Node->getOpcode() == ISD::SINT_TO_FP ||
4106  Node->getOpcode() == ISD::SETCC ||
4107  Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4108  Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4109  OVT = Node->getOperand(0).getSimpleValueType();
4110  }
4111  if (Node->getOpcode() == ISD::BR_CC)
4112  OVT = Node->getOperand(2).getSimpleValueType();
4113  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4114  SDLoc dl(Node);
4115  SDValue Tmp1, Tmp2, Tmp3;
4116  switch (Node->getOpcode()) {
4117  case ISD::CTTZ:
4118  case ISD::CTTZ_ZERO_UNDEF:
4119  case ISD::CTLZ:
4120  case ISD::CTLZ_ZERO_UNDEF:
4121  case ISD::CTPOP:
4122  // Zero extend the argument.
4123  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4124  if (Node->getOpcode() == ISD::CTTZ) {
4125  // The count is the same in the promoted type except if the original
4126  // value was zero. This can be handled by setting the bit just off
4127  // the top of the original type.
4128  auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
4129  OVT.getSizeInBits());
4130  Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4131  DAG.getConstant(TopBit, dl, NVT));
4132  }
4133  // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4134  // already the correct result.
4135  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4136  if (Node->getOpcode() == ISD::CTLZ ||
4137  Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4138  // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4139  Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4140  DAG.getConstant(NVT.getSizeInBits() -
4141  OVT.getSizeInBits(), dl, NVT));
4142  }
4143  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4144  break;
4145  case ISD::BITREVERSE:
4146  case ISD::BSWAP: {
4147  unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4148  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4149  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4150  Tmp1 = DAG.getNode(
4151  ISD::SRL, dl, NVT, Tmp1,
4152  DAG.getConstant(DiffBits, dl,
4153  TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4154 
4155  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4156  break;
4157  }
4158  case ISD::FP_TO_UINT:
4159  case ISD::FP_TO_SINT:
4160  Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4161  Node->getOpcode() == ISD::FP_TO_SINT, dl);
4162  Results.push_back(Tmp1);
4163  break;
4164  case ISD::UINT_TO_FP:
4165  case ISD::SINT_TO_FP:
4166  Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4167  Node->getOpcode() == ISD::SINT_TO_FP, dl);
4168  Results.push_back(Tmp1);
4169  break;
4170  case ISD::VAARG: {
4171  SDValue Chain = Node->getOperand(0); // Get the chain.
4172  SDValue Ptr = Node->getOperand(1); // Get the pointer.
4173 
4174  unsigned TruncOp;
4175  if (OVT.isVector()) {
4176  TruncOp = ISD::BITCAST;
4177  } else {
4178  assert(OVT.isInteger()
4179  && "VAARG promotion is supported only for vectors or integer types");
4180  TruncOp = ISD::TRUNCATE;
4181  }
4182 
4183  // Perform the larger operation, then convert back
4184  Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4185  Node->getConstantOperandVal(3));
4186  Chain = Tmp1.getValue(1);
4187 
4188  Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4189 
4190  // Modified the chain result - switch anything that used the old chain to
4191  // use the new one.
4192  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4193  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4194  if (UpdatedNodes) {
4195  UpdatedNodes->insert(Tmp2.getNode());
4196  UpdatedNodes->insert(Chain.getNode());
4197  }
4198  ReplacedNode(Node);
4199  break;
4200  }
4201  case ISD::MUL:
4202  case ISD::SDIV:
4203  case ISD::SREM:
4204  case ISD::UDIV:
4205  case ISD::UREM:
4206  case ISD::AND:
4207  case ISD::OR:
4208  case ISD::XOR: {
4209  unsigned ExtOp, TruncOp;
4210  if (OVT.isVector()) {
4211  ExtOp = ISD::BITCAST;
4212  TruncOp = ISD::BITCAST;
4213  } else {
4214  assert(OVT.isInteger() && "Cannot promote logic operation");
4215 
4216  switch (Node->getOpcode()) {
4217  default:
4218  ExtOp = ISD::ANY_EXTEND;
4219  break;
4220  case ISD::SDIV:
4221  case ISD::SREM:
4222  ExtOp = ISD::SIGN_EXTEND;
4223  break;
4224  case ISD::UDIV:
4225  case ISD::UREM:
4226  ExtOp = ISD::ZERO_EXTEND;
4227  break;
4228  }
4229  TruncOp = ISD::TRUNCATE;
4230  }
4231  // Promote each of the values to the new type.
4232  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4233  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4234  // Perform the larger operation, then convert back
4235  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4236  Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4237  break;
4238  }
4239  case ISD::UMUL_LOHI:
4240  case ISD::SMUL_LOHI: {
4241  // Promote to a multiply in a wider integer type.
4242  unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4243  : ISD::SIGN_EXTEND;
4244  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4245  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4246  Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4247 
4248  auto &DL = DAG.getDataLayout();
4249  unsigned OriginalSize = OVT.getScalarSizeInBits();
4250  Tmp2 = DAG.getNode(
4251  ISD::SRL, dl, NVT, Tmp1,
4252  DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4253  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4254  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4255  break;
4256  }
4257  case ISD::SELECT: {
4258  unsigned ExtOp, TruncOp;
4259  if (Node->getValueType(0).isVector() ||
4260  Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4261  ExtOp = ISD::BITCAST;
4262  TruncOp = ISD::BITCAST;
4263  } else if (Node->getValueType(0).isInteger()) {
4264  ExtOp = ISD::ANY_EXTEND;
4265  TruncOp = ISD::TRUNCATE;
4266  } else {
4267  ExtOp = ISD::FP_EXTEND;
4268  TruncOp = ISD::FP_ROUND;
4269  }
4270  Tmp1 = Node->getOperand(0);
4271  // Promote each of the values to the new type.
4272  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4273  Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4274  // Perform the larger operation, then round down.
4275  Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4276  if (TruncOp != ISD::FP_ROUND)
4277  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4278  else
4279  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4280  DAG.getIntPtrConstant(0, dl));
4281  Results.push_back(Tmp1);
4282  break;
4283  }
4284  case ISD::VECTOR_SHUFFLE: {
4285  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4286 
4287  // Cast the two input vectors.
4288  Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4289  Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4290 
4291  // Convert the shuffle mask to the right # elements.
4292  Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4293  Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4294  Results.push_back(Tmp1);
4295  break;
4296  }
4297  case ISD::SETCC: {
4298  unsigned ExtOp = ISD::FP_EXTEND;
4299  if (NVT.isInteger()) {
4300  ISD::CondCode CCCode =
4301  cast<CondCodeSDNode>(Node->getOperand(2))->get();
4303  }
4304  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4305  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4306  Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4307  Tmp1, Tmp2, Node->getOperand(2)));
4308  break;
4309  }
4310  case ISD::BR_CC: {
4311  unsigned ExtOp = ISD::FP_EXTEND;
4312  if (NVT.isInteger()) {
4313  ISD::CondCode CCCode =
4314  cast<CondCodeSDNode>(Node->getOperand(1))->get();
4316  }
4317  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4318  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4319  Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4320  Node->getOperand(0), Node->getOperand(1),
4321  Tmp1, Tmp2, Node->getOperand(4)));
4322  break;
4323  }
4324  case ISD::FADD:
4325  case ISD::FSUB:
4326  case ISD::FMUL:
4327  case ISD::FDIV:
4328  case ISD::FREM:
4329  case ISD::FMINNUM:
4330  case ISD::FMAXNUM:
4331  case ISD::FPOW:
4332  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4333  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4334  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4335  Node->getFlags());
4336  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4337  Tmp3, DAG.getIntPtrConstant(0, dl)));
4338  break;
4339  case ISD::FMA:
4340  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4341  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4342  Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4343  Results.push_back(
4344  DAG.getNode(ISD::FP_ROUND, dl, OVT,
4345  DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4346  DAG.getIntPtrConstant(0, dl)));
4347  break;
4348  case ISD::FCOPYSIGN:
4349  case ISD::FPOWI: {
4350  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4351  Tmp2 = Node->getOperand(1);
4352  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4353 
4354  // fcopysign doesn't change anything but the sign bit, so
4355  // (fp_round (fcopysign (fpext a), b))
4356  // is as precise as
4357  // (fp_round (fpext a))
4358  // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4359  const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4360  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4361  Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4362  break;
4363  }
4364  case ISD::FFLOOR:
4365  case ISD::FCEIL:
4366  case ISD::FRINT:
4367  case ISD::FNEARBYINT:
4368  case ISD::FROUND:
4369  case ISD::FTRUNC:
4370  case ISD::FNEG:
4371  case ISD::FSQRT:
4372  case ISD::FSIN:
4373  case ISD::FCOS:
4374  case ISD::FLOG:
4375  case ISD::FLOG2:
4376  case ISD::FLOG10:
4377  case ISD::FABS:
4378  case ISD::FEXP:
4379  case ISD::FEXP2:
4380  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4381  Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4382  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4383  Tmp2, DAG.getIntPtrConstant(0, dl)));
4384  break;
4385  case ISD::BUILD_VECTOR: {
4386  MVT EltVT = OVT.getVectorElementType();
4387  MVT NewEltVT = NVT.getVectorElementType();
4388 
4389  // Handle bitcasts to a different vector type with the same total bit size
4390  //
4391  // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4392  // =>
4393  // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4394 
4395  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4396  "Invalid promote type for build_vector");
4397  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4398 
4399  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4400 
4401  SmallVector<SDValue, 8> NewOps;
4402  for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4403  SDValue Op = Node->getOperand(I);
4404  NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4405  }
4406 
4407  SDLoc SL(Node);
4408  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4409  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4410  Results.push_back(CvtVec);
4411  break;
4412  }
4413  case ISD::EXTRACT_VECTOR_ELT: {
4414  MVT EltVT = OVT.getVectorElementType();
4415  MVT NewEltVT = NVT.getVectorElementType();
4416 
4417  // Handle bitcasts to a different vector type with the same total bit size.
4418  //
4419  // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4420  // =>
4421  // v4i32:castx = bitcast x:v2i64
4422  //
4423  // i64 = bitcast
4424  // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4425  // (i32 (extract_vector_elt castx, (2 * y + 1)))
4426  //
4427 
4428  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4429  "Invalid promote type for extract_vector_elt");
4430  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4431 
4432  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4433  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4434 
4435  SDValue Idx = Node->getOperand(1);
4436  EVT IdxVT = Idx.getValueType();
4437  SDLoc SL(Node);
4438  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4439  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4440 
4441  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4442 
4443  SmallVector<SDValue, 8> NewOps;
4444  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4445  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4446  SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4447 
4448  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4449  CastVec, TmpIdx);
4450  NewOps.push_back(Elt);
4451  }
4452 
4453  SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4454  Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4455  break;
4456  }
4457  case ISD::INSERT_VECTOR_ELT: {
4458  MVT EltVT = OVT.getVectorElementType();
4459  MVT NewEltVT = NVT.getVectorElementType();
4460 
4461  // Handle bitcasts to a different vector type with the same total bit size
4462  //
4463  // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4464  // =>
4465  // v4i32:castx = bitcast x:v2i64
4466  // v2i32:casty = bitcast y:i64
4467  //
4468  // v2i64 = bitcast
4469  // (v4i32 insert_vector_elt
4470  // (v4i32 insert_vector_elt v4i32:castx,
4471  // (extract_vector_elt casty, 0), 2 * z),
4472  // (extract_vector_elt casty, 1), (2 * z + 1))
4473 
4474  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4475  "Invalid promote type for insert_vector_elt");
4476  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4477 
4478  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4479  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4480 
4481  SDValue Val = Node->getOperand(1);
4482  SDValue Idx = Node->getOperand(2);
4483  EVT IdxVT = Idx.getValueType();
4484  SDLoc SL(Node);
4485 
4486  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4487  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4488 
4489  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4490  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4491 
4492  SDValue NewVec = CastVec;
4493  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4494  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4495  SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4496 
4497  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4498  CastVal, IdxOffset);
4499 
4500  NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4501  NewVec, Elt, InEltIdx);
4502  }
4503 
4504  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4505  break;
4506  }
4507  case ISD::SCALAR_TO_VECTOR: {
4508  MVT EltVT = OVT.getVectorElementType();
4509  MVT NewEltVT = NVT.getVectorElementType();
4510 
4511  // Handle bitcasts to different vector type with the same total bit size.
4512  //
4513  // e.g. v2i64 = scalar_to_vector x:i64
4514  // =>
4515  // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4516  //
4517 
4518  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4519  SDValue Val = Node->getOperand(0);
4520  SDLoc SL(Node);
4521 
4522  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4523  SDValue Undef = DAG.getUNDEF(MidVT);
4524 
4525  SmallVector<SDValue, 8> NewElts;
4526  NewElts.push_back(CastVal);
4527  for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4528  NewElts.push_back(Undef);
4529 
4530  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4531  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4532  Results.push_back(CvtVec);
4533  break;
4534  }
4535  case ISD::ATOMIC_SWAP: {
4536  AtomicSDNode *AM = cast<AtomicSDNode>(Node);
4537  SDLoc SL(Node);
4538  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
4539  assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
4540  "unexpected promotion type");
4541  assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
4542  "unexpected atomic_swap with illegal type");
4543 
4544  SDValue NewAtomic
4545  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, NVT,
4546  DAG.getVTList(NVT, MVT::Other),
4547  { AM->getChain(), AM->getBasePtr(), CastVal },
4548  AM->getMemOperand());
4549  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
4550  Results.push_back(NewAtomic.getValue(1));
4551  break;
4552  }
4553  }
4554 
4555  // Replace the original node with the legalized result.
4556  if (!Results.empty()) {
4557  LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
4558  ReplaceNode(Node, Results.data());
4559  } else
4560  LLVM_DEBUG(dbgs() << "Could not promote node\n");
4561 }
4562 
4563 /// This is the entry point for the file.
4565  AssignTopologicalOrder();
4566 
4567  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4568  // Use a delete listener to remove nodes which were deleted during
4569  // legalization from LegalizeNodes. This is needed to handle the situation
4570  // where a new node is allocated by the object pool to the same address of a
4571  // previously deleted node.
4572  DAGNodeDeletedListener DeleteListener(
4573  *this,
4574  [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(N); });
4575 
4576  SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4577 
4578  // Visit all the nodes. We start in topological order, so that we see
4579  // nodes with their original operands intact. Legalization can produce
4580  // new nodes which may themselves need to be legalized. Iterate until all
4581  // nodes have been legalized.
4582  while (true) {
4583  bool AnyLegalized = false;
4584  for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4585  --NI;
4586 
4587  SDNode *N = &*NI;
4588  if (N->use_empty() && N != getRoot().getNode()) {
4589  ++NI;
4590  DeleteNode(N);
4591  continue;
4592  }
4593 
4594  if (LegalizedNodes.insert(N).second) {
4595  AnyLegalized = true;
4596  Legalizer.LegalizeOp(N);
4597 
4598  if (N->use_empty() && N != getRoot().getNode()) {
4599  ++NI;
4600  DeleteNode(N);
4601  }
4602  }
4603  }
4604  if (!AnyLegalized)
4605  break;
4606 
4607  }
4608 
4609  // Remove dead nodes now.
4610  RemoveDeadNodes();
4611 }
4612 
4614  SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4615  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4616  SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4617 
4618  // Directly insert the node in question, and legalize it. This will recurse
4619  // as needed through operands.
4620  LegalizedNodes.insert(N);
4621  Legalizer.LegalizeOp(N);
4622 
4623  return LegalizedNodes.count(N);
4624 }
bool LegalizeOp(SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target ...
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:764
static Constant * getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced=false)
Definition: Constants.cpp:1679
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:571
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:538
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:877
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:594
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isInteger() const
Return true if this is an integer or a vector integer type.
static bool isConstant(const MachineInstr &MI)
bool isUndef() const
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:296
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:562
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:358
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:650
This class represents lattice values for constants.
Definition: AllocatorList.h:24
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:367
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:260
const SDValue & getVal() const
bool isVector() const
Return true if this is a vector value type.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void push_back(const T &Elt)
Definition: SmallVector.h:218
const SDValue & getValue() const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:699
SDVTList getVTList() const
This file contains the declarations for metadata subclasses.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
const SDValue & getBasePtr() const
unsigned getVectorNumElements() const
const SDValue & getChain() const
Function Alias Analysis Results
static MVT getPromotedVectorElementType(const TargetLowering &TLI, MVT EltVT, MVT NewEltVT)
unsigned getAlignment() const
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:802
unsigned second
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:811
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:289
static uint32_t Concat[]
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:177
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:384
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Same for subtraction.
Definition: ISDOpcodes.h:254
void reserve(size_type N)
Definition: SmallVector.h:376
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:212
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:353
The address of the GOT.
Definition: ISDOpcodes.h:66
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:781
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:435
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
const ConstantFP * getConstantFPValue() const
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:159
bool isTruncatingStore() const
Return true if the op does a truncation before store.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode *> &Visited, SmallVectorImpl< const SDNode *> &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
Definition: ISDOpcodes.h:114
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:456
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Shift and rotation operations.
Definition: ISDOpcodes.h:410
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:393
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:652
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:191
RESULT = SMULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same wi...
Definition: ISDOpcodes.h:280
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
op_iterator op_end() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
Definition: ISDOpcodes.h:546
SimpleValueType SimpleTy
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence, and carry arbitrary information that target might want to know.
Definition: ISDOpcodes.h:713
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA)...
Definition: ISDOpcodes.h:96
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:810
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:401
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
This is an SDNode representing atomic operations.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:695
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:91
unsigned getSizeInBits() const
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:298
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:478
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:142
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here...
Definition: ISDOpcodes.h:118
falkor hwpf fix Falkor HW Prefetch Fix Late Phase
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:402
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
bool bitsLT(MVT VT) const
Return true if this has less bits than VT.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
CallLoweringInfo & setZExtResult(bool Value=true)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:852
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:959
op_iterator op_begin() const
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:125
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:747
static bool useSinCos(SDNode *Node)
Only issue sincos libcall if both sin and cos are needed.
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:992
amdgpu Simplify well known AMD library false Value * Callee
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:151
MVT getVectorElementType() const