LLVM  9.0.0svn
LegalizeDAG.cpp
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1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAG::Legalize method.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/SetVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Metadata.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/Support/Casting.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/Debug.h"
47 #include <algorithm>
48 #include <cassert>
49 #include <cstdint>
50 #include <tuple>
51 #include <utility>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "legalizedag"
56 
57 namespace {
58 
59 /// Keeps track of state when getting the sign of a floating-point value as an
60 /// integer.
61 struct FloatSignAsInt {
62  EVT FloatVT;
63  SDValue Chain;
64  SDValue FloatPtr;
65  SDValue IntPtr;
66  MachinePointerInfo IntPointerInfo;
67  MachinePointerInfo FloatPointerInfo;
68  SDValue IntValue;
69  APInt SignMask;
70  uint8_t SignBit;
71 };
72 
73 //===----------------------------------------------------------------------===//
74 /// This takes an arbitrary SelectionDAG as input and
75 /// hacks on it until the target machine can handle it. This involves
76 /// eliminating value sizes the machine cannot handle (promoting small sizes to
77 /// large sizes or splitting up large values into small values) as well as
78 /// eliminating operations the machine cannot handle.
79 ///
80 /// This code also does a small amount of optimization and recognition of idioms
81 /// as part of its processing. For example, if a target does not support a
82 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
83 /// will attempt merge setcc and brc instructions into brcc's.
84 class SelectionDAGLegalize {
85  const TargetMachine &TM;
86  const TargetLowering &TLI;
87  SelectionDAG &DAG;
88 
89  /// The set of nodes which have already been legalized. We hold a
90  /// reference to it in order to update as necessary on node deletion.
91  SmallPtrSetImpl<SDNode *> &LegalizedNodes;
92 
93  /// A set of all the nodes updated during legalization.
94  SmallSetVector<SDNode *, 16> *UpdatedNodes;
95 
96  EVT getSetCCResultType(EVT VT) const {
97  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
98  }
99 
100  // Libcall insertion helpers.
101 
102 public:
103  SelectionDAGLegalize(SelectionDAG &DAG,
104  SmallPtrSetImpl<SDNode *> &LegalizedNodes,
105  SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
106  : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
107  LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
108 
109  /// Legalizes the given operation.
110  void LegalizeOp(SDNode *Node);
111 
112 private:
113  SDValue OptimizeFloatStore(StoreSDNode *ST);
114 
115  void LegalizeLoadOps(SDNode *Node);
116  void LegalizeStoreOps(SDNode *Node);
117 
118  /// Some targets cannot handle a variable
119  /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
120  /// is necessary to spill the vector being inserted into to memory, perform
121  /// the insert there, and then read the result back.
122  SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
123  const SDLoc &dl);
124  SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
125  const SDLoc &dl);
126 
127  /// Return a vector shuffle operation which
128  /// performs the same shuffe in terms of order or result bytes, but on a type
129  /// whose vector element type is narrower than the original shuffle type.
130  /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
131  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
132  SDValue N1, SDValue N2,
133  ArrayRef<int> Mask) const;
134 
135  bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
136  bool &NeedInvert, const SDLoc &dl);
137 
138  SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
139 
140  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
141  SDNode *Node, bool isSigned);
142  SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
143  RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
144  RTLIB::Libcall Call_F128,
145  RTLIB::Libcall Call_PPCF128);
146  SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
147  RTLIB::Libcall Call_I8,
148  RTLIB::Libcall Call_I16,
149  RTLIB::Libcall Call_I32,
150  RTLIB::Libcall Call_I64,
151  RTLIB::Libcall Call_I128);
152  SDValue ExpandArgFPLibCall(SDNode *Node,
153  RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
154  RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
155  RTLIB::Libcall Call_PPCF128);
156  void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
157  void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
158 
159  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
160  const SDLoc &dl);
161  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
162  const SDLoc &dl, SDValue ChainIn);
163  SDValue ExpandBUILD_VECTOR(SDNode *Node);
164  SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
165  void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
166  SmallVectorImpl<SDValue> &Results);
167  void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
168  SDValue Value) const;
169  SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
170  SDValue NewIntValue) const;
171  SDValue ExpandFCOPYSIGN(SDNode *Node) const;
172  SDValue ExpandFABS(SDNode *Node) const;
173  SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
174  const SDLoc &dl);
175  SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
176  const SDLoc &dl);
177  SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
178  const SDLoc &dl);
179 
180  SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
181  SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
182 
183  SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
184  SDValue ExpandInsertToVectorThroughStack(SDValue Op);
185  SDValue ExpandVectorBuildThroughStack(SDNode* Node);
186 
187  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
188  SDValue ExpandConstant(ConstantSDNode *CP);
189 
190  // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
191  bool ExpandNode(SDNode *Node);
192  void ConvertNodeToLibcall(SDNode *Node);
193  void PromoteNode(SDNode *Node);
194 
195 public:
196  // Node replacement helpers
197 
198  void ReplacedNode(SDNode *N) {
199  LegalizedNodes.erase(N);
200  if (UpdatedNodes)
201  UpdatedNodes->insert(N);
202  }
203 
204  void ReplaceNode(SDNode *Old, SDNode *New) {
205  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
206  dbgs() << " with: "; New->dump(&DAG));
207 
208  assert(Old->getNumValues() == New->getNumValues() &&
209  "Replacing one node with another that produces a different number "
210  "of values!");
211  DAG.ReplaceAllUsesWith(Old, New);
212  if (UpdatedNodes)
213  UpdatedNodes->insert(New);
214  ReplacedNode(Old);
215  }
216 
217  void ReplaceNode(SDValue Old, SDValue New) {
218  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
219  dbgs() << " with: "; New->dump(&DAG));
220 
221  DAG.ReplaceAllUsesWith(Old, New);
222  if (UpdatedNodes)
223  UpdatedNodes->insert(New.getNode());
224  ReplacedNode(Old.getNode());
225  }
226 
227  void ReplaceNode(SDNode *Old, const SDValue *New) {
228  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
229 
230  DAG.ReplaceAllUsesWith(Old, New);
231  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
232  LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
233  New[i]->dump(&DAG));
234  if (UpdatedNodes)
235  UpdatedNodes->insert(New[i].getNode());
236  }
237  ReplacedNode(Old);
238  }
239 };
240 
241 } // end anonymous namespace
242 
243 /// Return a vector shuffle operation which
244 /// performs the same shuffle in terms of order or result bytes, but on a type
245 /// whose vector element type is narrower than the original shuffle type.
246 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
247 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
248  EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
249  ArrayRef<int> Mask) const {
250  unsigned NumMaskElts = VT.getVectorNumElements();
251  unsigned NumDestElts = NVT.getVectorNumElements();
252  unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
253 
254  assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
255 
256  if (NumEltsGrowth == 1)
257  return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
258 
259  SmallVector<int, 8> NewMask;
260  for (unsigned i = 0; i != NumMaskElts; ++i) {
261  int Idx = Mask[i];
262  for (unsigned j = 0; j != NumEltsGrowth; ++j) {
263  if (Idx < 0)
264  NewMask.push_back(-1);
265  else
266  NewMask.push_back(Idx * NumEltsGrowth + j);
267  }
268  }
269  assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
270  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
271  return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
272 }
273 
274 /// Expands the ConstantFP node to an integer constant or
275 /// a load from the constant pool.
276 SDValue
277 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
278  bool Extend = false;
279  SDLoc dl(CFP);
280 
281  // If a FP immediate is precise when represented as a float and if the
282  // target can do an extending load from float to double, we put it into
283  // the constant pool as a float, even if it's is statically typed as a
284  // double. This shrinks FP constants and canonicalizes them for targets where
285  // an FP extending load is the same cost as a normal load (such as on the x87
286  // fp stack or PPC FP unit).
287  EVT VT = CFP->getValueType(0);
288  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
289  if (!UseCP) {
290  assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
291  return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
292  (VT == MVT::f64) ? MVT::i64 : MVT::i32);
293  }
294 
295  APFloat APF = CFP->getValueAPF();
296  EVT OrigVT = VT;
297  EVT SVT = VT;
298 
299  // We don't want to shrink SNaNs. Converting the SNaN back to its real type
300  // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
301  if (!APF.isSignaling()) {
302  while (SVT != MVT::f32 && SVT != MVT::f16) {
303  SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
305  // Only do this if the target has a native EXTLOAD instruction from
306  // smaller type.
307  TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
308  TLI.ShouldShrinkFPConstant(OrigVT)) {
309  Type *SType = SVT.getTypeForEVT(*DAG.getContext());
310  LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
311  VT = SVT;
312  Extend = true;
313  }
314  }
315  }
316 
317  SDValue CPIdx =
318  DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
319  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
320  if (Extend) {
321  SDValue Result = DAG.getExtLoad(
322  ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
323  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
324  Alignment);
325  return Result;
326  }
327  SDValue Result = DAG.getLoad(
328  OrigVT, dl, DAG.getEntryNode(), CPIdx,
329  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
330  return Result;
331 }
332 
333 /// Expands the Constant node to a load from the constant pool.
334 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
335  SDLoc dl(CP);
336  EVT VT = CP->getValueType(0);
337  SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
338  TLI.getPointerTy(DAG.getDataLayout()));
339  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
340  SDValue Result = DAG.getLoad(
341  VT, dl, DAG.getEntryNode(), CPIdx,
342  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
343  return Result;
344 }
345 
346 /// Some target cannot handle a variable insertion index for the
347 /// INSERT_VECTOR_ELT instruction. In this case, it
348 /// is necessary to spill the vector being inserted into to memory, perform
349 /// the insert there, and then read the result back.
350 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
351  SDValue Val,
352  SDValue Idx,
353  const SDLoc &dl) {
354  SDValue Tmp1 = Vec;
355  SDValue Tmp2 = Val;
356  SDValue Tmp3 = Idx;
357 
358  // If the target doesn't support this, we have to spill the input vector
359  // to a temporary stack slot, update the element, then reload it. This is
360  // badness. We could also load the value into a vector register (either
361  // with a "move to register" or "extload into register" instruction, then
362  // permute it into place, if the idx is a constant and if the idx is
363  // supported by the target.
364  EVT VT = Tmp1.getValueType();
365  EVT EltVT = VT.getVectorElementType();
366  SDValue StackPtr = DAG.CreateStackTemporary(VT);
367 
368  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
369 
370  // Store the vector.
371  SDValue Ch = DAG.getStore(
372  DAG.getEntryNode(), dl, Tmp1, StackPtr,
373  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
374 
375  SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
376 
377  // Store the scalar value.
378  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT);
379  // Load the updated vector.
380  return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
381  DAG.getMachineFunction(), SPFI));
382 }
383 
384 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
385  SDValue Idx,
386  const SDLoc &dl) {
387  if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
388  // SCALAR_TO_VECTOR requires that the type of the value being inserted
389  // match the element type of the vector being created, except for
390  // integers in which case the inserted value can be over width.
391  EVT EltVT = Vec.getValueType().getVectorElementType();
392  if (Val.getValueType() == EltVT ||
393  (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
394  SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
395  Vec.getValueType(), Val);
396 
397  unsigned NumElts = Vec.getValueType().getVectorNumElements();
398  // We generate a shuffle of InVec and ScVec, so the shuffle mask
399  // should be 0,1,2,3,4,5... with the appropriate element replaced with
400  // elt 0 of the RHS.
401  SmallVector<int, 8> ShufOps;
402  for (unsigned i = 0; i != NumElts; ++i)
403  ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
404 
405  return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
406  }
407  }
408  return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
409 }
410 
411 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
412  LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
413  // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
414  // FIXME: We shouldn't do this for TargetConstantFP's.
415  // FIXME: move this to the DAG Combiner! Note that we can't regress due
416  // to phase ordering between legalized code and the dag combiner. This
417  // probably means that we need to integrate dag combiner and legalizer
418  // together.
419  // We generally can't do this one for long doubles.
420  SDValue Chain = ST->getChain();
421  SDValue Ptr = ST->getBasePtr();
422  unsigned Alignment = ST->getAlignment();
423  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
424  AAMDNodes AAInfo = ST->getAAInfo();
425  SDLoc dl(ST);
426  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
427  if (CFP->getValueType(0) == MVT::f32 &&
428  TLI.isTypeLegal(MVT::i32)) {
429  SDValue Con = DAG.getConstant(CFP->getValueAPF().
430  bitcastToAPInt().zextOrTrunc(32),
431  SDLoc(CFP), MVT::i32);
432  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), Alignment,
433  MMOFlags, AAInfo);
434  }
435 
436  if (CFP->getValueType(0) == MVT::f64) {
437  // If this target supports 64-bit registers, do a single 64-bit store.
438  if (TLI.isTypeLegal(MVT::i64)) {
439  SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
440  zextOrTrunc(64), SDLoc(CFP), MVT::i64);
441  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
442  Alignment, MMOFlags, AAInfo);
443  }
444 
445  if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
446  // Otherwise, if the target supports 32-bit registers, use 2 32-bit
447  // stores. If the target supports neither 32- nor 64-bits, this
448  // xform is certainly not worth it.
449  const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
450  SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
451  SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
452  if (DAG.getDataLayout().isBigEndian())
453  std::swap(Lo, Hi);
454 
455  Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
456  MMOFlags, AAInfo);
457  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
458  DAG.getConstant(4, dl, Ptr.getValueType()));
459  Hi = DAG.getStore(Chain, dl, Hi, Ptr,
460  ST->getPointerInfo().getWithOffset(4),
461  MinAlign(Alignment, 4U), MMOFlags, AAInfo);
462 
463  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
464  }
465  }
466  }
467  return SDValue(nullptr, 0);
468 }
469 
470 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
471  StoreSDNode *ST = cast<StoreSDNode>(Node);
472  SDValue Chain = ST->getChain();
473  SDValue Ptr = ST->getBasePtr();
474  SDLoc dl(Node);
475 
476  unsigned Alignment = ST->getAlignment();
477  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
478  AAMDNodes AAInfo = ST->getAAInfo();
479 
480  if (!ST->isTruncatingStore()) {
481  LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
482  if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
483  ReplaceNode(ST, OptStore);
484  return;
485  }
486 
487  SDValue Value = ST->getValue();
488  MVT VT = Value.getSimpleValueType();
489  switch (TLI.getOperationAction(ISD::STORE, VT)) {
490  default: llvm_unreachable("This action is not supported yet!");
491  case TargetLowering::Legal: {
492  // If this is an unaligned store and the target doesn't support it,
493  // expand it.
494  EVT MemVT = ST->getMemoryVT();
495  unsigned AS = ST->getAddressSpace();
496  unsigned Align = ST->getAlignment();
497  const DataLayout &DL = DAG.getDataLayout();
498  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
499  LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
500  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
501  ReplaceNode(SDValue(ST, 0), Result);
502  } else
503  LLVM_DEBUG(dbgs() << "Legal store\n");
504  break;
505  }
506  case TargetLowering::Custom: {
507  LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
508  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
509  if (Res && Res != SDValue(Node, 0))
510  ReplaceNode(SDValue(Node, 0), Res);
511  return;
512  }
514  MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
515  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
516  "Can only promote stores to same size type");
517  Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
518  SDValue Result =
519  DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
520  Alignment, MMOFlags, AAInfo);
521  ReplaceNode(SDValue(Node, 0), Result);
522  break;
523  }
524  }
525  return;
526  }
527 
528  LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
529  SDValue Value = ST->getValue();
530  EVT StVT = ST->getMemoryVT();
531  unsigned StWidth = StVT.getSizeInBits();
532  auto &DL = DAG.getDataLayout();
533 
534  if (StWidth != StVT.getStoreSizeInBits()) {
535  // Promote to a byte-sized store with upper bits zero if not
536  // storing an integral number of bytes. For example, promote
537  // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
538  EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
539  StVT.getStoreSizeInBits());
540  Value = DAG.getZeroExtendInReg(Value, dl, StVT);
541  SDValue Result =
542  DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
543  Alignment, MMOFlags, AAInfo);
544  ReplaceNode(SDValue(Node, 0), Result);
545  } else if (StWidth & (StWidth - 1)) {
546  // If not storing a power-of-2 number of bits, expand as two stores.
547  assert(!StVT.isVector() && "Unsupported truncstore!");
548  unsigned LogStWidth = Log2_32(StWidth);
549  assert(LogStWidth < 32);
550  unsigned RoundWidth = 1 << LogStWidth;
551  assert(RoundWidth < StWidth);
552  unsigned ExtraWidth = StWidth - RoundWidth;
553  assert(ExtraWidth < RoundWidth);
554  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
555  "Store size not an integral number of bytes!");
556  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
557  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
558  SDValue Lo, Hi;
559  unsigned IncrementSize;
560 
561  if (DL.isLittleEndian()) {
562  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
563  // Store the bottom RoundWidth bits.
564  Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
565  RoundVT, Alignment, MMOFlags, AAInfo);
566 
567  // Store the remaining ExtraWidth bits.
568  IncrementSize = RoundWidth / 8;
569  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
570  DAG.getConstant(IncrementSize, dl,
571  Ptr.getValueType()));
572  Hi = DAG.getNode(
573  ISD::SRL, dl, Value.getValueType(), Value,
574  DAG.getConstant(RoundWidth, dl,
575  TLI.getShiftAmountTy(Value.getValueType(), DL)));
576  Hi = DAG.getTruncStore(
577  Chain, dl, Hi, Ptr,
578  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
579  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
580  } else {
581  // Big endian - avoid unaligned stores.
582  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
583  // Store the top RoundWidth bits.
584  Hi = DAG.getNode(
585  ISD::SRL, dl, Value.getValueType(), Value,
586  DAG.getConstant(ExtraWidth, dl,
587  TLI.getShiftAmountTy(Value.getValueType(), DL)));
588  Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
589  RoundVT, Alignment, MMOFlags, AAInfo);
590 
591  // Store the remaining ExtraWidth bits.
592  IncrementSize = RoundWidth / 8;
593  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
594  DAG.getConstant(IncrementSize, dl,
595  Ptr.getValueType()));
596  Lo = DAG.getTruncStore(
597  Chain, dl, Value, Ptr,
598  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
599  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
600  }
601 
602  // The order of the stores doesn't matter.
603  SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
604  ReplaceNode(SDValue(Node, 0), Result);
605  } else {
606  switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
607  default: llvm_unreachable("This action is not supported yet!");
608  case TargetLowering::Legal: {
609  EVT MemVT = ST->getMemoryVT();
610  unsigned AS = ST->getAddressSpace();
611  unsigned Align = ST->getAlignment();
612  // If this is an unaligned store and the target doesn't support it,
613  // expand it.
614  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
615  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
616  ReplaceNode(SDValue(ST, 0), Result);
617  }
618  break;
619  }
620  case TargetLowering::Custom: {
621  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
622  if (Res && Res != SDValue(Node, 0))
623  ReplaceNode(SDValue(Node, 0), Res);
624  return;
625  }
627  assert(!StVT.isVector() &&
628  "Vector Stores are handled in LegalizeVectorOps");
629 
630  SDValue Result;
631 
632  // TRUNCSTORE:i16 i32 -> STORE i16
633  if (TLI.isTypeLegal(StVT)) {
634  Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
635  Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
636  Alignment, MMOFlags, AAInfo);
637  } else {
638  // The in-memory type isn't legal. Truncate to the type it would promote
639  // to, and then do a truncstore.
640  Value = DAG.getNode(ISD::TRUNCATE, dl,
641  TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
642  Value);
643  Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
644  StVT, Alignment, MMOFlags, AAInfo);
645  }
646 
647  ReplaceNode(SDValue(Node, 0), Result);
648  break;
649  }
650  }
651 }
652 
653 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
654  LoadSDNode *LD = cast<LoadSDNode>(Node);
655  SDValue Chain = LD->getChain(); // The chain.
656  SDValue Ptr = LD->getBasePtr(); // The base pointer.
657  SDValue Value; // The value returned by the load op.
658  SDLoc dl(Node);
659 
661  if (ExtType == ISD::NON_EXTLOAD) {
662  LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
663  MVT VT = Node->getSimpleValueType(0);
664  SDValue RVal = SDValue(Node, 0);
665  SDValue RChain = SDValue(Node, 1);
666 
667  switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
668  default: llvm_unreachable("This action is not supported yet!");
669  case TargetLowering::Legal: {
670  EVT MemVT = LD->getMemoryVT();
671  unsigned AS = LD->getAddressSpace();
672  unsigned Align = LD->getAlignment();
673  const DataLayout &DL = DAG.getDataLayout();
674  // If this is an unaligned load and the target doesn't support it,
675  // expand it.
676  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
677  std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
678  }
679  break;
680  }
682  if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
683  RVal = Res;
684  RChain = Res.getValue(1);
685  }
686  break;
687 
689  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
690  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
691  "Can only promote loads to same size type");
692 
693  SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
694  RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
695  RChain = Res.getValue(1);
696  break;
697  }
698  }
699  if (RChain.getNode() != Node) {
700  assert(RVal.getNode() != Node && "Load must be completely replaced");
701  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
702  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
703  if (UpdatedNodes) {
704  UpdatedNodes->insert(RVal.getNode());
705  UpdatedNodes->insert(RChain.getNode());
706  }
707  ReplacedNode(Node);
708  }
709  return;
710  }
711 
712  LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
713  EVT SrcVT = LD->getMemoryVT();
714  unsigned SrcWidth = SrcVT.getSizeInBits();
715  unsigned Alignment = LD->getAlignment();
716  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
717  AAMDNodes AAInfo = LD->getAAInfo();
718 
719  if (SrcWidth != SrcVT.getStoreSizeInBits() &&
720  // Some targets pretend to have an i1 loading operation, and actually
721  // load an i8. This trick is correct for ZEXTLOAD because the top 7
722  // bits are guaranteed to be zero; it helps the optimizers understand
723  // that these bits are zero. It is also useful for EXTLOAD, since it
724  // tells the optimizers that those bits are undefined. It would be
725  // nice to have an effective generic way of getting these benefits...
726  // Until such a way is found, don't insist on promoting i1 here.
727  (SrcVT != MVT::i1 ||
728  TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
730  // Promote to a byte-sized load if not loading an integral number of
731  // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
732  unsigned NewWidth = SrcVT.getStoreSizeInBits();
733  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
734  SDValue Ch;
735 
736  // The extra bits are guaranteed to be zero, since we stored them that
737  // way. A zext load from NVT thus automatically gives zext from SrcVT.
738 
739  ISD::LoadExtType NewExtType =
741 
742  SDValue Result =
743  DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Chain, Ptr,
744  LD->getPointerInfo(), NVT, Alignment, MMOFlags, AAInfo);
745 
746  Ch = Result.getValue(1); // The chain.
747 
748  if (ExtType == ISD::SEXTLOAD)
749  // Having the top bits zero doesn't help when sign extending.
750  Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
751  Result.getValueType(),
752  Result, DAG.getValueType(SrcVT));
753  else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
754  // All the top bits are guaranteed to be zero - inform the optimizers.
755  Result = DAG.getNode(ISD::AssertZext, dl,
756  Result.getValueType(), Result,
757  DAG.getValueType(SrcVT));
758 
759  Value = Result;
760  Chain = Ch;
761  } else if (SrcWidth & (SrcWidth - 1)) {
762  // If not loading a power-of-2 number of bits, expand as two loads.
763  assert(!SrcVT.isVector() && "Unsupported extload!");
764  unsigned LogSrcWidth = Log2_32(SrcWidth);
765  assert(LogSrcWidth < 32);
766  unsigned RoundWidth = 1 << LogSrcWidth;
767  assert(RoundWidth < SrcWidth);
768  unsigned ExtraWidth = SrcWidth - RoundWidth;
769  assert(ExtraWidth < RoundWidth);
770  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
771  "Load size not an integral number of bytes!");
772  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
773  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
774  SDValue Lo, Hi, Ch;
775  unsigned IncrementSize;
776  auto &DL = DAG.getDataLayout();
777 
778  if (DL.isLittleEndian()) {
779  // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
780  // Load the bottom RoundWidth bits.
781  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
782  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
783  AAInfo);
784 
785  // Load the remaining ExtraWidth bits.
786  IncrementSize = RoundWidth / 8;
787  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
788  DAG.getConstant(IncrementSize, dl,
789  Ptr.getValueType()));
790  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
791  LD->getPointerInfo().getWithOffset(IncrementSize),
792  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
793  AAInfo);
794 
795  // Build a factor node to remember that this load is independent of
796  // the other one.
797  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
798  Hi.getValue(1));
799 
800  // Move the top bits to the right place.
801  Hi = DAG.getNode(
802  ISD::SHL, dl, Hi.getValueType(), Hi,
803  DAG.getConstant(RoundWidth, dl,
804  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
805 
806  // Join the hi and lo parts.
807  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
808  } else {
809  // Big endian - avoid unaligned loads.
810  // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
811  // Load the top RoundWidth bits.
812  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
813  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
814  AAInfo);
815 
816  // Load the remaining ExtraWidth bits.
817  IncrementSize = RoundWidth / 8;
818  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
819  DAG.getConstant(IncrementSize, dl,
820  Ptr.getValueType()));
821  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
822  LD->getPointerInfo().getWithOffset(IncrementSize),
823  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
824  AAInfo);
825 
826  // Build a factor node to remember that this load is independent of
827  // the other one.
828  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
829  Hi.getValue(1));
830 
831  // Move the top bits to the right place.
832  Hi = DAG.getNode(
833  ISD::SHL, dl, Hi.getValueType(), Hi,
834  DAG.getConstant(ExtraWidth, dl,
835  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
836 
837  // Join the hi and lo parts.
838  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
839  }
840 
841  Chain = Ch;
842  } else {
843  bool isCustom = false;
844  switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
845  SrcVT.getSimpleVT())) {
846  default: llvm_unreachable("This action is not supported yet!");
848  isCustom = true;
851  Value = SDValue(Node, 0);
852  Chain = SDValue(Node, 1);
853 
854  if (isCustom) {
855  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
856  Value = Res;
857  Chain = Res.getValue(1);
858  }
859  } else {
860  // If this is an unaligned load and the target doesn't support it,
861  // expand it.
862  EVT MemVT = LD->getMemoryVT();
863  unsigned AS = LD->getAddressSpace();
864  unsigned Align = LD->getAlignment();
865  const DataLayout &DL = DAG.getDataLayout();
866  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
867  std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
868  }
869  }
870  break;
871 
872  case TargetLowering::Expand: {
873  EVT DestVT = Node->getValueType(0);
874  if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
875  // If the source type is not legal, see if there is a legal extload to
876  // an intermediate type that we can then extend further.
877  EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
878  if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
879  TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
880  // If we are loading a legal type, this is a non-extload followed by a
881  // full extend.
882  ISD::LoadExtType MidExtType =
883  (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
884 
885  SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
886  SrcVT, LD->getMemOperand());
887  unsigned ExtendOp =
889  Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
890  Chain = Load.getValue(1);
891  break;
892  }
893 
894  // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
895  // normal undefined upper bits behavior to allow using an in-reg extend
896  // with the illegal FP type, so load as an integer and do the
897  // from-integer conversion.
898  if (SrcVT.getScalarType() == MVT::f16) {
899  EVT ISrcVT = SrcVT.changeTypeToInteger();
900  EVT IDestVT = DestVT.changeTypeToInteger();
901  EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
902 
903  SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
904  Chain, Ptr, ISrcVT,
905  LD->getMemOperand());
906  Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
907  Chain = Result.getValue(1);
908  break;
909  }
910  }
911 
912  assert(!SrcVT.isVector() &&
913  "Vector Loads are handled in LegalizeVectorOps");
914 
915  // FIXME: This does not work for vectors on most targets. Sign-
916  // and zero-extend operations are currently folded into extending
917  // loads, whether they are legal or not, and then we end up here
918  // without any support for legalizing them.
919  assert(ExtType != ISD::EXTLOAD &&
920  "EXTLOAD should always be supported!");
921  // Turn the unsupported load into an EXTLOAD followed by an
922  // explicit zero/sign extend inreg.
923  SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
924  Node->getValueType(0),
925  Chain, Ptr, SrcVT,
926  LD->getMemOperand());
927  SDValue ValRes;
928  if (ExtType == ISD::SEXTLOAD)
929  ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
930  Result.getValueType(),
931  Result, DAG.getValueType(SrcVT));
932  else
933  ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
934  Value = ValRes;
935  Chain = Result.getValue(1);
936  break;
937  }
938  }
939  }
940 
941  // Since loads produce two values, make sure to remember that we legalized
942  // both of them.
943  if (Chain.getNode() != Node) {
944  assert(Value.getNode() != Node && "Load must be completely replaced");
945  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
946  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
947  if (UpdatedNodes) {
948  UpdatedNodes->insert(Value.getNode());
949  UpdatedNodes->insert(Chain.getNode());
950  }
951  ReplacedNode(Node);
952  }
953 }
954 
955 /// Return a legal replacement for the given operation, with all legal operands.
956 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
957  LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
958 
959  // Allow illegal target nodes and illegal registers.
960  if (Node->getOpcode() == ISD::TargetConstant ||
961  Node->getOpcode() == ISD::Register)
962  return;
963 
964 #ifndef NDEBUG
965  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
966  assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
968  TLI.isTypeLegal(Node->getValueType(i))) &&
969  "Unexpected illegal type!");
970 
971  for (const SDValue &Op : Node->op_values())
972  assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
974  TLI.isTypeLegal(Op.getValueType()) ||
975  Op.getOpcode() == ISD::TargetConstant ||
976  Op.getOpcode() == ISD::Register) &&
977  "Unexpected illegal type!");
978 #endif
979 
980  // Figure out the correct action; the way to query this varies by opcode
982  bool SimpleFinishLegalizing = true;
983  switch (Node->getOpcode()) {
986  case ISD::INTRINSIC_VOID:
987  case ISD::STACKSAVE:
988  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
989  break;
991  Action = TLI.getOperationAction(Node->getOpcode(),
992  Node->getValueType(0));
993  break;
994  case ISD::VAARG:
995  Action = TLI.getOperationAction(Node->getOpcode(),
996  Node->getValueType(0));
997  if (Action != TargetLowering::Promote)
998  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
999  break;
1000  case ISD::FP_TO_FP16:
1001  case ISD::SINT_TO_FP:
1002  case ISD::UINT_TO_FP:
1004  case ISD::LROUND:
1005  case ISD::LLROUND:
1006  Action = TLI.getOperationAction(Node->getOpcode(),
1007  Node->getOperand(0).getValueType());
1008  break;
1009  case ISD::FP_ROUND_INREG:
1010  case ISD::SIGN_EXTEND_INREG: {
1011  EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1012  Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1013  break;
1014  }
1015  case ISD::ATOMIC_STORE:
1016  Action = TLI.getOperationAction(Node->getOpcode(),
1017  Node->getOperand(2).getValueType());
1018  break;
1019  case ISD::SELECT_CC:
1020  case ISD::SETCC:
1021  case ISD::BR_CC: {
1022  unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1023  Node->getOpcode() == ISD::SETCC ? 2 : 1;
1024  unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1025  MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1026  ISD::CondCode CCCode =
1027  cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1028  Action = TLI.getCondCodeAction(CCCode, OpVT);
1029  if (Action == TargetLowering::Legal) {
1030  if (Node->getOpcode() == ISD::SELECT_CC)
1031  Action = TLI.getOperationAction(Node->getOpcode(),
1032  Node->getValueType(0));
1033  else
1034  Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1035  }
1036  break;
1037  }
1038  case ISD::LOAD:
1039  case ISD::STORE:
1040  // FIXME: Model these properly. LOAD and STORE are complicated, and
1041  // STORE expects the unlegalized operand in some cases.
1042  SimpleFinishLegalizing = false;
1043  break;
1044  case ISD::CALLSEQ_START:
1045  case ISD::CALLSEQ_END:
1046  // FIXME: This shouldn't be necessary. These nodes have special properties
1047  // dealing with the recursive nature of legalization. Removing this
1048  // special case should be done as part of making LegalizeDAG non-recursive.
1049  SimpleFinishLegalizing = false;
1050  break;
1051  case ISD::EXTRACT_ELEMENT:
1052  case ISD::FLT_ROUNDS_:
1053  case ISD::MERGE_VALUES:
1054  case ISD::EH_RETURN:
1056  case ISD::EH_DWARF_CFA:
1057  case ISD::EH_SJLJ_SETJMP:
1058  case ISD::EH_SJLJ_LONGJMP:
1060  // These operations lie about being legal: when they claim to be legal,
1061  // they should actually be expanded.
1062  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1063  if (Action == TargetLowering::Legal)
1064  Action = TargetLowering::Expand;
1065  break;
1066  case ISD::INIT_TRAMPOLINE:
1068  case ISD::FRAMEADDR:
1069  case ISD::RETURNADDR:
1070  case ISD::ADDROFRETURNADDR:
1071  case ISD::SPONENTRY:
1072  // These operations lie about being legal: when they claim to be legal,
1073  // they should actually be custom-lowered.
1074  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1075  if (Action == TargetLowering::Legal)
1076  Action = TargetLowering::Custom;
1077  break;
1078  case ISD::READCYCLECOUNTER:
1079  // READCYCLECOUNTER returns an i64, even if type legalization might have
1080  // expanded that to several smaller types.
1081  Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1082  break;
1083  case ISD::READ_REGISTER:
1084  case ISD::WRITE_REGISTER:
1085  // Named register is legal in the DAG, but blocked by register name
1086  // selection if not implemented by target (to chose the correct register)
1087  // They'll be converted to Copy(To/From)Reg.
1088  Action = TargetLowering::Legal;
1089  break;
1090  case ISD::DEBUGTRAP:
1091  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1092  if (Action == TargetLowering::Expand) {
1093  // replace ISD::DEBUGTRAP with ISD::TRAP
1094  SDValue NewVal;
1095  NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1096  Node->getOperand(0));
1097  ReplaceNode(Node, NewVal.getNode());
1098  LegalizeOp(NewVal.getNode());
1099  return;
1100  }
1101  break;
1102  case ISD::STRICT_FADD:
1103  case ISD::STRICT_FSUB:
1104  case ISD::STRICT_FMUL:
1105  case ISD::STRICT_FDIV:
1106  case ISD::STRICT_FREM:
1107  case ISD::STRICT_FSQRT:
1108  case ISD::STRICT_FMA:
1109  case ISD::STRICT_FPOW:
1110  case ISD::STRICT_FPOWI:
1111  case ISD::STRICT_FSIN:
1112  case ISD::STRICT_FCOS:
1113  case ISD::STRICT_FEXP:
1114  case ISD::STRICT_FEXP2:
1115  case ISD::STRICT_FLOG:
1116  case ISD::STRICT_FLOG10:
1117  case ISD::STRICT_FLOG2:
1118  case ISD::STRICT_FRINT:
1120  case ISD::STRICT_FMAXNUM:
1121  case ISD::STRICT_FMINNUM:
1122  case ISD::STRICT_FCEIL:
1123  case ISD::STRICT_FFLOOR:
1124  case ISD::STRICT_FROUND:
1125  case ISD::STRICT_FTRUNC:
1126  case ISD::STRICT_FP_ROUND:
1127  case ISD::STRICT_FP_EXTEND:
1128  // These pseudo-ops get legalized as if they were their non-strict
1129  // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
1130  // is also legal, but if ISD::FSQRT requires expansion then so does
1131  // ISD::STRICT_FSQRT.
1132  Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
1133  Node->getValueType(0));
1134  break;
1135  case ISD::SADDSAT:
1136  case ISD::UADDSAT:
1137  case ISD::SSUBSAT:
1138  case ISD::USUBSAT: {
1139  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1140  break;
1141  }
1142  case ISD::SMULFIX:
1143  case ISD::UMULFIX: {
1144  unsigned Scale = Node->getConstantOperandVal(2);
1145  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
1146  Node->getValueType(0), Scale);
1147  break;
1148  }
1149  case ISD::MSCATTER:
1150  Action = TLI.getOperationAction(Node->getOpcode(),
1151  cast<MaskedScatterSDNode>(Node)->getValue().getValueType());
1152  break;
1153  case ISD::MSTORE:
1154  Action = TLI.getOperationAction(Node->getOpcode(),
1155  cast<MaskedStoreSDNode>(Node)->getValue().getValueType());
1156  break;
1157  case ISD::VECREDUCE_FADD:
1158  case ISD::VECREDUCE_FMUL:
1159  case ISD::VECREDUCE_ADD:
1160  case ISD::VECREDUCE_MUL:
1161  case ISD::VECREDUCE_AND:
1162  case ISD::VECREDUCE_OR:
1163  case ISD::VECREDUCE_XOR:
1164  case ISD::VECREDUCE_SMAX:
1165  case ISD::VECREDUCE_SMIN:
1166  case ISD::VECREDUCE_UMAX:
1167  case ISD::VECREDUCE_UMIN:
1168  case ISD::VECREDUCE_FMAX:
1169  case ISD::VECREDUCE_FMIN:
1170  Action = TLI.getOperationAction(
1171  Node->getOpcode(), Node->getOperand(0).getValueType());
1172  break;
1173  default:
1174  if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1175  Action = TargetLowering::Legal;
1176  } else {
1177  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1178  }
1179  break;
1180  }
1181 
1182  if (SimpleFinishLegalizing) {
1183  SDNode *NewNode = Node;
1184  switch (Node->getOpcode()) {
1185  default: break;
1186  case ISD::SHL:
1187  case ISD::SRL:
1188  case ISD::SRA:
1189  case ISD::ROTL:
1190  case ISD::ROTR: {
1191  // Legalizing shifts/rotates requires adjusting the shift amount
1192  // to the appropriate width.
1193  SDValue Op0 = Node->getOperand(0);
1194  SDValue Op1 = Node->getOperand(1);
1195  if (!Op1.getValueType().isVector()) {
1196  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1197  // The getShiftAmountOperand() may create a new operand node or
1198  // return the existing one. If new operand is created we need
1199  // to update the parent node.
1200  // Do not try to legalize SAO here! It will be automatically legalized
1201  // in the next round.
1202  if (SAO != Op1)
1203  NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1204  }
1205  }
1206  break;
1207  case ISD::FSHL:
1208  case ISD::FSHR:
1209  case ISD::SRL_PARTS:
1210  case ISD::SRA_PARTS:
1211  case ISD::SHL_PARTS: {
1212  // Legalizing shifts/rotates requires adjusting the shift amount
1213  // to the appropriate width.
1214  SDValue Op0 = Node->getOperand(0);
1215  SDValue Op1 = Node->getOperand(1);
1216  SDValue Op2 = Node->getOperand(2);
1217  if (!Op2.getValueType().isVector()) {
1218  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1219  // The getShiftAmountOperand() may create a new operand node or
1220  // return the existing one. If new operand is created we need
1221  // to update the parent node.
1222  if (SAO != Op2)
1223  NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1224  }
1225  break;
1226  }
1227  }
1228 
1229  if (NewNode != Node) {
1230  ReplaceNode(Node, NewNode);
1231  Node = NewNode;
1232  }
1233  switch (Action) {
1234  case TargetLowering::Legal:
1235  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1236  return;
1238  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1239  // FIXME: The handling for custom lowering with multiple results is
1240  // a complete mess.
1241  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1242  if (!(Res.getNode() != Node || Res.getResNo() != 0))
1243  return;
1244 
1245  if (Node->getNumValues() == 1) {
1246  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1247  // We can just directly replace this node with the lowered value.
1248  ReplaceNode(SDValue(Node, 0), Res);
1249  return;
1250  }
1251 
1252  SmallVector<SDValue, 8> ResultVals;
1253  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1254  ResultVals.push_back(Res.getValue(i));
1255  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1256  ReplaceNode(Node, ResultVals.data());
1257  return;
1258  }
1259  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1262  if (ExpandNode(Node))
1263  return;
1266  ConvertNodeToLibcall(Node);
1267  return;
1269  PromoteNode(Node);
1270  return;
1271  }
1272  }
1273 
1274  switch (Node->getOpcode()) {
1275  default:
1276 #ifndef NDEBUG
1277  dbgs() << "NODE: ";
1278  Node->dump( &DAG);
1279  dbgs() << "\n";
1280 #endif
1281  llvm_unreachable("Do not know how to legalize this operator!");
1282 
1283  case ISD::CALLSEQ_START:
1284  case ISD::CALLSEQ_END:
1285  break;
1286  case ISD::LOAD:
1287  return LegalizeLoadOps(Node);
1288  case ISD::STORE:
1289  return LegalizeStoreOps(Node);
1290  }
1291 }
1292 
1293 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1294  SDValue Vec = Op.getOperand(0);
1295  SDValue Idx = Op.getOperand(1);
1296  SDLoc dl(Op);
1297 
1298  // Before we generate a new store to a temporary stack slot, see if there is
1299  // already one that we can use. There often is because when we scalarize
1300  // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1301  // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1302  // the vector. If all are expanded here, we don't want one store per vector
1303  // element.
1304 
1305  // Caches for hasPredecessorHelper
1308  Visited.insert(Op.getNode());
1309  Worklist.push_back(Idx.getNode());
1310  SDValue StackPtr, Ch;
1311  for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1312  UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1313  SDNode *User = *UI;
1314  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1315  if (ST->isIndexed() || ST->isTruncatingStore() ||
1316  ST->getValue() != Vec)
1317  continue;
1318 
1319  // Make sure that nothing else could have stored into the destination of
1320  // this store.
1321  if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1322  continue;
1323 
1324  // If the index is dependent on the store we will introduce a cycle when
1325  // creating the load (the load uses the index, and by replacing the chain
1326  // we will make the index dependent on the load). Also, the store might be
1327  // dependent on the extractelement and introduce a cycle when creating
1328  // the load.
1329  if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
1330  ST->hasPredecessor(Op.getNode()))
1331  continue;
1332 
1333  StackPtr = ST->getBasePtr();
1334  Ch = SDValue(ST, 0);
1335  break;
1336  }
1337  }
1338 
1339  EVT VecVT = Vec.getValueType();
1340 
1341  if (!Ch.getNode()) {
1342  // Store the value to a temporary stack slot, then LOAD the returned part.
1343  StackPtr = DAG.CreateStackTemporary(VecVT);
1344  Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1345  MachinePointerInfo());
1346  }
1347 
1348  StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1349 
1350  SDValue NewLoad;
1351 
1352  if (Op.getValueType().isVector())
1353  NewLoad =
1354  DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, MachinePointerInfo());
1355  else
1356  NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1358  VecVT.getVectorElementType());
1359 
1360  // Replace the chain going out of the store, by the one out of the load.
1361  DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1362 
1363  // We introduced a cycle though, so update the loads operands, making sure
1364  // to use the original store's chain as an incoming chain.
1365  SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1366  NewLoad->op_end());
1367  NewLoadOperands[0] = Ch;
1368  NewLoad =
1369  SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1370  return NewLoad;
1371 }
1372 
1373 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1374  assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1375 
1376  SDValue Vec = Op.getOperand(0);
1377  SDValue Part = Op.getOperand(1);
1378  SDValue Idx = Op.getOperand(2);
1379  SDLoc dl(Op);
1380 
1381  // Store the value to a temporary stack slot, then LOAD the returned part.
1382  EVT VecVT = Vec.getValueType();
1383  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1384  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1385  MachinePointerInfo PtrInfo =
1386  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1387 
1388  // First store the whole vector.
1389  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1390 
1391  // Then store the inserted part.
1392  SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1393 
1394  // Store the subvector.
1395  Ch = DAG.getStore(Ch, dl, Part, SubStackPtr, MachinePointerInfo());
1396 
1397  // Finally, load the updated vector.
1398  return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1399 }
1400 
1401 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1402  // We can't handle this case efficiently. Allocate a sufficiently
1403  // aligned object on the stack, store each element into it, then load
1404  // the result as a vector.
1405  // Create the stack frame object.
1406  EVT VT = Node->getValueType(0);
1407  EVT EltVT = VT.getVectorElementType();
1408  SDLoc dl(Node);
1409  SDValue FIPtr = DAG.CreateStackTemporary(VT);
1410  int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1411  MachinePointerInfo PtrInfo =
1412  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1413 
1414  // Emit a store of each element to the stack slot.
1415  SmallVector<SDValue, 8> Stores;
1416  unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1417  // Store (in the right endianness) the elements to memory.
1418  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1419  // Ignore undef elements.
1420  if (Node->getOperand(i).isUndef()) continue;
1421 
1422  unsigned Offset = TypeByteSize*i;
1423 
1424  SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1425  Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1426 
1427  // If the destination vector element type is narrower than the source
1428  // element type, only store the bits necessary.
1429  if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1430  Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1431  Node->getOperand(i), Idx,
1432  PtrInfo.getWithOffset(Offset), EltVT));
1433  } else
1434  Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1435  Idx, PtrInfo.getWithOffset(Offset)));
1436  }
1437 
1438  SDValue StoreChain;
1439  if (!Stores.empty()) // Not all undef elements?
1440  StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1441  else
1442  StoreChain = DAG.getEntryNode();
1443 
1444  // Result is a load from the stack slot.
1445  return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1446 }
1447 
1448 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1449 /// containing the sign bit if the target has no integer value capable of
1450 /// holding all bits of the floating-point value.
1451 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1452  const SDLoc &DL,
1453  SDValue Value) const {
1454  EVT FloatVT = Value.getValueType();
1455  unsigned NumBits = FloatVT.getSizeInBits();
1456  State.FloatVT = FloatVT;
1457  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1458  // Convert to an integer of the same size.
1459  if (TLI.isTypeLegal(IVT)) {
1460  State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1461  State.SignMask = APInt::getSignMask(NumBits);
1462  State.SignBit = NumBits - 1;
1463  return;
1464  }
1465 
1466  auto &DataLayout = DAG.getDataLayout();
1467  // Store the float to memory, then load the sign part out as an integer.
1468  MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1469  // First create a temporary that is aligned for both the load and store.
1470  SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1471  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1472  // Then store the float to it.
1473  State.FloatPtr = StackPtr;
1474  MachineFunction &MF = DAG.getMachineFunction();
1475  State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1476  State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1477  State.FloatPointerInfo);
1478 
1479  SDValue IntPtr;
1480  if (DataLayout.isBigEndian()) {
1481  assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1482  // Load out a legal integer with the same sign bit as the float.
1483  IntPtr = StackPtr;
1484  State.IntPointerInfo = State.FloatPointerInfo;
1485  } else {
1486  // Advance the pointer so that the loaded byte will contain the sign bit.
1487  unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1488  IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1489  DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1490  State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1491  ByteOffset);
1492  }
1493 
1494  State.IntPtr = IntPtr;
1495  State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1496  State.IntPointerInfo, MVT::i8);
1497  State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1498  State.SignBit = 7;
1499 }
1500 
1501 /// Replace the integer value produced by getSignAsIntValue() with a new value
1502 /// and cast the result back to a floating-point type.
1503 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1504  const SDLoc &DL,
1505  SDValue NewIntValue) const {
1506  if (!State.Chain)
1507  return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1508 
1509  // Override the part containing the sign bit in the value stored on the stack.
1510  SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1511  State.IntPointerInfo, MVT::i8);
1512  return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1513  State.FloatPointerInfo);
1514 }
1515 
1516 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1517  SDLoc DL(Node);
1518  SDValue Mag = Node->getOperand(0);
1519  SDValue Sign = Node->getOperand(1);
1520 
1521  // Get sign bit into an integer value.
1522  FloatSignAsInt SignAsInt;
1523  getSignAsIntValue(SignAsInt, DL, Sign);
1524 
1525  EVT IntVT = SignAsInt.IntValue.getValueType();
1526  SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1527  SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1528  SignMask);
1529 
1530  // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1531  EVT FloatVT = Mag.getValueType();
1532  if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1533  TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1534  SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1535  SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1536  SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1537  DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1538  return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1539  }
1540 
1541  // Transform Mag value to integer, and clear the sign bit.
1542  FloatSignAsInt MagAsInt;
1543  getSignAsIntValue(MagAsInt, DL, Mag);
1544  EVT MagVT = MagAsInt.IntValue.getValueType();
1545  SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1546  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1547  ClearSignMask);
1548 
1549  // Get the signbit at the right position for MagAsInt.
1550  int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1551  EVT ShiftVT = IntVT;
1552  if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1553  SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1554  ShiftVT = MagVT;
1555  }
1556  if (ShiftAmount > 0) {
1557  SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1558  SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst);
1559  } else if (ShiftAmount < 0) {
1560  SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
1561  SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
1562  }
1563  if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1564  SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1565  }
1566 
1567  // Store the part with the modified sign and convert back to float.
1568  SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1569  return modifySignAsInt(MagAsInt, DL, CopiedSign);
1570 }
1571 
1572 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1573  SDLoc DL(Node);
1574  SDValue Value = Node->getOperand(0);
1575 
1576  // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1577  EVT FloatVT = Value.getValueType();
1578  if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1579  SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1580  return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1581  }
1582 
1583  // Transform value to integer, clear the sign bit and transform back.
1584  FloatSignAsInt ValueAsInt;
1585  getSignAsIntValue(ValueAsInt, DL, Value);
1586  EVT IntVT = ValueAsInt.IntValue.getValueType();
1587  SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1588  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1589  ClearSignMask);
1590  return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1591 }
1592 
1593 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1595  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1596  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1597  " not tell us which reg is the stack pointer!");
1598  SDLoc dl(Node);
1599  EVT VT = Node->getValueType(0);
1600  SDValue Tmp1 = SDValue(Node, 0);
1601  SDValue Tmp2 = SDValue(Node, 1);
1602  SDValue Tmp3 = Node->getOperand(2);
1603  SDValue Chain = Tmp1.getOperand(0);
1604 
1605  // Chain the dynamic stack allocation so that it doesn't modify the stack
1606  // pointer when other instructions are using the stack.
1607  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1608 
1609  SDValue Size = Tmp2.getOperand(1);
1610  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1611  Chain = SP.getValue(1);
1612  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1613  unsigned StackAlign =
1614  DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1615  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1616  if (Align > StackAlign)
1617  Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1618  DAG.getConstant(-(uint64_t)Align, dl, VT));
1619  Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1620 
1621  Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1622  DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1623 
1624  Results.push_back(Tmp1);
1625  Results.push_back(Tmp2);
1626 }
1627 
1628 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1629 /// target.
1630 ///
1631 /// If the SETCC has been legalized using AND / OR, then the legalized node
1632 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1633 /// will be set to false.
1634 ///
1635 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1636 /// then the values of LHS and RHS will be swapped, CC will be set to the
1637 /// new condition, and NeedInvert will be set to false.
1638 ///
1639 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1640 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1641 /// will be set to true. The caller must invert the result of the SETCC with
1642 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1643 /// of a true/false result.
1644 ///
1645 /// \returns true if the SetCC has been legalized, false if it hasn't.
1646 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1647  SDValue &RHS, SDValue &CC,
1648  bool &NeedInvert,
1649  const SDLoc &dl) {
1650  MVT OpVT = LHS.getSimpleValueType();
1651  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1652  NeedInvert = false;
1653  bool NeedSwap = false;
1654  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1655  default: llvm_unreachable("Unknown condition code action!");
1656  case TargetLowering::Legal:
1657  // Nothing to do.
1658  break;
1659  case TargetLowering::Expand: {
1661  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1662  std::swap(LHS, RHS);
1663  CC = DAG.getCondCode(InvCC);
1664  return true;
1665  }
1666  // Swapping operands didn't work. Try inverting the condition.
1667  InvCC = getSetCCInverse(CCCode, OpVT.isInteger());
1668  if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1669  // If inverting the condition is not enough, try swapping operands
1670  // on top of it.
1671  InvCC = ISD::getSetCCSwappedOperands(InvCC);
1672  NeedSwap = true;
1673  }
1674  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1675  CC = DAG.getCondCode(InvCC);
1676  NeedInvert = true;
1677  if (NeedSwap)
1678  std::swap(LHS, RHS);
1679  return true;
1680  }
1681 
1683  unsigned Opc = 0;
1684  switch (CCCode) {
1685  default: llvm_unreachable("Don't know how to expand this condition!");
1686  case ISD::SETO:
1687  assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
1688  && "If SETO is expanded, SETOEQ must be legal!");
1689  CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1690  case ISD::SETUO:
1691  assert(TLI.isCondCodeLegal(ISD::SETUNE, OpVT)
1692  && "If SETUO is expanded, SETUNE must be legal!");
1693  CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1694  case ISD::SETOEQ:
1695  case ISD::SETOGT:
1696  case ISD::SETOGE:
1697  case ISD::SETOLT:
1698  case ISD::SETOLE:
1699  case ISD::SETONE:
1700  case ISD::SETUEQ:
1701  case ISD::SETUNE:
1702  case ISD::SETUGT:
1703  case ISD::SETUGE:
1704  case ISD::SETULT:
1705  case ISD::SETULE:
1706  // If we are floating point, assign and break, otherwise fall through.
1707  if (!OpVT.isInteger()) {
1708  // We can use the 4th bit to tell if we are the unordered
1709  // or ordered version of the opcode.
1710  CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1711  Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1712  CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1713  break;
1714  }
1715  // Fallthrough if we are unsigned integer.
1717  case ISD::SETLE:
1718  case ISD::SETGT:
1719  case ISD::SETGE:
1720  case ISD::SETLT:
1721  case ISD::SETNE:
1722  case ISD::SETEQ:
1723  // If all combinations of inverting the condition and swapping operands
1724  // didn't work then we have no means to expand the condition.
1725  llvm_unreachable("Don't know how to expand this condition!");
1726  }
1727 
1728  SDValue SetCC1, SetCC2;
1729  if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1730  // If we aren't the ordered or unorder operation,
1731  // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1732  SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1733  SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1734  } else {
1735  // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1736  SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1737  SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1738  }
1739  LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1740  RHS = SDValue();
1741  CC = SDValue();
1742  return true;
1743  }
1744  }
1745  return false;
1746 }
1747 
1748 /// Emit a store/load combination to the stack. This stores
1749 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1750 /// a load from the stack slot to DestVT, extending it if needed.
1751 /// The resultant code need not be legal.
1752 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1753  EVT DestVT, const SDLoc &dl) {
1754  return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode());
1755 }
1756 
1757 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1758  EVT DestVT, const SDLoc &dl,
1759  SDValue Chain) {
1760  // Create the stack frame object.
1761  unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1762  SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1763  SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1764 
1765  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1766  int SPFI = StackPtrFI->getIndex();
1767  MachinePointerInfo PtrInfo =
1768  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1769 
1770  unsigned SrcSize = SrcOp.getValueSizeInBits();
1771  unsigned SlotSize = SlotVT.getSizeInBits();
1772  unsigned DestSize = DestVT.getSizeInBits();
1773  Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1774  unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1775 
1776  // Emit a store to the stack slot. Use a truncstore if the input value is
1777  // later than DestVT.
1778  SDValue Store;
1779 
1780  if (SrcSize > SlotSize)
1781  Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo,
1782  SlotVT, SrcAlign);
1783  else {
1784  assert(SrcSize == SlotSize && "Invalid store");
1785  Store =
1786  DAG.getStore(Chain, dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1787  }
1788 
1789  // Result is a load from the stack slot.
1790  if (SlotSize == DestSize)
1791  return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1792 
1793  assert(SlotSize < DestSize && "Unknown extension!");
1794  return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1795  DestAlign);
1796 }
1797 
1798 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1799  SDLoc dl(Node);
1800  // Create a vector sized/aligned stack slot, store the value to element #0,
1801  // then load the whole vector back out.
1802  SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1803 
1804  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1805  int SPFI = StackPtrFI->getIndex();
1806 
1807  SDValue Ch = DAG.getTruncStore(
1808  DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1809  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1810  Node->getValueType(0).getVectorElementType());
1811  return DAG.getLoad(
1812  Node->getValueType(0), dl, Ch, StackPtr,
1813  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1814 }
1815 
1816 static bool
1818  const TargetLowering &TLI, SDValue &Res) {
1819  unsigned NumElems = Node->getNumOperands();
1820  SDLoc dl(Node);
1821  EVT VT = Node->getValueType(0);
1822 
1823  // Try to group the scalars into pairs, shuffle the pairs together, then
1824  // shuffle the pairs of pairs together, etc. until the vector has
1825  // been built. This will work only if all of the necessary shuffle masks
1826  // are legal.
1827 
1828  // We do this in two phases; first to check the legality of the shuffles,
1829  // and next, assuming that all shuffles are legal, to create the new nodes.
1830  for (int Phase = 0; Phase < 2; ++Phase) {
1832  NewIntermedVals;
1833  for (unsigned i = 0; i < NumElems; ++i) {
1834  SDValue V = Node->getOperand(i);
1835  if (V.isUndef())
1836  continue;
1837 
1838  SDValue Vec;
1839  if (Phase)
1840  Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1841  IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1842  }
1843 
1844  while (IntermedVals.size() > 2) {
1845  NewIntermedVals.clear();
1846  for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1847  // This vector and the next vector are shuffled together (simply to
1848  // append the one to the other).
1849  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1850 
1851  SmallVector<int, 16> FinalIndices;
1852  FinalIndices.reserve(IntermedVals[i].second.size() +
1853  IntermedVals[i+1].second.size());
1854 
1855  int k = 0;
1856  for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1857  ++j, ++k) {
1858  ShuffleVec[k] = j;
1859  FinalIndices.push_back(IntermedVals[i].second[j]);
1860  }
1861  for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1862  ++j, ++k) {
1863  ShuffleVec[k] = NumElems + j;
1864  FinalIndices.push_back(IntermedVals[i+1].second[j]);
1865  }
1866 
1867  SDValue Shuffle;
1868  if (Phase)
1869  Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1870  IntermedVals[i+1].first,
1871  ShuffleVec);
1872  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1873  return false;
1874  NewIntermedVals.push_back(
1875  std::make_pair(Shuffle, std::move(FinalIndices)));
1876  }
1877 
1878  // If we had an odd number of defined values, then append the last
1879  // element to the array of new vectors.
1880  if ((IntermedVals.size() & 1) != 0)
1881  NewIntermedVals.push_back(IntermedVals.back());
1882 
1883  IntermedVals.swap(NewIntermedVals);
1884  }
1885 
1886  assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1887  "Invalid number of intermediate vectors");
1888  SDValue Vec1 = IntermedVals[0].first;
1889  SDValue Vec2;
1890  if (IntermedVals.size() > 1)
1891  Vec2 = IntermedVals[1].first;
1892  else if (Phase)
1893  Vec2 = DAG.getUNDEF(VT);
1894 
1895  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1896  for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1897  ShuffleVec[IntermedVals[0].second[i]] = i;
1898  for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1899  ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1900 
1901  if (Phase)
1902  Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1903  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1904  return false;
1905  }
1906 
1907  return true;
1908 }
1909 
1910 /// Expand a BUILD_VECTOR node on targets that don't
1911 /// support the operation, but do support the resultant vector type.
1912 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1913  unsigned NumElems = Node->getNumOperands();
1914  SDValue Value1, Value2;
1915  SDLoc dl(Node);
1916  EVT VT = Node->getValueType(0);
1917  EVT OpVT = Node->getOperand(0).getValueType();
1918  EVT EltVT = VT.getVectorElementType();
1919 
1920  // If the only non-undef value is the low element, turn this into a
1921  // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1922  bool isOnlyLowElement = true;
1923  bool MoreThanTwoValues = false;
1924  bool isConstant = true;
1925  for (unsigned i = 0; i < NumElems; ++i) {
1926  SDValue V = Node->getOperand(i);
1927  if (V.isUndef())
1928  continue;
1929  if (i > 0)
1930  isOnlyLowElement = false;
1931  if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1932  isConstant = false;
1933 
1934  if (!Value1.getNode()) {
1935  Value1 = V;
1936  } else if (!Value2.getNode()) {
1937  if (V != Value1)
1938  Value2 = V;
1939  } else if (V != Value1 && V != Value2) {
1940  MoreThanTwoValues = true;
1941  }
1942  }
1943 
1944  if (!Value1.getNode())
1945  return DAG.getUNDEF(VT);
1946 
1947  if (isOnlyLowElement)
1948  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1949 
1950  // If all elements are constants, create a load from the constant pool.
1951  if (isConstant) {
1953  for (unsigned i = 0, e = NumElems; i != e; ++i) {
1954  if (ConstantFPSDNode *V =
1955  dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1956  CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1957  } else if (ConstantSDNode *V =
1958  dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1959  if (OpVT==EltVT)
1960  CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1961  else {
1962  // If OpVT and EltVT don't match, EltVT is not legal and the
1963  // element values have been promoted/truncated earlier. Undo this;
1964  // we don't want a v16i8 to become a v16i32 for example.
1965  const ConstantInt *CI = V->getConstantIntValue();
1966  CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1967  CI->getZExtValue()));
1968  }
1969  } else {
1970  assert(Node->getOperand(i).isUndef());
1971  Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1972  CV.push_back(UndefValue::get(OpNTy));
1973  }
1974  }
1975  Constant *CP = ConstantVector::get(CV);
1976  SDValue CPIdx =
1977  DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1978  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1979  return DAG.getLoad(
1980  VT, dl, DAG.getEntryNode(), CPIdx,
1981  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1982  Alignment);
1983  }
1984 
1985  SmallSet<SDValue, 16> DefinedValues;
1986  for (unsigned i = 0; i < NumElems; ++i) {
1987  if (Node->getOperand(i).isUndef())
1988  continue;
1989  DefinedValues.insert(Node->getOperand(i));
1990  }
1991 
1992  if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1993  if (!MoreThanTwoValues) {
1994  SmallVector<int, 8> ShuffleVec(NumElems, -1);
1995  for (unsigned i = 0; i < NumElems; ++i) {
1996  SDValue V = Node->getOperand(i);
1997  if (V.isUndef())
1998  continue;
1999  ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2000  }
2001  if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2002  // Get the splatted value into the low element of a vector register.
2003  SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2004  SDValue Vec2;
2005  if (Value2.getNode())
2006  Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2007  else
2008  Vec2 = DAG.getUNDEF(VT);
2009 
2010  // Return shuffle(LowValVec, undef, <0,0,0,0>)
2011  return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
2012  }
2013  } else {
2014  SDValue Res;
2015  if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2016  return Res;
2017  }
2018  }
2019 
2020  // Otherwise, we can't handle this case efficiently.
2021  return ExpandVectorBuildThroughStack(Node);
2022 }
2023 
2024 // Expand a node into a call to a libcall. If the result value
2025 // does not fit into a register, return the lo part and set the hi part to the
2026 // by-reg argument. If it does fit into a single register, return the result
2027 // and leave the Hi part unset.
2028 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2029  bool isSigned) {
2031  TargetLowering::ArgListEntry Entry;
2032  for (const SDValue &Op : Node->op_values()) {
2033  EVT ArgVT = Op.getValueType();
2034  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2035  Entry.Node = Op;
2036  Entry.Ty = ArgTy;
2037  Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2038  Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2039  Args.push_back(Entry);
2040  }
2041  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2042  TLI.getPointerTy(DAG.getDataLayout()));
2043 
2044  EVT RetVT = Node->getValueType(0);
2045  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2046 
2047  // By default, the input chain to this libcall is the entry node of the
2048  // function. If the libcall is going to be emitted as a tail call then
2049  // TLI.isUsedByReturnOnly will change it to the right chain if the return
2050  // node which is being folded has a non-entry input chain.
2051  SDValue InChain = DAG.getEntryNode();
2052 
2053  // isTailCall may be true since the callee does not reference caller stack
2054  // frame. Check if it's in the right position and that the return types match.
2055  SDValue TCChain = InChain;
2056  const Function &F = DAG.getMachineFunction().getFunction();
2057  bool isTailCall =
2058  TLI.isInTailCallPosition(DAG, Node, TCChain) &&
2059  (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2060  if (isTailCall)
2061  InChain = TCChain;
2062 
2064  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2065  CLI.setDebugLoc(SDLoc(Node))
2066  .setChain(InChain)
2067  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2068  std::move(Args))
2069  .setTailCall(isTailCall)
2070  .setSExtResult(signExtend)
2071  .setZExtResult(!signExtend)
2073 
2074  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2075 
2076  if (!CallInfo.second.getNode()) {
2077  LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump());
2078  // It's a tailcall, return the chain (which is the DAG root).
2079  return DAG.getRoot();
2080  }
2081 
2082  LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump());
2083  return CallInfo.first;
2084 }
2085 
2086 // Expand a node into a call to a libcall. Similar to
2087 // ExpandLibCall except that the first operand is the in-chain.
2088 std::pair<SDValue, SDValue>
2089 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2090  SDNode *Node,
2091  bool isSigned) {
2092  SDValue InChain = Node->getOperand(0);
2093 
2095  TargetLowering::ArgListEntry Entry;
2096  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2097  EVT ArgVT = Node->getOperand(i).getValueType();
2098  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2099  Entry.Node = Node->getOperand(i);
2100  Entry.Ty = ArgTy;
2101  Entry.IsSExt = isSigned;
2102  Entry.IsZExt = !isSigned;
2103  Args.push_back(Entry);
2104  }
2105  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2106  TLI.getPointerTy(DAG.getDataLayout()));
2107 
2108  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2109 
2111  CLI.setDebugLoc(SDLoc(Node))
2112  .setChain(InChain)
2113  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2114  std::move(Args))
2115  .setSExtResult(isSigned)
2116  .setZExtResult(!isSigned);
2117 
2118  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2119 
2120  return CallInfo;
2121 }
2122 
2123 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2124  RTLIB::Libcall Call_F32,
2125  RTLIB::Libcall Call_F64,
2126  RTLIB::Libcall Call_F80,
2127  RTLIB::Libcall Call_F128,
2128  RTLIB::Libcall Call_PPCF128) {
2129  if (Node->isStrictFPOpcode())
2130  Node = DAG.mutateStrictFPToFP(Node);
2131 
2132  RTLIB::Libcall LC;
2133  switch (Node->getSimpleValueType(0).SimpleTy) {
2134  default: llvm_unreachable("Unexpected request for libcall!");
2135  case MVT::f32: LC = Call_F32; break;
2136  case MVT::f64: LC = Call_F64; break;
2137  case MVT::f80: LC = Call_F80; break;
2138  case MVT::f128: LC = Call_F128; break;
2139  case MVT::ppcf128: LC = Call_PPCF128; break;
2140  }
2141  return ExpandLibCall(LC, Node, false);
2142 }
2143 
2144 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2145  RTLIB::Libcall Call_I8,
2146  RTLIB::Libcall Call_I16,
2147  RTLIB::Libcall Call_I32,
2148  RTLIB::Libcall Call_I64,
2149  RTLIB::Libcall Call_I128) {
2150  RTLIB::Libcall LC;
2151  switch (Node->getSimpleValueType(0).SimpleTy) {
2152  default: llvm_unreachable("Unexpected request for libcall!");
2153  case MVT::i8: LC = Call_I8; break;
2154  case MVT::i16: LC = Call_I16; break;
2155  case MVT::i32: LC = Call_I32; break;
2156  case MVT::i64: LC = Call_I64; break;
2157  case MVT::i128: LC = Call_I128; break;
2158  }
2159  return ExpandLibCall(LC, Node, isSigned);
2160 }
2161 
2162 /// Expand the node to a libcall based on first argument type (for instance
2163 /// lround and its variant).
2164 SDValue SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
2165  RTLIB::Libcall Call_F32,
2166  RTLIB::Libcall Call_F64,
2167  RTLIB::Libcall Call_F80,
2168  RTLIB::Libcall Call_F128,
2169  RTLIB::Libcall Call_PPCF128) {
2170  RTLIB::Libcall LC;
2171  switch (Node->getOperand(0).getValueType().getSimpleVT().SimpleTy) {
2172  default: llvm_unreachable("Unexpected request for libcall!");
2173  case MVT::f32: LC = Call_F32; break;
2174  case MVT::f64: LC = Call_F64; break;
2175  case MVT::f80: LC = Call_F80; break;
2176  case MVT::f128: LC = Call_F128; break;
2177  case MVT::ppcf128: LC = Call_PPCF128; break;
2178  }
2179 
2180  return ExpandLibCall(LC, Node, false);
2181 }
2182 
2183 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2184 void
2185 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2186  SmallVectorImpl<SDValue> &Results) {
2187  unsigned Opcode = Node->getOpcode();
2188  bool isSigned = Opcode == ISD::SDIVREM;
2189 
2190  RTLIB::Libcall LC;
2191  switch (Node->getSimpleValueType(0).SimpleTy) {
2192  default: llvm_unreachable("Unexpected request for libcall!");
2193  case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2194  case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2195  case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2196  case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2197  case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2198  }
2199 
2200  // The input chain to this libcall is the entry node of the function.
2201  // Legalizing the call will automatically add the previous call to the
2202  // dependence.
2203  SDValue InChain = DAG.getEntryNode();
2204 
2205  EVT RetVT = Node->getValueType(0);
2206  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2207 
2209  TargetLowering::ArgListEntry Entry;
2210  for (const SDValue &Op : Node->op_values()) {
2211  EVT ArgVT = Op.getValueType();
2212  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2213  Entry.Node = Op;
2214  Entry.Ty = ArgTy;
2215  Entry.IsSExt = isSigned;
2216  Entry.IsZExt = !isSigned;
2217  Args.push_back(Entry);
2218  }
2219 
2220  // Also pass the return address of the remainder.
2221  SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2222  Entry.Node = FIPtr;
2223  Entry.Ty = RetTy->getPointerTo();
2224  Entry.IsSExt = isSigned;
2225  Entry.IsZExt = !isSigned;
2226  Args.push_back(Entry);
2227 
2228  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2229  TLI.getPointerTy(DAG.getDataLayout()));
2230 
2231  SDLoc dl(Node);
2233  CLI.setDebugLoc(dl)
2234  .setChain(InChain)
2235  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2236  std::move(Args))
2237  .setSExtResult(isSigned)
2238  .setZExtResult(!isSigned);
2239 
2240  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2241 
2242  // Remainder is loaded back from the stack frame.
2243  SDValue Rem =
2244  DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2245  Results.push_back(CallInfo.first);
2246  Results.push_back(Rem);
2247 }
2248 
2249 /// Return true if sincos libcall is available.
2250 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2251  RTLIB::Libcall LC;
2252  switch (Node->getSimpleValueType(0).SimpleTy) {
2253  default: llvm_unreachable("Unexpected request for libcall!");
2254  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2255  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2256  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2257  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2258  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2259  }
2260  return TLI.getLibcallName(LC) != nullptr;
2261 }
2262 
2263 /// Only issue sincos libcall if both sin and cos are needed.
2264 static bool useSinCos(SDNode *Node) {
2265  unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2266  ? ISD::FCOS : ISD::FSIN;
2267 
2268  SDValue Op0 = Node->getOperand(0);
2269  for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2270  UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2271  SDNode *User = *UI;
2272  if (User == Node)
2273  continue;
2274  // The other user might have been turned into sincos already.
2275  if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2276  return true;
2277  }
2278  return false;
2279 }
2280 
2281 /// Issue libcalls to sincos to compute sin / cos pairs.
2282 void
2283 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2284  SmallVectorImpl<SDValue> &Results) {
2285  RTLIB::Libcall LC;
2286  switch (Node->getSimpleValueType(0).SimpleTy) {
2287  default: llvm_unreachable("Unexpected request for libcall!");
2288  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2289  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2290  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2291  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2292  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2293  }
2294 
2295  // The input chain to this libcall is the entry node of the function.
2296  // Legalizing the call will automatically add the previous call to the
2297  // dependence.
2298  SDValue InChain = DAG.getEntryNode();
2299 
2300  EVT RetVT = Node->getValueType(0);
2301  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2302 
2304  TargetLowering::ArgListEntry Entry;
2305 
2306  // Pass the argument.
2307  Entry.Node = Node->getOperand(0);
2308  Entry.Ty = RetTy;
2309  Entry.IsSExt = false;
2310  Entry.IsZExt = false;
2311  Args.push_back(Entry);
2312 
2313  // Pass the return address of sin.
2314  SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2315  Entry.Node = SinPtr;
2316  Entry.Ty = RetTy->getPointerTo();
2317  Entry.IsSExt = false;
2318  Entry.IsZExt = false;
2319  Args.push_back(Entry);
2320 
2321  // Also pass the return address of the cos.
2322  SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2323  Entry.Node = CosPtr;
2324  Entry.Ty = RetTy->getPointerTo();
2325  Entry.IsSExt = false;
2326  Entry.IsZExt = false;
2327  Args.push_back(Entry);
2328 
2329  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2330  TLI.getPointerTy(DAG.getDataLayout()));
2331 
2332  SDLoc dl(Node);
2334  CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2335  TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee,
2336  std::move(Args));
2337 
2338  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2339 
2340  Results.push_back(
2341  DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2342  Results.push_back(
2343  DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2344 }
2345 
2346 /// This function is responsible for legalizing a
2347 /// INT_TO_FP operation of the specified operand when the target requests that
2348 /// we expand it. At this point, we know that the result and operand types are
2349 /// legal for the target.
2350 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
2351  EVT DestVT,
2352  const SDLoc &dl) {
2353  EVT SrcVT = Op0.getValueType();
2354 
2355  // TODO: Should any fast-math-flags be set for the created nodes?
2356  LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2357  if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2358  LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2359  "expansion\n");
2360 
2361  // Get the stack frame index of a 8 byte buffer.
2362  SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2363 
2364  // word offset constant for Hi/Lo address computation
2365  SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2366  StackSlot.getValueType());
2367  // set up Hi and Lo (into buffer) address based on endian
2368  SDValue Hi = StackSlot;
2369  SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2370  StackSlot, WordOff);
2371  if (DAG.getDataLayout().isLittleEndian())
2372  std::swap(Hi, Lo);
2373 
2374  // if signed map to unsigned space
2375  SDValue Op0Mapped;
2376  if (isSigned) {
2377  // constant used to invert sign bit (signed to unsigned mapping)
2378  SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2379  Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2380  } else {
2381  Op0Mapped = Op0;
2382  }
2383  // store the lo of the constructed double - based on integer input
2384  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo,
2385  MachinePointerInfo());
2386  // initial hi portion of constructed double
2387  SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2388  // store the hi of the constructed double - biased exponent
2389  SDValue Store2 =
2390  DAG.getStore(Store1, dl, InitialHi, Hi, MachinePointerInfo());
2391  // load the constructed double
2392  SDValue Load =
2393  DAG.getLoad(MVT::f64, dl, Store2, StackSlot, MachinePointerInfo());
2394  // FP constant to bias correct the final result
2395  SDValue Bias = DAG.getConstantFP(isSigned ?
2396  BitsToDouble(0x4330000080000000ULL) :
2397  BitsToDouble(0x4330000000000000ULL),
2398  dl, MVT::f64);
2399  // subtract the bias
2400  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2401  // final result
2402  SDValue Result = DAG.getFPExtendOrRound(Sub, dl, DestVT);
2403  return Result;
2404  }
2405  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2406  // Code below here assumes !isSigned without checking again.
2407 
2408  SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2409 
2410  SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
2411  DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2412  SDValue Zero = DAG.getIntPtrConstant(0, dl),
2413  Four = DAG.getIntPtrConstant(4, dl);
2414  SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2415  SignSet, Four, Zero);
2416 
2417  // If the sign bit of the integer is set, the large number will be treated
2418  // as a negative number. To counteract this, the dynamic code adds an
2419  // offset depending on the data type.
2420  uint64_t FF;
2421  switch (SrcVT.getSimpleVT().SimpleTy) {
2422  default: llvm_unreachable("Unsupported integer type!");
2423  case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2424  case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2425  case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2426  case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2427  }
2428  if (DAG.getDataLayout().isLittleEndian())
2429  FF <<= 32;
2430  Constant *FudgeFactor = ConstantInt::get(
2431  Type::getInt64Ty(*DAG.getContext()), FF);
2432 
2433  SDValue CPIdx =
2434  DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2435  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2436  CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2437  Alignment = std::min(Alignment, 4u);
2438  SDValue FudgeInReg;
2439  if (DestVT == MVT::f32)
2440  FudgeInReg = DAG.getLoad(
2441  MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2442  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2443  Alignment);
2444  else {
2445  SDValue Load = DAG.getExtLoad(
2446  ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2447  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2448  Alignment);
2449  HandleSDNode Handle(Load);
2450  LegalizeOp(Load.getNode());
2451  FudgeInReg = Handle.getValue();
2452  }
2453 
2454  return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2455 }
2456 
2457 /// This function is responsible for legalizing a
2458 /// *INT_TO_FP operation of the specified operand when the target requests that
2459 /// we promote it. At this point, we know that the result and operand types are
2460 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2461 /// operation that takes a larger input.
2462 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
2463  bool isSigned,
2464  const SDLoc &dl) {
2465  // First step, figure out the appropriate *INT_TO_FP operation to use.
2466  EVT NewInTy = LegalOp.getValueType();
2467 
2468  unsigned OpToUse = 0;
2469 
2470  // Scan for the appropriate larger type to use.
2471  while (true) {
2472  NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2473  assert(NewInTy.isInteger() && "Ran out of possibilities!");
2474 
2475  // If the target supports SINT_TO_FP of this type, use it.
2476  if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2477  OpToUse = ISD::SINT_TO_FP;
2478  break;
2479  }
2480  if (isSigned) continue;
2481 
2482  // If the target supports UINT_TO_FP of this type, use it.
2483  if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2484  OpToUse = ISD::UINT_TO_FP;
2485  break;
2486  }
2487 
2488  // Otherwise, try a larger type.
2489  }
2490 
2491  // Okay, we found the operation and type to use. Zero extend our input to the
2492  // desired type then run the operation on it.
2493  return DAG.getNode(OpToUse, dl, DestVT,
2494  DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2495  dl, NewInTy, LegalOp));
2496 }
2497 
2498 /// This function is responsible for legalizing a
2499 /// FP_TO_*INT operation of the specified operand when the target requests that
2500 /// we promote it. At this point, we know that the result and operand types are
2501 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2502 /// operation that returns a larger result.
2503 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
2504  bool isSigned,
2505  const SDLoc &dl) {
2506  // First step, figure out the appropriate FP_TO*INT operation to use.
2507  EVT NewOutTy = DestVT;
2508 
2509  unsigned OpToUse = 0;
2510 
2511  // Scan for the appropriate larger type to use.
2512  while (true) {
2513  NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2514  assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2515 
2516  // A larger signed type can hold all unsigned values of the requested type,
2517  // so using FP_TO_SINT is valid
2518  if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2519  OpToUse = ISD::FP_TO_SINT;
2520  break;
2521  }
2522 
2523  // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2524  if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2525  OpToUse = ISD::FP_TO_UINT;
2526  break;
2527  }
2528 
2529  // Otherwise, try a larger type.
2530  }
2531 
2532  // Okay, we found the operation and type to use.
2533  SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2534 
2535  // Truncate the result of the extended FP_TO_*INT operation to the desired
2536  // size.
2537  return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2538 }
2539 
2540 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2541 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
2542  EVT VT = Op.getValueType();
2543  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2544  unsigned Sz = VT.getScalarSizeInBits();
2545 
2546  SDValue Tmp, Tmp2, Tmp3;
2547 
2548  // If we can, perform BSWAP first and then the mask+swap the i4, then i2
2549  // and finally the i1 pairs.
2550  // TODO: We can easily support i4/i2 legal types if any target ever does.
2551  if (Sz >= 8 && isPowerOf2_32(Sz)) {
2552  // Create the masks - repeating the pattern every byte.
2553  APInt MaskHi4 = APInt::getSplat(Sz, APInt(8, 0xF0));
2554  APInt MaskHi2 = APInt::getSplat(Sz, APInt(8, 0xCC));
2555  APInt MaskHi1 = APInt::getSplat(Sz, APInt(8, 0xAA));
2556  APInt MaskLo4 = APInt::getSplat(Sz, APInt(8, 0x0F));
2557  APInt MaskLo2 = APInt::getSplat(Sz, APInt(8, 0x33));
2558  APInt MaskLo1 = APInt::getSplat(Sz, APInt(8, 0x55));
2559 
2560  // BSWAP if the type is wider than a single byte.
2561  Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2562 
2563  // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4)
2564  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2565  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2566  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT));
2567  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT));
2568  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2569 
2570  // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2)
2571  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2572  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2573  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT));
2574  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT));
2575  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2576 
2577  // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
2578  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2579  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2580  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT));
2581  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT));
2582  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2583  return Tmp;
2584  }
2585 
2586  Tmp = DAG.getConstant(0, dl, VT);
2587  for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2588  if (I < J)
2589  Tmp2 =
2590  DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2591  else
2592  Tmp2 =
2593  DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2594 
2595  APInt Shift(Sz, 1);
2596  Shift <<= J;
2597  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2598  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2599  }
2600 
2601  return Tmp;
2602 }
2603 
2604 /// Open code the operations for BSWAP of the specified operation.
2605 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
2606  EVT VT = Op.getValueType();
2607  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2608  SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2609  switch (VT.getSimpleVT().getScalarType().SimpleTy) {
2610  default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2611  case MVT::i16:
2612  // Use a rotate by 8. This can be further expanded if necessary.
2613  return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2614  case MVT::i32:
2615  Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2616  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2617  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2618  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2619  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2620  DAG.getConstant(0xFF0000, dl, VT));
2621  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2622  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2623  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2624  return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2625  case MVT::i64:
2626  Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2627  Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2628  Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2629  Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2630  Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2631  Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2632  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2633  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2634  Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2635  DAG.getConstant(255ULL<<48, dl, VT));
2636  Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2637  DAG.getConstant(255ULL<<40, dl, VT));
2638  Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2639  DAG.getConstant(255ULL<<32, dl, VT));
2640  Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2641  DAG.getConstant(255ULL<<24, dl, VT));
2642  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2643  DAG.getConstant(255ULL<<16, dl, VT));
2644  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2645  DAG.getConstant(255ULL<<8 , dl, VT));
2646  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2647  Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2648  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2649  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2650  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2651  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2652  return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2653  }
2654 }
2655 
2656 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2657  LLVM_DEBUG(dbgs() << "Trying to expand node\n");
2659  SDLoc dl(Node);
2660  SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2661  bool NeedInvert;
2662  switch (Node->getOpcode()) {
2663  case ISD::ABS:
2664  if (TLI.expandABS(Node, Tmp1, DAG))
2665  Results.push_back(Tmp1);
2666  break;
2667  case ISD::CTPOP:
2668  if (TLI.expandCTPOP(Node, Tmp1, DAG))
2669  Results.push_back(Tmp1);
2670  break;
2671  case ISD::CTLZ:
2672  case ISD::CTLZ_ZERO_UNDEF:
2673  if (TLI.expandCTLZ(Node, Tmp1, DAG))
2674  Results.push_back(Tmp1);
2675  break;
2676  case ISD::CTTZ:
2677  case ISD::CTTZ_ZERO_UNDEF:
2678  if (TLI.expandCTTZ(Node, Tmp1, DAG))
2679  Results.push_back(Tmp1);
2680  break;
2681  case ISD::BITREVERSE:
2682  Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
2683  break;
2684  case ISD::BSWAP:
2685  Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2686  break;
2687  case ISD::FRAMEADDR:
2688  case ISD::RETURNADDR:
2690  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2691  break;
2692  case ISD::EH_DWARF_CFA: {
2693  SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2694  TLI.getPointerTy(DAG.getDataLayout()));
2695  SDValue Offset = DAG.getNode(ISD::ADD, dl,
2696  CfaArg.getValueType(),
2697  DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2698  CfaArg.getValueType()),
2699  CfaArg);
2700  SDValue FA = DAG.getNode(
2701  ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2702  DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2703  Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2704  FA, Offset));
2705  break;
2706  }
2707  case ISD::FLT_ROUNDS_:
2708  Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2709  break;
2710  case ISD::EH_RETURN:
2711  case ISD::EH_LABEL:
2712  case ISD::PREFETCH:
2713  case ISD::VAEND:
2714  case ISD::EH_SJLJ_LONGJMP:
2715  // If the target didn't expand these, there's nothing to do, so just
2716  // preserve the chain and be done.
2717  Results.push_back(Node->getOperand(0));
2718  break;
2719  case ISD::READCYCLECOUNTER:
2720  // If the target didn't expand this, just return 'zero' and preserve the
2721  // chain.
2722  Results.append(Node->getNumValues() - 1,
2723  DAG.getConstant(0, dl, Node->getValueType(0)));
2724  Results.push_back(Node->getOperand(0));
2725  break;
2726  case ISD::EH_SJLJ_SETJMP:
2727  // If the target didn't expand this, just return 'zero' and preserve the
2728  // chain.
2729  Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2730  Results.push_back(Node->getOperand(0));
2731  break;
2732  case ISD::ATOMIC_LOAD: {
2733  // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2734  SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2735  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2736  SDValue Swap = DAG.getAtomicCmpSwap(
2737  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2738  Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2739  cast<AtomicSDNode>(Node)->getMemOperand());
2740  Results.push_back(Swap.getValue(0));
2741  Results.push_back(Swap.getValue(1));
2742  break;
2743  }
2744  case ISD::ATOMIC_STORE: {
2745  // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2746  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2747  cast<AtomicSDNode>(Node)->getMemoryVT(),
2748  Node->getOperand(0),
2749  Node->getOperand(1), Node->getOperand(2),
2750  cast<AtomicSDNode>(Node)->getMemOperand());
2751  Results.push_back(Swap.getValue(1));
2752  break;
2753  }
2755  // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2756  // splits out the success value as a comparison. Expanding the resulting
2757  // ATOMIC_CMP_SWAP will produce a libcall.
2758  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2759  SDValue Res = DAG.getAtomicCmpSwap(
2760  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2761  Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2762  Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2763 
2764  SDValue ExtRes = Res;
2765  SDValue LHS = Res;
2766  SDValue RHS = Node->getOperand(1);
2767 
2768  EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2769  EVT OuterType = Node->getValueType(0);
2770  switch (TLI.getExtendForAtomicOps()) {
2771  case ISD::SIGN_EXTEND:
2772  LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2773  DAG.getValueType(AtomicType));
2774  RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2775  Node->getOperand(2), DAG.getValueType(AtomicType));
2776  ExtRes = LHS;
2777  break;
2778  case ISD::ZERO_EXTEND:
2779  LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2780  DAG.getValueType(AtomicType));
2781  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2782  ExtRes = LHS;
2783  break;
2784  case ISD::ANY_EXTEND:
2785  LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2786  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2787  break;
2788  default:
2789  llvm_unreachable("Invalid atomic op extension");
2790  }
2791 
2792  SDValue Success =
2793  DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2794 
2795  Results.push_back(ExtRes.getValue(0));
2796  Results.push_back(Success);
2797  Results.push_back(Res.getValue(1));
2798  break;
2799  }
2801  ExpandDYNAMIC_STACKALLOC(Node, Results);
2802  break;
2803  case ISD::MERGE_VALUES:
2804  for (unsigned i = 0; i < Node->getNumValues(); i++)
2805  Results.push_back(Node->getOperand(i));
2806  break;
2807  case ISD::UNDEF: {
2808  EVT VT = Node->getValueType(0);
2809  if (VT.isInteger())
2810  Results.push_back(DAG.getConstant(0, dl, VT));
2811  else {
2812  assert(VT.isFloatingPoint() && "Unknown value type!");
2813  Results.push_back(DAG.getConstantFP(0, dl, VT));
2814  }
2815  break;
2816  }
2817  case ISD::STRICT_FP_ROUND:
2818  Tmp1 = EmitStackConvert(Node->getOperand(1),
2819  Node->getValueType(0),
2820  Node->getValueType(0), dl, Node->getOperand(0));
2821  ReplaceNode(Node, Tmp1.getNode());
2822  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_ROUND node\n");
2823  return true;
2824  case ISD::FP_ROUND:
2825  case ISD::BITCAST:
2826  Tmp1 = EmitStackConvert(Node->getOperand(0),
2827  Node->getValueType(0),
2828  Node->getValueType(0), dl);
2829  Results.push_back(Tmp1);
2830  break;
2831  case ISD::STRICT_FP_EXTEND:
2832  Tmp1 = EmitStackConvert(Node->getOperand(1),
2833  Node->getOperand(1).getValueType(),
2834  Node->getValueType(0), dl, Node->getOperand(0));
2835  ReplaceNode(Node, Tmp1.getNode());
2836  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_EXTEND node\n");
2837  return true;
2838  case ISD::FP_EXTEND:
2839  Tmp1 = EmitStackConvert(Node->getOperand(0),
2840  Node->getOperand(0).getValueType(),
2841  Node->getValueType(0), dl);
2842  Results.push_back(Tmp1);
2843  break;
2844  case ISD::SIGN_EXTEND_INREG: {
2845  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2846  EVT VT = Node->getValueType(0);
2847 
2848  // An in-register sign-extend of a boolean is a negation:
2849  // 'true' (1) sign-extended is -1.
2850  // 'false' (0) sign-extended is 0.
2851  // However, we must mask the high bits of the source operand because the
2852  // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2853 
2854  // TODO: Do this for vectors too?
2855  if (ExtraVT.getSizeInBits() == 1) {
2856  SDValue One = DAG.getConstant(1, dl, VT);
2857  SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2858  SDValue Zero = DAG.getConstant(0, dl, VT);
2859  SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2860  Results.push_back(Neg);
2861  break;
2862  }
2863 
2864  // NOTE: we could fall back on load/store here too for targets without
2865  // SRA. However, it is doubtful that any exist.
2866  EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2867  unsigned BitsDiff = VT.getScalarSizeInBits() -
2868  ExtraVT.getScalarSizeInBits();
2869  SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2870  Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2871  Node->getOperand(0), ShiftCst);
2872  Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2873  Results.push_back(Tmp1);
2874  break;
2875  }
2876  case ISD::FP_ROUND_INREG: {
2877  // The only way we can lower this is to turn it into a TRUNCSTORE,
2878  // EXTLOAD pair, targeting a temporary location (a stack slot).
2879 
2880  // NOTE: there is a choice here between constantly creating new stack
2881  // slots and always reusing the same one. We currently always create
2882  // new ones, as reuse may inhibit scheduling.
2883  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2884  Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2885  Node->getValueType(0), dl);
2886  Results.push_back(Tmp1);
2887  break;
2888  }
2889  case ISD::UINT_TO_FP:
2890  if (TLI.expandUINT_TO_FP(Node, Tmp1, DAG)) {
2891  Results.push_back(Tmp1);
2892  break;
2893  }
2895  case ISD::SINT_TO_FP:
2896  Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2897  Node->getOperand(0), Node->getValueType(0), dl);
2898  Results.push_back(Tmp1);
2899  break;
2900  case ISD::FP_TO_SINT:
2901  if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
2902  Results.push_back(Tmp1);
2903  break;
2904  case ISD::FP_TO_UINT:
2905  if (TLI.expandFP_TO_UINT(Node, Tmp1, DAG))
2906  Results.push_back(Tmp1);
2907  break;
2908  case ISD::LROUND:
2909  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LROUND_F32,
2910  RTLIB::LROUND_F64, RTLIB::LROUND_F80,
2911  RTLIB::LROUND_F128,
2912  RTLIB::LROUND_PPCF128));
2913  break;
2914  case ISD::LLROUND:
2915  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LLROUND_F32,
2916  RTLIB::LLROUND_F64, RTLIB::LLROUND_F80,
2917  RTLIB::LLROUND_F128,
2918  RTLIB::LLROUND_PPCF128));
2919  break;
2920  case ISD::VAARG:
2921  Results.push_back(DAG.expandVAArg(Node));
2922  Results.push_back(Results[0].getValue(1));
2923  break;
2924  case ISD::VACOPY:
2925  Results.push_back(DAG.expandVACopy(Node));
2926  break;
2928  if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2929  // This must be an access of the only element. Return it.
2930  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2931  Node->getOperand(0));
2932  else
2933  Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2934  Results.push_back(Tmp1);
2935  break;
2937  Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2938  break;
2939  case ISD::INSERT_SUBVECTOR:
2940  Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2941  break;
2942  case ISD::CONCAT_VECTORS:
2943  Results.push_back(ExpandVectorBuildThroughStack(Node));
2944  break;
2945  case ISD::SCALAR_TO_VECTOR:
2946  Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2947  break;
2949  Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2950  Node->getOperand(1),
2951  Node->getOperand(2), dl));
2952  break;
2953  case ISD::VECTOR_SHUFFLE: {
2954  SmallVector<int, 32> NewMask;
2955  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2956 
2957  EVT VT = Node->getValueType(0);
2958  EVT EltVT = VT.getVectorElementType();
2959  SDValue Op0 = Node->getOperand(0);
2960  SDValue Op1 = Node->getOperand(1);
2961  if (!TLI.isTypeLegal(EltVT)) {
2962  EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2963 
2964  // BUILD_VECTOR operands are allowed to be wider than the element type.
2965  // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
2966  // it.
2967  if (NewEltVT.bitsLT(EltVT)) {
2968  // Convert shuffle node.
2969  // If original node was v4i64 and the new EltVT is i32,
2970  // cast operands to v8i32 and re-build the mask.
2971 
2972  // Calculate new VT, the size of the new VT should be equal to original.
2973  EVT NewVT =
2974  EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2975  VT.getSizeInBits() / NewEltVT.getSizeInBits());
2976  assert(NewVT.bitsEq(VT));
2977 
2978  // cast operands to new VT
2979  Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2980  Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2981 
2982  // Convert the shuffle mask
2983  unsigned int factor =
2985 
2986  // EltVT gets smaller
2987  assert(factor > 0);
2988 
2989  for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2990  if (Mask[i] < 0) {
2991  for (unsigned fi = 0; fi < factor; ++fi)
2992  NewMask.push_back(Mask[i]);
2993  }
2994  else {
2995  for (unsigned fi = 0; fi < factor; ++fi)
2996  NewMask.push_back(Mask[i]*factor+fi);
2997  }
2998  }
2999  Mask = NewMask;
3000  VT = NewVT;
3001  }
3002  EltVT = NewEltVT;
3003  }
3004  unsigned NumElems = VT.getVectorNumElements();
3006  for (unsigned i = 0; i != NumElems; ++i) {
3007  if (Mask[i] < 0) {
3008  Ops.push_back(DAG.getUNDEF(EltVT));
3009  continue;
3010  }
3011  unsigned Idx = Mask[i];
3012  if (Idx < NumElems)
3013  Ops.push_back(DAG.getNode(
3014  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3015  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3016  else
3017  Ops.push_back(DAG.getNode(
3018  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3019  DAG.getConstant(Idx - NumElems, dl,
3020  TLI.getVectorIdxTy(DAG.getDataLayout()))));
3021  }
3022 
3023  Tmp1 = DAG.getBuildVector(VT, dl, Ops);
3024  // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3025  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3026  Results.push_back(Tmp1);
3027  break;
3028  }
3029  case ISD::EXTRACT_ELEMENT: {
3030  EVT OpTy = Node->getOperand(0).getValueType();
3031  if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3032  // 1 -> Hi
3033  Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3034  DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3035  TLI.getShiftAmountTy(
3036  Node->getOperand(0).getValueType(),
3037  DAG.getDataLayout())));
3038  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3039  } else {
3040  // 0 -> Lo
3041  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3042  Node->getOperand(0));
3043  }
3044  Results.push_back(Tmp1);
3045  break;
3046  }
3047  case ISD::STACKSAVE:
3048  // Expand to CopyFromReg if the target set
3049  // StackPointerRegisterToSaveRestore.
3050  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3051  Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3052  Node->getValueType(0)));
3053  Results.push_back(Results[0].getValue(1));
3054  } else {
3055  Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3056  Results.push_back(Node->getOperand(0));
3057  }
3058  break;
3059  case ISD::STACKRESTORE:
3060  // Expand to CopyToReg if the target set
3061  // StackPointerRegisterToSaveRestore.
3062  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3063  Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3064  Node->getOperand(1)));
3065  } else {
3066  Results.push_back(Node->getOperand(0));
3067  }
3068  break;
3070  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3071  Results.push_back(Results[0].getValue(0));
3072  break;
3073  case ISD::FCOPYSIGN:
3074  Results.push_back(ExpandFCOPYSIGN(Node));
3075  break;
3076  case ISD::FNEG:
3077  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3078  Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3079  // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3080  Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3081  Node->getOperand(0));
3082  Results.push_back(Tmp1);
3083  break;
3084  case ISD::FABS:
3085  Results.push_back(ExpandFABS(Node));
3086  break;
3087  case ISD::SMIN:
3088  case ISD::SMAX:
3089  case ISD::UMIN:
3090  case ISD::UMAX: {
3091  // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3092  ISD::CondCode Pred;
3093  switch (Node->getOpcode()) {
3094  default: llvm_unreachable("How did we get here?");
3095  case ISD::SMAX: Pred = ISD::SETGT; break;
3096  case ISD::SMIN: Pred = ISD::SETLT; break;
3097  case ISD::UMAX: Pred = ISD::SETUGT; break;
3098  case ISD::UMIN: Pred = ISD::SETULT; break;
3099  }
3100  Tmp1 = Node->getOperand(0);
3101  Tmp2 = Node->getOperand(1);
3102  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3103  Results.push_back(Tmp1);
3104  break;
3105  }
3106  case ISD::FMINNUM:
3107  case ISD::FMAXNUM: {
3108  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Node, DAG))
3109  Results.push_back(Expanded);
3110  break;
3111  }
3112  case ISD::FSIN:
3113  case ISD::FCOS: {
3114  EVT VT = Node->getValueType(0);
3115  // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3116  // fcos which share the same operand and both are used.
3117  if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3118  isSinCosLibcallAvailable(Node, TLI))
3119  && useSinCos(Node)) {
3120  SDVTList VTs = DAG.getVTList(VT, VT);
3121  Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3122  if (Node->getOpcode() == ISD::FCOS)
3123  Tmp1 = Tmp1.getValue(1);
3124  Results.push_back(Tmp1);
3125  }
3126  break;
3127  }
3128  case ISD::FMAD:
3129  llvm_unreachable("Illegal fmad should never be formed");
3130 
3131  case ISD::FP16_TO_FP:
3132  if (Node->getValueType(0) != MVT::f32) {
3133  // We can extend to types bigger than f32 in two steps without changing
3134  // the result. Since "f16 -> f32" is much more commonly available, give
3135  // CodeGen the option of emitting that before resorting to a libcall.
3136  SDValue Res =
3137  DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3138  Results.push_back(
3139  DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3140  }
3141  break;
3142  case ISD::FP_TO_FP16:
3143  LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3144  if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3145  SDValue Op = Node->getOperand(0);
3146  MVT SVT = Op.getSimpleValueType();
3147  if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3148  TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3149  // Under fastmath, we can expand this node into a fround followed by
3150  // a float-half conversion.
3151  SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3152  DAG.getIntPtrConstant(0, dl));
3153  Results.push_back(
3154  DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3155  }
3156  }
3157  break;
3158  case ISD::ConstantFP: {
3159  ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3160  // Check to see if this FP immediate is already legal.
3161  // If this is a legal constant, turn it into a TargetConstantFP node.
3162  if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0),
3163  DAG.getMachineFunction().getFunction().hasOptSize()))
3164  Results.push_back(ExpandConstantFP(CFP, true));
3165  break;
3166  }
3167  case ISD::Constant: {
3168  ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3169  Results.push_back(ExpandConstant(CP));
3170  break;
3171  }
3172  case ISD::FSUB: {
3173  EVT VT = Node->getValueType(0);
3174  if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3175  TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3176  const SDNodeFlags Flags = Node->getFlags();
3177  Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3178  Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3179  Results.push_back(Tmp1);
3180  }
3181  break;
3182  }
3183  case ISD::SUB: {
3184  EVT VT = Node->getValueType(0);
3185  assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3186  TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3187  "Don't know how to expand this subtraction!");
3188  Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3189  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3190  VT));
3191  Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3192  Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3193  break;
3194  }
3195  case ISD::UREM:
3196  case ISD::SREM: {
3197  EVT VT = Node->getValueType(0);
3198  bool isSigned = Node->getOpcode() == ISD::SREM;
3199  unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3200  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3201  Tmp2 = Node->getOperand(0);
3202  Tmp3 = Node->getOperand(1);
3203  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3204  SDVTList VTs = DAG.getVTList(VT, VT);
3205  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3206  Results.push_back(Tmp1);
3207  } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3208  // X % Y -> X-X/Y*Y
3209  Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3210  Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3211  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3212  Results.push_back(Tmp1);
3213  }
3214  break;
3215  }
3216  case ISD::UDIV:
3217  case ISD::SDIV: {
3218  bool isSigned = Node->getOpcode() == ISD::SDIV;
3219  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3220  EVT VT = Node->getValueType(0);
3221  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3222  SDVTList VTs = DAG.getVTList(VT, VT);
3223  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3224  Node->getOperand(1));
3225  Results.push_back(Tmp1);
3226  }
3227  break;
3228  }
3229  case ISD::MULHU:
3230  case ISD::MULHS: {
3231  unsigned ExpandOpcode =
3233  EVT VT = Node->getValueType(0);
3234  SDVTList VTs = DAG.getVTList(VT, VT);
3235 
3236  Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3237  Node->getOperand(1));
3238  Results.push_back(Tmp1.getValue(1));
3239  break;
3240  }
3241  case ISD::UMUL_LOHI:
3242  case ISD::SMUL_LOHI: {
3243  SDValue LHS = Node->getOperand(0);
3244  SDValue RHS = Node->getOperand(1);
3245  MVT VT = LHS.getSimpleValueType();
3246  unsigned MULHOpcode =
3248 
3249  if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3250  Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3251  Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3252  break;
3253  }
3254 
3255  SmallVector<SDValue, 4> Halves;
3256  EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3257  assert(TLI.isTypeLegal(HalfType));
3258  if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3259  HalfType, DAG,
3261  for (unsigned i = 0; i < 2; ++i) {
3262  SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3263  SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3264  SDValue Shift = DAG.getConstant(
3265  HalfType.getScalarSizeInBits(), dl,
3266  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3267  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3268  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3269  }
3270  break;
3271  }
3272  break;
3273  }
3274  case ISD::MUL: {
3275  EVT VT = Node->getValueType(0);
3276  SDVTList VTs = DAG.getVTList(VT, VT);
3277  // See if multiply or divide can be lowered using two-result operations.
3278  // We just need the low half of the multiply; try both the signed
3279  // and unsigned forms. If the target supports both SMUL_LOHI and
3280  // UMUL_LOHI, form a preference by checking which forms of plain
3281  // MULH it supports.
3282  bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3283  bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3284  bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3285  bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3286  unsigned OpToUse = 0;
3287  if (HasSMUL_LOHI && !HasMULHS) {
3288  OpToUse = ISD::SMUL_LOHI;
3289  } else if (HasUMUL_LOHI && !HasMULHU) {
3290  OpToUse = ISD::UMUL_LOHI;
3291  } else if (HasSMUL_LOHI) {
3292  OpToUse = ISD::SMUL_LOHI;
3293  } else if (HasUMUL_LOHI) {
3294  OpToUse = ISD::UMUL_LOHI;
3295  }
3296  if (OpToUse) {
3297  Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3298  Node->getOperand(1)));
3299  break;
3300  }
3301 
3302  SDValue Lo, Hi;
3303  EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3304  if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3305  TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3306  TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3307  TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3308  TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3310  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3311  Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3312  SDValue Shift =
3313  DAG.getConstant(HalfType.getSizeInBits(), dl,
3314  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3315  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3316  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3317  }
3318  break;
3319  }
3320  case ISD::FSHL:
3321  case ISD::FSHR:
3322  if (TLI.expandFunnelShift(Node, Tmp1, DAG))
3323  Results.push_back(Tmp1);
3324  break;
3325  case ISD::ROTL:
3326  case ISD::ROTR:
3327  if (TLI.expandROT(Node, Tmp1, DAG))
3328  Results.push_back(Tmp1);
3329  break;
3330  case ISD::SADDSAT:
3331  case ISD::UADDSAT:
3332  case ISD::SSUBSAT:
3333  case ISD::USUBSAT:
3334  Results.push_back(TLI.expandAddSubSat(Node, DAG));
3335  break;
3336  case ISD::SMULFIX:
3337  case ISD::UMULFIX:
3338  Results.push_back(TLI.expandFixedPointMul(Node, DAG));
3339  break;
3340  case ISD::ADDCARRY:
3341  case ISD::SUBCARRY: {
3342  SDValue LHS = Node->getOperand(0);
3343  SDValue RHS = Node->getOperand(1);
3344  SDValue Carry = Node->getOperand(2);
3345 
3346  bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;
3347 
3348  // Initial add of the 2 operands.
3349  unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
3350  EVT VT = LHS.getValueType();
3351  SDValue Sum = DAG.getNode(Op, dl, VT, LHS, RHS);
3352 
3353  // Initial check for overflow.
3354  EVT CarryType = Node->getValueType(1);
3355  EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3356  ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3357  SDValue Overflow = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3358 
3359  // Add of the sum and the carry.
3360  SDValue CarryExt =
3361  DAG.getZeroExtendInReg(DAG.getZExtOrTrunc(Carry, dl, VT), dl, MVT::i1);
3362  SDValue Sum2 = DAG.getNode(Op, dl, VT, Sum, CarryExt);
3363 
3364  // Second check for overflow. If we are adding, we can only overflow if the
3365  // initial sum is all 1s ang the carry is set, resulting in a new sum of 0.
3366  // If we are subtracting, we can only overflow if the initial sum is 0 and
3367  // the carry is set, resulting in a new sum of all 1s.
3368  SDValue Zero = DAG.getConstant(0, dl, VT);
3369  SDValue Overflow2 =
3370  IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ)
3371  : DAG.getSetCC(dl, SetCCType, Sum, Zero, ISD::SETEQ);
3372  Overflow2 = DAG.getNode(ISD::AND, dl, SetCCType, Overflow2,
3373  DAG.getZExtOrTrunc(Carry, dl, SetCCType));
3374 
3375  SDValue ResultCarry =
3376  DAG.getNode(ISD::OR, dl, SetCCType, Overflow, Overflow2);
3377 
3378  Results.push_back(Sum2);
3379  Results.push_back(DAG.getBoolExtOrTrunc(ResultCarry, dl, CarryType, VT));
3380  break;
3381  }
3382  case ISD::SADDO:
3383  case ISD::SSUBO: {
3384  SDValue LHS = Node->getOperand(0);
3385  SDValue RHS = Node->getOperand(1);
3386  bool IsAdd = Node->getOpcode() == ISD::SADDO;
3387 
3388  SDValue Sum = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
3389  LHS.getValueType(), LHS, RHS);
3390  Results.push_back(Sum);
3391 
3392  EVT ResultType = Node->getValueType(1);
3393  EVT OType = getSetCCResultType(Node->getValueType(0));
3394 
3395  // If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
3396  unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT;
3397  if (TLI.isOperationLegalOrCustom(OpcSat, LHS.getValueType())) {
3398  SDValue Sat = DAG.getNode(OpcSat, dl, LHS.getValueType(), LHS, RHS);
3399  SDValue SetCC = DAG.getSetCC(dl, OType, Sum, Sat, ISD::SETNE);
3400  Results.push_back(
3401  DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3402  break;
3403  }
3404 
3405  SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3406 
3407  // LHSSign -> LHS >= 0
3408  // RHSSign -> RHS >= 0
3409  // SumSign -> Sum >= 0
3410  //
3411  // Add:
3412  // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3413  // Sub:
3414  // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3415  SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3416  SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3417  SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3418  IsAdd ? ISD::SETEQ : ISD::SETNE);
3419 
3420  SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3421  SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3422 
3423  SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3424  Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3425  break;
3426  }
3427  case ISD::UADDO:
3428  case ISD::USUBO: {
3429  SDValue LHS = Node->getOperand(0);
3430  SDValue RHS = Node->getOperand(1);
3431  bool IsAdd = Node->getOpcode() == ISD::UADDO;
3432 
3433  // If ADD/SUBCARRY is legal, use that instead.
3434  unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;
3435  if (TLI.isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) {
3436  SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1));
3437  SDValue NodeCarry = DAG.getNode(OpcCarry, dl, Node->getVTList(),
3438  { LHS, RHS, CarryIn });
3439  Results.push_back(SDValue(NodeCarry.getNode(), 0));
3440  Results.push_back(SDValue(NodeCarry.getNode(), 1));
3441  break;
3442  }
3443 
3444  SDValue Sum = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
3445  LHS.getValueType(), LHS, RHS);
3446  Results.push_back(Sum);
3447 
3448  EVT ResultType = Node->getValueType(1);
3449  EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3450  ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3451  SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3452 
3453  Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3454  break;
3455  }
3456  case ISD::UMULO:
3457  case ISD::SMULO: {
3458  SDValue Result, Overflow;
3459  if (TLI.expandMULO(Node, Result, Overflow, DAG)) {
3460  Results.push_back(Result);
3461  Results.push_back(Overflow);
3462  }
3463  break;
3464  }
3465  case ISD::BUILD_PAIR: {
3466  EVT PairTy = Node->getValueType(0);
3467  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3468  Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3469  Tmp2 = DAG.getNode(
3470  ISD::SHL, dl, PairTy, Tmp2,
3471  DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3472  TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3473  Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3474  break;
3475  }
3476  case ISD::SELECT:
3477  Tmp1 = Node->getOperand(0);
3478  Tmp2 = Node->getOperand(1);
3479  Tmp3 = Node->getOperand(2);
3480  if (Tmp1.getOpcode() == ISD::SETCC) {
3481  Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3482  Tmp2, Tmp3,
3483  cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3484  } else {
3485  Tmp1 = DAG.getSelectCC(dl, Tmp1,
3486  DAG.getConstant(0, dl, Tmp1.getValueType()),
3487  Tmp2, Tmp3, ISD::SETNE);
3488  }
3489  Results.push_back(Tmp1);
3490  break;
3491  case ISD::BR_JT: {
3492  SDValue Chain = Node->getOperand(0);
3493  SDValue Table = Node->getOperand(1);
3494  SDValue Index = Node->getOperand(2);
3495 
3496  const DataLayout &TD = DAG.getDataLayout();
3497  EVT PTy = TLI.getPointerTy(TD);
3498 
3499  unsigned EntrySize =
3500  DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3501 
3502  // For power-of-two jumptable entry sizes convert multiplication to a shift.
3503  // This transformation needs to be done here since otherwise the MIPS
3504  // backend will end up emitting a three instruction multiply sequence
3505  // instead of a single shift and MSP430 will call a runtime function.
3506  if (llvm::isPowerOf2_32(EntrySize))
3507  Index = DAG.getNode(
3508  ISD::SHL, dl, Index.getValueType(), Index,
3509  DAG.getConstant(llvm::Log2_32(EntrySize), dl, Index.getValueType()));
3510  else
3511  Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3512  DAG.getConstant(EntrySize, dl, Index.getValueType()));
3513  SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3514  Index, Table);
3515 
3516  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3517  SDValue LD = DAG.getExtLoad(
3518  ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3519  MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3520  Addr = LD;
3521  if (TLI.isJumpTableRelative()) {
3522  // For PIC, the sequence is:
3523  // BRIND(load(Jumptable + index) + RelocBase)
3524  // RelocBase can be JumpTable, GOT or some sort of global base.
3525  Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3526  TLI.getPICJumpTableRelocBase(Table, DAG));
3527  }
3528 
3529  Tmp1 = TLI.expandIndirectJTBranch(dl, LD.getValue(1), Addr, DAG);
3530  Results.push_back(Tmp1);
3531  break;
3532  }
3533  case ISD::BRCOND:
3534  // Expand brcond's setcc into its constituent parts and create a BR_CC
3535  // Node.
3536  Tmp1 = Node->getOperand(0);
3537  Tmp2 = Node->getOperand(1);
3538  if (Tmp2.getOpcode() == ISD::SETCC) {
3539  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3540  Tmp1, Tmp2.getOperand(2),
3541  Tmp2.getOperand(0), Tmp2.getOperand(1),
3542  Node->getOperand(2));
3543  } else {
3544  // We test only the i1 bit. Skip the AND if UNDEF or another AND.
3545  if (Tmp2.isUndef() ||
3546  (Tmp2.getOpcode() == ISD::AND &&
3547  isa<ConstantSDNode>(Tmp2.getOperand(1)) &&
3548  cast<ConstantSDNode>(Tmp2.getOperand(1))->getZExtValue() == 1))
3549  Tmp3 = Tmp2;
3550  else
3551  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3552  DAG.getConstant(1, dl, Tmp2.getValueType()));
3553  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3554  DAG.getCondCode(ISD::SETNE), Tmp3,
3555  DAG.getConstant(0, dl, Tmp3.getValueType()),
3556  Node->getOperand(2));
3557  }
3558  Results.push_back(Tmp1);
3559  break;
3560  case ISD::SETCC: {
3561  Tmp1 = Node->getOperand(0);
3562  Tmp2 = Node->getOperand(1);
3563  Tmp3 = Node->getOperand(2);
3564  bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3565  Tmp3, NeedInvert, dl);
3566 
3567  if (Legalized) {
3568  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3569  // condition code, create a new SETCC node.
3570  if (Tmp3.getNode())
3571  Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3572  Tmp1, Tmp2, Tmp3);
3573 
3574  // If we expanded the SETCC by inverting the condition code, then wrap
3575  // the existing SETCC in a NOT to restore the intended condition.
3576  if (NeedInvert)
3577  Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3578 
3579  Results.push_back(Tmp1);
3580  break;
3581  }
3582 
3583  // Otherwise, SETCC for the given comparison type must be completely
3584  // illegal; expand it into a SELECT_CC.
3585  EVT VT = Node->getValueType(0);
3586  int TrueValue;
3587  switch (TLI.getBooleanContents(Tmp1.getValueType())) {
3590  TrueValue = 1;
3591  break;
3593  TrueValue = -1;
3594  break;
3595  }
3596  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3597  DAG.getConstant(TrueValue, dl, VT),
3598  DAG.getConstant(0, dl, VT),
3599  Tmp3);
3600  Results.push_back(Tmp1);
3601  break;
3602  }
3603  case ISD::SELECT_CC: {
3604  Tmp1 = Node->getOperand(0); // LHS
3605  Tmp2 = Node->getOperand(1); // RHS
3606  Tmp3 = Node->getOperand(2); // True
3607  Tmp4 = Node->getOperand(3); // False
3608  EVT VT = Node->getValueType(0);
3609  SDValue CC = Node->getOperand(4);
3610  ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3611 
3612  if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) {
3613  // If the condition code is legal, then we need to expand this
3614  // node using SETCC and SELECT.
3615  EVT CmpVT = Tmp1.getValueType();
3616  assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3617  "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3618  "expanded.");
3619  EVT CCVT =
3620  TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3621  SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3622  Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3623  break;
3624  }
3625 
3626  // SELECT_CC is legal, so the condition code must not be.
3627  bool Legalized = false;
3628  // Try to legalize by inverting the condition. This is for targets that
3629  // might support an ordered version of a condition, but not the unordered
3630  // version (or vice versa).
3631  ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3632  Tmp1.getValueType().isInteger());
3633  if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
3634  // Use the new condition code and swap true and false
3635  Legalized = true;
3636  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3637  } else {
3638  // If The inverse is not legal, then try to swap the arguments using
3639  // the inverse condition code.
3640  ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3641  if (TLI.isCondCodeLegalOrCustom(SwapInvCC, Tmp1.getSimpleValueType())) {
3642  // The swapped inverse condition is legal, so swap true and false,
3643  // lhs and rhs.
3644  Legalized = true;
3645  Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3646  }
3647  }
3648 
3649  if (!Legalized) {
3650  Legalized = LegalizeSetCCCondCode(
3651  getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3652  dl);
3653 
3654  assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3655 
3656  // If we expanded the SETCC by inverting the condition code, then swap
3657  // the True/False operands to match.
3658  if (NeedInvert)
3659  std::swap(Tmp3, Tmp4);
3660 
3661  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3662  // condition code, create a new SELECT_CC node.
3663  if (CC.getNode()) {
3664  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3665  Tmp1, Tmp2, Tmp3, Tmp4, CC);
3666  } else {
3667  Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3668  CC = DAG.getCondCode(ISD::SETNE);
3669  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3670  Tmp2, Tmp3, Tmp4, CC);
3671  }
3672  }
3673  Results.push_back(Tmp1);
3674  break;
3675  }
3676  case ISD::BR_CC: {
3677  Tmp1 = Node->getOperand(0); // Chain
3678  Tmp2 = Node->getOperand(2); // LHS
3679  Tmp3 = Node->getOperand(3); // RHS
3680  Tmp4 = Node->getOperand(1); // CC
3681 
3682  bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3683  Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3684  (void)Legalized;
3685  assert(Legalized && "Can't legalize BR_CC with legal condition!");
3686 
3687  assert(!NeedInvert && "Don't know how to invert BR_CC!");
3688 
3689  // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3690  // node.
3691  if (Tmp4.getNode()) {
3692  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3693  Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3694  } else {
3695  Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3696  Tmp4 = DAG.getCondCode(ISD::SETNE);
3697  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3698  Tmp2, Tmp3, Node->getOperand(4));
3699  }
3700  Results.push_back(Tmp1);
3701  break;
3702  }
3703  case ISD::BUILD_VECTOR:
3704  Results.push_back(ExpandBUILD_VECTOR(Node));
3705  break;
3706  case ISD::SRA:
3707  case ISD::SRL:
3708  case ISD::SHL: {
3709  // Scalarize vector SRA/SRL/SHL.
3710  EVT VT = Node->getValueType(0);
3711  assert(VT.isVector() && "Unable to legalize non-vector shift");
3712  assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3713  unsigned NumElem = VT.getVectorNumElements();
3714 
3715  SmallVector<SDValue, 8> Scalars;
3716  for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3717  SDValue Ex = DAG.getNode(
3718  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3719  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3720  SDValue Sh = DAG.getNode(
3721  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3722  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3723  Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3724  VT.getScalarType(), Ex, Sh));
3725  }
3726 
3727  SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
3728  ReplaceNode(SDValue(Node, 0), Result);
3729  break;
3730  }
3731  case ISD::VECREDUCE_FADD:
3732  case ISD::VECREDUCE_FMUL:
3733  case ISD::VECREDUCE_ADD:
3734  case ISD::VECREDUCE_MUL:
3735  case ISD::VECREDUCE_AND:
3736  case ISD::VECREDUCE_OR:
3737  case ISD::VECREDUCE_XOR:
3738  case ISD::VECREDUCE_SMAX:
3739  case ISD::VECREDUCE_SMIN:
3740  case ISD::VECREDUCE_UMAX:
3741  case ISD::VECREDUCE_UMIN:
3742  case ISD::VECREDUCE_FMAX:
3743  case ISD::VECREDUCE_FMIN:
3744  Results.push_back(TLI.expandVecReduce(Node, DAG));
3745  break;
3747  case ISD::GlobalAddress:
3748  case ISD::GlobalTLSAddress:
3749  case ISD::ExternalSymbol:
3750  case ISD::ConstantPool:
3751  case ISD::JumpTable:
3754  case ISD::INTRINSIC_VOID:
3755  // FIXME: Custom lowering for these operations shouldn't return null!
3756  break;
3757  }
3758 
3759  // Replace the original node with the legalized result.
3760  if (Results.empty()) {
3761  LLVM_DEBUG(dbgs() << "Cannot expand node\n");
3762  return false;
3763  }
3764 
3765  LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
3766  ReplaceNode(Node, Results.data());
3767  return true;
3768 }
3769 
3770 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3771  LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
3773  SDLoc dl(Node);
3774  // FIXME: Check flags on the node to see if we can use a finite call.
3775  bool CanUseFiniteLibCall = TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath;
3776  unsigned Opc = Node->getOpcode();
3777  switch (Opc) {
3778  case ISD::ATOMIC_FENCE: {
3779  // If the target didn't lower this, lower it to '__sync_synchronize()' call
3780  // FIXME: handle "fence singlethread" more efficiently.
3782 
3784  CLI.setDebugLoc(dl)
3785  .setChain(Node->getOperand(0))
3786  .setLibCallee(
3787  CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3788  DAG.getExternalSymbol("__sync_synchronize",
3789  TLI.getPointerTy(DAG.getDataLayout())),
3790  std::move(Args));
3791 
3792  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3793 
3794  Results.push_back(CallResult.second);
3795  break;
3796  }
3797  // By default, atomic intrinsics are marked Legal and lowered. Targets
3798  // which don't support them directly, however, may want libcalls, in which
3799  // case they mark them Expand, and we get here.
3800  case ISD::ATOMIC_SWAP:
3801  case ISD::ATOMIC_LOAD_ADD:
3802  case ISD::ATOMIC_LOAD_SUB:
3803  case ISD::ATOMIC_LOAD_AND:
3804  case ISD::ATOMIC_LOAD_CLR:
3805  case ISD::ATOMIC_LOAD_OR:
3806  case ISD::ATOMIC_LOAD_XOR:
3807  case ISD::ATOMIC_LOAD_NAND:
3808  case ISD::ATOMIC_LOAD_MIN:
3809  case ISD::ATOMIC_LOAD_MAX:
3810  case ISD::ATOMIC_LOAD_UMIN:
3811  case ISD::ATOMIC_LOAD_UMAX:
3812  case ISD::ATOMIC_CMP_SWAP: {
3813  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3814  RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
3815  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3816 
3817  std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3818  Results.push_back(Tmp.first);
3819  Results.push_back(Tmp.second);
3820  break;
3821  }
3822  case ISD::TRAP: {
3823  // If this operation is not supported, lower it to 'abort()' call
3826  CLI.setDebugLoc(dl)
3827  .setChain(Node->getOperand(0))
3828  .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3829  DAG.getExternalSymbol(
3830  "abort", TLI.getPointerTy(DAG.getDataLayout())),
3831  std::move(Args));
3832  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3833 
3834  Results.push_back(CallResult.second);
3835  break;
3836  }
3837  case ISD::FMINNUM:
3838  case ISD::STRICT_FMINNUM:
3839  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3840  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3841  RTLIB::FMIN_PPCF128));
3842  break;
3843  case ISD::FMAXNUM:
3844  case ISD::STRICT_FMAXNUM:
3845  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3846  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3847  RTLIB::FMAX_PPCF128));
3848  break;
3849  case ISD::FSQRT:
3850  case ISD::STRICT_FSQRT:
3851  Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3852  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3853  RTLIB::SQRT_PPCF128));
3854  break;
3855  case ISD::FCBRT:
3856  Results.push_back(ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
3857  RTLIB::CBRT_F80, RTLIB::CBRT_F128,
3858  RTLIB::CBRT_PPCF128));
3859  break;
3860  case ISD::FSIN:
3861  case ISD::STRICT_FSIN:
3862  Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3863  RTLIB::SIN_F80, RTLIB::SIN_F128,
3864  RTLIB::SIN_PPCF128));
3865  break;
3866  case ISD::FCOS:
3867  case ISD::STRICT_FCOS:
3868  Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3869  RTLIB::COS_F80, RTLIB::COS_F128,
3870  RTLIB::COS_PPCF128));
3871  break;
3872  case ISD::FSINCOS:
3873  // Expand into sincos libcall.
3874  ExpandSinCosLibCall(Node, Results);
3875  break;
3876  case ISD::FLOG:
3877  case ISD::STRICT_FLOG:
3878  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log_finite))
3879  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_FINITE_F32,
3880  RTLIB::LOG_FINITE_F64,
3881  RTLIB::LOG_FINITE_F80,
3882  RTLIB::LOG_FINITE_F128,
3883  RTLIB::LOG_FINITE_PPCF128));
3884  else
3885  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3886  RTLIB::LOG_F80, RTLIB::LOG_F128,
3887  RTLIB::LOG_PPCF128));
3888  break;
3889  case ISD::FLOG2:
3890  case ISD::STRICT_FLOG2:
3891  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log2_finite))
3892  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_FINITE_F32,
3893  RTLIB::LOG2_FINITE_F64,
3894  RTLIB::LOG2_FINITE_F80,
3895  RTLIB::LOG2_FINITE_F128,
3896  RTLIB::LOG2_FINITE_PPCF128));
3897  else
3898  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3899  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3900  RTLIB::LOG2_PPCF128));
3901  break;
3902  case ISD::FLOG10:
3903  case ISD::STRICT_FLOG10:
3904  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log10_finite))
3905  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_FINITE_F32,
3906  RTLIB::LOG10_FINITE_F64,
3907  RTLIB::LOG10_FINITE_F80,
3908  RTLIB::LOG10_FINITE_F128,
3909  RTLIB::LOG10_FINITE_PPCF128));
3910  else
3911  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3912  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3913  RTLIB::LOG10_PPCF128));
3914  break;
3915  case ISD::FEXP:
3916  case ISD::STRICT_FEXP:
3917  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp_finite))
3918  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_FINITE_F32,
3919  RTLIB::EXP_FINITE_F64,
3920  RTLIB::EXP_FINITE_F80,
3921  RTLIB::EXP_FINITE_F128,
3922  RTLIB::EXP_FINITE_PPCF128));
3923  else
3924  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3925  RTLIB::EXP_F80, RTLIB::EXP_F128,
3926  RTLIB::EXP_PPCF128));
3927  break;
3928  case ISD::FEXP2:
3929  case ISD::STRICT_FEXP2:
3930  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp2_finite))
3931  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_FINITE_F32,
3932  RTLIB::EXP2_FINITE_F64,
3933  RTLIB::EXP2_FINITE_F80,
3934  RTLIB::EXP2_FINITE_F128,
3935  RTLIB::EXP2_FINITE_PPCF128));
3936  else
3937  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3938  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3939  RTLIB::EXP2_PPCF128));
3940  break;
3941  case ISD::FTRUNC:
3942  case ISD::STRICT_FTRUNC:
3943  Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3944  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3945  RTLIB::TRUNC_PPCF128));
3946  break;
3947  case ISD::FFLOOR:
3948  case ISD::STRICT_FFLOOR:
3949  Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3950  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3951  RTLIB::FLOOR_PPCF128));
3952  break;
3953  case ISD::FCEIL:
3954  case ISD::STRICT_FCEIL:
3955  Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3956  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3957  RTLIB::CEIL_PPCF128));
3958  break;
3959  case ISD::FRINT:
3960  case ISD::STRICT_FRINT:
3961  Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3962  RTLIB::RINT_F80, RTLIB::RINT_F128,
3963  RTLIB::RINT_PPCF128));
3964  break;
3965  case ISD::FNEARBYINT:
3967  Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3968  RTLIB::NEARBYINT_F64,
3969  RTLIB::NEARBYINT_F80,
3970  RTLIB::NEARBYINT_F128,
3971  RTLIB::NEARBYINT_PPCF128));
3972  break;
3973  case ISD::FROUND:
3974  case ISD::STRICT_FROUND:
3975  Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3976  RTLIB::ROUND_F64,
3977  RTLIB::ROUND_F80,
3978  RTLIB::ROUND_F128,
3979  RTLIB::ROUND_PPCF128));
3980  break;
3981  case ISD::FPOWI:
3982  case ISD::STRICT_FPOWI:
3983  Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3984  RTLIB::POWI_F80, RTLIB::POWI_F128,
3985  RTLIB::POWI_PPCF128));
3986  break;
3987  case ISD::FPOW:
3988  case ISD::STRICT_FPOW:
3989  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_pow_finite))
3990  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_FINITE_F32,
3991  RTLIB::POW_FINITE_F64,
3992  RTLIB::POW_FINITE_F80,
3993  RTLIB::POW_FINITE_F128,
3994  RTLIB::POW_FINITE_PPCF128));
3995  else
3996  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3997  RTLIB::POW_F80, RTLIB::POW_F128,
3998  RTLIB::POW_PPCF128));
3999  break;
4000  case ISD::FDIV:
4001  Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
4002  RTLIB::DIV_F80, RTLIB::DIV_F128,
4003  RTLIB::DIV_PPCF128));
4004  break;
4005  case ISD::FREM:
4006  case ISD::STRICT_FREM:
4007  Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
4008  RTLIB::REM_F80, RTLIB::REM_F128,
4009  RTLIB::REM_PPCF128));
4010  break;
4011  case ISD::FMA:
4012  case ISD::STRICT_FMA:
4013  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4014  RTLIB::FMA_F80, RTLIB::FMA_F128,
4015  RTLIB::FMA_PPCF128));
4016  break;
4017  case ISD::FADD:
4018  Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4019  RTLIB::ADD_F80, RTLIB::ADD_F128,
4020  RTLIB::ADD_PPCF128));
4021  break;
4022  case ISD::FMUL:
4023  Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4024  RTLIB::MUL_F80, RTLIB::MUL_F128,
4025  RTLIB::MUL_PPCF128));
4026  break;
4027  case ISD::FP16_TO_FP:
4028  if (Node->getValueType(0) == MVT::f32) {
4029  Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4030  }
4031  break;
4032  case ISD::FP_TO_FP16: {
4033  RTLIB::Libcall LC =
4035  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4036  Results.push_back(ExpandLibCall(LC, Node, false));
4037  break;
4038  }
4039  case ISD::FSUB:
4040  Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4041  RTLIB::SUB_F80, RTLIB::SUB_F128,
4042  RTLIB::SUB_PPCF128));
4043  break;
4044  case ISD::SREM:
4045  Results.push_back(ExpandIntLibCall(Node, true,
4046  RTLIB::SREM_I8,
4047  RTLIB::SREM_I16, RTLIB::SREM_I32,
4048  RTLIB::SREM_I64, RTLIB::SREM_I128));
4049  break;
4050  case ISD::UREM:
4051  Results.push_back(ExpandIntLibCall(Node, false,
4052  RTLIB::UREM_I8,
4053  RTLIB::UREM_I16, RTLIB::UREM_I32,
4054  RTLIB::UREM_I64, RTLIB::UREM_I128));
4055  break;
4056  case ISD::SDIV:
4057  Results.push_back(ExpandIntLibCall(Node, true,
4058  RTLIB::SDIV_I8,
4059  RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4060  RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4061  break;
4062  case ISD::UDIV:
4063  Results.push_back(ExpandIntLibCall(Node, false,
4064  RTLIB::UDIV_I8,
4065  RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4066  RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4067  break;
4068  case ISD::SDIVREM:
4069  case ISD::UDIVREM:
4070  // Expand into divrem libcall
4071  ExpandDivRemLibCall(Node, Results);
4072  break;
4073  case ISD::MUL:
4074  Results.push_back(ExpandIntLibCall(Node, false,
4075  RTLIB::MUL_I8,
4076  RTLIB::MUL_I16, RTLIB::MUL_I32,
4077  RTLIB::MUL_I64, RTLIB::MUL_I128));
4078  break;
4079  case ISD::CTLZ_ZERO_UNDEF:
4080  switch (Node->getSimpleValueType(0).SimpleTy) {
4081  default:
4082  llvm_unreachable("LibCall explicitly requested, but not available");
4083  case MVT::i32:
4084  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false));
4085  break;
4086  case MVT::i64:
4087  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false));
4088  break;
4089  case MVT::i128:
4090  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false));
4091  break;
4092  }
4093  break;
4094  }
4095 
4096  // Replace the original node with the legalized result.
4097  if (!Results.empty()) {
4098  LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
4099  ReplaceNode(Node, Results.data());
4100  } else
4101  LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
4102 }
4103 
4104 // Determine the vector type to use in place of an original scalar element when
4105 // promoting equally sized vectors.
4107  MVT EltVT, MVT NewEltVT) {
4108  unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4109  MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4110  assert(TLI.isTypeLegal(MidVT) && "unexpected");
4111  return MidVT;
4112 }
4113 
4114 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4115  LLVM_DEBUG(dbgs() << "Trying to promote node\n");
4117  MVT OVT = Node->getSimpleValueType(0);
4118  if (Node->getOpcode() == ISD::UINT_TO_FP ||
4119  Node->getOpcode() == ISD::SINT_TO_FP ||
4120  Node->getOpcode() == ISD::SETCC ||
4121  Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4122  Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4123  OVT = Node->getOperand(0).getSimpleValueType();
4124  }
4125  if (Node->getOpcode() == ISD::BR_CC)
4126  OVT = Node->getOperand(2).getSimpleValueType();
4127  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4128  SDLoc dl(Node);
4129  SDValue Tmp1, Tmp2, Tmp3;
4130  switch (Node->getOpcode()) {
4131  case ISD::CTTZ:
4132  case ISD::CTTZ_ZERO_UNDEF:
4133  case ISD::CTLZ:
4134  case ISD::CTLZ_ZERO_UNDEF:
4135  case ISD::CTPOP:
4136  // Zero extend the argument.
4137  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4138  if (Node->getOpcode() == ISD::CTTZ) {
4139  // The count is the same in the promoted type except if the original
4140  // value was zero. This can be handled by setting the bit just off
4141  // the top of the original type.
4142  auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
4143  OVT.getSizeInBits());
4144  Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4145  DAG.getConstant(TopBit, dl, NVT));
4146  }
4147  // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4148  // already the correct result.
4149  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4150  if (Node->getOpcode() == ISD::CTLZ ||
4151  Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4152  // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4153  Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4154  DAG.getConstant(NVT.getSizeInBits() -
4155  OVT.getSizeInBits(), dl, NVT));
4156  }
4157  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4158  break;
4159  case ISD::BITREVERSE:
4160  case ISD::BSWAP: {
4161  unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4162  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4163  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4164  Tmp1 = DAG.getNode(
4165  ISD::SRL, dl, NVT, Tmp1,
4166  DAG.getConstant(DiffBits, dl,
4167  TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4168 
4169  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4170  break;
4171  }
4172  case ISD::FP_TO_UINT:
4173  case ISD::FP_TO_SINT:
4174  Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4175  Node->getOpcode() == ISD::FP_TO_SINT, dl);
4176  Results.push_back(Tmp1);
4177  break;
4178  case ISD::UINT_TO_FP:
4179  case ISD::SINT_TO_FP:
4180  Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4181  Node->getOpcode() == ISD::SINT_TO_FP, dl);
4182  Results.push_back(Tmp1);
4183  break;
4184  case ISD::VAARG: {
4185  SDValue Chain = Node->getOperand(0); // Get the chain.
4186  SDValue Ptr = Node->getOperand(1); // Get the pointer.
4187 
4188  unsigned TruncOp;
4189  if (OVT.isVector()) {
4190  TruncOp = ISD::BITCAST;
4191  } else {
4192  assert(OVT.isInteger()
4193  && "VAARG promotion is supported only for vectors or integer types");
4194  TruncOp = ISD::TRUNCATE;
4195  }
4196 
4197  // Perform the larger operation, then convert back
4198  Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4199  Node->getConstantOperandVal(3));
4200  Chain = Tmp1.getValue(1);
4201 
4202  Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4203 
4204  // Modified the chain result - switch anything that used the old chain to
4205  // use the new one.
4206  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4207  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4208  if (UpdatedNodes) {
4209  UpdatedNodes->insert(Tmp2.getNode());
4210  UpdatedNodes->insert(Chain.getNode());
4211  }
4212  ReplacedNode(Node);
4213  break;
4214  }
4215  case ISD::MUL:
4216  case ISD::SDIV:
4217  case ISD::SREM:
4218  case ISD::UDIV:
4219  case ISD::UREM:
4220  case ISD::AND:
4221  case ISD::OR:
4222  case ISD::XOR: {
4223  unsigned ExtOp, TruncOp;
4224  if (OVT.isVector()) {
4225  ExtOp = ISD::BITCAST;
4226  TruncOp = ISD::BITCAST;
4227  } else {
4228  assert(OVT.isInteger() && "Cannot promote logic operation");
4229 
4230  switch (Node->getOpcode()) {
4231  default:
4232  ExtOp = ISD::ANY_EXTEND;
4233  break;
4234  case ISD::SDIV:
4235  case ISD::SREM:
4236  ExtOp = ISD::SIGN_EXTEND;
4237  break;
4238  case ISD::UDIV:
4239  case ISD::UREM:
4240  ExtOp = ISD::ZERO_EXTEND;
4241  break;
4242  }
4243  TruncOp = ISD::TRUNCATE;
4244  }
4245  // Promote each of the values to the new type.
4246  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4247  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4248  // Perform the larger operation, then convert back
4249  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4250  Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4251  break;
4252  }
4253  case ISD::UMUL_LOHI:
4254  case ISD::SMUL_LOHI: {
4255  // Promote to a multiply in a wider integer type.
4256  unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4257  : ISD::SIGN_EXTEND;
4258  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4259  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4260  Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4261 
4262  auto &DL = DAG.getDataLayout();
4263  unsigned OriginalSize = OVT.getScalarSizeInBits();
4264  Tmp2 = DAG.getNode(
4265  ISD::SRL, dl, NVT, Tmp1,
4266  DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4267  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4268  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4269  break;
4270  }
4271  case ISD::SELECT: {
4272  unsigned ExtOp, TruncOp;
4273  if (Node->getValueType(0).isVector() ||
4274  Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4275  ExtOp = ISD::BITCAST;
4276  TruncOp = ISD::BITCAST;
4277  } else if (Node->getValueType(0).isInteger()) {
4278  ExtOp = ISD::ANY_EXTEND;
4279  TruncOp = ISD::TRUNCATE;
4280  } else {
4281  ExtOp = ISD::FP_EXTEND;
4282  TruncOp = ISD::FP_ROUND;
4283  }
4284  Tmp1 = Node->getOperand(0);
4285  // Promote each of the values to the new type.
4286  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4287  Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4288  // Perform the larger operation, then round down.
4289  Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4290  if (TruncOp != ISD::FP_ROUND)
4291  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4292  else
4293  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4294  DAG.getIntPtrConstant(0, dl));
4295  Results.push_back(Tmp1);
4296  break;
4297  }
4298  case ISD::VECTOR_SHUFFLE: {
4299  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4300 
4301  // Cast the two input vectors.
4302  Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4303  Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4304 
4305  // Convert the shuffle mask to the right # elements.
4306  Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4307  Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4308  Results.push_back(Tmp1);
4309  break;
4310  }
4311  case ISD::SETCC: {
4312  unsigned ExtOp = ISD::FP_EXTEND;
4313  if (NVT.isInteger()) {
4314  ISD::CondCode CCCode =
4315  cast<CondCodeSDNode>(Node->getOperand(2))->get();
4317  }
4318  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4319  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4320  Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4321  Tmp1, Tmp2, Node->getOperand(2)));
4322  break;
4323  }
4324  case ISD::BR_CC: {
4325  unsigned ExtOp = ISD::FP_EXTEND;
4326  if (NVT.isInteger()) {
4327  ISD::CondCode CCCode =
4328  cast<CondCodeSDNode>(Node->getOperand(1))->get();
4330  }
4331  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4332  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4333  Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4334  Node->getOperand(0), Node->getOperand(1),
4335  Tmp1, Tmp2, Node->getOperand(4)));
4336  break;
4337  }
4338  case ISD::FADD:
4339  case ISD::FSUB:
4340  case ISD::FMUL:
4341  case ISD::FDIV:
4342  case ISD::FREM:
4343  case ISD::FMINNUM:
4344  case ISD::FMAXNUM:
4345  case ISD::FPOW:
4346  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4347  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4348  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4349  Node->getFlags());
4350  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4351  Tmp3, DAG.getIntPtrConstant(0, dl)));
4352  break;
4353  case ISD::FMA:
4354  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4355  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4356  Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4357  Results.push_back(
4358  DAG.getNode(ISD::FP_ROUND, dl, OVT,
4359  DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4360  DAG.getIntPtrConstant(0, dl)));
4361  break;
4362  case ISD::FCOPYSIGN:
4363  case ISD::FPOWI: {
4364  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4365  Tmp2 = Node->getOperand(1);
4366  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4367 
4368  // fcopysign doesn't change anything but the sign bit, so
4369  // (fp_round (fcopysign (fpext a), b))
4370  // is as precise as
4371  // (fp_round (fpext a))
4372  // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4373  const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4374  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4375  Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4376  break;
4377  }
4378  case ISD::FFLOOR:
4379  case ISD::FCEIL:
4380  case ISD::FRINT:
4381  case ISD::FNEARBYINT:
4382  case ISD::FROUND:
4383  case ISD::FTRUNC:
4384  case ISD::FNEG:
4385  case ISD::FSQRT:
4386  case ISD::FSIN:
4387  case ISD::FCOS:
4388  case ISD::FLOG:
4389  case ISD::FLOG2:
4390  case ISD::FLOG10:
4391  case ISD::FABS:
4392  case ISD::FEXP:
4393  case ISD::FEXP2:
4394  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4395  Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4396  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4397  Tmp2, DAG.getIntPtrConstant(0, dl)));
4398  break;
4399  case ISD::BUILD_VECTOR: {
4400  MVT EltVT = OVT.getVectorElementType();
4401  MVT NewEltVT = NVT.getVectorElementType();
4402 
4403  // Handle bitcasts to a different vector type with the same total bit size
4404  //
4405  // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4406  // =>
4407  // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4408 
4409  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4410  "Invalid promote type for build_vector");
4411  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4412 
4413  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4414 
4415  SmallVector<SDValue, 8> NewOps;
4416  for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4417  SDValue Op = Node->getOperand(I);
4418  NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4419  }
4420 
4421  SDLoc SL(Node);
4422  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4423  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4424  Results.push_back(CvtVec);
4425  break;
4426  }
4427  case ISD::EXTRACT_VECTOR_ELT: {
4428  MVT EltVT = OVT.getVectorElementType();
4429  MVT NewEltVT = NVT.getVectorElementType();
4430 
4431  // Handle bitcasts to a different vector type with the same total bit size.
4432  //
4433  // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4434  // =>
4435  // v4i32:castx = bitcast x:v2i64
4436  //
4437  // i64 = bitcast
4438  // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4439  // (i32 (extract_vector_elt castx, (2 * y + 1)))
4440  //
4441 
4442  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4443  "Invalid promote type for extract_vector_elt");
4444  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4445 
4446  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4447  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4448 
4449  SDValue Idx = Node->getOperand(1);
4450  EVT IdxVT = Idx.getValueType();
4451  SDLoc SL(Node);
4452  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4453  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4454 
4455  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4456 
4457  SmallVector<SDValue, 8> NewOps;
4458  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4459  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4460  SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4461 
4462  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4463  CastVec, TmpIdx);
4464  NewOps.push_back(Elt);
4465  }
4466 
4467  SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4468  Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4469  break;
4470  }
4471  case ISD::INSERT_VECTOR_ELT: {
4472  MVT EltVT = OVT.getVectorElementType();
4473  MVT NewEltVT = NVT.getVectorElementType();
4474 
4475  // Handle bitcasts to a different vector type with the same total bit size
4476  //
4477  // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4478  // =>
4479  // v4i32:castx = bitcast x:v2i64
4480  // v2i32:casty = bitcast y:i64
4481  //
4482  // v2i64 = bitcast
4483  // (v4i32 insert_vector_elt
4484  // (v4i32 insert_vector_elt v4i32:castx,
4485  // (extract_vector_elt casty, 0), 2 * z),
4486  // (extract_vector_elt casty, 1), (2 * z + 1))
4487 
4488  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4489  "Invalid promote type for insert_vector_elt");
4490  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4491 
4492  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4493  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4494 
4495  SDValue Val = Node->getOperand(1);
4496  SDValue Idx = Node->getOperand(2);
4497  EVT IdxVT = Idx.getValueType();
4498  SDLoc SL(Node);
4499 
4500  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4501  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4502 
4503  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4504  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4505 
4506  SDValue NewVec = CastVec;
4507  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4508  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4509  SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4510 
4511  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4512  CastVal, IdxOffset);
4513 
4514  NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4515  NewVec, Elt, InEltIdx);
4516  }
4517 
4518  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4519  break;
4520  }
4521  case ISD::SCALAR_TO_VECTOR: {
4522  MVT EltVT = OVT.getVectorElementType();
4523  MVT NewEltVT = NVT.getVectorElementType();
4524 
4525  // Handle bitcasts to different vector type with the same total bit size.
4526  //
4527  // e.g. v2i64 = scalar_to_vector x:i64
4528  // =>
4529  // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4530  //
4531 
4532  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4533  SDValue Val = Node->getOperand(0);
4534  SDLoc SL(Node);
4535 
4536  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4537  SDValue Undef = DAG.getUNDEF(MidVT);
4538 
4539  SmallVector<SDValue, 8> NewElts;
4540  NewElts.push_back(CastVal);
4541  for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4542  NewElts.push_back(Undef);
4543 
4544  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4545  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4546  Results.push_back(CvtVec);
4547  break;
4548  }
4549  case ISD::ATOMIC_SWAP: {
4550  AtomicSDNode *AM = cast<AtomicSDNode>(Node);
4551  SDLoc SL(Node);
4552  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
4553  assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
4554  "unexpected promotion type");
4555  assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
4556  "unexpected atomic_swap with illegal type");
4557 
4558  SDValue NewAtomic
4559  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, NVT,
4560  DAG.getVTList(NVT, MVT::Other),
4561  { AM->getChain(), AM->getBasePtr(), CastVal },
4562  AM->getMemOperand());
4563  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
4564  Results.push_back(NewAtomic.getValue(1));
4565  break;
4566  }
4567  }
4568 
4569  // Replace the original node with the legalized result.
4570  if (!Results.empty()) {
4571  LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
4572  ReplaceNode(Node, Results.data());
4573  } else
4574  LLVM_DEBUG(dbgs() << "Could not promote node\n");
4575 }
4576 
4577 /// This is the entry point for the file.
4579  AssignTopologicalOrder();
4580 
4581  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4582  // Use a delete listener to remove nodes which were deleted during
4583  // legalization from LegalizeNodes. This is needed to handle the situation
4584  // where a new node is allocated by the object pool to the same address of a
4585  // previously deleted node.
4586  DAGNodeDeletedListener DeleteListener(
4587  *this,
4588  [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(N); });
4589 
4590  SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4591 
4592  // Visit all the nodes. We start in topological order, so that we see
4593  // nodes with their original operands intact. Legalization can produce
4594  // new nodes which may themselves need to be legalized. Iterate until all
4595  // nodes have been legalized.
4596  while (true) {
4597  bool AnyLegalized = false;
4598  for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4599  --NI;
4600 
4601  SDNode *N = &*NI;
4602  if (N->use_empty() && N != getRoot().getNode()) {
4603  ++NI;
4604  DeleteNode(N);
4605  continue;
4606  }
4607 
4608  if (LegalizedNodes.insert(N).second) {
4609  AnyLegalized = true;
4610  Legalizer.LegalizeOp(N);
4611 
4612  if (N->use_empty() && N != getRoot().getNode()) {
4613  ++NI;
4614  DeleteNode(N);
4615  }
4616  }
4617  }
4618  if (!AnyLegalized)
4619  break;
4620 
4621  }
4622 
4623  // Remove dead nodes now.
4624  RemoveDeadNodes();
4625 }
4626 
4628  SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4629  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4630  SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4631 
4632  // Directly insert the node in question, and legalize it. This will recurse
4633  // as needed through operands.
4634  LegalizedNodes.insert(N);
4635  Legalizer.LegalizeOp(N);
4636 
4637  return LegalizedNodes.count(N);
4638 }
bool LegalizeOp(SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target ...
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:790
static Constant * getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced=false)
Definition: Constants.cpp:1688
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:590
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:557
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:908
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:617
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isInteger() const
Return true if this is an integer or a vector integer type.
static bool isConstant(const MachineInstr &MI)
bool isUndef() const
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:295
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:377
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:673
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static MVT getVectorVT(MVT VT, unsigned NumElements)
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:386
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
const SDValue & getVal() const
bool isVector() const
Return true if this is a vector value type.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void push_back(const T &Elt)
Definition: SmallVector.h:211
const SDValue & getValue() const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:725
SDVTList getVTList() const
This file contains the declarations for metadata subclasses.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
const SDValue & getBasePtr() const
unsigned getVectorNumElements() const
const SDValue & getChain() const
Function Alias Analysis Results
static MVT getPromotedVectorElementType(const TargetLowering &TLI, MVT EltVT, MVT NewEltVT)
unsigned getAlignment() const
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:828
unsigned second
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:288
static uint32_t Concat[]
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:176
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:403
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Same for subtraction.
Definition: ISDOpcodes.h:253
void reserve(size_type N)
Definition: SmallVector.h:369
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:372
The address of the GOT.
Definition: ISDOpcodes.h:65
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:807
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:454
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
const ConstantFP * getConstantFPValue() const
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isTruncatingStore() const
Return true if the op does a truncation before store.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode *> &Visited, SmallVectorImpl< const SDNode *> &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
Definition: ISDOpcodes.h:113
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:475
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Shift and rotation operations.
Definition: ISDOpcodes.h:429
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:412
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:651
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
op_iterator op_end() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
Definition: ISDOpcodes.h:565
SimpleValueType SimpleTy
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence, and carry arbitrary information that target might want to know.
Definition: ISDOpcodes.h:739
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA)...
Definition: ISDOpcodes.h:95
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:836
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
This is an SDNode representing atomic operations.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:721
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:90
unsigned getSizeInBits() const
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:497
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here...
Definition: ISDOpcodes.h:117
falkor hwpf fix Falkor HW Prefetch Fix Late Phase
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:404
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool bitsLT(MVT VT) const
Return true if this has less bits than VT.
ArrayRef - Repr