Go to the source code of this file.
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#define | DEBUG_TYPE "legalizevectorops" |
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#define | DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) case ISD::STRICT_##DAGN: |
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#define | BEGIN_REGISTER_VP_SDNODE(VPID, LEGALPOS, ...) |
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#define | DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) case ISD::STRICT_##DAGN: |
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◆ BEGIN_REGISTER_VP_SDNODE
#define BEGIN_REGISTER_VP_SDNODE |
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VPID, |
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LEGALPOS, |
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... |
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) |
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Value: case ISD::VPID: { \
EVT LegalizeVT = LEGALPOS < 0 ?
Node->getValueType(-(1 + LEGALPOS)) \
:
Node->getOperand(LEGALPOS).getValueType(); \
if (ISD::VPID == ISD::VP_SETCC) { \
Action = TLI.getCondCodeAction(CCCode, LegalizeVT.
getSimpleVT()); \
if (Action != TargetLowering::Legal) \
break; \
} \
Action = TLI.getOperationAction(
Node->getOpcode(), LegalizeVT); \
} break;
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
◆ DAG_INSTRUCTION [1/2]
#define DAG_INSTRUCTION |
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NAME, |
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NARG, |
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ROUND_MODE, |
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INTRINSIC, |
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DAGN |
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| case ISD::STRICT_##DAGN: |
◆ DAG_INSTRUCTION [2/2]
#define DAG_INSTRUCTION |
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NAME, |
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NARG, |
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ROUND_MODE, |
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INTRINSIC, |
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DAGN |
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| case ISD::STRICT_##DAGN: |
◆ DEBUG_TYPE
#define DEBUG_TYPE "legalizevectorops" |
◆ createBSWAPShuffleMask()