LLVM  9.0.0svn
LegalizeVectorOps.cpp
Go to the documentation of this file.
1 //===- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAG::LegalizeVectors method.
10 //
11 // The vector legalizer looks for vector operations which might need to be
12 // scalarized and legalizes them. This is a separate step from Legalize because
13 // scalarizing can introduce illegal types. For example, suppose we have an
14 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
15 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
16 // operation, which introduces nodes with the illegal type i64 which must be
17 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
18 // the operation must be unrolled, which introduces nodes with the illegal
19 // type i8 which must be promoted.
20 //
21 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
22 // or operations that happen to take a vector which are custom-lowered;
23 // the legalization for such operations never produces nodes
24 // with illegal types, so it's okay to put off legalizing them until
25 // SelectionDAG::Legalize runs.
26 //
27 //===----------------------------------------------------------------------===//
28 
29 #include "llvm/ADT/APInt.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/Compiler.h"
44 #include <cassert>
45 #include <cstdint>
46 #include <iterator>
47 #include <utility>
48 
49 using namespace llvm;
50 
51 #define DEBUG_TYPE "legalizevectorops"
52 
53 namespace {
54 
55 class VectorLegalizer {
56  SelectionDAG& DAG;
57  const TargetLowering &TLI;
58  bool Changed = false; // Keep track of whether anything changed
59 
60  /// For nodes that are of legal width, and that have more than one use, this
61  /// map indicates what regularized operand to use. This allows us to avoid
62  /// legalizing the same thing more than once.
64 
65  /// Adds a node to the translation cache.
66  void AddLegalizedOperand(SDValue From, SDValue To) {
67  LegalizedNodes.insert(std::make_pair(From, To));
68  // If someone requests legalization of the new node, return itself.
69  if (From != To)
70  LegalizedNodes.insert(std::make_pair(To, To));
71  }
72 
73  /// Legalizes the given node.
74  SDValue LegalizeOp(SDValue Op);
75 
76  /// Assuming the node is legal, "legalize" the results.
77  SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
78 
79  /// Implements unrolling a VSETCC.
80  SDValue UnrollVSETCC(SDValue Op);
81 
82  /// Implement expand-based legalization of vector operations.
83  ///
84  /// This is just a high-level routine to dispatch to specific code paths for
85  /// operations to legalize them.
86  SDValue Expand(SDValue Op);
87 
88  /// Implements expansion for FP_TO_UINT; falls back to UnrollVectorOp if
89  /// FP_TO_SINT isn't legal.
90  SDValue ExpandFP_TO_UINT(SDValue Op);
91 
92  /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
93  /// SINT_TO_FLOAT and SHR on vectors isn't legal.
94  SDValue ExpandUINT_TO_FLOAT(SDValue Op);
95 
96  /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
97  SDValue ExpandSEXTINREG(SDValue Op);
98 
99  /// Implement expansion for ANY_EXTEND_VECTOR_INREG.
100  ///
101  /// Shuffles the low lanes of the operand into place and bitcasts to the proper
102  /// type. The contents of the bits in the extended part of each element are
103  /// undef.
104  SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
105 
106  /// Implement expansion for SIGN_EXTEND_VECTOR_INREG.
107  ///
108  /// Shuffles the low lanes of the operand into place, bitcasts to the proper
109  /// type, then shifts left and arithmetic shifts right to introduce a sign
110  /// extension.
111  SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
112 
113  /// Implement expansion for ZERO_EXTEND_VECTOR_INREG.
114  ///
115  /// Shuffles the low lanes of the operand into place and blends zeros into
116  /// the remaining lanes, finally bitcasting to the proper type.
117  SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
118 
119  /// Implement expand-based legalization of ABS vector operations.
120  /// If following expanding is legal/custom then do it:
121  /// (ABS x) --> (XOR (ADD x, (SRA x, sizeof(x)-1)), (SRA x, sizeof(x)-1))
122  /// else unroll the operation.
123  SDValue ExpandABS(SDValue Op);
124 
125  /// Expand bswap of vectors into a shuffle if legal.
126  SDValue ExpandBSWAP(SDValue Op);
127 
128  /// Implement vselect in terms of XOR, AND, OR when blend is not
129  /// supported by the target.
130  SDValue ExpandVSELECT(SDValue Op);
131  SDValue ExpandSELECT(SDValue Op);
132  SDValue ExpandLoad(SDValue Op);
133  SDValue ExpandStore(SDValue Op);
134  SDValue ExpandFNEG(SDValue Op);
135  SDValue ExpandFSUB(SDValue Op);
136  SDValue ExpandBITREVERSE(SDValue Op);
137  SDValue ExpandCTPOP(SDValue Op);
138  SDValue ExpandCTLZ(SDValue Op);
139  SDValue ExpandCTTZ(SDValue Op);
140  SDValue ExpandFunnelShift(SDValue Op);
141  SDValue ExpandROT(SDValue Op);
142  SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);
143  SDValue ExpandMULO(SDValue Op);
144  SDValue ExpandAddSubSat(SDValue Op);
145  SDValue ExpandFixedPointMul(SDValue Op);
146  SDValue ExpandStrictFPOp(SDValue Op);
147 
148  /// Implements vector promotion.
149  ///
150  /// This is essentially just bitcasting the operands to a different type and
151  /// bitcasting the result back to the original type.
152  SDValue Promote(SDValue Op);
153 
154  /// Implements [SU]INT_TO_FP vector promotion.
155  ///
156  /// This is a [zs]ext of the input operand to a larger integer type.
157  SDValue PromoteINT_TO_FP(SDValue Op);
158 
159  /// Implements FP_TO_[SU]INT vector promotion of the result type.
160  ///
161  /// It is promoted to a larger integer type. The result is then
162  /// truncated back to the original type.
163  SDValue PromoteFP_TO_INT(SDValue Op);
164 
165 public:
166  VectorLegalizer(SelectionDAG& dag) :
167  DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
168 
169  /// Begin legalizer the vector operations in the DAG.
170  bool Run();
171 };
172 
173 } // end anonymous namespace
174 
175 bool VectorLegalizer::Run() {
176  // Before we start legalizing vector nodes, check if there are any vectors.
177  bool HasVectors = false;
178  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
179  E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
180  // Check if the values of the nodes contain vectors. We don't need to check
181  // the operands because we are going to check their values at some point.
182  for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
183  J != E; ++J)
184  HasVectors |= J->isVector();
185 
186  // If we found a vector node we can start the legalization.
187  if (HasVectors)
188  break;
189  }
190 
191  // If this basic block has no vectors then no need to legalize vectors.
192  if (!HasVectors)
193  return false;
194 
195  // The legalize process is inherently a bottom-up recursive process (users
196  // legalize their uses before themselves). Given infinite stack space, we
197  // could just start legalizing on the root and traverse the whole graph. In
198  // practice however, this causes us to run out of stack space on large basic
199  // blocks. To avoid this problem, compute an ordering of the nodes where each
200  // node is only legalized after all of its operands are legalized.
201  DAG.AssignTopologicalOrder();
202  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
203  E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
204  LegalizeOp(SDValue(&*I, 0));
205 
206  // Finally, it's possible the root changed. Get the new root.
207  SDValue OldRoot = DAG.getRoot();
208  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
209  DAG.setRoot(LegalizedNodes[OldRoot]);
210 
211  LegalizedNodes.clear();
212 
213  // Remove dead nodes now.
214  DAG.RemoveDeadNodes();
215 
216  return Changed;
217 }
218 
219 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
220  // Generic legalization: just pass the operand through.
221  for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
222  AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
223  return Result.getValue(Op.getResNo());
224 }
225 
226 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
227  // Note that LegalizeOp may be reentered even from single-use nodes, which
228  // means that we always must cache transformed nodes.
229  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
230  if (I != LegalizedNodes.end()) return I->second;
231 
232  SDNode* Node = Op.getNode();
233 
234  // Legalize the operands
236  for (const SDValue &Op : Node->op_values())
237  Ops.push_back(LegalizeOp(Op));
238 
239  SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops),
240  Op.getResNo());
241 
242  if (Op.getOpcode() == ISD::LOAD) {
243  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
245  if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
246  LLVM_DEBUG(dbgs() << "\nLegalizing extending vector load: ";
247  Node->dump(&DAG));
248  switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
249  LD->getMemoryVT())) {
250  default: llvm_unreachable("This action is not supported yet!");
252  return TranslateLegalizeResults(Op, Result);
254  if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
255  assert(Lowered->getNumValues() == Op->getNumValues() &&
256  "Unexpected number of results");
257  if (Lowered != Result) {
258  // Make sure the new code is also legal.
259  Lowered = LegalizeOp(Lowered);
260  Changed = true;
261  }
262  return TranslateLegalizeResults(Op, Lowered);
263  }
266  Changed = true;
267  return ExpandLoad(Op);
268  }
269  }
270  } else if (Op.getOpcode() == ISD::STORE) {
271  StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
272  EVT StVT = ST->getMemoryVT();
273  MVT ValVT = ST->getValue().getSimpleValueType();
274  if (StVT.isVector() && ST->isTruncatingStore()) {
275  LLVM_DEBUG(dbgs() << "\nLegalizing truncating vector store: ";
276  Node->dump(&DAG));
277  switch (TLI.getTruncStoreAction(ValVT, StVT)) {
278  default: llvm_unreachable("This action is not supported yet!");
280  return TranslateLegalizeResults(Op, Result);
281  case TargetLowering::Custom: {
282  SDValue Lowered = TLI.LowerOperation(Result, DAG);
283  if (Lowered != Result) {
284  // Make sure the new code is also legal.
285  Lowered = LegalizeOp(Lowered);
286  Changed = true;
287  }
288  return TranslateLegalizeResults(Op, Lowered);
289  }
291  Changed = true;
292  return ExpandStore(Op);
293  }
294  }
295  }
296 
297  bool HasVectorValueOrOp = false;
298  for (auto J = Node->value_begin(), E = Node->value_end(); J != E; ++J)
299  HasVectorValueOrOp |= J->isVector();
300  for (const SDValue &Op : Node->op_values())
301  HasVectorValueOrOp |= Op.getValueType().isVector();
302 
303  if (!HasVectorValueOrOp)
304  return TranslateLegalizeResults(Op, Result);
305 
307  switch (Op.getOpcode()) {
308  default:
309  return TranslateLegalizeResults(Op, Result);
310  case ISD::STRICT_FADD:
311  case ISD::STRICT_FSUB:
312  case ISD::STRICT_FMUL:
313  case ISD::STRICT_FDIV:
314  case ISD::STRICT_FREM:
315  case ISD::STRICT_FSQRT:
316  case ISD::STRICT_FMA:
317  case ISD::STRICT_FPOW:
318  case ISD::STRICT_FPOWI:
319  case ISD::STRICT_FSIN:
320  case ISD::STRICT_FCOS:
321  case ISD::STRICT_FEXP:
322  case ISD::STRICT_FEXP2:
323  case ISD::STRICT_FLOG:
324  case ISD::STRICT_FLOG10:
325  case ISD::STRICT_FLOG2:
326  case ISD::STRICT_FRINT:
328  case ISD::STRICT_FMAXNUM:
329  case ISD::STRICT_FMINNUM:
330  case ISD::STRICT_FCEIL:
331  case ISD::STRICT_FFLOOR:
332  case ISD::STRICT_FROUND:
333  case ISD::STRICT_FTRUNC:
336  // These pseudo-ops get legalized as if they were their non-strict
337  // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
338  // is also legal, but if ISD::FSQRT requires expansion then so does
339  // ISD::STRICT_FSQRT.
340  Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
341  Node->getValueType(0));
342  break;
343  case ISD::ADD:
344  case ISD::SUB:
345  case ISD::MUL:
346  case ISD::MULHS:
347  case ISD::MULHU:
348  case ISD::SDIV:
349  case ISD::UDIV:
350  case ISD::SREM:
351  case ISD::UREM:
352  case ISD::SDIVREM:
353  case ISD::UDIVREM:
354  case ISD::FADD:
355  case ISD::FSUB:
356  case ISD::FMUL:
357  case ISD::FDIV:
358  case ISD::FREM:
359  case ISD::AND:
360  case ISD::OR:
361  case ISD::XOR:
362  case ISD::SHL:
363  case ISD::SRA:
364  case ISD::SRL:
365  case ISD::FSHL:
366  case ISD::FSHR:
367  case ISD::ROTL:
368  case ISD::ROTR:
369  case ISD::ABS:
370  case ISD::BSWAP:
371  case ISD::BITREVERSE:
372  case ISD::CTLZ:
373  case ISD::CTTZ:
376  case ISD::CTPOP:
377  case ISD::SELECT:
378  case ISD::VSELECT:
379  case ISD::SELECT_CC:
380  case ISD::SETCC:
381  case ISD::ZERO_EXTEND:
382  case ISD::ANY_EXTEND:
383  case ISD::TRUNCATE:
384  case ISD::SIGN_EXTEND:
385  case ISD::FP_TO_SINT:
386  case ISD::FP_TO_UINT:
387  case ISD::FNEG:
388  case ISD::FABS:
389  case ISD::FMINNUM:
390  case ISD::FMAXNUM:
391  case ISD::FMINNUM_IEEE:
392  case ISD::FMAXNUM_IEEE:
393  case ISD::FMINIMUM:
394  case ISD::FMAXIMUM:
395  case ISD::FCOPYSIGN:
396  case ISD::FSQRT:
397  case ISD::FSIN:
398  case ISD::FCOS:
399  case ISD::FPOWI:
400  case ISD::FPOW:
401  case ISD::FLOG:
402  case ISD::FLOG2:
403  case ISD::FLOG10:
404  case ISD::FEXP:
405  case ISD::FEXP2:
406  case ISD::FCEIL:
407  case ISD::FTRUNC:
408  case ISD::FRINT:
409  case ISD::FNEARBYINT:
410  case ISD::FROUND:
411  case ISD::FFLOOR:
412  case ISD::FP_ROUND:
413  case ISD::FP_EXTEND:
414  case ISD::FMA:
419  case ISD::SMIN:
420  case ISD::SMAX:
421  case ISD::UMIN:
422  case ISD::UMAX:
423  case ISD::SMUL_LOHI:
424  case ISD::UMUL_LOHI:
425  case ISD::SMULO:
426  case ISD::UMULO:
427  case ISD::FCANONICALIZE:
428  case ISD::SADDSAT:
429  case ISD::UADDSAT:
430  case ISD::SSUBSAT:
431  case ISD::USUBSAT:
432  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
433  break;
434  case ISD::SMULFIX:
435  case ISD::UMULFIX: {
436  unsigned Scale = Node->getConstantOperandVal(2);
437  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
438  Node->getValueType(0), Scale);
439  break;
440  }
441  case ISD::FP_ROUND_INREG:
442  Action = TLI.getOperationAction(Node->getOpcode(),
443  cast<VTSDNode>(Node->getOperand(1))->getVT());
444  break;
445  case ISD::SINT_TO_FP:
446  case ISD::UINT_TO_FP:
447  case ISD::VECREDUCE_ADD:
448  case ISD::VECREDUCE_MUL:
449  case ISD::VECREDUCE_AND:
450  case ISD::VECREDUCE_OR:
451  case ISD::VECREDUCE_XOR:
452  case ISD::VECREDUCE_SMAX:
453  case ISD::VECREDUCE_SMIN:
454  case ISD::VECREDUCE_UMAX:
455  case ISD::VECREDUCE_UMIN:
456  case ISD::VECREDUCE_FADD:
457  case ISD::VECREDUCE_FMUL:
458  case ISD::VECREDUCE_FMAX:
459  case ISD::VECREDUCE_FMIN:
460  Action = TLI.getOperationAction(Node->getOpcode(),
461  Node->getOperand(0).getValueType());
462  break;
463  }
464 
465  LLVM_DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG));
466 
467  switch (Action) {
468  default: llvm_unreachable("This action is not supported yet!");
470  Result = Promote(Op);
471  Changed = true;
472  break;
474  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
475  break;
476  case TargetLowering::Custom: {
477  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
478  if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
479  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
480  Result = Tmp1;
481  break;
482  }
483  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
485  }
487  Result = Expand(Op);
488  }
489 
490  // Make sure that the generated code is itself legal.
491  if (Result != Op) {
492  Result = LegalizeOp(Result);
493  Changed = true;
494  }
495 
496  // Note that LegalizeOp may be reentered even from single-use nodes, which
497  // means that we always must cache transformed nodes.
498  AddLegalizedOperand(Op, Result);
499  return Result;
500 }
501 
502 SDValue VectorLegalizer::Promote(SDValue Op) {
503  // For a few operations there is a specific concept for promotion based on
504  // the operand's type.
505  switch (Op.getOpcode()) {
506  case ISD::SINT_TO_FP:
507  case ISD::UINT_TO_FP:
508  // "Promote" the operation by extending the operand.
509  return PromoteINT_TO_FP(Op);
510  case ISD::FP_TO_UINT:
511  case ISD::FP_TO_SINT:
512  // Promote the operation by extending the operand.
513  return PromoteFP_TO_INT(Op);
514  }
515 
516  // There are currently two cases of vector promotion:
517  // 1) Bitcasting a vector of integers to a different type to a vector of the
518  // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
519  // 2) Extending a vector of floats to a vector of the same number of larger
520  // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
521  MVT VT = Op.getSimpleValueType();
522  assert(Op.getNode()->getNumValues() == 1 &&
523  "Can't promote a vector with multiple results!");
524  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
525  SDLoc dl(Op);
527 
528  for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
529  if (Op.getOperand(j).getValueType().isVector())
530  if (Op.getOperand(j)
531  .getValueType()
533  .isFloatingPoint() &&
534  NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
535  Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
536  else
537  Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
538  else
539  Operands[j] = Op.getOperand(j);
540  }
541 
542  Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
543  if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
545  NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
546  return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
547  else
548  return DAG.getNode(ISD::BITCAST, dl, VT, Op);
549 }
550 
551 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
552  // INT_TO_FP operations may require the input operand be promoted even
553  // when the type is otherwise legal.
554  MVT VT = Op.getOperand(0).getSimpleValueType();
555  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
557  "Vectors have different number of elements!");
558 
559  SDLoc dl(Op);
561 
562  unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
564  for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
565  if (Op.getOperand(j).getValueType().isVector())
566  Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
567  else
568  Operands[j] = Op.getOperand(j);
569  }
570 
571  return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
572 }
573 
574 // For FP_TO_INT we promote the result type to a vector type with wider
575 // elements and then truncate the result. This is different from the default
576 // PromoteVector which uses bitcast to promote thus assumning that the
577 // promoted vector type has the same overall size.
578 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op) {
579  MVT VT = Op.getSimpleValueType();
580  MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
582  "Vectors have different number of elements!");
583 
584  unsigned NewOpc = Op->getOpcode();
585  // Change FP_TO_UINT to FP_TO_SINT if possible.
586  // TODO: Should we only do this if FP_TO_UINT itself isn't legal?
587  if (NewOpc == ISD::FP_TO_UINT &&
588  TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
589  NewOpc = ISD::FP_TO_SINT;
590 
591  SDLoc dl(Op);
592  SDValue Promoted = DAG.getNode(NewOpc, dl, NVT, Op.getOperand(0));
593 
594  // Assert that the converted value fits in the original type. If it doesn't
595  // (eg: because the value being converted is too big), then the result of the
596  // original operation was undefined anyway, so the assert is still correct.
597  Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
598  : ISD::AssertSext,
599  dl, NVT, Promoted,
600  DAG.getValueType(VT.getScalarType()));
601  return DAG.getNode(ISD::TRUNCATE, dl, VT, Promoted);
602 }
603 
604 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
605  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
606 
607  EVT SrcVT = LD->getMemoryVT();
608  EVT SrcEltVT = SrcVT.getScalarType();
609  unsigned NumElem = SrcVT.getVectorNumElements();
610 
611  SDValue NewChain;
612  SDValue Value;
613  if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
614  SDLoc dl(Op);
615 
617  SmallVector<SDValue, 8> LoadChains;
618 
619  EVT DstEltVT = LD->getValueType(0).getScalarType();
620  SDValue Chain = LD->getChain();
621  SDValue BasePTR = LD->getBasePtr();
623 
624  // When elements in a vector is not byte-addressable, we cannot directly
625  // load each element by advancing pointer, which could only address bytes.
626  // Instead, we load all significant words, mask bits off, and concatenate
627  // them to form each element. Finally, they are extended to destination
628  // scalar type to build the destination vector.
629  EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
630 
631  assert(WideVT.isRound() &&
632  "Could not handle the sophisticated case when the widest integer is"
633  " not power of 2.");
634  assert(WideVT.bitsGE(SrcEltVT) &&
635  "Type is not legalized?");
636 
637  unsigned WideBytes = WideVT.getStoreSize();
638  unsigned Offset = 0;
639  unsigned RemainingBytes = SrcVT.getStoreSize();
640  SmallVector<SDValue, 8> LoadVals;
641  while (RemainingBytes > 0) {
642  SDValue ScalarLoad;
643  unsigned LoadBytes = WideBytes;
644 
645  if (RemainingBytes >= LoadBytes) {
646  ScalarLoad =
647  DAG.getLoad(WideVT, dl, Chain, BasePTR,
648  LD->getPointerInfo().getWithOffset(Offset),
649  MinAlign(LD->getAlignment(), Offset),
650  LD->getMemOperand()->getFlags(), LD->getAAInfo());
651  } else {
652  EVT LoadVT = WideVT;
653  while (RemainingBytes < LoadBytes) {
654  LoadBytes >>= 1; // Reduce the load size by half.
655  LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
656  }
657  ScalarLoad =
658  DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
659  LD->getPointerInfo().getWithOffset(Offset), LoadVT,
660  MinAlign(LD->getAlignment(), Offset),
661  LD->getMemOperand()->getFlags(), LD->getAAInfo());
662  }
663 
664  RemainingBytes -= LoadBytes;
665  Offset += LoadBytes;
666 
667  BasePTR = DAG.getObjectPtrOffset(dl, BasePTR, LoadBytes);
668 
669  LoadVals.push_back(ScalarLoad.getValue(0));
670  LoadChains.push_back(ScalarLoad.getValue(1));
671  }
672 
673  unsigned BitOffset = 0;
674  unsigned WideIdx = 0;
675  unsigned WideBits = WideVT.getSizeInBits();
676 
677  // Extract bits, pack and extend/trunc them into destination type.
678  unsigned SrcEltBits = SrcEltVT.getSizeInBits();
679  SDValue SrcEltBitMask = DAG.getConstant(
680  APInt::getLowBitsSet(WideBits, SrcEltBits), dl, WideVT);
681 
682  for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
683  assert(BitOffset < WideBits && "Unexpected offset!");
684 
685  SDValue ShAmt = DAG.getConstant(
686  BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
687  SDValue Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
688 
689  BitOffset += SrcEltBits;
690  if (BitOffset >= WideBits) {
691  WideIdx++;
692  BitOffset -= WideBits;
693  if (BitOffset > 0) {
694  ShAmt = DAG.getConstant(
695  SrcEltBits - BitOffset, dl,
696  TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
697  SDValue Hi =
698  DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
699  Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
700  }
701  }
702 
703  Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
704 
705  switch (ExtType) {
706  default: llvm_unreachable("Unknown extended-load op!");
707  case ISD::EXTLOAD:
708  Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
709  break;
710  case ISD::ZEXTLOAD:
711  Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
712  break;
713  case ISD::SEXTLOAD:
714  ShAmt =
715  DAG.getConstant(WideBits - SrcEltBits, dl,
716  TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
717  Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
718  Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
719  Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
720  break;
721  }
722  Vals.push_back(Lo);
723  }
724 
725  NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
726  Value = DAG.getBuildVector(Op.getNode()->getValueType(0), dl, Vals);
727  } else {
728  SDValue Scalarized = TLI.scalarizeVectorLoad(LD, DAG);
729  // Skip past MERGE_VALUE node if known.
730  if (Scalarized->getOpcode() == ISD::MERGE_VALUES) {
731  NewChain = Scalarized.getOperand(1);
732  Value = Scalarized.getOperand(0);
733  } else {
734  NewChain = Scalarized.getValue(1);
735  Value = Scalarized.getValue(0);
736  }
737  }
738 
739  AddLegalizedOperand(Op.getValue(0), Value);
740  AddLegalizedOperand(Op.getValue(1), NewChain);
741 
742  return (Op.getResNo() ? NewChain : Value);
743 }
744 
745 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
746  StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
747  SDValue TF = TLI.scalarizeVectorStore(ST, DAG);
748  AddLegalizedOperand(Op, TF);
749  return TF;
750 }
751 
752 SDValue VectorLegalizer::Expand(SDValue Op) {
753  switch (Op->getOpcode()) {
755  return ExpandSEXTINREG(Op);
757  return ExpandANY_EXTEND_VECTOR_INREG(Op);
759  return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
761  return ExpandZERO_EXTEND_VECTOR_INREG(Op);
762  case ISD::BSWAP:
763  return ExpandBSWAP(Op);
764  case ISD::VSELECT:
765  return ExpandVSELECT(Op);
766  case ISD::SELECT:
767  return ExpandSELECT(Op);
768  case ISD::FP_TO_UINT:
769  return ExpandFP_TO_UINT(Op);
770  case ISD::UINT_TO_FP:
771  return ExpandUINT_TO_FLOAT(Op);
772  case ISD::FNEG:
773  return ExpandFNEG(Op);
774  case ISD::FSUB:
775  return ExpandFSUB(Op);
776  case ISD::SETCC:
777  return UnrollVSETCC(Op);
778  case ISD::ABS:
779  return ExpandABS(Op);
780  case ISD::BITREVERSE:
781  return ExpandBITREVERSE(Op);
782  case ISD::CTPOP:
783  return ExpandCTPOP(Op);
784  case ISD::CTLZ:
786  return ExpandCTLZ(Op);
787  case ISD::CTTZ:
789  return ExpandCTTZ(Op);
790  case ISD::FSHL:
791  case ISD::FSHR:
792  return ExpandFunnelShift(Op);
793  case ISD::ROTL:
794  case ISD::ROTR:
795  return ExpandROT(Op);
796  case ISD::FMINNUM:
797  case ISD::FMAXNUM:
798  return ExpandFMINNUM_FMAXNUM(Op);
799  case ISD::UMULO:
800  case ISD::SMULO:
801  return ExpandMULO(Op);
802  case ISD::USUBSAT:
803  case ISD::SSUBSAT:
804  case ISD::UADDSAT:
805  case ISD::SADDSAT:
806  return ExpandAddSubSat(Op);
807  case ISD::SMULFIX:
808  case ISD::UMULFIX:
809  return ExpandFixedPointMul(Op);
810  case ISD::STRICT_FADD:
811  case ISD::STRICT_FSUB:
812  case ISD::STRICT_FMUL:
813  case ISD::STRICT_FDIV:
814  case ISD::STRICT_FREM:
815  case ISD::STRICT_FSQRT:
816  case ISD::STRICT_FMA:
817  case ISD::STRICT_FPOW:
818  case ISD::STRICT_FPOWI:
819  case ISD::STRICT_FSIN:
820  case ISD::STRICT_FCOS:
821  case ISD::STRICT_FEXP:
822  case ISD::STRICT_FEXP2:
823  case ISD::STRICT_FLOG:
824  case ISD::STRICT_FLOG10:
825  case ISD::STRICT_FLOG2:
826  case ISD::STRICT_FRINT:
828  case ISD::STRICT_FMAXNUM:
829  case ISD::STRICT_FMINNUM:
830  case ISD::STRICT_FCEIL:
831  case ISD::STRICT_FFLOOR:
832  case ISD::STRICT_FROUND:
833  case ISD::STRICT_FTRUNC:
834  return ExpandStrictFPOp(Op);
835  case ISD::VECREDUCE_ADD:
836  case ISD::VECREDUCE_MUL:
837  case ISD::VECREDUCE_AND:
838  case ISD::VECREDUCE_OR:
839  case ISD::VECREDUCE_XOR:
840  case ISD::VECREDUCE_SMAX:
841  case ISD::VECREDUCE_SMIN:
842  case ISD::VECREDUCE_UMAX:
843  case ISD::VECREDUCE_UMIN:
844  case ISD::VECREDUCE_FADD:
845  case ISD::VECREDUCE_FMUL:
846  case ISD::VECREDUCE_FMAX:
847  case ISD::VECREDUCE_FMIN:
848  return TLI.expandVecReduce(Op.getNode(), DAG);
849  default:
850  return DAG.UnrollVectorOp(Op.getNode());
851  }
852 }
853 
854 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
855  // Lower a select instruction where the condition is a scalar and the
856  // operands are vectors. Lower this select to VSELECT and implement it
857  // using XOR AND OR. The selector bit is broadcasted.
858  EVT VT = Op.getValueType();
859  SDLoc DL(Op);
860 
861  SDValue Mask = Op.getOperand(0);
862  SDValue Op1 = Op.getOperand(1);
863  SDValue Op2 = Op.getOperand(2);
864 
865  assert(VT.isVector() && !Mask.getValueType().isVector()
866  && Op1.getValueType() == Op2.getValueType() && "Invalid type");
867 
868  // If we can't even use the basic vector operations of
869  // AND,OR,XOR, we will have to scalarize the op.
870  // Notice that the operation may be 'promoted' which means that it is
871  // 'bitcasted' to another type which is handled.
872  // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
873  if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
874  TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
875  TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
876  TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
877  return DAG.UnrollVectorOp(Op.getNode());
878 
879  // Generate a mask operand.
881 
882  // What is the size of each element in the vector mask.
883  EVT BitTy = MaskTy.getScalarType();
884 
885  Mask = DAG.getSelect(DL, BitTy, Mask,
886  DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
887  BitTy),
888  DAG.getConstant(0, DL, BitTy));
889 
890  // Broadcast the mask so that the entire vector is all-one or all zero.
891  Mask = DAG.getSplatBuildVector(MaskTy, DL, Mask);
892 
893  // Bitcast the operands to be the same type as the mask.
894  // This is needed when we select between FP types because
895  // the mask is a vector of integers.
896  Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
897  Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
898 
899  SDValue AllOnes = DAG.getConstant(
900  APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
901  SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
902 
903  Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
904  Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
905  SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
906  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
907 }
908 
909 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
910  EVT VT = Op.getValueType();
911 
912  // Make sure that the SRA and SHL instructions are available.
913  if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
914  TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
915  return DAG.UnrollVectorOp(Op.getNode());
916 
917  SDLoc DL(Op);
918  EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
919 
920  unsigned BW = VT.getScalarSizeInBits();
921  unsigned OrigBW = OrigTy.getScalarSizeInBits();
922  SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
923 
924  Op = Op.getOperand(0);
925  Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
926  return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
927 }
928 
929 // Generically expand a vector anyext in register to a shuffle of the relevant
930 // lanes into the appropriate locations, with other lanes left undef.
931 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
932  SDLoc DL(Op);
933  EVT VT = Op.getValueType();
934  int NumElements = VT.getVectorNumElements();
935  SDValue Src = Op.getOperand(0);
936  EVT SrcVT = Src.getValueType();
937  int NumSrcElements = SrcVT.getVectorNumElements();
938 
939  // Build a base mask of undef shuffles.
940  SmallVector<int, 16> ShuffleMask;
941  ShuffleMask.resize(NumSrcElements, -1);
942 
943  // Place the extended lanes into the correct locations.
944  int ExtLaneScale = NumSrcElements / NumElements;
945  int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
946  for (int i = 0; i < NumElements; ++i)
947  ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
948 
949  return DAG.getNode(
950  ISD::BITCAST, DL, VT,
951  DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
952 }
953 
954 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
955  SDLoc DL(Op);
956  EVT VT = Op.getValueType();
957  SDValue Src = Op.getOperand(0);
958  EVT SrcVT = Src.getValueType();
959 
960  // First build an any-extend node which can be legalized above when we
961  // recurse through it.
962  Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src);
963 
964  // Now we need sign extend. Do this by shifting the elements. Even if these
965  // aren't legal operations, they have a better chance of being legalized
966  // without full scalarization than the sign extension does.
967  unsigned EltWidth = VT.getScalarSizeInBits();
968  unsigned SrcEltWidth = SrcVT.getScalarSizeInBits();
969  SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
970  return DAG.getNode(ISD::SRA, DL, VT,
971  DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
972  ShiftAmount);
973 }
974 
975 // Generically expand a vector zext in register to a shuffle of the relevant
976 // lanes into the appropriate locations, a blend of zero into the high bits,
977 // and a bitcast to the wider element type.
978 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
979  SDLoc DL(Op);
980  EVT VT = Op.getValueType();
981  int NumElements = VT.getVectorNumElements();
982  SDValue Src = Op.getOperand(0);
983  EVT SrcVT = Src.getValueType();
984  int NumSrcElements = SrcVT.getVectorNumElements();
985 
986  // Build up a zero vector to blend into this one.
987  SDValue Zero = DAG.getConstant(0, DL, SrcVT);
988 
989  // Shuffle the incoming lanes into the correct position, and pull all other
990  // lanes from the zero vector.
991  SmallVector<int, 16> ShuffleMask;
992  ShuffleMask.reserve(NumSrcElements);
993  for (int i = 0; i < NumSrcElements; ++i)
994  ShuffleMask.push_back(i);
995 
996  int ExtLaneScale = NumSrcElements / NumElements;
997  int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
998  for (int i = 0; i < NumElements; ++i)
999  ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
1000 
1001  return DAG.getNode(ISD::BITCAST, DL, VT,
1002  DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
1003 }
1004 
1005 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) {
1006  int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
1007  for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
1008  for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
1009  ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
1010 }
1011 
1012 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
1013  EVT VT = Op.getValueType();
1014 
1015  // Generate a byte wise shuffle mask for the BSWAP.
1016  SmallVector<int, 16> ShuffleMask;
1017  createBSWAPShuffleMask(VT, ShuffleMask);
1018  EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
1019 
1020  // Only emit a shuffle if the mask is legal.
1021  if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
1022  return DAG.UnrollVectorOp(Op.getNode());
1023 
1024  SDLoc DL(Op);
1025  Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
1026  Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), ShuffleMask);
1027  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
1028 }
1029 
1030 SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
1031  EVT VT = Op.getValueType();
1032 
1033  // If we have the scalar operation, it's probably cheaper to unroll it.
1034  if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
1035  return DAG.UnrollVectorOp(Op.getNode());
1036 
1037  // If the vector element width is a whole number of bytes, test if its legal
1038  // to BSWAP shuffle the bytes and then perform the BITREVERSE on the byte
1039  // vector. This greatly reduces the number of bit shifts necessary.
1040  unsigned ScalarSizeInBits = VT.getScalarSizeInBits();
1041  if (ScalarSizeInBits > 8 && (ScalarSizeInBits % 8) == 0) {
1042  SmallVector<int, 16> BSWAPMask;
1043  createBSWAPShuffleMask(VT, BSWAPMask);
1044 
1045  EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, BSWAPMask.size());
1046  if (TLI.isShuffleMaskLegal(BSWAPMask, ByteVT) &&
1047  (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
1048  (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
1049  TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) &&
1050  TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) &&
1051  TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) {
1052  SDLoc DL(Op);
1053  Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
1054  Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
1055  BSWAPMask);
1056  Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
1057  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
1058  }
1059  }
1060 
1061  // If we have the appropriate vector bit operations, it is better to use them
1062  // than unrolling and expanding each component.
1063  if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
1064  !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
1065  !TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
1066  !TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
1067  return DAG.UnrollVectorOp(Op.getNode());
1068 
1069  // Let LegalizeDAG handle this later.
1070  return Op;
1071 }
1072 
1073 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
1074  // Implement VSELECT in terms of XOR, AND, OR
1075  // on platforms which do not support blend natively.
1076  SDLoc DL(Op);
1077 
1078  SDValue Mask = Op.getOperand(0);
1079  SDValue Op1 = Op.getOperand(1);
1080  SDValue Op2 = Op.getOperand(2);
1081 
1082  EVT VT = Mask.getValueType();
1083 
1084  // If we can't even use the basic vector operations of
1085  // AND,OR,XOR, we will have to scalarize the op.
1086  // Notice that the operation may be 'promoted' which means that it is
1087  // 'bitcasted' to another type which is handled.
1088  // This operation also isn't safe with AND, OR, XOR when the boolean
1089  // type is 0/1 as we need an all ones vector constant to mask with.
1090  // FIXME: Sign extend 1 to all ones if thats legal on the target.
1091  if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
1092  TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
1093  TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
1094  TLI.getBooleanContents(Op1.getValueType()) !=
1096  return DAG.UnrollVectorOp(Op.getNode());
1097 
1098  // If the mask and the type are different sizes, unroll the vector op. This
1099  // can occur when getSetCCResultType returns something that is different in
1100  // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
1101  if (VT.getSizeInBits() != Op1.getValueSizeInBits())
1102  return DAG.UnrollVectorOp(Op.getNode());
1103 
1104  // Bitcast the operands to be the same type as the mask.
1105  // This is needed when we select between FP types because
1106  // the mask is a vector of integers.
1107  Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
1108  Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
1109 
1110  SDValue AllOnes = DAG.getConstant(
1112  SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
1113 
1114  Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
1115  Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
1116  SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
1117  return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
1118 }
1119 
1120 SDValue VectorLegalizer::ExpandABS(SDValue Op) {
1121  // Attempt to expand using TargetLowering.
1122  SDValue Result;
1123  if (TLI.expandABS(Op.getNode(), Result, DAG))
1124  return Result;
1125 
1126  // Otherwise go ahead and unroll.
1127  return DAG.UnrollVectorOp(Op.getNode());
1128 }
1129 
1130 SDValue VectorLegalizer::ExpandFP_TO_UINT(SDValue Op) {
1131  // Attempt to expand using TargetLowering.
1132  SDValue Result;
1133  if (TLI.expandFP_TO_UINT(Op.getNode(), Result, DAG))
1134  return Result;
1135 
1136  // Otherwise go ahead and unroll.
1137  return DAG.UnrollVectorOp(Op.getNode());
1138 }
1139 
1140 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
1141  EVT VT = Op.getOperand(0).getValueType();
1142  SDLoc DL(Op);
1143 
1144  // Attempt to expand using TargetLowering.
1145  SDValue Result;
1146  if (TLI.expandUINT_TO_FP(Op.getNode(), Result, DAG))
1147  return Result;
1148 
1149  // Make sure that the SINT_TO_FP and SRL instructions are available.
1150  if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
1151  TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
1152  return DAG.UnrollVectorOp(Op.getNode());
1153 
1154  unsigned BW = VT.getScalarSizeInBits();
1155  assert((BW == 64 || BW == 32) &&
1156  "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
1157 
1158  SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
1159 
1160  // Constants to clear the upper part of the word.
1161  // Notice that we can also use SHL+SHR, but using a constant is slightly
1162  // faster on x86.
1163  uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;
1164  SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
1165 
1166  // Two to the power of half-word-size.
1167  SDValue TWOHW = DAG.getConstantFP(1ULL << (BW / 2), DL, Op.getValueType());
1168 
1169  // Clear upper part of LO, lower HI
1170  SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1171  SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1172 
1173  // Convert hi and lo to floats
1174  // Convert the hi part back to the upper values
1175  // TODO: Can any fast-math-flags be set on these nodes?
1176  SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1177  fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1178  SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1179 
1180  // Add the two halves
1181  return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1182 }
1183 
1184 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1185  if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1186  SDLoc DL(Op);
1187  SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1188  // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1189  return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1190  Zero, Op.getOperand(0));
1191  }
1192  return DAG.UnrollVectorOp(Op.getNode());
1193 }
1194 
1195 SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
1196  // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
1197  // we can defer this to operation legalization where it will be lowered as
1198  // a+(-b).
1199  EVT VT = Op.getValueType();
1200  if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
1201  TLI.isOperationLegalOrCustom(ISD::FADD, VT))
1202  return Op; // Defer to LegalizeDAG
1203 
1204  return DAG.UnrollVectorOp(Op.getNode());
1205 }
1206 
1207 SDValue VectorLegalizer::ExpandCTPOP(SDValue Op) {
1208  SDValue Result;
1209  if (TLI.expandCTPOP(Op.getNode(), Result, DAG))
1210  return Result;
1211 
1212  return DAG.UnrollVectorOp(Op.getNode());
1213 }
1214 
1215 SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
1216  SDValue Result;
1217  if (TLI.expandCTLZ(Op.getNode(), Result, DAG))
1218  return Result;
1219 
1220  return DAG.UnrollVectorOp(Op.getNode());
1221 }
1222 
1223 SDValue VectorLegalizer::ExpandCTTZ(SDValue Op) {
1224  SDValue Result;
1225  if (TLI.expandCTTZ(Op.getNode(), Result, DAG))
1226  return Result;
1227 
1228  return DAG.UnrollVectorOp(Op.getNode());
1229 }
1230 
1231 SDValue VectorLegalizer::ExpandFunnelShift(SDValue Op) {
1232  SDValue Result;
1233  if (TLI.expandFunnelShift(Op.getNode(), Result, DAG))
1234  return Result;
1235 
1236  return DAG.UnrollVectorOp(Op.getNode());
1237 }
1238 
1239 SDValue VectorLegalizer::ExpandROT(SDValue Op) {
1240  SDValue Result;
1241  if (TLI.expandROT(Op.getNode(), Result, DAG))
1242  return Result;
1243 
1244  return DAG.UnrollVectorOp(Op.getNode());
1245 }
1246 
1247 SDValue VectorLegalizer::ExpandFMINNUM_FMAXNUM(SDValue Op) {
1248  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Op.getNode(), DAG))
1249  return Expanded;
1250  return DAG.UnrollVectorOp(Op.getNode());
1251 }
1252 
1253 SDValue VectorLegalizer::ExpandMULO(SDValue Op) {
1254  SDValue Result, Overflow;
1255  if (!TLI.expandMULO(Op.getNode(), Result, Overflow, DAG))
1256  std::tie(Result, Overflow) = DAG.UnrollVectorOverflowOp(Op.getNode());
1257 
1258  if (Op.getResNo() == 0) {
1259  AddLegalizedOperand(Op.getValue(1), LegalizeOp(Overflow));
1260  return Result;
1261  } else {
1262  AddLegalizedOperand(Op.getValue(0), LegalizeOp(Result));
1263  return Overflow;
1264  }
1265 }
1266 
1267 SDValue VectorLegalizer::ExpandAddSubSat(SDValue Op) {
1268  if (SDValue Expanded = TLI.expandAddSubSat(Op.getNode(), DAG))
1269  return Expanded;
1270  return DAG.UnrollVectorOp(Op.getNode());
1271 }
1272 
1273 SDValue VectorLegalizer::ExpandFixedPointMul(SDValue Op) {
1274  if (SDValue Expanded = TLI.expandFixedPointMul(Op.getNode(), DAG))
1275  return Expanded;
1276  return DAG.UnrollVectorOp(Op.getNode());
1277 }
1278 
1279 SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) {
1280  EVT VT = Op.getValueType();
1281  EVT EltVT = VT.getVectorElementType();
1282  unsigned NumElems = VT.getVectorNumElements();
1283  unsigned NumOpers = Op.getNumOperands();
1284  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1285  EVT ValueVTs[] = {EltVT, MVT::Other};
1286  SDValue Chain = Op.getOperand(0);
1287  SDLoc dl(Op);
1288 
1289  SmallVector<SDValue, 32> OpValues;
1290  SmallVector<SDValue, 32> OpChains;
1291  for (unsigned i = 0; i < NumElems; ++i) {
1293  SDValue Idx = DAG.getConstant(i, dl,
1294  TLI.getVectorIdxTy(DAG.getDataLayout()));
1295 
1296  // The Chain is the first operand.
1297  Opers.push_back(Chain);
1298 
1299  // Now process the remaining operands.
1300  for (unsigned j = 1; j < NumOpers; ++j) {
1301  SDValue Oper = Op.getOperand(j);
1302  EVT OperVT = Oper.getValueType();
1303 
1304  if (OperVT.isVector())
1305  Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1306  OperVT.getVectorElementType(), Oper, Idx);
1307 
1308  Opers.push_back(Oper);
1309  }
1310 
1311  SDValue ScalarOp = DAG.getNode(Op->getOpcode(), dl, ValueVTs, Opers);
1312 
1313  OpValues.push_back(ScalarOp.getValue(0));
1314  OpChains.push_back(ScalarOp.getValue(1));
1315  }
1316 
1317  SDValue Result = DAG.getBuildVector(VT, dl, OpValues);
1318  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OpChains);
1319 
1320  AddLegalizedOperand(Op.getValue(0), Result);
1321  AddLegalizedOperand(Op.getValue(1), NewChain);
1322 
1323  return Op.getResNo() ? NewChain : Result;
1324 }
1325 
1326 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1327  EVT VT = Op.getValueType();
1328  unsigned NumElems = VT.getVectorNumElements();
1329  EVT EltVT = VT.getVectorElementType();
1330  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1331  EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1332  SDLoc dl(Op);
1333  SmallVector<SDValue, 8> Ops(NumElems);
1334  for (unsigned i = 0; i < NumElems; ++i) {
1335  SDValue LHSElem = DAG.getNode(
1336  ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1337  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1338  SDValue RHSElem = DAG.getNode(
1339  ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1340  DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1341  Ops[i] = DAG.getNode(ISD::SETCC, dl,
1342  TLI.getSetCCResultType(DAG.getDataLayout(),
1343  *DAG.getContext(), TmpEltVT),
1344  LHSElem, RHSElem, CC);
1345  Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1346  DAG.getConstant(APInt::getAllOnesValue
1347  (EltVT.getSizeInBits()), dl, EltVT),
1348  DAG.getConstant(0, dl, EltVT));
1349  }
1350  return DAG.getBuildVector(VT, dl, Ops);
1351 }
1352 
1354  return VectorLegalizer(*this).Run();
1355 }
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:590
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:557
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:617
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:295
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:628
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:538
bool isVector() const
Return true if this is a vector value type.
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const SDValue & getValue() const
bool LegalizeVectors()
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported ...
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:647
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
unsigned getVectorNumElements() const
const SDValue & getChain() const
unsigned getAlignment() const
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:288
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:527
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:403
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
void reserve(size_type N)
Definition: SmallVector.h:369
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:454
bool isTruncatingStore() const
Return true if the op does a truncation before store.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
Shift and rotation operations.
Definition: ISDOpcodes.h:429
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:412
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: ValueTypes.h:303
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:497
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:448
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:318
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:516
MVT getVectorElementType() const
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:543
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:346
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Definition: ValueTypes.h:234
These reductions are non-strict, and have a single vector operand.
Definition: ISDOpcodes.h:896
Machine Value Type.
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isRound() const
Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:216
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:965
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:435
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:575
Extended Value Type.
Definition: ValueTypes.h:33
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:406
Iterator for intrusive lists based on ilist_node.
BlockVerifier::State From
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:338
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:358
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point val...
Definition: ISDOpcodes.h:572
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:95
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:623
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:432
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachinePointerInfo getWithOffset(int64_t O) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:72
EVT getMemoryVT() const
Return the type of the in-memory value.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:439
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:487
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:490
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:331
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:406
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:505
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:637
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:272
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:313
Same for multiplication.
Definition: ISDOpcodes.h:256
unsigned getOpcode() const
SDValue getValue(unsigned R) const
const MachinePointerInfo & getPointerInfo() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:321
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:902
unsigned getResNo() const
get the index which selects a specific result in the SDNode
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:898
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:462
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
unsigned getNumOperands() const
Conversion operators.
Definition: ISDOpcodes.h:484
const SDValue & getOperand(unsigned i) const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:493
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:605
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl< int > &ShuffleMask)
This file describes how to lower LLVM code to machine code.
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:399
void resize(size_type N)
Definition: SmallVector.h:344
This class is used to represent ISD::LOAD nodes.