LLVM  10.0.0svn
MSP430ISelLowering.cpp
Go to the documentation of this file.
1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the MSP430TargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MSP430ISelLowering.h"
14 #include "MSP430.h"
16 #include "MSP430Subtarget.h"
17 #include "MSP430TargetMachine.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/GlobalAlias.h"
30 #include "llvm/IR/GlobalVariable.h"
31 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/Debug.h"
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "msp430-lower"
39 
41  const MSP430Subtarget &STI)
42  : TargetLowering(TM) {
43 
44  // Set up the register classes.
45  addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
46  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
47 
48  // Compute derived properties from the register classes
50 
51  // Provide all sorts of operation actions
54  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
55 
56  // We have post-incremented loads / stores.
59 
60  for (MVT VT : MVT::integer_valuetypes()) {
66  }
67 
68  // We don't have any truncstores
70 
99 
106 
113 
115 
116  // FIXME: Implement efficiently multiplication by a constant
127 
140 
141  // varargs support
147 
148  // EABI Libcalls - EABI Section 6.2
149  const struct {
150  const RTLIB::Libcall Op;
151  const char * const Name;
152  const ISD::CondCode Cond;
153  } LibraryCalls[] = {
154  // Floating point conversions - EABI Table 6
155  { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID },
156  { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID },
157  // The following is NOT implemented in libgcc
158  //{ RTLIB::FPTOSINT_F64_I16, "__mspabi_fixdi", ISD::SETCC_INVALID },
159  { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID },
160  { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID },
161  // The following is NOT implemented in libgcc
162  //{ RTLIB::FPTOUINT_F64_I16, "__mspabi_fixdu", ISD::SETCC_INVALID },
163  { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID },
164  { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID },
165  // The following is NOT implemented in libgcc
166  //{ RTLIB::FPTOSINT_F32_I16, "__mspabi_fixfi", ISD::SETCC_INVALID },
167  { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID },
168  { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID },
169  // The following is NOT implemented in libgcc
170  //{ RTLIB::FPTOUINT_F32_I16, "__mspabi_fixfu", ISD::SETCC_INVALID },
171  { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID },
172  { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID },
173  // TODO The following IS implemented in libgcc
174  //{ RTLIB::SINTTOFP_I16_F64, "__mspabi_fltid", ISD::SETCC_INVALID },
175  { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID },
176  // TODO The following IS implemented in libgcc but is not in the EABI
177  { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID },
178  // TODO The following IS implemented in libgcc
179  //{ RTLIB::UINTTOFP_I16_F64, "__mspabi_fltud", ISD::SETCC_INVALID },
180  { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID },
181  // The following IS implemented in libgcc but is not in the EABI
182  { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID },
183  // TODO The following IS implemented in libgcc
184  //{ RTLIB::SINTTOFP_I16_F32, "__mspabi_fltif", ISD::SETCC_INVALID },
185  { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID },
186  // TODO The following IS implemented in libgcc but is not in the EABI
187  { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID },
188  // TODO The following IS implemented in libgcc
189  //{ RTLIB::UINTTOFP_I16_F32, "__mspabi_fltuf", ISD::SETCC_INVALID },
190  { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID },
191  // The following IS implemented in libgcc but is not in the EABI
192  { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID },
193 
194  // Floating point comparisons - EABI Table 7
195  { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
196  { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
197  { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
198  { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
199  { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
200  { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
201  { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
202  { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
203  { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
204  { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
205  { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
206  { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
207 
208  // Floating point arithmetic - EABI Table 8
209  { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID },
210  { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID },
211  { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID },
212  { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID },
213  { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID },
214  { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID },
215  { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID },
216  { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID },
217  // The following are NOT implemented in libgcc
218  // { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID },
219  // { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID },
220 
221  // Universal Integer Operations - EABI Table 9
222  { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID },
223  { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID },
224  { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID },
225  { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID },
226  { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID },
227  { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID },
228  { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID },
229  { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID },
230  { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID },
231  { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID },
232  { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID },
233  { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID },
234 
235  // Bitwise Operations - EABI Table 10
236  // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
237  { RTLIB::SRL_I32, "__mspabi_srll", ISD::SETCC_INVALID },
238  { RTLIB::SRA_I32, "__mspabi_sral", ISD::SETCC_INVALID },
239  { RTLIB::SHL_I32, "__mspabi_slll", ISD::SETCC_INVALID },
240  // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
241 
242  };
243 
244  for (const auto &LC : LibraryCalls) {
245  setLibcallName(LC.Op, LC.Name);
246  if (LC.Cond != ISD::SETCC_INVALID)
247  setCmpLibcallCC(LC.Op, LC.Cond);
248  }
249 
250  if (STI.hasHWMult16()) {
251  const struct {
252  const RTLIB::Libcall Op;
253  const char * const Name;
254  } LibraryCalls[] = {
255  // Integer Multiply - EABI Table 9
256  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
257  { RTLIB::MUL_I32, "__mspabi_mpyl_hw" },
258  { RTLIB::MUL_I64, "__mspabi_mpyll_hw" },
259  // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
260  // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
261  };
262  for (const auto &LC : LibraryCalls) {
263  setLibcallName(LC.Op, LC.Name);
264  }
265  } else if (STI.hasHWMult32()) {
266  const struct {
267  const RTLIB::Libcall Op;
268  const char * const Name;
269  } LibraryCalls[] = {
270  // Integer Multiply - EABI Table 9
271  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
272  { RTLIB::MUL_I32, "__mspabi_mpyl_hw32" },
273  { RTLIB::MUL_I64, "__mspabi_mpyll_hw32" },
274  // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
275  // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
276  };
277  for (const auto &LC : LibraryCalls) {
278  setLibcallName(LC.Op, LC.Name);
279  }
280  } else if (STI.hasHWMultF5()) {
281  const struct {
282  const RTLIB::Libcall Op;
283  const char * const Name;
284  } LibraryCalls[] = {
285  // Integer Multiply - EABI Table 9
286  { RTLIB::MUL_I16, "__mspabi_mpyi_f5hw" },
287  { RTLIB::MUL_I32, "__mspabi_mpyl_f5hw" },
288  { RTLIB::MUL_I64, "__mspabi_mpyll_f5hw" },
289  // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
290  // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
291  };
292  for (const auto &LC : LibraryCalls) {
293  setLibcallName(LC.Op, LC.Name);
294  }
295  } else { // NoHWMult
296  const struct {
297  const RTLIB::Libcall Op;
298  const char * const Name;
299  } LibraryCalls[] = {
300  // Integer Multiply - EABI Table 9
301  { RTLIB::MUL_I16, "__mspabi_mpyi" },
302  { RTLIB::MUL_I32, "__mspabi_mpyl" },
303  { RTLIB::MUL_I64, "__mspabi_mpyll" },
304  // The __mspabi_mpysl* functions are NOT implemented in libgcc
305  // The __mspabi_mpyul* functions are NOT implemented in libgcc
306  };
307  for (const auto &LC : LibraryCalls) {
308  setLibcallName(LC.Op, LC.Name);
309  }
311  }
312 
313  // Several of the runtime library functions use a special calling conv
328  // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
329 
332 }
333 
335  SelectionDAG &DAG) const {
336  switch (Op.getOpcode()) {
337  case ISD::SHL: // FALLTHROUGH
338  case ISD::SRL:
339  case ISD::SRA: return LowerShifts(Op, DAG);
340  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
341  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
342  case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
343  case ISD::SETCC: return LowerSETCC(Op, DAG);
344  case ISD::BR_CC: return LowerBR_CC(Op, DAG);
345  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
346  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
347  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
348  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
349  case ISD::VASTART: return LowerVASTART(Op, DAG);
350  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
351  default:
352  llvm_unreachable("unimplemented operand");
353  }
354 }
355 
357  return 2;
358 }
359 //===----------------------------------------------------------------------===//
360 // MSP430 Inline Assembly Support
361 //===----------------------------------------------------------------------===//
362 
363 /// getConstraintType - Given a constraint letter, return the type of
364 /// constraint it is for this target.
367  if (Constraint.size() == 1) {
368  switch (Constraint[0]) {
369  case 'r':
370  return C_RegisterClass;
371  default:
372  break;
373  }
374  }
375  return TargetLowering::getConstraintType(Constraint);
376 }
377 
378 std::pair<unsigned, const TargetRegisterClass *>
380  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
381  if (Constraint.size() == 1) {
382  // GCC Constraint Letters
383  switch (Constraint[0]) {
384  default: break;
385  case 'r': // GENERAL_REGS
386  if (VT == MVT::i8)
387  return std::make_pair(0U, &MSP430::GR8RegClass);
388 
389  return std::make_pair(0U, &MSP430::GR16RegClass);
390  }
391  }
392 
393  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
394 }
395 
396 //===----------------------------------------------------------------------===//
397 // Calling Convention Implementation
398 //===----------------------------------------------------------------------===//
399 
400 #include "MSP430GenCallingConv.inc"
401 
402 /// For each argument in a function store the number of pieces it is composed
403 /// of.
404 template<typename ArgT>
407  unsigned CurrentArgIndex;
408 
409  if (Args.empty())
410  return;
411 
412  CurrentArgIndex = Args[0].OrigArgIndex;
413  Out.push_back(0);
414 
415  for (auto &Arg : Args) {
416  if (CurrentArgIndex == Arg.OrigArgIndex) {
417  Out.back() += 1;
418  } else {
419  Out.push_back(1);
420  CurrentArgIndex = Arg.OrigArgIndex;
421  }
422  }
423 }
424 
425 static void AnalyzeVarArgs(CCState &State,
426  const SmallVectorImpl<ISD::OutputArg> &Outs) {
427  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
428 }
429 
430 static void AnalyzeVarArgs(CCState &State,
432  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
433 }
434 
435 /// Analyze incoming and outgoing function arguments. We need custom C++ code
436 /// to handle special constraints in the ABI like reversing the order of the
437 /// pieces of splitted arguments. In addition, all pieces of a certain argument
438 /// have to be passed either using registers or the stack but never mixing both.
439 template<typename ArgT>
440 static void AnalyzeArguments(CCState &State,
442  const SmallVectorImpl<ArgT> &Args) {
443  static const MCPhysReg CRegList[] = {
444  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
445  };
446  static const unsigned CNbRegs = array_lengthof(CRegList);
447  static const MCPhysReg BuiltinRegList[] = {
448  MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
449  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
450  };
451  static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
452 
453  ArrayRef<MCPhysReg> RegList;
454  unsigned NbRegs;
455 
456  bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
457  if (Builtin) {
458  RegList = BuiltinRegList;
459  NbRegs = BuiltinNbRegs;
460  } else {
461  RegList = CRegList;
462  NbRegs = CNbRegs;
463  }
464 
465  if (State.isVarArg()) {
466  AnalyzeVarArgs(State, Args);
467  return;
468  }
469 
470  SmallVector<unsigned, 4> ArgsParts;
471  ParseFunctionArgs(Args, ArgsParts);
472 
473  if (Builtin) {
474  assert(ArgsParts.size() == 2 &&
475  "Builtin calling convention requires two arguments");
476  }
477 
478  unsigned RegsLeft = NbRegs;
479  bool UsedStack = false;
480  unsigned ValNo = 0;
481 
482  for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
483  MVT ArgVT = Args[ValNo].VT;
484  ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
485  MVT LocVT = ArgVT;
487 
488  // Promote i8 to i16
489  if (LocVT == MVT::i8) {
490  LocVT = MVT::i16;
491  if (ArgFlags.isSExt())
492  LocInfo = CCValAssign::SExt;
493  else if (ArgFlags.isZExt())
494  LocInfo = CCValAssign::ZExt;
495  else
496  LocInfo = CCValAssign::AExt;
497  }
498 
499  // Handle byval arguments
500  if (ArgFlags.isByVal()) {
501  State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
502  continue;
503  }
504 
505  unsigned Parts = ArgsParts[i];
506 
507  if (Builtin) {
508  assert(Parts == 4 &&
509  "Builtin calling convention requires 64-bit arguments");
510  }
511 
512  if (!UsedStack && Parts == 2 && RegsLeft == 1) {
513  // Special case for 32-bit register split, see EABI section 3.3.3
514  unsigned Reg = State.AllocateReg(RegList);
515  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
516  RegsLeft -= 1;
517 
518  UsedStack = true;
519  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
520  } else if (Parts <= RegsLeft) {
521  for (unsigned j = 0; j < Parts; j++) {
522  unsigned Reg = State.AllocateReg(RegList);
523  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
524  RegsLeft--;
525  }
526  } else {
527  UsedStack = true;
528  for (unsigned j = 0; j < Parts; j++)
529  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
530  }
531  }
532 }
533 
534 static void AnalyzeRetResult(CCState &State,
536  State.AnalyzeCallResult(Ins, RetCC_MSP430);
537 }
538 
539 static void AnalyzeRetResult(CCState &State,
540  const SmallVectorImpl<ISD::OutputArg> &Outs) {
541  State.AnalyzeReturn(Outs, RetCC_MSP430);
542 }
543 
544 template<typename ArgT>
545 static void AnalyzeReturnValues(CCState &State,
547  const SmallVectorImpl<ArgT> &Args) {
548  AnalyzeRetResult(State, Args);
549 }
550 
551 SDValue MSP430TargetLowering::LowerFormalArguments(
552  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
553  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
554  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
555 
556  switch (CallConv) {
557  default:
558  report_fatal_error("Unsupported calling convention");
559  case CallingConv::C:
560  case CallingConv::Fast:
561  return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
563  if (Ins.empty())
564  return Chain;
565  report_fatal_error("ISRs cannot have arguments");
566  }
567 }
568 
569 SDValue
570 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
571  SmallVectorImpl<SDValue> &InVals) const {
572  SelectionDAG &DAG = CLI.DAG;
573  SDLoc &dl = CLI.DL;
575  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
577  SDValue Chain = CLI.Chain;
578  SDValue Callee = CLI.Callee;
579  bool &isTailCall = CLI.IsTailCall;
580  CallingConv::ID CallConv = CLI.CallConv;
581  bool isVarArg = CLI.IsVarArg;
582 
583  // MSP430 target does not yet support tail call optimization.
584  isTailCall = false;
585 
586  switch (CallConv) {
587  default:
588  report_fatal_error("Unsupported calling convention");
590  case CallingConv::Fast:
591  case CallingConv::C:
592  return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
593  Outs, OutVals, Ins, dl, DAG, InVals);
595  report_fatal_error("ISRs cannot be called directly");
596  }
597 }
598 
599 /// LowerCCCArguments - transform physical registers into virtual registers and
600 /// generate load operations for arguments places on the stack.
601 // FIXME: struct return stuff
602 SDValue MSP430TargetLowering::LowerCCCArguments(
603  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
604  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
605  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
607  MachineFrameInfo &MFI = MF.getFrameInfo();
608  MachineRegisterInfo &RegInfo = MF.getRegInfo();
610 
611  // Assign locations to all of the incoming arguments.
613  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
614  *DAG.getContext());
615  AnalyzeArguments(CCInfo, ArgLocs, Ins);
616 
617  // Create frame index for the start of the first vararg value
618  if (isVarArg) {
619  unsigned Offset = CCInfo.getNextStackOffset();
620  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
621  }
622 
623  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
624  CCValAssign &VA = ArgLocs[i];
625  if (VA.isRegLoc()) {
626  // Arguments passed in registers
627  EVT RegVT = VA.getLocVT();
628  switch (RegVT.getSimpleVT().SimpleTy) {
629  default:
630  {
631 #ifndef NDEBUG
632  errs() << "LowerFormalArguments Unhandled argument type: "
633  << RegVT.getEVTString() << "\n";
634 #endif
635  llvm_unreachable(nullptr);
636  }
637  case MVT::i16:
638  Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
639  RegInfo.addLiveIn(VA.getLocReg(), VReg);
640  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
641 
642  // If this is an 8-bit value, it is really passed promoted to 16
643  // bits. Insert an assert[sz]ext to capture this, then truncate to the
644  // right size.
645  if (VA.getLocInfo() == CCValAssign::SExt)
646  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
647  DAG.getValueType(VA.getValVT()));
648  else if (VA.getLocInfo() == CCValAssign::ZExt)
649  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
650  DAG.getValueType(VA.getValVT()));
651 
652  if (VA.getLocInfo() != CCValAssign::Full)
653  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
654 
655  InVals.push_back(ArgValue);
656  }
657  } else {
658  // Sanity check
659  assert(VA.isMemLoc());
660 
661  SDValue InVal;
662  ISD::ArgFlagsTy Flags = Ins[i].Flags;
663 
664  if (Flags.isByVal()) {
665  int FI = MFI.CreateFixedObject(Flags.getByValSize(),
666  VA.getLocMemOffset(), true);
667  InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
668  } else {
669  // Load the argument to a virtual register
670  unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
671  if (ObjSize > 2) {
672  errs() << "LowerFormalArguments Unhandled argument type: "
673  << EVT(VA.getLocVT()).getEVTString()
674  << "\n";
675  }
676  // Create the frame index object for this incoming parameter...
677  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
678 
679  // Create the SelectionDAG nodes corresponding to a load
680  //from this parameter
681  SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
682  InVal = DAG.getLoad(
683  VA.getLocVT(), dl, Chain, FIN,
685  }
686 
687  InVals.push_back(InVal);
688  }
689  }
690 
691  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
692  if (Ins[i].Flags.isSRet()) {
693  unsigned Reg = FuncInfo->getSRetReturnReg();
694  if (!Reg) {
697  FuncInfo->setSRetReturnReg(Reg);
698  }
699  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
700  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
701  }
702  }
703 
704  return Chain;
705 }
706 
707 bool
708 MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
709  MachineFunction &MF,
710  bool IsVarArg,
712  LLVMContext &Context) const {
714  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
715  return CCInfo.CheckReturn(Outs, RetCC_MSP430);
716 }
717 
718 SDValue
719 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
720  bool isVarArg,
722  const SmallVectorImpl<SDValue> &OutVals,
723  const SDLoc &dl, SelectionDAG &DAG) const {
724 
726 
727  // CCValAssign - represent the assignment of the return value to a location
729 
730  // ISRs cannot return any value.
731  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
732  report_fatal_error("ISRs cannot return any value");
733 
734  // CCState - Info about the registers and stack slot.
735  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
736  *DAG.getContext());
737 
738  // Analize return values.
739  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
740 
741  SDValue Flag;
742  SmallVector<SDValue, 4> RetOps(1, Chain);
743 
744  // Copy the result values into the output registers.
745  for (unsigned i = 0; i != RVLocs.size(); ++i) {
746  CCValAssign &VA = RVLocs[i];
747  assert(VA.isRegLoc() && "Can only return in registers!");
748 
749  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
750  OutVals[i], Flag);
751 
752  // Guarantee that all emitted copies are stuck together,
753  // avoiding something bad.
754  Flag = Chain.getValue(1);
755  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
756  }
757 
758  if (MF.getFunction().hasStructRetAttr()) {
760  unsigned Reg = FuncInfo->getSRetReturnReg();
761 
762  if (!Reg)
763  llvm_unreachable("sret virtual register not created in entry block");
764 
765  SDValue Val =
766  DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));
767  unsigned R12 = MSP430::R12;
768 
769  Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
770  Flag = Chain.getValue(1);
771  RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
772  }
773 
774  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
776 
777  RetOps[0] = Chain; // Update chain.
778 
779  // Add the flag if we have it.
780  if (Flag.getNode())
781  RetOps.push_back(Flag);
782 
783  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
784 }
785 
786 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
787 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
788 SDValue MSP430TargetLowering::LowerCCCCallTo(
789  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
790  bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
791  const SmallVectorImpl<SDValue> &OutVals,
792  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
793  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
794  // Analyze operands of the call, assigning locations to each operand.
796  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
797  *DAG.getContext());
798  AnalyzeArguments(CCInfo, ArgLocs, Outs);
799 
800  // Get a count of how many bytes are to be pushed on the stack.
801  unsigned NumBytes = CCInfo.getNextStackOffset();
802  auto PtrVT = getPointerTy(DAG.getDataLayout());
803 
804  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
805 
807  SmallVector<SDValue, 12> MemOpChains;
808  SDValue StackPtr;
809 
810  // Walk the register/memloc assignments, inserting copies/loads.
811  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
812  CCValAssign &VA = ArgLocs[i];
813 
814  SDValue Arg = OutVals[i];
815 
816  // Promote the value if needed.
817  switch (VA.getLocInfo()) {
818  default: llvm_unreachable("Unknown loc info!");
819  case CCValAssign::Full: break;
820  case CCValAssign::SExt:
821  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
822  break;
823  case CCValAssign::ZExt:
824  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
825  break;
826  case CCValAssign::AExt:
827  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
828  break;
829  }
830 
831  // Arguments that can be passed on register must be kept at RegsToPass
832  // vector
833  if (VA.isRegLoc()) {
834  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
835  } else {
836  assert(VA.isMemLoc());
837 
838  if (!StackPtr.getNode())
839  StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
840 
841  SDValue PtrOff =
842  DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
843  DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
844 
845  SDValue MemOp;
846  ISD::ArgFlagsTy Flags = Outs[i].Flags;
847 
848  if (Flags.isByVal()) {
849  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
850  MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
851  Flags.getByValAlign(),
852  /*isVolatile*/false,
853  /*AlwaysInline=*/true,
854  /*isTailCall=*/false,
857  } else {
858  MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
859  }
860 
861  MemOpChains.push_back(MemOp);
862  }
863  }
864 
865  // Transform all store nodes into one single node because all store nodes are
866  // independent of each other.
867  if (!MemOpChains.empty())
868  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
869 
870  // Build a sequence of copy-to-reg nodes chained together with token chain and
871  // flag operands which copy the outgoing args into registers. The InFlag in
872  // necessary since all emitted instructions must be stuck together.
873  SDValue InFlag;
874  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
875  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
876  RegsToPass[i].second, InFlag);
877  InFlag = Chain.getValue(1);
878  }
879 
880  // If the callee is a GlobalAddress node (quite common, every direct call is)
881  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
882  // Likewise ExternalSymbol -> TargetExternalSymbol.
883  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
884  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
885  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
886  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
887 
888  // Returns a chain & a flag for retval copy to use.
889  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
891  Ops.push_back(Chain);
892  Ops.push_back(Callee);
893 
894  // Add argument registers to the end of the list so that they are
895  // known live into the call.
896  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
897  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
898  RegsToPass[i].second.getValueType()));
899 
900  if (InFlag.getNode())
901  Ops.push_back(InFlag);
902 
903  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
904  InFlag = Chain.getValue(1);
905 
906  // Create the CALLSEQ_END node.
907  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
908  DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
909  InFlag = Chain.getValue(1);
910 
911  // Handle result values, copying them out of physregs into vregs that we
912  // return.
913  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
914  DAG, InVals);
915 }
916 
917 /// LowerCallResult - Lower the result values of a call into the
918 /// appropriate copies out of appropriate physical registers.
919 ///
920 SDValue MSP430TargetLowering::LowerCallResult(
921  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
922  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
923  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
924 
925  // Assign locations to each value returned by this call.
927  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
928  *DAG.getContext());
929 
930  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
931 
932  // Copy all of the result registers out of their specified physreg.
933  for (unsigned i = 0; i != RVLocs.size(); ++i) {
934  Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
935  RVLocs[i].getValVT(), InFlag).getValue(1);
936  InFlag = Chain.getValue(2);
937  InVals.push_back(Chain.getValue(0));
938  }
939 
940  return Chain;
941 }
942 
944  SelectionDAG &DAG) const {
945  unsigned Opc = Op.getOpcode();
946  SDNode* N = Op.getNode();
947  EVT VT = Op.getValueType();
948  SDLoc dl(N);
949 
950  // Expand non-constant shifts to loops:
951  if (!isa<ConstantSDNode>(N->getOperand(1)))
952  return Op;
953 
954  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
955 
956  // Expand the stuff into sequence of shifts.
957  SDValue Victim = N->getOperand(0);
958 
959  if (ShiftAmount >= 8) {
960  assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
961  switch(Opc) {
962  default:
963  llvm_unreachable("Unknown shift");
964  case ISD::SHL:
965  // foo << (8 + N) => swpb(zext(foo)) << N
966  Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
967  Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
968  break;
969  case ISD::SRA:
970  case ISD::SRL:
971  // foo >> (8 + N) => sxt(swpb(foo)) >> N
972  Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
973  Victim = (Opc == ISD::SRA)
974  ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
975  DAG.getValueType(MVT::i8))
976  : DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
977  break;
978  }
979  ShiftAmount -= 8;
980  }
981 
982  if (Opc == ISD::SRL && ShiftAmount) {
983  // Emit a special goodness here:
984  // srl A, 1 => clrc; rrc A
985  Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);
986  ShiftAmount -= 1;
987  }
988 
989  while (ShiftAmount--)
990  Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
991  dl, VT, Victim);
992 
993  return Victim;
994 }
995 
997  SelectionDAG &DAG) const {
998  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
999  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1000  auto PtrVT = getPointerTy(DAG.getDataLayout());
1001 
1002  // Create the TargetGlobalAddress node, folding in the constant offset.
1003  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
1004  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
1005 }
1006 
1008  SelectionDAG &DAG) const {
1009  SDLoc dl(Op);
1010  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
1011  auto PtrVT = getPointerTy(DAG.getDataLayout());
1012  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
1013 
1014  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1015 }
1016 
1018  SelectionDAG &DAG) const {
1019  SDLoc dl(Op);
1020  auto PtrVT = getPointerTy(DAG.getDataLayout());
1021  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1022  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1023 
1024  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1025 }
1026 
1027 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
1028  ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1029  // FIXME: Handle bittests someday
1030  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1031 
1032  // FIXME: Handle jump negative someday
1034  switch (CC) {
1035  default: llvm_unreachable("Invalid integer condition!");
1036  case ISD::SETEQ:
1037  TCC = MSP430CC::COND_E; // aka COND_Z
1038  // Minor optimization: if LHS is a constant, swap operands, then the
1039  // constant can be folded into comparison.
1040  if (LHS.getOpcode() == ISD::Constant)
1041  std::swap(LHS, RHS);
1042  break;
1043  case ISD::SETNE:
1044  TCC = MSP430CC::COND_NE; // aka COND_NZ
1045  // Minor optimization: if LHS is a constant, swap operands, then the
1046  // constant can be folded into comparison.
1047  if (LHS.getOpcode() == ISD::Constant)
1048  std::swap(LHS, RHS);
1049  break;
1050  case ISD::SETULE:
1051  std::swap(LHS, RHS);
1053  case ISD::SETUGE:
1054  // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1055  // fold constant into instruction.
1056  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1057  LHS = RHS;
1058  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1059  TCC = MSP430CC::COND_LO;
1060  break;
1061  }
1062  TCC = MSP430CC::COND_HS; // aka COND_C
1063  break;
1064  case ISD::SETUGT:
1065  std::swap(LHS, RHS);
1067  case ISD::SETULT:
1068  // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1069  // fold constant into instruction.
1070  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1071  LHS = RHS;
1072  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1073  TCC = MSP430CC::COND_HS;
1074  break;
1075  }
1076  TCC = MSP430CC::COND_LO; // aka COND_NC
1077  break;
1078  case ISD::SETLE:
1079  std::swap(LHS, RHS);
1081  case ISD::SETGE:
1082  // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1083  // fold constant into instruction.
1084  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1085  LHS = RHS;
1086  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1087  TCC = MSP430CC::COND_L;
1088  break;
1089  }
1090  TCC = MSP430CC::COND_GE;
1091  break;
1092  case ISD::SETGT:
1093  std::swap(LHS, RHS);
1095  case ISD::SETLT:
1096  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1097  // fold constant into instruction.
1098  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1099  LHS = RHS;
1100  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1101  TCC = MSP430CC::COND_GE;
1102  break;
1103  }
1104  TCC = MSP430CC::COND_L;
1105  break;
1106  }
1107 
1108  TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1109  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1110 }
1111 
1112 
1114  SDValue Chain = Op.getOperand(0);
1115  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1116  SDValue LHS = Op.getOperand(2);
1117  SDValue RHS = Op.getOperand(3);
1118  SDValue Dest = Op.getOperand(4);
1119  SDLoc dl (Op);
1120 
1121  SDValue TargetCC;
1122  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1123 
1124  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1125  Chain, Dest, TargetCC, Flag);
1126 }
1127 
1129  SDValue LHS = Op.getOperand(0);
1130  SDValue RHS = Op.getOperand(1);
1131  SDLoc dl (Op);
1132 
1133  // If we are doing an AND and testing against zero, then the CMP
1134  // will not be generated. The AND (or BIT) will generate the condition codes,
1135  // but they are different from CMP.
1136  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1137  // lowering & isel wouldn't diverge.
1138  bool andCC = false;
1139  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1140  if (RHSC->isNullValue() && LHS.hasOneUse() &&
1141  (LHS.getOpcode() == ISD::AND ||
1142  (LHS.getOpcode() == ISD::TRUNCATE &&
1143  LHS.getOperand(0).getOpcode() == ISD::AND))) {
1144  andCC = true;
1145  }
1146  }
1147  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1148  SDValue TargetCC;
1149  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1150 
1151  // Get the condition codes directly from the status register, if its easy.
1152  // Otherwise a branch will be generated. Note that the AND and BIT
1153  // instructions generate different flags than CMP, the carry bit can be used
1154  // for NE/EQ.
1155  bool Invert = false;
1156  bool Shift = false;
1157  bool Convert = true;
1158  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1159  default:
1160  Convert = false;
1161  break;
1162  case MSP430CC::COND_HS:
1163  // Res = SR & 1, no processing is required
1164  break;
1165  case MSP430CC::COND_LO:
1166  // Res = ~(SR & 1)
1167  Invert = true;
1168  break;
1169  case MSP430CC::COND_NE:
1170  if (andCC) {
1171  // C = ~Z, thus Res = SR & 1, no processing is required
1172  } else {
1173  // Res = ~((SR >> 1) & 1)
1174  Shift = true;
1175  Invert = true;
1176  }
1177  break;
1178  case MSP430CC::COND_E:
1179  Shift = true;
1180  // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1181  // Res = (SR >> 1) & 1 is 1 word shorter.
1182  break;
1183  }
1184  EVT VT = Op.getValueType();
1185  SDValue One = DAG.getConstant(1, dl, VT);
1186  if (Convert) {
1187  SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1188  MVT::i16, Flag);
1189  if (Shift)
1190  // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1191  SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1192  SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1193  if (Invert)
1194  SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1195  return SR;
1196  } else {
1197  SDValue Zero = DAG.getConstant(0, dl, VT);
1198  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1199  SDValue Ops[] = {One, Zero, TargetCC, Flag};
1200  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1201  }
1202 }
1203 
1205  SelectionDAG &DAG) const {
1206  SDValue LHS = Op.getOperand(0);
1207  SDValue RHS = Op.getOperand(1);
1208  SDValue TrueV = Op.getOperand(2);
1209  SDValue FalseV = Op.getOperand(3);
1210  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1211  SDLoc dl (Op);
1212 
1213  SDValue TargetCC;
1214  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1215 
1216  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1217  SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1218 
1219  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1220 }
1221 
1223  SelectionDAG &DAG) const {
1224  SDValue Val = Op.getOperand(0);
1225  EVT VT = Op.getValueType();
1226  SDLoc dl(Op);
1227 
1228  assert(VT == MVT::i16 && "Only support i16 for now!");
1229 
1230  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1231  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1232  DAG.getValueType(Val.getValueType()));
1233 }
1234 
1235 SDValue
1237  MachineFunction &MF = DAG.getMachineFunction();
1239  int ReturnAddrIndex = FuncInfo->getRAIndex();
1240  auto PtrVT = getPointerTy(MF.getDataLayout());
1241 
1242  if (ReturnAddrIndex == 0) {
1243  // Set up a frame object for the return address.
1244  uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1245  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1246  true);
1247  FuncInfo->setRAIndex(ReturnAddrIndex);
1248  }
1249 
1250  return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1251 }
1252 
1254  SelectionDAG &DAG) const {
1256  MFI.setReturnAddressIsTaken(true);
1257 
1259  return SDValue();
1260 
1261  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1262  SDLoc dl(Op);
1263  auto PtrVT = getPointerTy(DAG.getDataLayout());
1264 
1265  if (Depth > 0) {
1266  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1267  SDValue Offset =
1269  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1270  DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1271  MachinePointerInfo());
1272  }
1273 
1274  // Just load the return address.
1275  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1276  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1277  MachinePointerInfo());
1278 }
1279 
1281  SelectionDAG &DAG) const {
1283  MFI.setFrameAddressIsTaken(true);
1284 
1285  EVT VT = Op.getValueType();
1286  SDLoc dl(Op); // FIXME probably not meaningful
1287  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1288  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1289  MSP430::FP, VT);
1290  while (Depth--)
1291  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1292  MachinePointerInfo());
1293  return FrameAddr;
1294 }
1295 
1297  SelectionDAG &DAG) const {
1298  MachineFunction &MF = DAG.getMachineFunction();
1300  auto PtrVT = getPointerTy(DAG.getDataLayout());
1301 
1302  // Frame index of first vararg argument
1304  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1305  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1306 
1307  // Create a store of the frame index to the location operand
1308  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1),
1309  MachinePointerInfo(SV));
1310 }
1311 
1313  SelectionDAG &DAG) const {
1314  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1315  auto PtrVT = getPointerTy(DAG.getDataLayout());
1316  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1317  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1318 }
1319 
1320 /// getPostIndexedAddressParts - returns true by value, base pointer and
1321 /// offset pointer and addressing mode by reference if this node can be
1322 /// combined with a load / store to form a post-indexed load / store.
1323 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1324  SDValue &Base,
1325  SDValue &Offset,
1326  ISD::MemIndexedMode &AM,
1327  SelectionDAG &DAG) const {
1328 
1329  LoadSDNode *LD = cast<LoadSDNode>(N);
1330  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1331  return false;
1332 
1333  EVT VT = LD->getMemoryVT();
1334  if (VT != MVT::i8 && VT != MVT::i16)
1335  return false;
1336 
1337  if (Op->getOpcode() != ISD::ADD)
1338  return false;
1339 
1340  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1341  uint64_t RHSC = RHS->getZExtValue();
1342  if ((VT == MVT::i16 && RHSC != 2) ||
1343  (VT == MVT::i8 && RHSC != 1))
1344  return false;
1345 
1346  Base = Op->getOperand(0);
1347  Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1348  AM = ISD::POST_INC;
1349  return true;
1350  }
1351 
1352  return false;
1353 }
1354 
1355 
1356 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1357  switch ((MSP430ISD::NodeType)Opcode) {
1358  case MSP430ISD::FIRST_NUMBER: break;
1359  case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1360  case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1361  case MSP430ISD::RRA: return "MSP430ISD::RRA";
1362  case MSP430ISD::RLA: return "MSP430ISD::RLA";
1363  case MSP430ISD::RRC: return "MSP430ISD::RRC";
1364  case MSP430ISD::RRCL: return "MSP430ISD::RRCL";
1365  case MSP430ISD::CALL: return "MSP430ISD::CALL";
1366  case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1367  case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1368  case MSP430ISD::CMP: return "MSP430ISD::CMP";
1369  case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1370  case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1371  case MSP430ISD::DADD: return "MSP430ISD::DADD";
1372  }
1373  return nullptr;
1374 }
1375 
1377  Type *Ty2) const {
1378  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1379  return false;
1380 
1381  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1382 }
1383 
1385  if (!VT1.isInteger() || !VT2.isInteger())
1386  return false;
1387 
1388  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1389 }
1390 
1392  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1393  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1394 }
1395 
1397  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1398  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1399 }
1400 
1402  return isZExtFree(Val.getValueType(), VT2);
1403 }
1404 
1405 //===----------------------------------------------------------------------===//
1406 // Other Lowering Code
1407 //===----------------------------------------------------------------------===//
1408 
1411  MachineBasicBlock *BB) const {
1412  MachineFunction *F = BB->getParent();
1413  MachineRegisterInfo &RI = F->getRegInfo();
1414  DebugLoc dl = MI.getDebugLoc();
1415  const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1416 
1417  unsigned Opc;
1418  bool ClearCarry = false;
1419  const TargetRegisterClass * RC;
1420  switch (MI.getOpcode()) {
1421  default: llvm_unreachable("Invalid shift opcode!");
1422  case MSP430::Shl8:
1423  Opc = MSP430::ADD8rr;
1424  RC = &MSP430::GR8RegClass;
1425  break;
1426  case MSP430::Shl16:
1427  Opc = MSP430::ADD16rr;
1428  RC = &MSP430::GR16RegClass;
1429  break;
1430  case MSP430::Sra8:
1431  Opc = MSP430::RRA8r;
1432  RC = &MSP430::GR8RegClass;
1433  break;
1434  case MSP430::Sra16:
1435  Opc = MSP430::RRA16r;
1436  RC = &MSP430::GR16RegClass;
1437  break;
1438  case MSP430::Srl8:
1439  ClearCarry = true;
1440  Opc = MSP430::RRC8r;
1441  RC = &MSP430::GR8RegClass;
1442  break;
1443  case MSP430::Srl16:
1444  ClearCarry = true;
1445  Opc = MSP430::RRC16r;
1446  RC = &MSP430::GR16RegClass;
1447  break;
1448  case MSP430::Rrcl8:
1449  case MSP430::Rrcl16: {
1450  BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1451  .addReg(MSP430::SR).addImm(1);
1452  Register SrcReg = MI.getOperand(1).getReg();
1453  Register DstReg = MI.getOperand(0).getReg();
1454  unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1455  ? MSP430::RRC16r : MSP430::RRC8r;
1456  BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1457  .addReg(SrcReg);
1458  MI.eraseFromParent(); // The pseudo instruction is gone now.
1459  return BB;
1460  }
1461  }
1462 
1463  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1465 
1466  // Create loop block
1467  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1468  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1469 
1470  F->insert(I, LoopBB);
1471  F->insert(I, RemBB);
1472 
1473  // Update machine-CFG edges by transferring all successors of the current
1474  // block to the block containing instructions after shift.
1475  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1476  BB->end());
1478 
1479  // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1480  BB->addSuccessor(LoopBB);
1481  BB->addSuccessor(RemBB);
1482  LoopBB->addSuccessor(RemBB);
1483  LoopBB->addSuccessor(LoopBB);
1484 
1485  Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1486  Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1487  Register ShiftReg = RI.createVirtualRegister(RC);
1488  Register ShiftReg2 = RI.createVirtualRegister(RC);
1489  Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1490  Register SrcReg = MI.getOperand(1).getReg();
1491  Register DstReg = MI.getOperand(0).getReg();
1492 
1493  // BB:
1494  // cmp 0, N
1495  // je RemBB
1496  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1497  .addReg(ShiftAmtSrcReg).addImm(0);
1498  BuildMI(BB, dl, TII.get(MSP430::JCC))
1499  .addMBB(RemBB)
1501 
1502  // LoopBB:
1503  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1504  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1505  // ShiftReg2 = shift ShiftReg
1506  // ShiftAmt2 = ShiftAmt - 1;
1507  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1508  .addReg(SrcReg).addMBB(BB)
1509  .addReg(ShiftReg2).addMBB(LoopBB);
1510  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1511  .addReg(ShiftAmtSrcReg).addMBB(BB)
1512  .addReg(ShiftAmtReg2).addMBB(LoopBB);
1513  if (ClearCarry)
1514  BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1515  .addReg(MSP430::SR).addImm(1);
1516  if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1517  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1518  .addReg(ShiftReg)
1519  .addReg(ShiftReg);
1520  else
1521  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1522  .addReg(ShiftReg);
1523  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1524  .addReg(ShiftAmtReg).addImm(1);
1525  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1526  .addMBB(LoopBB)
1528 
1529  // RemBB:
1530  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1531  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1532  .addReg(SrcReg).addMBB(BB)
1533  .addReg(ShiftReg2).addMBB(LoopBB);
1534 
1535  MI.eraseFromParent(); // The pseudo instruction is gone now.
1536  return RemBB;
1537 }
1538 
1541  MachineBasicBlock *BB) const {
1542  unsigned Opc = MI.getOpcode();
1543 
1544  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1545  Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1546  Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1547  Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1548  return EmitShiftInstr(MI, BB);
1549 
1550  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1551  DebugLoc dl = MI.getDebugLoc();
1552 
1553  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1554  "Unexpected instr type to insert");
1555 
1556  // To "insert" a SELECT instruction, we actually have to insert the diamond
1557  // control-flow pattern. The incoming instruction knows the destination vreg
1558  // to set, the condition code register to branch on, the true/false values to
1559  // select between, and a branch opcode to use.
1560  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1562 
1563  // thisMBB:
1564  // ...
1565  // TrueVal = ...
1566  // cmpTY ccX, r1, r2
1567  // jCC copy1MBB
1568  // fallthrough --> copy0MBB
1569  MachineBasicBlock *thisMBB = BB;
1570  MachineFunction *F = BB->getParent();
1571  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1572  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1573  F->insert(I, copy0MBB);
1574  F->insert(I, copy1MBB);
1575  // Update machine-CFG edges by transferring all successors of the current
1576  // block to the new block which will contain the Phi node for the select.
1577  copy1MBB->splice(copy1MBB->begin(), BB,
1578  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1579  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1580  // Next, add the true and fallthrough blocks as its successors.
1581  BB->addSuccessor(copy0MBB);
1582  BB->addSuccessor(copy1MBB);
1583 
1584  BuildMI(BB, dl, TII.get(MSP430::JCC))
1585  .addMBB(copy1MBB)
1586  .addImm(MI.getOperand(3).getImm());
1587 
1588  // copy0MBB:
1589  // %FalseValue = ...
1590  // # fallthrough to copy1MBB
1591  BB = copy0MBB;
1592 
1593  // Update machine-CFG edges
1594  BB->addSuccessor(copy1MBB);
1595 
1596  // copy1MBB:
1597  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1598  // ...
1599  BB = copy1MBB;
1600  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1601  .addReg(MI.getOperand(2).getReg())
1602  .addMBB(copy0MBB)
1603  .addReg(MI.getOperand(1).getReg())
1604  .addMBB(thisMBB);
1605 
1606  MI.eraseFromParent(); // The pseudo instruction is gone now.
1607  return BB;
1608 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Return with a flag operand. Operand 0 is the chain operand.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:862
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:686
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
void push_back(const T &Elt)
Definition: SmallVector.h:211
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Y = RRC X, rotate right via carry.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:738
unsigned Reg
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
bool hasHWMult16() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned second
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:474
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool hasHWMult32() const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:605
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:495
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:839
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
const TargetRegisterInfo * getRegisterInfo() const override
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:449
Calling convention used for special MSP430 rtlib functions which have an "optimized" convention using...
Definition: CallingConv.h:216
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Rotate right via carry, carry gets cleared beforehand by clrc.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:652
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:477
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:417
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:734
unsigned getSizeInBits() const
Same as RET_FLAG, but used for returning from ISRs.
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:414
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinFunctionAlignment(Align Alignment)
Set the target&#39;s minimum function alignment.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it&#39;s free to truncate a value of type Ty1 to type Ty2...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1020
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
virtual const TargetInstrInfo * getInstrInfo() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getByValSize() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
void setPrefFunctionAlignment(Align Alignment)
Set the target&#39;s preferred function alignment.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
TargetInstrInfo - Interface to description of machine instruction set.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:767
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:654
const SDValue & getOperand(unsigned Num) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:850
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
constexpr double e
Definition: MathExtras.h:57
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:114
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
self_iterator getIterator()
Definition: ilist_node.h:81
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:758
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
This class contains a discriminated union of information about pointers in memory operands...
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:690
unsigned first
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:642
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
bool isVarArg() const
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:680
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
CallingConv::ID getCallingConv() const
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:452
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:695
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
EVT getMemoryVT() const
Return the type of the in-memory value.
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
unsigned getByValAlign() const
amdgpu Simplify well known AMD library false FunctionCallee Callee
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
Definition: CallingConv.h:110
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:459
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:507
bool hasHWMultF5() const
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:510
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:674
Representation of each machine instruction.
Definition: MachineInstr.h:63
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:763
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SmallVector< SDValue, 32 > OutVals
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:426
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:721
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:525
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
unsigned getShiftAmountThreshold(EVT VT) const override
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
SDValue getValue(unsigned R) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
CondCodes
Definition: MSP430.h:22
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Y = R{R,L}A X, rotate right (left) arithmetically.
void setReturnAddressIsTaken(bool s)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
LLVM Value Representation.
Definition: Value.h:74
SDValue getRegister(unsigned Reg, EVT VT)
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:482
Register getReg() const
getReg - Returns the register number.
Conversion operators.
Definition: ISDOpcodes.h:504
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:513
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
LLVMContext * getContext() const
Definition: SelectionDAG.h:424
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:958
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:419
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:659