LLVM  9.0.0svn
MSP430ISelLowering.cpp
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1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MSP430TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MSP430ISelLowering.h"
15 #include "MSP430.h"
17 #include "MSP430Subtarget.h"
18 #include "MSP430TargetMachine.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Intrinsics.h"
34 #include "llvm/Support/Debug.h"
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "msp430-lower"
40 
42  const MSP430Subtarget &STI)
43  : TargetLowering(TM) {
44 
45  // Set up the register classes.
46  addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
47  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
48 
49  // Compute derived properties from the register classes
51 
52  // Provide all sorts of operation actions
55  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
56 
57  // We have post-incremented loads / stores.
60 
61  for (MVT VT : MVT::integer_valuetypes()) {
67  }
68 
69  // We don't have any truncstores
71 
100 
107 
114 
116 
117  // FIXME: Implement efficiently multiplication by a constant
128 
141 
142  // varargs support
148 
149  // EABI Libcalls - EABI Section 6.2
150  const struct {
151  const RTLIB::Libcall Op;
152  const char * const Name;
153  const ISD::CondCode Cond;
154  } LibraryCalls[] = {
155  // Floating point conversions - EABI Table 6
156  { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID },
157  { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID },
158  // The following is NOT implemented in libgcc
159  //{ RTLIB::FPTOSINT_F64_I16, "__mspabi_fixdi", ISD::SETCC_INVALID },
160  { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID },
161  { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID },
162  // The following is NOT implemented in libgcc
163  //{ RTLIB::FPTOUINT_F64_I16, "__mspabi_fixdu", ISD::SETCC_INVALID },
164  { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID },
165  { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID },
166  // The following is NOT implemented in libgcc
167  //{ RTLIB::FPTOSINT_F32_I16, "__mspabi_fixfi", ISD::SETCC_INVALID },
168  { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID },
169  { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID },
170  // The following is NOT implemented in libgcc
171  //{ RTLIB::FPTOUINT_F32_I16, "__mspabi_fixfu", ISD::SETCC_INVALID },
172  { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID },
173  { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID },
174  // TODO The following IS implemented in libgcc
175  //{ RTLIB::SINTTOFP_I16_F64, "__mspabi_fltid", ISD::SETCC_INVALID },
176  { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID },
177  // TODO The following IS implemented in libgcc but is not in the EABI
178  { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID },
179  // TODO The following IS implemented in libgcc
180  //{ RTLIB::UINTTOFP_I16_F64, "__mspabi_fltud", ISD::SETCC_INVALID },
181  { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID },
182  // The following IS implemented in libgcc but is not in the EABI
183  { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID },
184  // TODO The following IS implemented in libgcc
185  //{ RTLIB::SINTTOFP_I16_F32, "__mspabi_fltif", ISD::SETCC_INVALID },
186  { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID },
187  // TODO The following IS implemented in libgcc but is not in the EABI
188  { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID },
189  // TODO The following IS implemented in libgcc
190  //{ RTLIB::UINTTOFP_I16_F32, "__mspabi_fltuf", ISD::SETCC_INVALID },
191  { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID },
192  // The following IS implemented in libgcc but is not in the EABI
193  { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID },
194 
195  // Floating point comparisons - EABI Table 7
196  { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
197  { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
198  { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
199  { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
200  { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
201  { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
202  { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
203  { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
204  { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
205  { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
206  { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
207  { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
208 
209  // Floating point arithmetic - EABI Table 8
210  { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID },
211  { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID },
212  { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID },
213  { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID },
214  { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID },
215  { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID },
216  { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID },
217  { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID },
218  // The following are NOT implemented in libgcc
219  // { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID },
220  // { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID },
221 
222  // Universal Integer Operations - EABI Table 9
223  { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID },
224  { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID },
225  { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID },
226  { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID },
227  { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID },
228  { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID },
229  { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID },
230  { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID },
231  { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID },
232  { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID },
233  { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID },
234  { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID },
235 
236  // Bitwise Operations - EABI Table 10
237  // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
238  { RTLIB::SRL_I32, "__mspabi_srll", ISD::SETCC_INVALID },
239  { RTLIB::SRA_I32, "__mspabi_sral", ISD::SETCC_INVALID },
240  { RTLIB::SHL_I32, "__mspabi_slll", ISD::SETCC_INVALID },
241  // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
242 
243  };
244 
245  for (const auto &LC : LibraryCalls) {
246  setLibcallName(LC.Op, LC.Name);
247  if (LC.Cond != ISD::SETCC_INVALID)
248  setCmpLibcallCC(LC.Op, LC.Cond);
249  }
250 
251  if (STI.hasHWMult16()) {
252  const struct {
253  const RTLIB::Libcall Op;
254  const char * const Name;
255  } LibraryCalls[] = {
256  // Integer Multiply - EABI Table 9
257  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
258  { RTLIB::MUL_I32, "__mspabi_mpyl_hw" },
259  { RTLIB::MUL_I64, "__mspabi_mpyll_hw" },
260  // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
261  // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
262  };
263  for (const auto &LC : LibraryCalls) {
264  setLibcallName(LC.Op, LC.Name);
265  }
266  } else if (STI.hasHWMult32()) {
267  const struct {
268  const RTLIB::Libcall Op;
269  const char * const Name;
270  } LibraryCalls[] = {
271  // Integer Multiply - EABI Table 9
272  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
273  { RTLIB::MUL_I32, "__mspabi_mpyl_hw32" },
274  { RTLIB::MUL_I64, "__mspabi_mpyll_hw32" },
275  // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
276  // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
277  };
278  for (const auto &LC : LibraryCalls) {
279  setLibcallName(LC.Op, LC.Name);
280  }
281  } else if (STI.hasHWMultF5()) {
282  const struct {
283  const RTLIB::Libcall Op;
284  const char * const Name;
285  } LibraryCalls[] = {
286  // Integer Multiply - EABI Table 9
287  { RTLIB::MUL_I16, "__mspabi_mpyi_f5hw" },
288  { RTLIB::MUL_I32, "__mspabi_mpyl_f5hw" },
289  { RTLIB::MUL_I64, "__mspabi_mpyll_f5hw" },
290  // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
291  // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
292  };
293  for (const auto &LC : LibraryCalls) {
294  setLibcallName(LC.Op, LC.Name);
295  }
296  } else { // NoHWMult
297  const struct {
298  const RTLIB::Libcall Op;
299  const char * const Name;
300  } LibraryCalls[] = {
301  // Integer Multiply - EABI Table 9
302  { RTLIB::MUL_I16, "__mspabi_mpyi" },
303  { RTLIB::MUL_I32, "__mspabi_mpyl" },
304  { RTLIB::MUL_I64, "__mspabi_mpyll" },
305  // The __mspabi_mpysl* functions are NOT implemented in libgcc
306  // The __mspabi_mpyul* functions are NOT implemented in libgcc
307  };
308  for (const auto &LC : LibraryCalls) {
309  setLibcallName(LC.Op, LC.Name);
310  }
312  }
313 
314  // Several of the runtime library functions use a special calling conv
329  // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
330 
333 }
334 
336  SelectionDAG &DAG) const {
337  switch (Op.getOpcode()) {
338  case ISD::SHL: // FALLTHROUGH
339  case ISD::SRL:
340  case ISD::SRA: return LowerShifts(Op, DAG);
341  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
342  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
343  case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
344  case ISD::SETCC: return LowerSETCC(Op, DAG);
345  case ISD::BR_CC: return LowerBR_CC(Op, DAG);
346  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
347  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
348  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
349  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
350  case ISD::VASTART: return LowerVASTART(Op, DAG);
351  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
352  default:
353  llvm_unreachable("unimplemented operand");
354  }
355 }
356 
357 //===----------------------------------------------------------------------===//
358 // MSP430 Inline Assembly Support
359 //===----------------------------------------------------------------------===//
360 
361 /// getConstraintType - Given a constraint letter, return the type of
362 /// constraint it is for this target.
365  if (Constraint.size() == 1) {
366  switch (Constraint[0]) {
367  case 'r':
368  return C_RegisterClass;
369  default:
370  break;
371  }
372  }
373  return TargetLowering::getConstraintType(Constraint);
374 }
375 
376 std::pair<unsigned, const TargetRegisterClass *>
378  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
379  if (Constraint.size() == 1) {
380  // GCC Constraint Letters
381  switch (Constraint[0]) {
382  default: break;
383  case 'r': // GENERAL_REGS
384  if (VT == MVT::i8)
385  return std::make_pair(0U, &MSP430::GR8RegClass);
386 
387  return std::make_pair(0U, &MSP430::GR16RegClass);
388  }
389  }
390 
391  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
392 }
393 
394 //===----------------------------------------------------------------------===//
395 // Calling Convention Implementation
396 //===----------------------------------------------------------------------===//
397 
398 #include "MSP430GenCallingConv.inc"
399 
400 /// For each argument in a function store the number of pieces it is composed
401 /// of.
402 template<typename ArgT>
405  unsigned CurrentArgIndex;
406 
407  if (Args.empty())
408  return;
409 
410  CurrentArgIndex = Args[0].OrigArgIndex;
411  Out.push_back(0);
412 
413  for (auto &Arg : Args) {
414  if (CurrentArgIndex == Arg.OrigArgIndex) {
415  Out.back() += 1;
416  } else {
417  Out.push_back(1);
418  CurrentArgIndex = Arg.OrigArgIndex;
419  }
420  }
421 }
422 
423 static void AnalyzeVarArgs(CCState &State,
424  const SmallVectorImpl<ISD::OutputArg> &Outs) {
425  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
426 }
427 
428 static void AnalyzeVarArgs(CCState &State,
430  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
431 }
432 
433 /// Analyze incoming and outgoing function arguments. We need custom C++ code
434 /// to handle special constraints in the ABI like reversing the order of the
435 /// pieces of splitted arguments. In addition, all pieces of a certain argument
436 /// have to be passed either using registers or the stack but never mixing both.
437 template<typename ArgT>
438 static void AnalyzeArguments(CCState &State,
440  const SmallVectorImpl<ArgT> &Args) {
441  static const MCPhysReg CRegList[] = {
442  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
443  };
444  static const unsigned CNbRegs = array_lengthof(CRegList);
445  static const MCPhysReg BuiltinRegList[] = {
446  MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
447  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
448  };
449  static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
450 
451  ArrayRef<MCPhysReg> RegList;
452  unsigned NbRegs;
453 
454  bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
455  if (Builtin) {
456  RegList = BuiltinRegList;
457  NbRegs = BuiltinNbRegs;
458  } else {
459  RegList = CRegList;
460  NbRegs = CNbRegs;
461  }
462 
463  if (State.isVarArg()) {
464  AnalyzeVarArgs(State, Args);
465  return;
466  }
467 
468  SmallVector<unsigned, 4> ArgsParts;
469  ParseFunctionArgs(Args, ArgsParts);
470 
471  if (Builtin) {
472  assert(ArgsParts.size() == 2 &&
473  "Builtin calling convention requires two arguments");
474  }
475 
476  unsigned RegsLeft = NbRegs;
477  bool UsedStack = false;
478  unsigned ValNo = 0;
479 
480  for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
481  MVT ArgVT = Args[ValNo].VT;
482  ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
483  MVT LocVT = ArgVT;
485 
486  // Promote i8 to i16
487  if (LocVT == MVT::i8) {
488  LocVT = MVT::i16;
489  if (ArgFlags.isSExt())
490  LocInfo = CCValAssign::SExt;
491  else if (ArgFlags.isZExt())
492  LocInfo = CCValAssign::ZExt;
493  else
494  LocInfo = CCValAssign::AExt;
495  }
496 
497  // Handle byval arguments
498  if (ArgFlags.isByVal()) {
499  State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
500  continue;
501  }
502 
503  unsigned Parts = ArgsParts[i];
504 
505  if (Builtin) {
506  assert(Parts == 4 &&
507  "Builtin calling convention requires 64-bit arguments");
508  }
509 
510  if (!UsedStack && Parts == 2 && RegsLeft == 1) {
511  // Special case for 32-bit register split, see EABI section 3.3.3
512  unsigned Reg = State.AllocateReg(RegList);
513  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
514  RegsLeft -= 1;
515 
516  UsedStack = true;
517  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
518  } else if (Parts <= RegsLeft) {
519  for (unsigned j = 0; j < Parts; j++) {
520  unsigned Reg = State.AllocateReg(RegList);
521  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
522  RegsLeft--;
523  }
524  } else {
525  UsedStack = true;
526  for (unsigned j = 0; j < Parts; j++)
527  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
528  }
529  }
530 }
531 
532 static void AnalyzeRetResult(CCState &State,
534  State.AnalyzeCallResult(Ins, RetCC_MSP430);
535 }
536 
537 static void AnalyzeRetResult(CCState &State,
538  const SmallVectorImpl<ISD::OutputArg> &Outs) {
539  State.AnalyzeReturn(Outs, RetCC_MSP430);
540 }
541 
542 template<typename ArgT>
543 static void AnalyzeReturnValues(CCState &State,
545  const SmallVectorImpl<ArgT> &Args) {
546  AnalyzeRetResult(State, Args);
547 }
548 
549 SDValue MSP430TargetLowering::LowerFormalArguments(
550  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
551  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
552  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
553 
554  switch (CallConv) {
555  default:
556  report_fatal_error("Unsupported calling convention");
557  case CallingConv::C:
558  case CallingConv::Fast:
559  return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
561  if (Ins.empty())
562  return Chain;
563  report_fatal_error("ISRs cannot have arguments");
564  }
565 }
566 
567 SDValue
568 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
569  SmallVectorImpl<SDValue> &InVals) const {
570  SelectionDAG &DAG = CLI.DAG;
571  SDLoc &dl = CLI.DL;
573  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
575  SDValue Chain = CLI.Chain;
576  SDValue Callee = CLI.Callee;
577  bool &isTailCall = CLI.IsTailCall;
578  CallingConv::ID CallConv = CLI.CallConv;
579  bool isVarArg = CLI.IsVarArg;
580 
581  // MSP430 target does not yet support tail call optimization.
582  isTailCall = false;
583 
584  switch (CallConv) {
585  default:
586  report_fatal_error("Unsupported calling convention");
588  case CallingConv::Fast:
589  case CallingConv::C:
590  return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
591  Outs, OutVals, Ins, dl, DAG, InVals);
593  report_fatal_error("ISRs cannot be called directly");
594  }
595 }
596 
597 /// LowerCCCArguments - transform physical registers into virtual registers and
598 /// generate load operations for arguments places on the stack.
599 // FIXME: struct return stuff
600 SDValue MSP430TargetLowering::LowerCCCArguments(
601  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
602  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
603  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
605  MachineFrameInfo &MFI = MF.getFrameInfo();
606  MachineRegisterInfo &RegInfo = MF.getRegInfo();
608 
609  // Assign locations to all of the incoming arguments.
611  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
612  *DAG.getContext());
613  AnalyzeArguments(CCInfo, ArgLocs, Ins);
614 
615  // Create frame index for the start of the first vararg value
616  if (isVarArg) {
617  unsigned Offset = CCInfo.getNextStackOffset();
618  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
619  }
620 
621  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
622  CCValAssign &VA = ArgLocs[i];
623  if (VA.isRegLoc()) {
624  // Arguments passed in registers
625  EVT RegVT = VA.getLocVT();
626  switch (RegVT.getSimpleVT().SimpleTy) {
627  default:
628  {
629 #ifndef NDEBUG
630  errs() << "LowerFormalArguments Unhandled argument type: "
631  << RegVT.getEVTString() << "\n";
632 #endif
633  llvm_unreachable(nullptr);
634  }
635  case MVT::i16:
636  unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
637  RegInfo.addLiveIn(VA.getLocReg(), VReg);
638  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
639 
640  // If this is an 8-bit value, it is really passed promoted to 16
641  // bits. Insert an assert[sz]ext to capture this, then truncate to the
642  // right size.
643  if (VA.getLocInfo() == CCValAssign::SExt)
644  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
645  DAG.getValueType(VA.getValVT()));
646  else if (VA.getLocInfo() == CCValAssign::ZExt)
647  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
648  DAG.getValueType(VA.getValVT()));
649 
650  if (VA.getLocInfo() != CCValAssign::Full)
651  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
652 
653  InVals.push_back(ArgValue);
654  }
655  } else {
656  // Sanity check
657  assert(VA.isMemLoc());
658 
659  SDValue InVal;
660  ISD::ArgFlagsTy Flags = Ins[i].Flags;
661 
662  if (Flags.isByVal()) {
663  int FI = MFI.CreateFixedObject(Flags.getByValSize(),
664  VA.getLocMemOffset(), true);
665  InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
666  } else {
667  // Load the argument to a virtual register
668  unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
669  if (ObjSize > 2) {
670  errs() << "LowerFormalArguments Unhandled argument type: "
671  << EVT(VA.getLocVT()).getEVTString()
672  << "\n";
673  }
674  // Create the frame index object for this incoming parameter...
675  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
676 
677  // Create the SelectionDAG nodes corresponding to a load
678  //from this parameter
679  SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
680  InVal = DAG.getLoad(
681  VA.getLocVT(), dl, Chain, FIN,
683  }
684 
685  InVals.push_back(InVal);
686  }
687  }
688 
689  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
690  if (Ins[i].Flags.isSRet()) {
691  unsigned Reg = FuncInfo->getSRetReturnReg();
692  if (!Reg) {
695  FuncInfo->setSRetReturnReg(Reg);
696  }
697  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
698  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
699  }
700  }
701 
702  return Chain;
703 }
704 
705 bool
706 MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
707  MachineFunction &MF,
708  bool IsVarArg,
710  LLVMContext &Context) const {
712  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
713  return CCInfo.CheckReturn(Outs, RetCC_MSP430);
714 }
715 
716 SDValue
717 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
718  bool isVarArg,
720  const SmallVectorImpl<SDValue> &OutVals,
721  const SDLoc &dl, SelectionDAG &DAG) const {
722 
724 
725  // CCValAssign - represent the assignment of the return value to a location
727 
728  // ISRs cannot return any value.
729  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
730  report_fatal_error("ISRs cannot return any value");
731 
732  // CCState - Info about the registers and stack slot.
733  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
734  *DAG.getContext());
735 
736  // Analize return values.
737  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
738 
739  SDValue Flag;
740  SmallVector<SDValue, 4> RetOps(1, Chain);
741 
742  // Copy the result values into the output registers.
743  for (unsigned i = 0; i != RVLocs.size(); ++i) {
744  CCValAssign &VA = RVLocs[i];
745  assert(VA.isRegLoc() && "Can only return in registers!");
746 
747  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
748  OutVals[i], Flag);
749 
750  // Guarantee that all emitted copies are stuck together,
751  // avoiding something bad.
752  Flag = Chain.getValue(1);
753  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
754  }
755 
756  if (MF.getFunction().hasStructRetAttr()) {
758  unsigned Reg = FuncInfo->getSRetReturnReg();
759 
760  if (!Reg)
761  llvm_unreachable("sret virtual register not created in entry block");
762 
763  SDValue Val =
764  DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));
765  unsigned R12 = MSP430::R12;
766 
767  Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
768  Flag = Chain.getValue(1);
769  RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
770  }
771 
772  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
774 
775  RetOps[0] = Chain; // Update chain.
776 
777  // Add the flag if we have it.
778  if (Flag.getNode())
779  RetOps.push_back(Flag);
780 
781  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
782 }
783 
784 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
785 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
786 SDValue MSP430TargetLowering::LowerCCCCallTo(
787  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
788  bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
789  const SmallVectorImpl<SDValue> &OutVals,
790  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
791  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
792  // Analyze operands of the call, assigning locations to each operand.
794  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
795  *DAG.getContext());
796  AnalyzeArguments(CCInfo, ArgLocs, Outs);
797 
798  // Get a count of how many bytes are to be pushed on the stack.
799  unsigned NumBytes = CCInfo.getNextStackOffset();
800  auto PtrVT = getPointerTy(DAG.getDataLayout());
801 
802  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
803 
805  SmallVector<SDValue, 12> MemOpChains;
806  SDValue StackPtr;
807 
808  // Walk the register/memloc assignments, inserting copies/loads.
809  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
810  CCValAssign &VA = ArgLocs[i];
811 
812  SDValue Arg = OutVals[i];
813 
814  // Promote the value if needed.
815  switch (VA.getLocInfo()) {
816  default: llvm_unreachable("Unknown loc info!");
817  case CCValAssign::Full: break;
818  case CCValAssign::SExt:
819  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
820  break;
821  case CCValAssign::ZExt:
822  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
823  break;
824  case CCValAssign::AExt:
825  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
826  break;
827  }
828 
829  // Arguments that can be passed on register must be kept at RegsToPass
830  // vector
831  if (VA.isRegLoc()) {
832  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
833  } else {
834  assert(VA.isMemLoc());
835 
836  if (!StackPtr.getNode())
837  StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
838 
839  SDValue PtrOff =
840  DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
841  DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
842 
843  SDValue MemOp;
844  ISD::ArgFlagsTy Flags = Outs[i].Flags;
845 
846  if (Flags.isByVal()) {
847  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
848  MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
849  Flags.getByValAlign(),
850  /*isVolatile*/false,
851  /*AlwaysInline=*/true,
852  /*isTailCall=*/false,
855  } else {
856  MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
857  }
858 
859  MemOpChains.push_back(MemOp);
860  }
861  }
862 
863  // Transform all store nodes into one single node because all store nodes are
864  // independent of each other.
865  if (!MemOpChains.empty())
866  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
867 
868  // Build a sequence of copy-to-reg nodes chained together with token chain and
869  // flag operands which copy the outgoing args into registers. The InFlag in
870  // necessary since all emitted instructions must be stuck together.
871  SDValue InFlag;
872  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
873  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
874  RegsToPass[i].second, InFlag);
875  InFlag = Chain.getValue(1);
876  }
877 
878  // If the callee is a GlobalAddress node (quite common, every direct call is)
879  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
880  // Likewise ExternalSymbol -> TargetExternalSymbol.
881  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
882  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
883  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
884  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
885 
886  // Returns a chain & a flag for retval copy to use.
887  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
889  Ops.push_back(Chain);
890  Ops.push_back(Callee);
891 
892  // Add argument registers to the end of the list so that they are
893  // known live into the call.
894  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
895  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
896  RegsToPass[i].second.getValueType()));
897 
898  if (InFlag.getNode())
899  Ops.push_back(InFlag);
900 
901  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
902  InFlag = Chain.getValue(1);
903 
904  // Create the CALLSEQ_END node.
905  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
906  DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
907  InFlag = Chain.getValue(1);
908 
909  // Handle result values, copying them out of physregs into vregs that we
910  // return.
911  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
912  DAG, InVals);
913 }
914 
915 /// LowerCallResult - Lower the result values of a call into the
916 /// appropriate copies out of appropriate physical registers.
917 ///
918 SDValue MSP430TargetLowering::LowerCallResult(
919  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
920  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
921  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
922 
923  // Assign locations to each value returned by this call.
925  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
926  *DAG.getContext());
927 
928  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
929 
930  // Copy all of the result registers out of their specified physreg.
931  for (unsigned i = 0; i != RVLocs.size(); ++i) {
932  Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
933  RVLocs[i].getValVT(), InFlag).getValue(1);
934  InFlag = Chain.getValue(2);
935  InVals.push_back(Chain.getValue(0));
936  }
937 
938  return Chain;
939 }
940 
942  SelectionDAG &DAG) const {
943  unsigned Opc = Op.getOpcode();
944  SDNode* N = Op.getNode();
945  EVT VT = Op.getValueType();
946  SDLoc dl(N);
947 
948  // Expand non-constant shifts to loops:
949  if (!isa<ConstantSDNode>(N->getOperand(1)))
950  return Op;
951 
952  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
953 
954  // Expand the stuff into sequence of shifts.
955  SDValue Victim = N->getOperand(0);
956 
957  if (ShiftAmount >= 8) {
958  assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
959  switch(Opc) {
960  default:
961  llvm_unreachable("Unknown shift");
962  case ISD::SHL:
963  // foo << (8 + N) => swpb(zext(foo)) << N
964  Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
965  Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
966  break;
967  case ISD::SRA:
968  case ISD::SRL:
969  // foo >> (8 + N) => sxt(swpb(foo)) >> N
970  Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
971  Victim = (Opc == ISD::SRA)
972  ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
973  DAG.getValueType(MVT::i8))
974  : DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
975  break;
976  }
977  ShiftAmount -= 8;
978  }
979 
980  if (Opc == ISD::SRL && ShiftAmount) {
981  // Emit a special goodness here:
982  // srl A, 1 => clrc; rrc A
983  Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);
984  ShiftAmount -= 1;
985  }
986 
987  while (ShiftAmount--)
988  Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
989  dl, VT, Victim);
990 
991  return Victim;
992 }
993 
995  SelectionDAG &DAG) const {
996  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
997  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
998  auto PtrVT = getPointerTy(DAG.getDataLayout());
999 
1000  // Create the TargetGlobalAddress node, folding in the constant offset.
1001  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
1002  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
1003 }
1004 
1006  SelectionDAG &DAG) const {
1007  SDLoc dl(Op);
1008  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
1009  auto PtrVT = getPointerTy(DAG.getDataLayout());
1010  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
1011 
1012  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1013 }
1014 
1016  SelectionDAG &DAG) const {
1017  SDLoc dl(Op);
1018  auto PtrVT = getPointerTy(DAG.getDataLayout());
1019  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1020  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1021 
1022  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1023 }
1024 
1025 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
1026  ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1027  // FIXME: Handle bittests someday
1028  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1029 
1030  // FIXME: Handle jump negative someday
1032  switch (CC) {
1033  default: llvm_unreachable("Invalid integer condition!");
1034  case ISD::SETEQ:
1035  TCC = MSP430CC::COND_E; // aka COND_Z
1036  // Minor optimization: if LHS is a constant, swap operands, then the
1037  // constant can be folded into comparison.
1038  if (LHS.getOpcode() == ISD::Constant)
1039  std::swap(LHS, RHS);
1040  break;
1041  case ISD::SETNE:
1042  TCC = MSP430CC::COND_NE; // aka COND_NZ
1043  // Minor optimization: if LHS is a constant, swap operands, then the
1044  // constant can be folded into comparison.
1045  if (LHS.getOpcode() == ISD::Constant)
1046  std::swap(LHS, RHS);
1047  break;
1048  case ISD::SETULE:
1049  std::swap(LHS, RHS);
1051  case ISD::SETUGE:
1052  // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1053  // fold constant into instruction.
1054  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1055  LHS = RHS;
1056  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1057  TCC = MSP430CC::COND_LO;
1058  break;
1059  }
1060  TCC = MSP430CC::COND_HS; // aka COND_C
1061  break;
1062  case ISD::SETUGT:
1063  std::swap(LHS, RHS);
1065  case ISD::SETULT:
1066  // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1067  // fold constant into instruction.
1068  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1069  LHS = RHS;
1070  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1071  TCC = MSP430CC::COND_HS;
1072  break;
1073  }
1074  TCC = MSP430CC::COND_LO; // aka COND_NC
1075  break;
1076  case ISD::SETLE:
1077  std::swap(LHS, RHS);
1079  case ISD::SETGE:
1080  // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1081  // fold constant into instruction.
1082  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1083  LHS = RHS;
1084  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1085  TCC = MSP430CC::COND_L;
1086  break;
1087  }
1088  TCC = MSP430CC::COND_GE;
1089  break;
1090  case ISD::SETGT:
1091  std::swap(LHS, RHS);
1093  case ISD::SETLT:
1094  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1095  // fold constant into instruction.
1096  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1097  LHS = RHS;
1098  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1099  TCC = MSP430CC::COND_GE;
1100  break;
1101  }
1102  TCC = MSP430CC::COND_L;
1103  break;
1104  }
1105 
1106  TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1107  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1108 }
1109 
1110 
1112  SDValue Chain = Op.getOperand(0);
1113  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1114  SDValue LHS = Op.getOperand(2);
1115  SDValue RHS = Op.getOperand(3);
1116  SDValue Dest = Op.getOperand(4);
1117  SDLoc dl (Op);
1118 
1119  SDValue TargetCC;
1120  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1121 
1122  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1123  Chain, Dest, TargetCC, Flag);
1124 }
1125 
1127  SDValue LHS = Op.getOperand(0);
1128  SDValue RHS = Op.getOperand(1);
1129  SDLoc dl (Op);
1130 
1131  // If we are doing an AND and testing against zero, then the CMP
1132  // will not be generated. The AND (or BIT) will generate the condition codes,
1133  // but they are different from CMP.
1134  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1135  // lowering & isel wouldn't diverge.
1136  bool andCC = false;
1137  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1138  if (RHSC->isNullValue() && LHS.hasOneUse() &&
1139  (LHS.getOpcode() == ISD::AND ||
1140  (LHS.getOpcode() == ISD::TRUNCATE &&
1141  LHS.getOperand(0).getOpcode() == ISD::AND))) {
1142  andCC = true;
1143  }
1144  }
1145  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1146  SDValue TargetCC;
1147  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1148 
1149  // Get the condition codes directly from the status register, if its easy.
1150  // Otherwise a branch will be generated. Note that the AND and BIT
1151  // instructions generate different flags than CMP, the carry bit can be used
1152  // for NE/EQ.
1153  bool Invert = false;
1154  bool Shift = false;
1155  bool Convert = true;
1156  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1157  default:
1158  Convert = false;
1159  break;
1160  case MSP430CC::COND_HS:
1161  // Res = SR & 1, no processing is required
1162  break;
1163  case MSP430CC::COND_LO:
1164  // Res = ~(SR & 1)
1165  Invert = true;
1166  break;
1167  case MSP430CC::COND_NE:
1168  if (andCC) {
1169  // C = ~Z, thus Res = SR & 1, no processing is required
1170  } else {
1171  // Res = ~((SR >> 1) & 1)
1172  Shift = true;
1173  Invert = true;
1174  }
1175  break;
1176  case MSP430CC::COND_E:
1177  Shift = true;
1178  // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1179  // Res = (SR >> 1) & 1 is 1 word shorter.
1180  break;
1181  }
1182  EVT VT = Op.getValueType();
1183  SDValue One = DAG.getConstant(1, dl, VT);
1184  if (Convert) {
1185  SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1186  MVT::i16, Flag);
1187  if (Shift)
1188  // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1189  SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1190  SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1191  if (Invert)
1192  SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1193  return SR;
1194  } else {
1195  SDValue Zero = DAG.getConstant(0, dl, VT);
1196  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1197  SDValue Ops[] = {One, Zero, TargetCC, Flag};
1198  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1199  }
1200 }
1201 
1203  SelectionDAG &DAG) const {
1204  SDValue LHS = Op.getOperand(0);
1205  SDValue RHS = Op.getOperand(1);
1206  SDValue TrueV = Op.getOperand(2);
1207  SDValue FalseV = Op.getOperand(3);
1208  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1209  SDLoc dl (Op);
1210 
1211  SDValue TargetCC;
1212  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1213 
1214  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1215  SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1216 
1217  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1218 }
1219 
1221  SelectionDAG &DAG) const {
1222  SDValue Val = Op.getOperand(0);
1223  EVT VT = Op.getValueType();
1224  SDLoc dl(Op);
1225 
1226  assert(VT == MVT::i16 && "Only support i16 for now!");
1227 
1228  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1229  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1230  DAG.getValueType(Val.getValueType()));
1231 }
1232 
1233 SDValue
1235  MachineFunction &MF = DAG.getMachineFunction();
1237  int ReturnAddrIndex = FuncInfo->getRAIndex();
1238  auto PtrVT = getPointerTy(MF.getDataLayout());
1239 
1240  if (ReturnAddrIndex == 0) {
1241  // Set up a frame object for the return address.
1242  uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1243  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1244  true);
1245  FuncInfo->setRAIndex(ReturnAddrIndex);
1246  }
1247 
1248  return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1249 }
1250 
1252  SelectionDAG &DAG) const {
1254  MFI.setReturnAddressIsTaken(true);
1255 
1257  return SDValue();
1258 
1259  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1260  SDLoc dl(Op);
1261  auto PtrVT = getPointerTy(DAG.getDataLayout());
1262 
1263  if (Depth > 0) {
1264  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1265  SDValue Offset =
1267  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1268  DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1269  MachinePointerInfo());
1270  }
1271 
1272  // Just load the return address.
1273  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1274  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1275  MachinePointerInfo());
1276 }
1277 
1279  SelectionDAG &DAG) const {
1281  MFI.setFrameAddressIsTaken(true);
1282 
1283  EVT VT = Op.getValueType();
1284  SDLoc dl(Op); // FIXME probably not meaningful
1285  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1286  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1287  MSP430::FP, VT);
1288  while (Depth--)
1289  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1290  MachinePointerInfo());
1291  return FrameAddr;
1292 }
1293 
1295  SelectionDAG &DAG) const {
1296  MachineFunction &MF = DAG.getMachineFunction();
1298  auto PtrVT = getPointerTy(DAG.getDataLayout());
1299 
1300  // Frame index of first vararg argument
1302  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1303  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1304 
1305  // Create a store of the frame index to the location operand
1306  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1),
1307  MachinePointerInfo(SV));
1308 }
1309 
1311  SelectionDAG &DAG) const {
1312  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1313  auto PtrVT = getPointerTy(DAG.getDataLayout());
1314  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1315  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1316 }
1317 
1318 /// getPostIndexedAddressParts - returns true by value, base pointer and
1319 /// offset pointer and addressing mode by reference if this node can be
1320 /// combined with a load / store to form a post-indexed load / store.
1321 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1322  SDValue &Base,
1323  SDValue &Offset,
1324  ISD::MemIndexedMode &AM,
1325  SelectionDAG &DAG) const {
1326 
1327  LoadSDNode *LD = cast<LoadSDNode>(N);
1328  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1329  return false;
1330 
1331  EVT VT = LD->getMemoryVT();
1332  if (VT != MVT::i8 && VT != MVT::i16)
1333  return false;
1334 
1335  if (Op->getOpcode() != ISD::ADD)
1336  return false;
1337 
1338  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1339  uint64_t RHSC = RHS->getZExtValue();
1340  if ((VT == MVT::i16 && RHSC != 2) ||
1341  (VT == MVT::i8 && RHSC != 1))
1342  return false;
1343 
1344  Base = Op->getOperand(0);
1345  Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1346  AM = ISD::POST_INC;
1347  return true;
1348  }
1349 
1350  return false;
1351 }
1352 
1353 
1354 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1355  switch ((MSP430ISD::NodeType)Opcode) {
1356  case MSP430ISD::FIRST_NUMBER: break;
1357  case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1358  case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1359  case MSP430ISD::RRA: return "MSP430ISD::RRA";
1360  case MSP430ISD::RLA: return "MSP430ISD::RLA";
1361  case MSP430ISD::RRC: return "MSP430ISD::RRC";
1362  case MSP430ISD::RRCL: return "MSP430ISD::RRCL";
1363  case MSP430ISD::CALL: return "MSP430ISD::CALL";
1364  case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1365  case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1366  case MSP430ISD::CMP: return "MSP430ISD::CMP";
1367  case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1368  case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1369  case MSP430ISD::DADD: return "MSP430ISD::DADD";
1370  }
1371  return nullptr;
1372 }
1373 
1375  Type *Ty2) const {
1376  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1377  return false;
1378 
1379  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1380 }
1381 
1383  if (!VT1.isInteger() || !VT2.isInteger())
1384  return false;
1385 
1386  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1387 }
1388 
1390  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1391  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1392 }
1393 
1395  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1396  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1397 }
1398 
1400  return isZExtFree(Val.getValueType(), VT2);
1401 }
1402 
1403 //===----------------------------------------------------------------------===//
1404 // Other Lowering Code
1405 //===----------------------------------------------------------------------===//
1406 
1409  MachineBasicBlock *BB) const {
1410  MachineFunction *F = BB->getParent();
1411  MachineRegisterInfo &RI = F->getRegInfo();
1412  DebugLoc dl = MI.getDebugLoc();
1413  const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1414 
1415  unsigned Opc;
1416  bool ClearCarry = false;
1417  const TargetRegisterClass * RC;
1418  switch (MI.getOpcode()) {
1419  default: llvm_unreachable("Invalid shift opcode!");
1420  case MSP430::Shl8:
1421  Opc = MSP430::ADD8rr;
1422  RC = &MSP430::GR8RegClass;
1423  break;
1424  case MSP430::Shl16:
1425  Opc = MSP430::ADD16rr;
1426  RC = &MSP430::GR16RegClass;
1427  break;
1428  case MSP430::Sra8:
1429  Opc = MSP430::RRA8r;
1430  RC = &MSP430::GR8RegClass;
1431  break;
1432  case MSP430::Sra16:
1433  Opc = MSP430::RRA16r;
1434  RC = &MSP430::GR16RegClass;
1435  break;
1436  case MSP430::Srl8:
1437  ClearCarry = true;
1438  Opc = MSP430::RRC8r;
1439  RC = &MSP430::GR8RegClass;
1440  break;
1441  case MSP430::Srl16:
1442  ClearCarry = true;
1443  Opc = MSP430::RRC16r;
1444  RC = &MSP430::GR16RegClass;
1445  break;
1446  case MSP430::Rrcl8:
1447  case MSP430::Rrcl16: {
1448  BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1449  .addReg(MSP430::SR).addImm(1);
1450  unsigned SrcReg = MI.getOperand(1).getReg();
1451  unsigned DstReg = MI.getOperand(0).getReg();
1452  unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1453  ? MSP430::RRC16r : MSP430::RRC8r;
1454  BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1455  .addReg(SrcReg);
1456  MI.eraseFromParent(); // The pseudo instruction is gone now.
1457  return BB;
1458  }
1459  }
1460 
1461  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1463 
1464  // Create loop block
1465  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1466  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1467 
1468  F->insert(I, LoopBB);
1469  F->insert(I, RemBB);
1470 
1471  // Update machine-CFG edges by transferring all successors of the current
1472  // block to the block containing instructions after shift.
1473  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1474  BB->end());
1476 
1477  // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1478  BB->addSuccessor(LoopBB);
1479  BB->addSuccessor(RemBB);
1480  LoopBB->addSuccessor(RemBB);
1481  LoopBB->addSuccessor(LoopBB);
1482 
1483  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1484  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1485  unsigned ShiftReg = RI.createVirtualRegister(RC);
1486  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1487  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1488  unsigned SrcReg = MI.getOperand(1).getReg();
1489  unsigned DstReg = MI.getOperand(0).getReg();
1490 
1491  // BB:
1492  // cmp 0, N
1493  // je RemBB
1494  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1495  .addReg(ShiftAmtSrcReg).addImm(0);
1496  BuildMI(BB, dl, TII.get(MSP430::JCC))
1497  .addMBB(RemBB)
1499 
1500  // LoopBB:
1501  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1502  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1503  // ShiftReg2 = shift ShiftReg
1504  // ShiftAmt2 = ShiftAmt - 1;
1505  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1506  .addReg(SrcReg).addMBB(BB)
1507  .addReg(ShiftReg2).addMBB(LoopBB);
1508  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1509  .addReg(ShiftAmtSrcReg).addMBB(BB)
1510  .addReg(ShiftAmtReg2).addMBB(LoopBB);
1511  if (ClearCarry)
1512  BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1513  .addReg(MSP430::SR).addImm(1);
1514  if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1515  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1516  .addReg(ShiftReg)
1517  .addReg(ShiftReg);
1518  else
1519  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1520  .addReg(ShiftReg);
1521  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1522  .addReg(ShiftAmtReg).addImm(1);
1523  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1524  .addMBB(LoopBB)
1526 
1527  // RemBB:
1528  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1529  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1530  .addReg(SrcReg).addMBB(BB)
1531  .addReg(ShiftReg2).addMBB(LoopBB);
1532 
1533  MI.eraseFromParent(); // The pseudo instruction is gone now.
1534  return RemBB;
1535 }
1536 
1539  MachineBasicBlock *BB) const {
1540  unsigned Opc = MI.getOpcode();
1541 
1542  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1543  Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1544  Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1545  Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1546  return EmitShiftInstr(MI, BB);
1547 
1548  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1549  DebugLoc dl = MI.getDebugLoc();
1550 
1551  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1552  "Unexpected instr type to insert");
1553 
1554  // To "insert" a SELECT instruction, we actually have to insert the diamond
1555  // control-flow pattern. The incoming instruction knows the destination vreg
1556  // to set, the condition code register to branch on, the true/false values to
1557  // select between, and a branch opcode to use.
1558  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1560 
1561  // thisMBB:
1562  // ...
1563  // TrueVal = ...
1564  // cmpTY ccX, r1, r2
1565  // jCC copy1MBB
1566  // fallthrough --> copy0MBB
1567  MachineBasicBlock *thisMBB = BB;
1568  MachineFunction *F = BB->getParent();
1569  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1570  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1571  F->insert(I, copy0MBB);
1572  F->insert(I, copy1MBB);
1573  // Update machine-CFG edges by transferring all successors of the current
1574  // block to the new block which will contain the Phi node for the select.
1575  copy1MBB->splice(copy1MBB->begin(), BB,
1576  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1577  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1578  // Next, add the true and fallthrough blocks as its successors.
1579  BB->addSuccessor(copy0MBB);
1580  BB->addSuccessor(copy1MBB);
1581 
1582  BuildMI(BB, dl, TII.get(MSP430::JCC))
1583  .addMBB(copy1MBB)
1584  .addImm(MI.getOperand(3).getImm());
1585 
1586  // copy0MBB:
1587  // %FalseValue = ...
1588  // # fallthrough to copy1MBB
1589  BB = copy0MBB;
1590 
1591  // Update machine-CFG edges
1592  BB->addSuccessor(copy1MBB);
1593 
1594  // copy1MBB:
1595  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1596  // ...
1597  BB = copy1MBB;
1598  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1599  .addReg(MI.getOperand(2).getReg())
1600  .addMBB(copy0MBB)
1601  .addReg(MI.getOperand(1).getReg())
1602  .addMBB(thisMBB);
1603 
1604  MI.eraseFromParent(); // The pseudo instruction is gone now.
1605  return BB;
1606 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
Return with a flag operand. Operand 0 is the chain operand.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:836
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:650
This class represents lattice values for constants.
Definition: AllocatorList.h:24
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
void push_back(const T &Elt)
Definition: SmallVector.h:218
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
Y = RRC X, rotate right via carry.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:699
unsigned Reg
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
bool hasHWMult16() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned second
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
Calling convention used for special MSP430 rtlib functions which have an "optimized" convention using...
Definition: CallingConv.h:212
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:435
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool hasHWMult32() const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:579
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:456
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:840
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
amdgpu Simplify well known AMD library false Value Value const Twine & Name
const TargetRegisterInfo * getRegisterInfo() const override
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:410
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Rotate right via carry, carry gets cleared beforehand by clrc.
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:460
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:401
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:695
unsigned getSizeInBits() const
Same as RET_FLAG, but used for returning from ISRs.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:398
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
SmallVector< ISD::OutputArg, 32 > Outs
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it&#39;s free to truncate a value of type Ty1 to type Ty2...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:959
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
virtual const TargetInstrInfo * getInstrInfo() const
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:337
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getByValSize() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:728
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:629
const SDValue & getOperand(unsigned Num) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:824
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:115
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:82
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:719
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:53
This class contains a discriminated union of information about pointers in memory operands...
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:633
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
bool isVarArg() const
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1044
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:644
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
CallingConv::ID getCallingConv() const
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:413
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:679
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:941
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
EVT getMemoryVT() const
Return the type of the in-memory value.
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
unsigned getByValAlign() const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:420
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:468
bool hasHWMultF5() const
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:471
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:638
Representation of each machine instruction.
Definition: MachineInstr.h:64
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:724
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:673
SmallVector< SDValue, 32 > OutVals
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:387
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:705
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:486
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
SDValue getValue(unsigned R) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
CondCodes
Definition: MSP430.h:23
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Y = R{R,L}A X, rotate right (left) arithmetically.
void setReturnAddressIsTaken(bool s)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
LLVM Value Representation.
Definition: Value.h:73
SDValue getRegister(unsigned Reg, EVT VT)
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:251
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:443
Conversion operators.
Definition: ISDOpcodes.h:465
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:474
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
LLVMContext * getContext() const
Definition: SelectionDAG.h:407
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
Definition: CallingConv.h:106
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:622
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:914
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:380
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:623