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MSP430ISelLowering.h
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1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that MSP430 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
15 #define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
16 
17 #include "MSP430.h"
20 
21 namespace llvm {
22  namespace MSP430ISD {
23  enum NodeType : unsigned {
25 
26  /// Return with a flag operand. Operand 0 is the chain operand.
28 
29  /// Same as RET_FLAG, but used for returning from ISRs.
31 
32  /// Y = R{R,L}A X, rotate right (left) arithmetically
33  RRA, RLA,
34 
35  /// Y = RRC X, rotate right via carry
36  RRC,
37 
38  /// Rotate right via carry, carry gets cleared beforehand by clrc
40 
41  /// CALL - These operations represent an abstract call
42  /// instruction, which includes a bunch of information.
44 
45  /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
46  /// and TargetGlobalAddress.
48 
49  /// CMP - Compare instruction.
50  CMP,
51 
52  /// SetCC - Operand 0 is condition code, and operand 1 is the flag
53  /// operand produced by a CMP instruction.
55 
56  /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
57  /// is the block to branch if condition is true, operand 2 is the
58  /// condition code, and operand 3 is the flag operand produced by a CMP
59  /// instruction.
61 
62  /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
63  /// is condition code and operand 4 is flag operand.
65 
66  /// DADD - Decimal addition with carry
67  /// TODO Nothing generates a node of this type yet.
69  };
70  }
71 
72  class MSP430Subtarget;
74  public:
75  explicit MSP430TargetLowering(const TargetMachine &TM,
76  const MSP430Subtarget &STI);
77 
78  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
79  return MVT::i8;
80  }
81 
82  /// LowerOperation - Provide custom lowering hooks for some operations.
83  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
84 
85  /// getTargetNodeName - This method returns the name of a target specific
86  /// DAG node.
87  const char *getTargetNodeName(unsigned Opcode) const override;
88 
89  SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
93  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
94  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
99  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
100  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
101  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
102 
104  getConstraintType(StringRef Constraint) const override;
105  std::pair<unsigned, const TargetRegisterClass *>
106  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
107  StringRef Constraint, MVT VT) const override;
108 
109  /// isTruncateFree - Return true if it's free to truncate a value of type
110  /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
111  /// register R15W to i8 by referencing its sub-register R15B.
112  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
113  bool isTruncateFree(EVT VT1, EVT VT2) const override;
114 
115  /// isZExtFree - Return true if any actual instruction that defines a value
116  /// of type Ty1 implicit zero-extends the value to Ty2 in the result
117  /// register. This does not necessarily include registers defined in unknown
118  /// ways, such as incoming arguments, or copies from unknown virtual
119  /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
120  /// necessarily apply to truncate instructions. e.g. on msp430, all
121  /// instructions that define 8-bit values implicit zero-extend the result
122  /// out to 16 bits.
123  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
124  bool isZExtFree(EVT VT1, EVT VT2) const override;
125  bool isZExtFree(SDValue Val, EVT VT2) const override;
126 
128  EmitInstrWithCustomInserter(MachineInstr &MI,
129  MachineBasicBlock *BB) const override;
130  MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
131  MachineBasicBlock *BB) const;
132 
133  private:
134  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
135  CallingConv::ID CallConv, bool isVarArg,
136  bool isTailCall,
138  const SmallVectorImpl<SDValue> &OutVals,
140  const SDLoc &dl, SelectionDAG &DAG,
141  SmallVectorImpl<SDValue> &InVals) const;
142 
143  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
144  bool isVarArg,
146  const SDLoc &dl, SelectionDAG &DAG,
147  SmallVectorImpl<SDValue> &InVals) const;
148 
149  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
150  CallingConv::ID CallConv, bool isVarArg,
152  const SDLoc &dl, SelectionDAG &DAG,
153  SmallVectorImpl<SDValue> &InVals) const;
154 
155  SDValue
156  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
158  const SDLoc &dl, SelectionDAG &DAG,
159  SmallVectorImpl<SDValue> &InVals) const override;
160  SDValue
161  LowerCall(TargetLowering::CallLoweringInfo &CLI,
162  SmallVectorImpl<SDValue> &InVals) const override;
163 
164  bool CanLowerReturn(CallingConv::ID CallConv,
165  MachineFunction &MF,
166  bool IsVarArg,
168  LLVMContext &Context) const override;
169 
170  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
172  const SmallVectorImpl<SDValue> &OutVals,
173  const SDLoc &dl, SelectionDAG &DAG) const override;
174 
175  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
176  SDValue &Base,
177  SDValue &Offset,
179  SelectionDAG &DAG) const override;
180  };
181 } // namespace llvm
182 
183 #endif
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:914
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:112
Return with a flag operand. Operand 0 is the chain operand.
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MSP430 conditional branches.
static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
Y = RRC X, rotate right via carry.
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
unsigned const TargetRegisterInfo * TRI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Rotate right via carry, carry gets cleared beforehand by clrc.
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Same as RET_FLAG, but used for returning from ISRs.
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define N
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Y = R{R,L}A X, rotate right (left) arithmetically.
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:951