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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
34 
35 /// Class which stores all the state required in a MachineIRBuilder.
36 /// Since MachineIRBuilders will only store state in this object, it allows
37 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39  /// MachineFunction under construction.
41  /// Information used to access the description of the opcodes.
43  /// Information used to verify types are consistent and to create virtual registers.
45  /// Debug location to be set to any instruction we create.
47 
48  /// \name Fields describing the insertion point.
49  /// @{
52  /// @}
53 
55 
57 };
58 
59 class DstOp {
60  union {
62  unsigned Reg;
64  };
65 
66 public:
67  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
68  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
70  DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
72 
74  switch (Ty) {
75  case DstType::Ty_Reg:
76  MIB.addDef(Reg);
77  break;
78  case DstType::Ty_LLT:
79  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
80  break;
81  case DstType::Ty_RC:
82  MIB.addDef(MRI.createVirtualRegister(RC));
83  break;
84  }
85  }
86 
88  switch (Ty) {
89  case DstType::Ty_RC:
90  return LLT{};
91  case DstType::Ty_LLT:
92  return LLTTy;
93  case DstType::Ty_Reg:
94  return MRI.getType(Reg);
95  }
96  llvm_unreachable("Unrecognised DstOp::DstType enum");
97  }
98 
99  unsigned getReg() const {
100  assert(Ty == DstType::Ty_Reg && "Not a register");
101  return Reg;
102  }
103 
105  switch (Ty) {
106  case DstType::Ty_RC:
107  return RC;
108  default:
109  llvm_unreachable("Not a RC Operand");
110  }
111  }
112 
113  DstType getDstOpKind() const { return Ty; }
114 
115 private:
116  DstType Ty;
117 };
118 
119 class SrcOp {
120  union {
122  unsigned Reg;
124  };
125 
126 public:
127  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
128  SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}
129  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
130  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
131  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
132 
133  void addSrcToMIB(MachineInstrBuilder &MIB) const {
134  switch (Ty) {
135  case SrcType::Ty_Predicate:
136  MIB.addPredicate(Pred);
137  break;
138  case SrcType::Ty_Reg:
139  MIB.addUse(Reg);
140  break;
141  case SrcType::Ty_MIB:
142  MIB.addUse(SrcMIB->getOperand(0).getReg());
143  break;
144  }
145  }
146 
148  switch (Ty) {
149  case SrcType::Ty_Predicate:
150  llvm_unreachable("Not a register operand");
151  case SrcType::Ty_Reg:
152  return MRI.getType(Reg);
153  case SrcType::Ty_MIB:
154  return MRI.getType(SrcMIB->getOperand(0).getReg());
155  }
156  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
157  }
158 
159  unsigned getReg() const {
160  switch (Ty) {
161  case SrcType::Ty_Predicate:
162  llvm_unreachable("Not a register operand");
163  case SrcType::Ty_Reg:
164  return Reg;
165  case SrcType::Ty_MIB:
166  return SrcMIB->getOperand(0).getReg();
167  }
168  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
169  }
170 
172  switch (Ty) {
173  case SrcType::Ty_Predicate:
174  return Pred;
175  default:
176  llvm_unreachable("Not a register operand");
177  }
178  }
179 
180  SrcType getSrcOpKind() const { return Ty; }
181 
182 private:
183  SrcType Ty;
184 };
185 
186 class FlagsOp {
187  Optional<unsigned> Flags;
188 
189 public:
190  explicit FlagsOp(unsigned F) : Flags(F) {}
191  FlagsOp() : Flags(None) {}
192  Optional<unsigned> getFlags() const { return Flags; }
193 };
194 /// Helper class to build MachineInstr.
195 /// It keeps internally the insertion point and debug location for all
196 /// the new instructions we want to create.
197 /// This information can be modify via the related setters.
199 
200  MachineIRBuilderState State;
201 
202 protected:
203  void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
204 
205  void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
206  void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
207 
208  void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
209  const LLT &Op1Ty);
210  void recordInsertion(MachineInstr *MI) const;
211 
212 public:
213  /// Some constructors for easy use.
214  MachineIRBuilder() = default;
217  setInstr(MI);
218  }
219 
220  virtual ~MachineIRBuilder() = default;
221 
222  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
223 
225  assert(State.TII && "TargetInstrInfo is not set");
226  return *State.TII;
227  }
228 
229  /// Getter for the function we currently build.
231  assert(State.MF && "MachineFunction is not set");
232  return *State.MF;
233  }
234 
235  const MachineFunction &getMF() const {
236  assert(State.MF && "MachineFunction is not set");
237  return *State.MF;
238  }
239 
240  const DataLayout &getDataLayout() const {
241  return getMF().getFunction().getParent()->getDataLayout();
242  }
243 
244  /// Getter for DebugLoc
245  const DebugLoc &getDL() { return State.DL; }
246 
247  /// Getter for MRI
248  MachineRegisterInfo *getMRI() { return State.MRI; }
249  const MachineRegisterInfo *getMRI() const { return State.MRI; }
250 
251  /// Getter for the State
252  MachineIRBuilderState &getState() { return State; }
253 
254  /// Getter for the basic block we currently build.
255  const MachineBasicBlock &getMBB() const {
256  assert(State.MBB && "MachineBasicBlock is not set");
257  return *State.MBB;
258  }
259 
261  return const_cast<MachineBasicBlock &>(
262  const_cast<const MachineIRBuilder *>(this)->getMBB());
263  }
264 
265  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
266  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
267 
268  /// Current insertion point for new instructions.
270 
271  /// Set the insertion point before the specified position.
272  /// \pre MBB must be in getMF().
273  /// \pre II must be a valid iterator in MBB.
275  /// @}
276 
277  void setCSEInfo(GISelCSEInfo *Info);
278 
279  /// \name Setters for the insertion point.
280  /// @{
281  /// Set the MachineFunction where to build instructions.
282  void setMF(MachineFunction &MF);
283 
284  /// Set the insertion point to the end of \p MBB.
285  /// \pre \p MBB must be contained by getMF().
286  void setMBB(MachineBasicBlock &MBB);
287 
288  /// Set the insertion point to before MI.
289  /// \pre MI must be in getMF().
290  void setInstr(MachineInstr &MI);
291  /// @}
292 
293  void setChangeObserver(GISelChangeObserver &Observer);
294  void stopObservingChanges();
295  /// @}
296 
297  /// Set the debug location to \p DL for all the next build instructions.
298  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
299 
300  /// Get the current instruction's debug location.
301  DebugLoc getDebugLoc() { return State.DL; }
302 
303  /// Build and insert <empty> = \p Opcode <empty>.
304  /// The insertion point is the one set by the last call of either
305  /// setBasicBlock or setMI.
306  ///
307  /// \pre setBasicBlock or setMI must have been called.
308  ///
309  /// \return a MachineInstrBuilder for the newly created instruction.
310  MachineInstrBuilder buildInstr(unsigned Opcode);
311 
312  /// Build but don't insert <empty> = \p Opcode <empty>.
313  ///
314  /// \pre setMF, setBasicBlock or setMI must have been called.
315  ///
316  /// \return a MachineInstrBuilder for the newly created instruction.
317  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
318 
319  /// Insert an existing instruction at the insertion point.
320  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
321 
322  /// Build and insert a DBG_VALUE instruction expressing the fact that the
323  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
324  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
325  const MDNode *Expr);
326 
327  /// Build and insert a DBG_VALUE instruction expressing the fact that the
328  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
329  /// Expr).
330  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
331  const MDNode *Variable,
332  const MDNode *Expr);
333 
334  /// Build and insert a DBG_VALUE instruction expressing the fact that the
335  /// associated \p Variable lives in the stack slot specified by \p FI
336  /// (suitably modified by \p Expr).
337  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
338  const MDNode *Expr);
339 
340  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
341  /// given by \p C (suitably modified by \p Expr).
342  MachineInstrBuilder buildConstDbgValue(const Constant &C,
343  const MDNode *Variable,
344  const MDNode *Expr);
345 
346  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
347  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
348  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
349 
350  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
351  ///
352  /// G_FRAME_INDEX materializes the address of an alloca value or other
353  /// stack-based object.
354  ///
355  /// \pre setBasicBlock or setMI must have been called.
356  /// \pre \p Res must be a generic virtual register with pointer type.
357  ///
358  /// \return a MachineInstrBuilder for the newly created instruction.
359  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
360 
361  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
362  ///
363  /// G_GLOBAL_VALUE materializes the address of the specified global
364  /// into \p Res.
365  ///
366  /// \pre setBasicBlock or setMI must have been called.
367  /// \pre \p Res must be a generic virtual register with pointer type
368  /// in the same address space as \p GV.
369  ///
370  /// \return a MachineInstrBuilder for the newly created instruction.
371  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
372 
373 
374  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
375  ///
376  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
377  /// storing the resulting pointer in \p Res.
378  ///
379  /// \pre setBasicBlock or setMI must have been called.
380  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
381  /// type.
382  /// \pre \p Op1 must be a generic virtual register with scalar type.
383  ///
384  /// \return a MachineInstrBuilder for the newly created instruction.
385  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
386  unsigned Op1);
387 
388  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
389  ///
390  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
391  /// storing the resulting pointer in \p Res. If \p Value is zero then no
392  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
393  /// \p Res.
394  ///
395  /// \pre setBasicBlock or setMI must have been called.
396  /// \pre \p Op0 must be a generic virtual register with pointer type.
397  /// \pre \p ValueTy must be a scalar type.
398  /// \pre \p Res must be 0. This is to detect confusion between
399  /// materializeGEP() and buildGEP().
400  /// \post \p Res will either be a new generic virtual register of the same
401  /// type as \p Op0 or \p Op0 itself.
402  ///
403  /// \return a MachineInstrBuilder for the newly created instruction.
404  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
405  const LLT &ValueTy,
406  uint64_t Value);
407 
408  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
409  ///
410  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
411  /// pointer properties. This has the effect of rounding the address *down* to
412  /// a specified alignment in bits.
413  ///
414  /// \pre setBasicBlock or setMI must have been called.
415  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
416  /// type.
417  /// \pre \p NumBits must be an integer representing the number of low bits to
418  /// be cleared in \p Op0.
419  ///
420  /// \return a MachineInstrBuilder for the newly created instruction.
421  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
422  uint32_t NumBits);
423 
424  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
425  ///
426  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
427  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
428  ///
429  /// \pre setBasicBlock or setMI must have been called.
430  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
431  /// same scalar type.
432  ////\pre \p CarryOut must be generic virtual register with scalar type
433  ///(typically s1)
434  ///
435  /// \return The newly created instruction.
436  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
437  const SrcOp &Op0, const SrcOp &Op1);
438 
439  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
440  /// \p Op1, \p CarryIn
441  ///
442  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
443  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
444  /// arithmetic.
445  ///
446  /// \pre setBasicBlock or setMI must have been called.
447  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
448  /// with the same scalar type.
449  /// \pre \p CarryOut and \p CarryIn must be generic virtual
450  /// registers with the same scalar type (typically s1)
451  ///
452  /// \return The newly created instruction.
453  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
454  const SrcOp &Op0, const SrcOp &Op1,
455  const SrcOp &CarryIn);
456 
457  /// Build and insert \p Res = G_ANYEXT \p Op0
458  ///
459  /// G_ANYEXT produces a register of the specified width, with bits 0 to
460  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
461  /// (i.e. this is neither zero nor sign-extension). For a vector register,
462  /// each element is extended individually.
463  ///
464  /// \pre setBasicBlock or setMI must have been called.
465  /// \pre \p Res must be a generic virtual register with scalar or vector type.
466  /// \pre \p Op must be a generic virtual register with scalar or vector type.
467  /// \pre \p Op must be smaller than \p Res
468  ///
469  /// \return The newly created instruction.
470 
471  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
472 
473  /// Build and insert \p Res = G_SEXT \p Op
474  ///
475  /// G_SEXT produces a register of the specified width, with bits 0 to
476  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
477  /// high bit of \p Op (i.e. 2s-complement sign extended).
478  ///
479  /// \pre setBasicBlock or setMI must have been called.
480  /// \pre \p Res must be a generic virtual register with scalar or vector type.
481  /// \pre \p Op must be a generic virtual register with scalar or vector type.
482  /// \pre \p Op must be smaller than \p Res
483  ///
484  /// \return The newly created instruction.
485  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
486 
487  /// Build and insert a G_PTRTOINT instruction.
488  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
489  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
490  }
491 
492  /// Build and insert \p Dst = G_BITCAST \p Src
493  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
494  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
495  }
496 
497  /// \return The opcode of the extension the target wants to use for boolean
498  /// values.
499  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
500 
501  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
502  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
503  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
504  bool IsFP);
505 
506  /// Build and insert \p Res = G_ZEXT \p Op
507  ///
508  /// G_ZEXT produces a register of the specified width, with bits 0 to
509  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
510  /// register, each element is extended individually.
511  ///
512  /// \pre setBasicBlock or setMI must have been called.
513  /// \pre \p Res must be a generic virtual register with scalar or vector type.
514  /// \pre \p Op must be a generic virtual register with scalar or vector type.
515  /// \pre \p Op must be smaller than \p Res
516  ///
517  /// \return The newly created instruction.
518  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
519 
520  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
521  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
522  /// ///
523  /// \pre setBasicBlock or setMI must have been called.
524  /// \pre \p Res must be a generic virtual register with scalar or vector type.
525  /// \pre \p Op must be a generic virtual register with scalar or vector type.
526  ///
527  /// \return The newly created instruction.
528  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
529 
530  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
531  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
532  /// ///
533  /// \pre setBasicBlock or setMI must have been called.
534  /// \pre \p Res must be a generic virtual register with scalar or vector type.
535  /// \pre \p Op must be a generic virtual register with scalar or vector type.
536  ///
537  /// \return The newly created instruction.
538  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
539 
540  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
541  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
542  /// ///
543  /// \pre setBasicBlock or setMI must have been called.
544  /// \pre \p Res must be a generic virtual register with scalar or vector type.
545  /// \pre \p Op must be a generic virtual register with scalar or vector type.
546  ///
547  /// \return The newly created instruction.
548  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
549 
550  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
551  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
552  /// \p Op.
553  /// ///
554  /// \pre setBasicBlock or setMI must have been called.
555  /// \pre \p Res must be a generic virtual register with scalar or vector type.
556  /// \pre \p Op must be a generic virtual register with scalar or vector type.
557  ///
558  /// \return The newly created instruction.
559  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
560  const SrcOp &Op);
561 
562  /// Build and insert an appropriate cast between two registers of equal size.
563  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
564 
565  /// Build and insert G_BR \p Dest
566  ///
567  /// G_BR is an unconditional branch to \p Dest.
568  ///
569  /// \pre setBasicBlock or setMI must have been called.
570  ///
571  /// \return a MachineInstrBuilder for the newly created instruction.
572  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
573 
574  /// Build and insert G_BRCOND \p Tst, \p Dest
575  ///
576  /// G_BRCOND is a conditional branch to \p Dest.
577  ///
578  /// \pre setBasicBlock or setMI must have been called.
579  /// \pre \p Tst must be a generic virtual register with scalar
580  /// type. At the beginning of legalization, this will be a single
581  /// bit (s1). Targets with interesting flags registers may change
582  /// this. For a wider type, whether the branch is taken must only
583  /// depend on bit 0 (for now).
584  ///
585  /// \return The newly created instruction.
586  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
587 
588  /// Build and insert G_BRINDIRECT \p Tgt
589  ///
590  /// G_BRINDIRECT is an indirect branch to \p Tgt.
591  ///
592  /// \pre setBasicBlock or setMI must have been called.
593  /// \pre \p Tgt must be a generic virtual register with pointer type.
594  ///
595  /// \return a MachineInstrBuilder for the newly created instruction.
596  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
597 
598  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
599  ///
600  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
601  /// jump table index \p JTI and index \p IndexReg
602  ///
603  /// \pre setBasicBlock or setMI must have been called.
604  /// \pre \p TablePtr must be a generic virtual register with pointer type.
605  /// \pre \p JTI must be be a jump table index.
606  /// \pre \p IndexReg must be a generic virtual register with pointer type.
607  ///
608  /// \return a MachineInstrBuilder for the newly created instruction.
609  MachineInstrBuilder buildBrJT(unsigned TablePtr, unsigned JTI,
610  unsigned IndexReg);
611 
612  /// Build and insert \p Res = G_CONSTANT \p Val
613  ///
614  /// G_CONSTANT is an integer constant with the specified size and value. \p
615  /// Val will be extended or truncated to the size of \p Reg.
616  ///
617  /// \pre setBasicBlock or setMI must have been called.
618  /// \pre \p Res must be a generic virtual register with scalar or pointer
619  /// type.
620  ///
621  /// \return The newly created instruction.
622  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
623  const ConstantInt &Val);
624 
625  /// Build and insert \p Res = G_CONSTANT \p Val
626  ///
627  /// G_CONSTANT is an integer constant with the specified size and value.
628  ///
629  /// \pre setBasicBlock or setMI must have been called.
630  /// \pre \p Res must be a generic virtual register with scalar type.
631  ///
632  /// \return The newly created instruction.
633  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
634  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
635 
636  /// Build and insert \p Res = G_FCONSTANT \p Val
637  ///
638  /// G_FCONSTANT is a floating-point constant with the specified size and
639  /// value.
640  ///
641  /// \pre setBasicBlock or setMI must have been called.
642  /// \pre \p Res must be a generic virtual register with scalar type.
643  ///
644  /// \return The newly created instruction.
645  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
646  const ConstantFP &Val);
647 
648  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
649  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
650 
651  /// Build and insert \p Res = COPY Op
652  ///
653  /// Register-to-register COPY sets \p Res to \p Op.
654  ///
655  /// \pre setBasicBlock or setMI must have been called.
656  ///
657  /// \return a MachineInstrBuilder for the newly created instruction.
658  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
659 
660  /// Build and insert `Res = G_LOAD Addr, MMO`.
661  ///
662  /// Loads the value stored at \p Addr. Puts the result in \p Res.
663  ///
664  /// \pre setBasicBlock or setMI must have been called.
665  /// \pre \p Res must be a generic virtual register.
666  /// \pre \p Addr must be a generic virtual register with pointer type.
667  ///
668  /// \return a MachineInstrBuilder for the newly created instruction.
669  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
670  MachineMemOperand &MMO);
671 
672  /// Build and insert `Res = <opcode> Addr, MMO`.
673  ///
674  /// Loads the value stored at \p Addr. Puts the result in \p Res.
675  ///
676  /// \pre setBasicBlock or setMI must have been called.
677  /// \pre \p Res must be a generic virtual register.
678  /// \pre \p Addr must be a generic virtual register with pointer type.
679  ///
680  /// \return a MachineInstrBuilder for the newly created instruction.
681  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
682  unsigned Addr, MachineMemOperand &MMO);
683 
684  /// Build and insert `G_STORE Val, Addr, MMO`.
685  ///
686  /// Stores the value \p Val to \p Addr.
687  ///
688  /// \pre setBasicBlock or setMI must have been called.
689  /// \pre \p Val must be a generic virtual register.
690  /// \pre \p Addr must be a generic virtual register with pointer type.
691  ///
692  /// \return a MachineInstrBuilder for the newly created instruction.
693  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
694  MachineMemOperand &MMO);
695 
696  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
697  ///
698  /// \pre setBasicBlock or setMI must have been called.
699  /// \pre \p Res and \p Src must be generic virtual registers.
700  ///
701  /// \return a MachineInstrBuilder for the newly created instruction.
702  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
703 
704  /// Build and insert \p Res = IMPLICIT_DEF.
705  MachineInstrBuilder buildUndef(const DstOp &Res);
706 
707  /// Build and insert instructions to put \p Ops together at the specified p
708  /// Indices to form a larger register.
709  ///
710  /// If the types of the input registers are uniform and cover the entirity of
711  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
712  /// followed by a sequence of G_INSERT instructions.
713  ///
714  /// \pre setBasicBlock or setMI must have been called.
715  /// \pre The final element of the sequence must not extend past the end of the
716  /// destination register.
717  /// \pre The bits defined by each Op (derived from index and scalar size) must
718  /// not overlap.
719  /// \pre \p Indices must be in ascending order of bit position.
720  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
721  ArrayRef<uint64_t> Indices);
722 
723  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
724  ///
725  /// G_MERGE_VALUES combines the input elements contiguously into a larger
726  /// register.
727  ///
728  /// \pre setBasicBlock or setMI must have been called.
729  /// \pre The entire register \p Res (and no more) must be covered by the input
730  /// registers.
731  /// \pre The type of all \p Ops registers must be identical.
732  ///
733  /// \return a MachineInstrBuilder for the newly created instruction.
734  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<unsigned> Ops);
735 
736  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
737  ///
738  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
739  ///
740  /// \pre setBasicBlock or setMI must have been called.
741  /// \pre The entire register \p Res (and no more) must be covered by the input
742  /// registers.
743  /// \pre The type of all \p Res registers must be identical.
744  ///
745  /// \return a MachineInstrBuilder for the newly created instruction.
746  MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
747  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, const SrcOp &Op);
748 
749  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
750  MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
751 
752  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
753  ///
754  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
755  /// \pre setBasicBlock or setMI must have been called.
756  /// \pre The entire register \p Res (and no more) must be covered by the
757  /// input scalar registers.
758  /// \pre The type of all \p Ops registers must be identical.
759  ///
760  /// \return a MachineInstrBuilder for the newly created instruction.
761  MachineInstrBuilder buildBuildVector(const DstOp &Res,
762  ArrayRef<unsigned> Ops);
763 
764  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
765  /// the number of elements
766  MachineInstrBuilder buildSplatVector(const DstOp &Res,
767  const SrcOp &Src);
768 
769  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
770  ///
771  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
772  /// which have types larger than the destination vector element type, and
773  /// truncates the values to fit.
774  ///
775  /// If the operands given are already the same size as the vector elt type,
776  /// then this method will instead create a G_BUILD_VECTOR instruction.
777  ///
778  /// \pre setBasicBlock or setMI must have been called.
779  /// \pre The type of all \p Ops registers must be identical.
780  ///
781  /// \return a MachineInstrBuilder for the newly created instruction.
782  MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
783  ArrayRef<unsigned> Ops);
784 
785  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
786  ///
787  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
788  /// vectors.
789  ///
790  /// \pre setBasicBlock or setMI must have been called.
791  /// \pre The entire register \p Res (and no more) must be covered by the input
792  /// registers.
793  /// \pre The type of all source operands must be identical.
794  ///
795  /// \return a MachineInstrBuilder for the newly created instruction.
796  MachineInstrBuilder buildConcatVectors(const DstOp &Res,
797  ArrayRef<unsigned> Ops);
798 
799  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
800  unsigned Op, unsigned Index);
801 
802  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
803  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
804  /// result register definition unless \p Reg is NoReg (== 0). The second
805  /// operand will be the intrinsic's ID.
806  ///
807  /// Callers are expected to add the required definitions and uses afterwards.
808  ///
809  /// \pre setBasicBlock or setMI must have been called.
810  ///
811  /// \return a MachineInstrBuilder for the newly created instruction.
813  bool HasSideEffects);
814  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
815  bool HasSideEffects);
816 
817  /// Build and insert \p Res = G_FPTRUNC \p Op
818  ///
819  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
820  ///
821  /// \pre setBasicBlock or setMI must have been called.
822  /// \pre \p Res must be a generic virtual register with scalar or vector type.
823  /// \pre \p Op must be a generic virtual register with scalar or vector type.
824  /// \pre \p Res must be smaller than \p Op
825  ///
826  /// \return The newly created instruction.
827  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
828 
829  /// Build and insert \p Res = G_TRUNC \p Op
830  ///
831  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
832  /// truncated independently before being packed into the destination.
833  ///
834  /// \pre setBasicBlock or setMI must have been called.
835  /// \pre \p Res must be a generic virtual register with scalar or vector type.
836  /// \pre \p Op must be a generic virtual register with scalar or vector type.
837  /// \pre \p Res must be smaller than \p Op
838  ///
839  /// \return The newly created instruction.
840  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
841 
842  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
843  ///
844  /// \pre setBasicBlock or setMI must have been called.
845 
846  /// \pre \p Res must be a generic virtual register with scalar or
847  /// vector type. Typically this starts as s1 or <N x s1>.
848  /// \pre \p Op0 and Op1 must be generic virtual registers with the
849  /// same number of elements as \p Res. If \p Res is a scalar,
850  /// \p Op0 must be either a scalar or pointer.
851  /// \pre \p Pred must be an integer predicate.
852  ///
853  /// \return a MachineInstrBuilder for the newly created instruction.
854  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
855  const SrcOp &Op0, const SrcOp &Op1);
856 
857  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
858  ///
859  /// \pre setBasicBlock or setMI must have been called.
860 
861  /// \pre \p Res must be a generic virtual register with scalar or
862  /// vector type. Typically this starts as s1 or <N x s1>.
863  /// \pre \p Op0 and Op1 must be generic virtual registers with the
864  /// same number of elements as \p Res (or scalar, if \p Res is
865  /// scalar).
866  /// \pre \p Pred must be a floating-point predicate.
867  ///
868  /// \return a MachineInstrBuilder for the newly created instruction.
869  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
870  const SrcOp &Op0, const SrcOp &Op1);
871 
872  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
873  ///
874  /// \pre setBasicBlock or setMI must have been called.
875  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
876  /// with the same type.
877  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
878  /// vector type. If vector then it must have the same number of
879  /// elements as the other parameters.
880  ///
881  /// \return a MachineInstrBuilder for the newly created instruction.
882  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
883  const SrcOp &Op0, const SrcOp &Op1);
884 
885  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
886  /// \p Elt, \p Idx
887  ///
888  /// \pre setBasicBlock or setMI must have been called.
889  /// \pre \p Res and \p Val must be a generic virtual register
890  // with the same vector type.
891  /// \pre \p Elt and \p Idx must be a generic virtual register
892  /// with scalar type.
893  ///
894  /// \return The newly created instruction.
895  MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
896  const SrcOp &Val,
897  const SrcOp &Elt,
898  const SrcOp &Idx);
899 
900  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
901  ///
902  /// \pre setBasicBlock or setMI must have been called.
903  /// \pre \p Res must be a generic virtual register with scalar type.
904  /// \pre \p Val must be a generic virtual register with vector type.
905  /// \pre \p Idx must be a generic virtual register with scalar type.
906  ///
907  /// \return The newly created instruction.
908  MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
909  const SrcOp &Val,
910  const SrcOp &Idx);
911 
912  /// Build and insert `OldValRes<def>, SuccessRes<def> =
913  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
914  ///
915  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
916  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
917  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
918  ///
919  /// \pre setBasicBlock or setMI must have been called.
920  /// \pre \p OldValRes must be a generic virtual register of scalar type.
921  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
922  /// will be assigned 0 on failure and 1 on success.
923  /// \pre \p Addr must be a generic virtual register with pointer type.
924  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
925  /// registers of the same type.
926  ///
927  /// \return a MachineInstrBuilder for the newly created instruction.
929  buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
930  unsigned Addr, unsigned CmpVal, unsigned NewVal,
931  MachineMemOperand &MMO);
932 
933  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
934  /// MMO`.
935  ///
936  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
937  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
938  /// Addr in \p Res.
939  ///
940  /// \pre setBasicBlock or setMI must have been called.
941  /// \pre \p OldValRes must be a generic virtual register of scalar type.
942  /// \pre \p Addr must be a generic virtual register with pointer type.
943  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
944  /// registers of the same type.
945  ///
946  /// \return a MachineInstrBuilder for the newly created instruction.
947  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
948  unsigned CmpVal, unsigned NewVal,
949  MachineMemOperand &MMO);
950 
951  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
952  ///
953  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
954  /// original value from \p Addr in \p OldValRes. The modification is
955  /// determined by the opcode.
956  ///
957  /// \pre setBasicBlock or setMI must have been called.
958  /// \pre \p OldValRes must be a generic virtual register.
959  /// \pre \p Addr must be a generic virtual register with pointer type.
960  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
961  /// same type.
962  ///
963  /// \return a MachineInstrBuilder for the newly created instruction.
964  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
965  unsigned Addr, unsigned Val,
966  MachineMemOperand &MMO);
967 
968  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
969  ///
970  /// Atomically replace the value at \p Addr with \p Val. Puts the original
971  /// value from \p Addr in \p OldValRes.
972  ///
973  /// \pre setBasicBlock or setMI must have been called.
974  /// \pre \p OldValRes must be a generic virtual register.
975  /// \pre \p Addr must be a generic virtual register with pointer type.
976  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
977  /// same type.
978  ///
979  /// \return a MachineInstrBuilder for the newly created instruction.
980  MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
981  unsigned Val, MachineMemOperand &MMO);
982 
983  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
984  ///
985  /// Atomically replace the value at \p Addr with the addition of \p Val and
986  /// the original value. Puts the original value from \p Addr in \p OldValRes.
987  ///
988  /// \pre setBasicBlock or setMI must have been called.
989  /// \pre \p OldValRes must be a generic virtual register.
990  /// \pre \p Addr must be a generic virtual register with pointer type.
991  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
992  /// same type.
993  ///
994  /// \return a MachineInstrBuilder for the newly created instruction.
995  MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
996  unsigned Val, MachineMemOperand &MMO);
997 
998  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
999  ///
1000  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1001  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1002  ///
1003  /// \pre setBasicBlock or setMI must have been called.
1004  /// \pre \p OldValRes must be a generic virtual register.
1005  /// \pre \p Addr must be a generic virtual register with pointer type.
1006  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1007  /// same type.
1008  ///
1009  /// \return a MachineInstrBuilder for the newly created instruction.
1010  MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
1011  unsigned Val, MachineMemOperand &MMO);
1012 
1013  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1014  ///
1015  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1016  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1017  ///
1018  /// \pre setBasicBlock or setMI must have been called.
1019  /// \pre \p OldValRes must be a generic virtual register.
1020  /// \pre \p Addr must be a generic virtual register with pointer type.
1021  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1022  /// same type.
1023  ///
1024  /// \return a MachineInstrBuilder for the newly created instruction.
1025  MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
1026  unsigned Val, MachineMemOperand &MMO);
1027 
1028  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1029  ///
1030  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1031  /// and the original value. Puts the original value from \p Addr in \p
1032  /// OldValRes.
1033  ///
1034  /// \pre setBasicBlock or setMI must have been called.
1035  /// \pre \p OldValRes must be a generic virtual register.
1036  /// \pre \p Addr must be a generic virtual register with pointer type.
1037  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1038  /// same type.
1039  ///
1040  /// \return a MachineInstrBuilder for the newly created instruction.
1041  MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
1042  unsigned Val, MachineMemOperand &MMO);
1043 
1044  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1045  ///
1046  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1047  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1048  ///
1049  /// \pre setBasicBlock or setMI must have been called.
1050  /// \pre \p OldValRes must be a generic virtual register.
1051  /// \pre \p Addr must be a generic virtual register with pointer type.
1052  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1053  /// same type.
1054  ///
1055  /// \return a MachineInstrBuilder for the newly created instruction.
1056  MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
1057  unsigned Val, MachineMemOperand &MMO);
1058 
1059  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1060  ///
1061  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1062  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1063  ///
1064  /// \pre setBasicBlock or setMI must have been called.
1065  /// \pre \p OldValRes must be a generic virtual register.
1066  /// \pre \p Addr must be a generic virtual register with pointer type.
1067  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1068  /// same type.
1069  ///
1070  /// \return a MachineInstrBuilder for the newly created instruction.
1071  MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
1072  unsigned Val, MachineMemOperand &MMO);
1073 
1074  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1075  ///
1076  /// Atomically replace the value at \p Addr with the signed maximum of \p
1077  /// Val and the original value. Puts the original value from \p Addr in \p
1078  /// OldValRes.
1079  ///
1080  /// \pre setBasicBlock or setMI must have been called.
1081  /// \pre \p OldValRes must be a generic virtual register.
1082  /// \pre \p Addr must be a generic virtual register with pointer type.
1083  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1084  /// same type.
1085  ///
1086  /// \return a MachineInstrBuilder for the newly created instruction.
1087  MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
1088  unsigned Val, MachineMemOperand &MMO);
1089 
1090  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1091  ///
1092  /// Atomically replace the value at \p Addr with the signed minimum of \p
1093  /// Val and the original value. Puts the original value from \p Addr in \p
1094  /// OldValRes.
1095  ///
1096  /// \pre setBasicBlock or setMI must have been called.
1097  /// \pre \p OldValRes must be a generic virtual register.
1098  /// \pre \p Addr must be a generic virtual register with pointer type.
1099  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1100  /// same type.
1101  ///
1102  /// \return a MachineInstrBuilder for the newly created instruction.
1103  MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
1104  unsigned Val, MachineMemOperand &MMO);
1105 
1106  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1107  ///
1108  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1109  /// Val and the original value. Puts the original value from \p Addr in \p
1110  /// OldValRes.
1111  ///
1112  /// \pre setBasicBlock or setMI must have been called.
1113  /// \pre \p OldValRes must be a generic virtual register.
1114  /// \pre \p Addr must be a generic virtual register with pointer type.
1115  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1116  /// same type.
1117  ///
1118  /// \return a MachineInstrBuilder for the newly created instruction.
1119  MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
1120  unsigned Val, MachineMemOperand &MMO);
1121 
1122  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1123  ///
1124  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1125  /// Val and the original value. Puts the original value from \p Addr in \p
1126  /// OldValRes.
1127  ///
1128  /// \pre setBasicBlock or setMI must have been called.
1129  /// \pre \p OldValRes must be a generic virtual register.
1130  /// \pre \p Addr must be a generic virtual register with pointer type.
1131  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1132  /// same type.
1133  ///
1134  /// \return a MachineInstrBuilder for the newly created instruction.
1135  MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
1136  unsigned Val, MachineMemOperand &MMO);
1137 
1138  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1139  ///
1140  /// G_BLOCK_ADDR computes the address of a basic block.
1141  ///
1142  /// \pre setBasicBlock or setMI must have been called.
1143  /// \pre \p Res must be a generic virtual register of a pointer type.
1144  ///
1145  /// \return The newly created instruction.
1146  MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
1147 
1148  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1149  ///
1150  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1151  /// truncated to their width.
1152  ///
1153  /// \pre setBasicBlock or setMI must have been called.
1154  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1155  /// with the same (scalar or vector) type).
1156  ///
1157  /// \return a MachineInstrBuilder for the newly created instruction.
1158 
1159  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1160  const SrcOp &Src1,
1161  Optional<unsigned> Flags = None) {
1162  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1163  }
1164 
1165  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1166  ///
1167  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1168  /// truncated to their width.
1169  ///
1170  /// \pre setBasicBlock or setMI must have been called.
1171  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1172  /// with the same (scalar or vector) type).
1173  ///
1174  /// \return a MachineInstrBuilder for the newly created instruction.
1175 
1176  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1177  const SrcOp &Src1,
1178  Optional<unsigned> Flags = None) {
1179  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1180  }
1181 
1182  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1183  ///
1184  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1185  /// truncated to their width.
1186  ///
1187  /// \pre setBasicBlock or setMI must have been called.
1188  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1189  /// with the same (scalar or vector) type).
1190  ///
1191  /// \return a MachineInstrBuilder for the newly created instruction.
1192  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1193  const SrcOp &Src1,
1194  Optional<unsigned> Flags = None) {
1195  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1196  }
1197 
1198  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1199  const SrcOp &Src1,
1200  Optional<unsigned> Flags = None) {
1201  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1202  }
1203 
1204  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1205  const SrcOp &Src1,
1206  Optional<unsigned> Flags = None) {
1207  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1208  }
1209 
1210  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1211  const SrcOp &Src1,
1212  Optional<unsigned> Flags = None) {
1213  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1214  }
1215 
1216  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1217  const SrcOp &Src1,
1218  Optional<unsigned> Flags = None) {
1219  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1220  }
1221 
1222  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1223  const SrcOp &Src1,
1224  Optional<unsigned> Flags = None) {
1225  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1226  }
1227 
1228  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1229  ///
1230  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1231  /// Op1.
1232  ///
1233  /// \pre setBasicBlock or setMI must have been called.
1234  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1235  /// with the same (scalar or vector) type).
1236  ///
1237  /// \return a MachineInstrBuilder for the newly created instruction.
1238 
1239  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1240  const SrcOp &Src1) {
1241  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1242  }
1243 
1244  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1245  ///
1246  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1247  /// Op1.
1248  ///
1249  /// \pre setBasicBlock or setMI must have been called.
1250  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1251  /// with the same (scalar or vector) type).
1252  ///
1253  /// \return a MachineInstrBuilder for the newly created instruction.
1254  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1255  const SrcOp &Src1) {
1256  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1257  }
1258 
1259  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1260  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1261  const SrcOp &Src1) {
1262  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1263  }
1264 
1265  /// Build and insert a bitwise not,
1266  /// \p NegOne = G_CONSTANT -1
1267  /// \p Res = G_OR \p Op0, NegOne
1268  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1269  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1270  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1271  }
1272 
1273  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1274  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1275  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1276  }
1277 
1278  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1279  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1280  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1281  }
1282 
1283  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1285  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1286  }
1287 
1288  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1289  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1290  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1291  }
1292 
1293  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1295  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1296  }
1297 
1298  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1299  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1300  const SrcOp &Src1) {
1301  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1});
1302  }
1303 
1304  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1305  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1306  const SrcOp &Src1) {
1307  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});
1308  }
1309 
1310  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1311  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1312  const SrcOp &Src1, const SrcOp &Src2) {
1313  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2});
1314  }
1315 
1316  /// Build and insert \p Res = G_FNEG \p Op0
1317  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0) {
1318  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0});
1319  }
1320 
1321  /// Build and insert \p Res = G_FABS \p Op0
1322  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0) {
1323  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0});
1324  }
1325 
1326  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1328  const SrcOp &Src1) {
1329  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1330  }
1331 
1332  /// Build and insert \p Res = G_UITOFP \p Src0
1333  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1334  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1335  }
1336 
1337  /// Build and insert \p Res = G_SITOFP \p Src0
1338  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1339  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1340  }
1341 
1342  /// Build and insert \p Res = G_FPTOUI \p Src0
1343  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1344  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1345  }
1346 
1347  /// Build and insert \p Res = G_FPTOSI \p Src0
1348  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1349  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1350  }
1351 
1352  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1353  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1354  const SrcOp &Src1) {
1355  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1356  }
1357 
1358  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1359  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1360  const SrcOp &Src1) {
1361  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1362  }
1363 
1364  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1365  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1366  const SrcOp &Src1) {
1367  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1368  }
1369 
1370  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1371  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1372  const SrcOp &Src1) {
1373  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1374  }
1375 
1376  /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1377  ///
1378  /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1379  /// the jump table index \p JTI.
1380  ///
1381  /// \return a MachineInstrBuilder for the newly created instruction.
1382  MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1383 
1384  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1385  ArrayRef<SrcOp> SrcOps,
1386  Optional<unsigned> Flags = None);
1387 };
1388 
1389 } // End namespace llvm.
1390 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineBasicBlock & getMBB()
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
CmpInst::Predicate Pred
unsigned getReg() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
DstType getDstOpKind() const
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
unsigned Reg
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
const MachineFunction & getMF() const
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
F(f)
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2)
Build and insert Res = G_FMA Op0, Op1, Op2.
The address of a basic block.
Definition: Constants.h:839
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
A description of a memory reference used in the backend.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
GISelCSEInfo * getCSEInfo()
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineBasicBlock::iterator II
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
DstOp(unsigned R)
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FSUB Op0, Op1.
SrcOp(const CmpInst::Predicate P)
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FNEG Op0.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
#define P(N)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
FlagsOp(unsigned F)
unsigned getReg() const
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Helper class to build MachineInstr.
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FADD Op0, Op1.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
DebugLoc DL
Debug location to be set to any instruction we create.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
DstOp(const MachineOperand &Op)
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
const GISelCSEInfo * getCSEInfo() const
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
SrcOp(const MachineOperand &Op)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
DstOp(const LLT &T)
Representation of each machine instruction.
Definition: MachineInstr.h:63
MachineIRBuilderState & getState()
Getter for the State.
SrcOp(unsigned R)
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
const TargetRegisterClass * getRegClass() const
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
CmpInst::Predicate getPredicate() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1389
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.