LLVM  10.0.0svn
MachineVerifier.cpp
Go to the documentation of this file.
1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Pass to verify generated machine code. The following is checked:
10 //
11 // Operand counts: All explicit operands must be present.
12 //
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
15 //
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
18 //
19 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
20 // command-line option -verify-machineinstrs, or by defining the environment
21 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
22 // the verifier errors.
23 //===----------------------------------------------------------------------===//
24 
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/DenseSet.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SetOperations.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringRef.h"
34 #include "llvm/ADT/Twine.h"
53 #include "llvm/CodeGen/StackMaps.h"
58 #include "llvm/IR/BasicBlock.h"
59 #include "llvm/IR/Function.h"
60 #include "llvm/IR/InlineAsm.h"
61 #include "llvm/IR/Instructions.h"
62 #include "llvm/MC/LaneBitmask.h"
63 #include "llvm/MC/MCAsmInfo.h"
64 #include "llvm/MC/MCInstrDesc.h"
65 #include "llvm/MC/MCRegisterInfo.h"
67 #include "llvm/Pass.h"
68 #include "llvm/Support/Casting.h"
74 #include <algorithm>
75 #include <cassert>
76 #include <cstddef>
77 #include <cstdint>
78 #include <iterator>
79 #include <string>
80 #include <utility>
81 
82 using namespace llvm;
83 
84 namespace {
85 
86  struct MachineVerifier {
87  MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
88 
89  unsigned verify(MachineFunction &MF);
90 
91  Pass *const PASS;
92  const char *Banner;
93  const MachineFunction *MF;
94  const TargetMachine *TM;
95  const TargetInstrInfo *TII;
96  const TargetRegisterInfo *TRI;
97  const MachineRegisterInfo *MRI;
98 
99  unsigned foundErrors;
100 
101  // Avoid querying the MachineFunctionProperties for each operand.
102  bool isFunctionRegBankSelected;
103  bool isFunctionSelected;
104 
105  using RegVector = SmallVector<unsigned, 16>;
106  using RegMaskVector = SmallVector<const uint32_t *, 4>;
107  using RegSet = DenseSet<unsigned>;
110 
111  const MachineInstr *FirstNonPHI;
112  const MachineInstr *FirstTerminator;
113  BlockSet FunctionBlocks;
114 
115  BitVector regsReserved;
116  RegSet regsLive;
117  RegVector regsDefined, regsDead, regsKilled;
118  RegMaskVector regMasks;
119 
120  SlotIndex lastIndex;
121 
122  // Add Reg and any sub-registers to RV
123  void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
124  RV.push_back(Reg);
126  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
127  RV.push_back(*SubRegs);
128  }
129 
130  struct BBInfo {
131  // Is this MBB reachable from the MF entry point?
132  bool reachable = false;
133 
134  // Vregs that must be live in because they are used without being
135  // defined. Map value is the user.
136  RegMap vregsLiveIn;
137 
138  // Regs killed in MBB. They may be defined again, and will then be in both
139  // regsKilled and regsLiveOut.
140  RegSet regsKilled;
141 
142  // Regs defined in MBB and live out. Note that vregs passing through may
143  // be live out without being mentioned here.
144  RegSet regsLiveOut;
145 
146  // Vregs that pass through MBB untouched. This set is disjoint from
147  // regsKilled and regsLiveOut.
148  RegSet vregsPassed;
149 
150  // Vregs that must pass through MBB because they are needed by a successor
151  // block. This set is disjoint from regsLiveOut.
152  RegSet vregsRequired;
153 
154  // Set versions of block's predecessor and successor lists.
155  BlockSet Preds, Succs;
156 
157  BBInfo() = default;
158 
159  // Add register to vregsPassed if it belongs there. Return true if
160  // anything changed.
161  bool addPassed(unsigned Reg) {
162  if (!Register::isVirtualRegister(Reg))
163  return false;
164  if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
165  return false;
166  return vregsPassed.insert(Reg).second;
167  }
168 
169  // Same for a full set.
170  bool addPassed(const RegSet &RS) {
171  bool changed = false;
172  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
173  if (addPassed(*I))
174  changed = true;
175  return changed;
176  }
177 
178  // Add register to vregsRequired if it belongs there. Return true if
179  // anything changed.
180  bool addRequired(unsigned Reg) {
181  if (!Register::isVirtualRegister(Reg))
182  return false;
183  if (regsLiveOut.count(Reg))
184  return false;
185  return vregsRequired.insert(Reg).second;
186  }
187 
188  // Same for a full set.
189  bool addRequired(const RegSet &RS) {
190  bool changed = false;
191  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
192  if (addRequired(*I))
193  changed = true;
194  return changed;
195  }
196 
197  // Same for a full map.
198  bool addRequired(const RegMap &RM) {
199  bool changed = false;
200  for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
201  if (addRequired(I->first))
202  changed = true;
203  return changed;
204  }
205 
206  // Live-out registers are either in regsLiveOut or vregsPassed.
207  bool isLiveOut(unsigned Reg) const {
208  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
209  }
210  };
211 
212  // Extra register info per MBB.
214 
215  bool isReserved(unsigned Reg) {
216  return Reg < regsReserved.size() && regsReserved.test(Reg);
217  }
218 
219  bool isAllocatable(unsigned Reg) const {
220  return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
221  !regsReserved.test(Reg);
222  }
223 
224  // Analysis information if available
225  LiveVariables *LiveVars;
226  LiveIntervals *LiveInts;
227  LiveStacks *LiveStks;
228  SlotIndexes *Indexes;
229 
230  void visitMachineFunctionBefore();
231  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
232  void visitMachineBundleBefore(const MachineInstr *MI);
233 
234  bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
235  void verifyPreISelGenericInstruction(const MachineInstr *MI);
236  void visitMachineInstrBefore(const MachineInstr *MI);
237  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
238  void visitMachineInstrAfter(const MachineInstr *MI);
239  void visitMachineBundleAfter(const MachineInstr *MI);
240  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
241  void visitMachineFunctionAfter();
242 
243  void report(const char *msg, const MachineFunction *MF);
244  void report(const char *msg, const MachineBasicBlock *MBB);
245  void report(const char *msg, const MachineInstr *MI);
246  void report(const char *msg, const MachineOperand *MO, unsigned MONum,
247  LLT MOVRegType = LLT{});
248 
249  void report_context(const LiveInterval &LI) const;
250  void report_context(const LiveRange &LR, unsigned VRegUnit,
251  LaneBitmask LaneMask) const;
252  void report_context(const LiveRange::Segment &S) const;
253  void report_context(const VNInfo &VNI) const;
254  void report_context(SlotIndex Pos) const;
255  void report_context(MCPhysReg PhysReg) const;
256  void report_context_liverange(const LiveRange &LR) const;
257  void report_context_lanemask(LaneBitmask LaneMask) const;
258  void report_context_vreg(unsigned VReg) const;
259  void report_context_vreg_regunit(unsigned VRegOrUnit) const;
260 
261  void verifyInlineAsm(const MachineInstr *MI);
262 
263  void checkLiveness(const MachineOperand *MO, unsigned MONum);
264  void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
265  SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
266  LaneBitmask LaneMask = LaneBitmask::getNone());
267  void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
268  SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
269  bool SubRangeCheck = false,
270  LaneBitmask LaneMask = LaneBitmask::getNone());
271 
272  void markReachable(const MachineBasicBlock *MBB);
273  void calcRegsPassed();
274  void checkPHIOps(const MachineBasicBlock &MBB);
275 
276  void calcRegsRequired();
277  void verifyLiveVariables();
278  void verifyLiveIntervals();
279  void verifyLiveInterval(const LiveInterval&);
280  void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
281  LaneBitmask);
282  void verifyLiveRangeSegment(const LiveRange&,
283  const LiveRange::const_iterator I, unsigned,
284  LaneBitmask);
285  void verifyLiveRange(const LiveRange&, unsigned,
286  LaneBitmask LaneMask = LaneBitmask::getNone());
287 
288  void verifyStackFrame();
289 
290  void verifySlotIndexes() const;
291  void verifyProperties(const MachineFunction &MF);
292  };
293 
294  struct MachineVerifierPass : public MachineFunctionPass {
295  static char ID; // Pass ID, replacement for typeid
296 
297  const std::string Banner;
298 
299  MachineVerifierPass(std::string banner = std::string())
300  : MachineFunctionPass(ID), Banner(std::move(banner)) {
302  }
303 
304  void getAnalysisUsage(AnalysisUsage &AU) const override {
305  AU.setPreservesAll();
307  }
308 
309  bool runOnMachineFunction(MachineFunction &MF) override {
310  unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
311  if (FoundErrors)
312  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
313  return false;
314  }
315  };
316 
317 } // end anonymous namespace
318 
319 char MachineVerifierPass::ID = 0;
320 
321 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
322  "Verify generated machine code", false, false)
323 
325  return new MachineVerifierPass(Banner);
326 }
327 
328 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
329  const {
330  MachineFunction &MF = const_cast<MachineFunction&>(*this);
331  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
332  if (AbortOnErrors && FoundErrors)
333  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
334  return FoundErrors == 0;
335 }
336 
337 void MachineVerifier::verifySlotIndexes() const {
338  if (Indexes == nullptr)
339  return;
340 
341  // Ensure the IdxMBB list is sorted by slot indexes.
342  SlotIndex Last;
344  E = Indexes->MBBIndexEnd(); I != E; ++I) {
345  assert(!Last.isValid() || I->first > Last);
346  Last = I->first;
347  }
348 }
349 
350 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
351  // If a pass has introduced virtual registers without clearing the
352  // NoVRegs property (or set it without allocating the vregs)
353  // then report an error.
354  if (MF.getProperties().hasProperty(
356  MRI->getNumVirtRegs())
357  report("Function has NoVRegs property but there are VReg operands", &MF);
358 }
359 
361  foundErrors = 0;
362 
363  this->MF = &MF;
364  TM = &MF.getTarget();
365  TII = MF.getSubtarget().getInstrInfo();
366  TRI = MF.getSubtarget().getRegisterInfo();
367  MRI = &MF.getRegInfo();
368 
369  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
371 
372  // If we're mid-GlobalISel and we already triggered the fallback path then
373  // it's expected that the MIR is somewhat broken but that's ok since we'll
374  // reset it and clear the FailedISel attribute in ResetMachineFunctions.
375  if (isFunctionFailedISel)
376  return foundErrors;
377 
378  isFunctionRegBankSelected =
379  !isFunctionFailedISel &&
382  isFunctionSelected = !isFunctionFailedISel &&
385  LiveVars = nullptr;
386  LiveInts = nullptr;
387  LiveStks = nullptr;
388  Indexes = nullptr;
389  if (PASS) {
390  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
391  // We don't want to verify LiveVariables if LiveIntervals is available.
392  if (!LiveInts)
393  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
394  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
395  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
396  }
397 
398  verifySlotIndexes();
399 
400  verifyProperties(MF);
401 
402  visitMachineFunctionBefore();
403  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
404  MFI!=MFE; ++MFI) {
405  visitMachineBasicBlockBefore(&*MFI);
406  // Keep track of the current bundle header.
407  const MachineInstr *CurBundle = nullptr;
408  // Do we expect the next instruction to be part of the same bundle?
409  bool InBundle = false;
410 
411  for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
412  MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
413  if (MBBI->getParent() != &*MFI) {
414  report("Bad instruction parent pointer", &*MFI);
415  errs() << "Instruction: " << *MBBI;
416  continue;
417  }
418 
419  // Check for consistent bundle flags.
420  if (InBundle && !MBBI->isBundledWithPred())
421  report("Missing BundledPred flag, "
422  "BundledSucc was set on predecessor",
423  &*MBBI);
424  if (!InBundle && MBBI->isBundledWithPred())
425  report("BundledPred flag is set, "
426  "but BundledSucc not set on predecessor",
427  &*MBBI);
428 
429  // Is this a bundle header?
430  if (!MBBI->isInsideBundle()) {
431  if (CurBundle)
432  visitMachineBundleAfter(CurBundle);
433  CurBundle = &*MBBI;
434  visitMachineBundleBefore(CurBundle);
435  } else if (!CurBundle)
436  report("No bundle header", &*MBBI);
437  visitMachineInstrBefore(&*MBBI);
438  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
439  const MachineInstr &MI = *MBBI;
440  const MachineOperand &Op = MI.getOperand(I);
441  if (Op.getParent() != &MI) {
442  // Make sure to use correct addOperand / RemoveOperand / ChangeTo
443  // functions when replacing operands of a MachineInstr.
444  report("Instruction has operand with wrong parent set", &MI);
445  }
446 
447  visitMachineOperand(&Op, I);
448  }
449 
450  visitMachineInstrAfter(&*MBBI);
451 
452  // Was this the last bundled instruction?
453  InBundle = MBBI->isBundledWithSucc();
454  }
455  if (CurBundle)
456  visitMachineBundleAfter(CurBundle);
457  if (InBundle)
458  report("BundledSucc flag set on last instruction in block", &MFI->back());
459  visitMachineBasicBlockAfter(&*MFI);
460  }
461  visitMachineFunctionAfter();
462 
463  // Clean up.
464  regsLive.clear();
465  regsDefined.clear();
466  regsDead.clear();
467  regsKilled.clear();
468  regMasks.clear();
469  MBBInfoMap.clear();
470 
471  return foundErrors;
472 }
473 
474 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
475  assert(MF);
476  errs() << '\n';
477  if (!foundErrors++) {
478  if (Banner)
479  errs() << "# " << Banner << '\n';
480  if (LiveInts != nullptr)
481  LiveInts->print(errs());
482  else
483  MF->print(errs(), Indexes);
484  }
485  errs() << "*** Bad machine code: " << msg << " ***\n"
486  << "- function: " << MF->getName() << "\n";
487 }
488 
489 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
490  assert(MBB);
491  report(msg, MBB->getParent());
492  errs() << "- basic block: " << printMBBReference(*MBB) << ' '
493  << MBB->getName() << " (" << (const void *)MBB << ')';
494  if (Indexes)
495  errs() << " [" << Indexes->getMBBStartIdx(MBB)
496  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
497  errs() << '\n';
498 }
499 
500 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
501  assert(MI);
502  report(msg, MI->getParent());
503  errs() << "- instruction: ";
504  if (Indexes && Indexes->hasIndex(*MI))
505  errs() << Indexes->getInstructionIndex(*MI) << '\t';
506  MI->print(errs(), /*SkipOpers=*/true);
507 }
508 
509 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
510  unsigned MONum, LLT MOVRegType) {
511  assert(MO);
512  report(msg, MO->getParent());
513  errs() << "- operand " << MONum << ": ";
514  MO->print(errs(), MOVRegType, TRI);
515  errs() << "\n";
516 }
517 
518 void MachineVerifier::report_context(SlotIndex Pos) const {
519  errs() << "- at: " << Pos << '\n';
520 }
521 
522 void MachineVerifier::report_context(const LiveInterval &LI) const {
523  errs() << "- interval: " << LI << '\n';
524 }
525 
526 void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
527  LaneBitmask LaneMask) const {
528  report_context_liverange(LR);
529  report_context_vreg_regunit(VRegUnit);
530  if (LaneMask.any())
531  report_context_lanemask(LaneMask);
532 }
533 
534 void MachineVerifier::report_context(const LiveRange::Segment &S) const {
535  errs() << "- segment: " << S << '\n';
536 }
537 
538 void MachineVerifier::report_context(const VNInfo &VNI) const {
539  errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
540 }
541 
542 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
543  errs() << "- liverange: " << LR << '\n';
544 }
545 
546 void MachineVerifier::report_context(MCPhysReg PReg) const {
547  errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
548 }
549 
550 void MachineVerifier::report_context_vreg(unsigned VReg) const {
551  errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
552 }
553 
554 void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
555  if (Register::isVirtualRegister(VRegOrUnit)) {
556  report_context_vreg(VRegOrUnit);
557  } else {
558  errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
559  }
560 }
561 
562 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
563  errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
564 }
565 
566 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
567  BBInfo &MInfo = MBBInfoMap[MBB];
568  if (!MInfo.reachable) {
569  MInfo.reachable = true;
571  SuE = MBB->succ_end(); SuI != SuE; ++SuI)
572  markReachable(*SuI);
573  }
574 }
575 
576 void MachineVerifier::visitMachineFunctionBefore() {
577  lastIndex = SlotIndex();
578  regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
579  : TRI->getReservedRegs(*MF);
580 
581  if (!MF->empty())
582  markReachable(&MF->front());
583 
584  // Build a set of the basic blocks in the function.
585  FunctionBlocks.clear();
586  for (const auto &MBB : *MF) {
587  FunctionBlocks.insert(&MBB);
588  BBInfo &MInfo = MBBInfoMap[&MBB];
589 
590  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
591  if (MInfo.Preds.size() != MBB.pred_size())
592  report("MBB has duplicate entries in its predecessor list.", &MBB);
593 
594  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
595  if (MInfo.Succs.size() != MBB.succ_size())
596  report("MBB has duplicate entries in its successor list.", &MBB);
597  }
598 
599  // Check that the register use lists are sane.
600  MRI->verifyUseLists();
601 
602  if (!MF->empty())
603  verifyStackFrame();
604 }
605 
606 // Does iterator point to a and b as the first two elements?
608  const MachineBasicBlock *a, const MachineBasicBlock *b) {
609  if (*i == a)
610  return *++i == b;
611  if (*i == b)
612  return *++i == a;
613  return false;
614 }
615 
616 void
617 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
618  FirstTerminator = nullptr;
619  FirstNonPHI = nullptr;
620 
621  if (!MF->getProperties().hasProperty(
623  // If this block has allocatable physical registers live-in, check that
624  // it is an entry block or landing pad.
625  for (const auto &LI : MBB->liveins()) {
626  if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
627  MBB->getIterator() != MBB->getParent()->begin()) {
628  report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
629  report_context(LI.PhysReg);
630  }
631  }
632  }
633 
634  // Count the number of landing pad successors.
635  SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
637  E = MBB->succ_end(); I != E; ++I) {
638  if ((*I)->isEHPad())
639  LandingPadSuccs.insert(*I);
640  if (!FunctionBlocks.count(*I))
641  report("MBB has successor that isn't part of the function.", MBB);
642  if (!MBBInfoMap[*I].Preds.count(MBB)) {
643  report("Inconsistent CFG", MBB);
644  errs() << "MBB is not in the predecessor list of the successor "
645  << printMBBReference(*(*I)) << ".\n";
646  }
647  }
648 
649  // Check the predecessor list.
651  E = MBB->pred_end(); I != E; ++I) {
652  if (!FunctionBlocks.count(*I))
653  report("MBB has predecessor that isn't part of the function.", MBB);
654  if (!MBBInfoMap[*I].Succs.count(MBB)) {
655  report("Inconsistent CFG", MBB);
656  errs() << "MBB is not in the successor list of the predecessor "
657  << printMBBReference(*(*I)) << ".\n";
658  }
659  }
660 
661  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
662  const BasicBlock *BB = MBB->getBasicBlock();
663  const Function &F = MF->getFunction();
664  if (LandingPadSuccs.size() > 1 &&
665  !(AsmInfo &&
667  BB && isa<SwitchInst>(BB->getTerminator())) &&
669  report("MBB has more than one landing pad successor", MBB);
670 
671  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
672  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
674  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
675  Cond)) {
676  // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
677  // check whether its answers match up with reality.
678  if (!TBB && !FBB) {
679  // Block falls through to its successor.
681  ++MBBI;
682  if (MBBI == MF->end()) {
683  // It's possible that the block legitimately ends with a noreturn
684  // call or an unreachable, in which case it won't actually fall
685  // out the bottom of the function.
686  } else if (MBB->succ_size() == LandingPadSuccs.size()) {
687  // It's possible that the block legitimately ends with a noreturn
688  // call or an unreachable, in which case it won't actually fall
689  // out of the block.
690  } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
691  report("MBB exits via unconditional fall-through but doesn't have "
692  "exactly one CFG successor!", MBB);
693  } else if (!MBB->isSuccessor(&*MBBI)) {
694  report("MBB exits via unconditional fall-through but its successor "
695  "differs from its CFG successor!", MBB);
696  }
697  if (!MBB->empty() && MBB->back().isBarrier() &&
698  !TII->isPredicated(MBB->back())) {
699  report("MBB exits via unconditional fall-through but ends with a "
700  "barrier instruction!", MBB);
701  }
702  if (!Cond.empty()) {
703  report("MBB exits via unconditional fall-through but has a condition!",
704  MBB);
705  }
706  } else if (TBB && !FBB && Cond.empty()) {
707  // Block unconditionally branches somewhere.
708  // If the block has exactly one successor, that happens to be a
709  // landingpad, accept it as valid control flow.
710  if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
711  (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
712  *MBB->succ_begin() != *LandingPadSuccs.begin())) {
713  report("MBB exits via unconditional branch but doesn't have "
714  "exactly one CFG successor!", MBB);
715  } else if (!MBB->isSuccessor(TBB)) {
716  report("MBB exits via unconditional branch but the CFG "
717  "successor doesn't match the actual successor!", MBB);
718  }
719  if (MBB->empty()) {
720  report("MBB exits via unconditional branch but doesn't contain "
721  "any instructions!", MBB);
722  } else if (!MBB->back().isBarrier()) {
723  report("MBB exits via unconditional branch but doesn't end with a "
724  "barrier instruction!", MBB);
725  } else if (!MBB->back().isTerminator()) {
726  report("MBB exits via unconditional branch but the branch isn't a "
727  "terminator instruction!", MBB);
728  }
729  } else if (TBB && !FBB && !Cond.empty()) {
730  // Block conditionally branches somewhere, otherwise falls through.
732  ++MBBI;
733  if (MBBI == MF->end()) {
734  report("MBB conditionally falls through out of function!", MBB);
735  } else if (MBB->succ_size() == 1) {
736  // A conditional branch with only one successor is weird, but allowed.
737  if (&*MBBI != TBB)
738  report("MBB exits via conditional branch/fall-through but only has "
739  "one CFG successor!", MBB);
740  else if (TBB != *MBB->succ_begin())
741  report("MBB exits via conditional branch/fall-through but the CFG "
742  "successor don't match the actual successor!", MBB);
743  } else if (MBB->succ_size() != 2) {
744  report("MBB exits via conditional branch/fall-through but doesn't have "
745  "exactly two CFG successors!", MBB);
746  } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
747  report("MBB exits via conditional branch/fall-through but the CFG "
748  "successors don't match the actual successors!", MBB);
749  }
750  if (MBB->empty()) {
751  report("MBB exits via conditional branch/fall-through but doesn't "
752  "contain any instructions!", MBB);
753  } else if (MBB->back().isBarrier()) {
754  report("MBB exits via conditional branch/fall-through but ends with a "
755  "barrier instruction!", MBB);
756  } else if (!MBB->back().isTerminator()) {
757  report("MBB exits via conditional branch/fall-through but the branch "
758  "isn't a terminator instruction!", MBB);
759  }
760  } else if (TBB && FBB) {
761  // Block conditionally branches somewhere, otherwise branches
762  // somewhere else.
763  if (MBB->succ_size() == 1) {
764  // A conditional branch with only one successor is weird, but allowed.
765  if (FBB != TBB)
766  report("MBB exits via conditional branch/branch through but only has "
767  "one CFG successor!", MBB);
768  else if (TBB != *MBB->succ_begin())
769  report("MBB exits via conditional branch/branch through but the CFG "
770  "successor don't match the actual successor!", MBB);
771  } else if (MBB->succ_size() != 2) {
772  report("MBB exits via conditional branch/branch but doesn't have "
773  "exactly two CFG successors!", MBB);
774  } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
775  report("MBB exits via conditional branch/branch but the CFG "
776  "successors don't match the actual successors!", MBB);
777  }
778  if (MBB->empty()) {
779  report("MBB exits via conditional branch/branch but doesn't "
780  "contain any instructions!", MBB);
781  } else if (!MBB->back().isBarrier()) {
782  report("MBB exits via conditional branch/branch but doesn't end with a "
783  "barrier instruction!", MBB);
784  } else if (!MBB->back().isTerminator()) {
785  report("MBB exits via conditional branch/branch but the branch "
786  "isn't a terminator instruction!", MBB);
787  }
788  if (Cond.empty()) {
789  report("MBB exits via conditional branch/branch but there's no "
790  "condition!", MBB);
791  }
792  } else {
793  report("AnalyzeBranch returned invalid data!", MBB);
794  }
795  }
796 
797  regsLive.clear();
798  if (MRI->tracksLiveness()) {
799  for (const auto &LI : MBB->liveins()) {
800  if (!Register::isPhysicalRegister(LI.PhysReg)) {
801  report("MBB live-in list contains non-physical register", MBB);
802  continue;
803  }
804  for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
805  SubRegs.isValid(); ++SubRegs)
806  regsLive.insert(*SubRegs);
807  }
808  }
809 
810  const MachineFrameInfo &MFI = MF->getFrameInfo();
811  BitVector PR = MFI.getPristineRegs(*MF);
812  for (unsigned I : PR.set_bits()) {
813  for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
814  SubRegs.isValid(); ++SubRegs)
815  regsLive.insert(*SubRegs);
816  }
817 
818  regsKilled.clear();
819  regsDefined.clear();
820 
821  if (Indexes)
822  lastIndex = Indexes->getMBBStartIdx(MBB);
823 }
824 
825 // This function gets called for all bundle headers, including normal
826 // stand-alone unbundled instructions.
827 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
828  if (Indexes && Indexes->hasIndex(*MI)) {
829  SlotIndex idx = Indexes->getInstructionIndex(*MI);
830  if (!(idx > lastIndex)) {
831  report("Instruction index out of order", MI);
832  errs() << "Last instruction was at " << lastIndex << '\n';
833  }
834  lastIndex = idx;
835  }
836 
837  // Ensure non-terminators don't follow terminators.
838  // Ignore predicated terminators formed by if conversion.
839  // FIXME: If conversion shouldn't need to violate this rule.
840  if (MI->isTerminator() && !TII->isPredicated(*MI)) {
841  if (!FirstTerminator)
842  FirstTerminator = MI;
843  } else if (FirstTerminator && !MI->isDebugEntryValue()) {
844  report("Non-terminator instruction after the first terminator", MI);
845  errs() << "First terminator was:\t" << *FirstTerminator;
846  }
847 }
848 
849 // The operands on an INLINEASM instruction must follow a template.
850 // Verify that the flag operands make sense.
851 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
852  // The first two operands on INLINEASM are the asm string and global flags.
853  if (MI->getNumOperands() < 2) {
854  report("Too few operands on inline asm", MI);
855  return;
856  }
857  if (!MI->getOperand(0).isSymbol())
858  report("Asm string must be an external symbol", MI);
859  if (!MI->getOperand(1).isImm())
860  report("Asm flags must be an immediate", MI);
861  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
862  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
863  // and Extra_IsConvergent = 32.
864  if (!isUInt<6>(MI->getOperand(1).getImm()))
865  report("Unknown asm flags", &MI->getOperand(1), 1);
866 
867  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
868 
869  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
870  unsigned NumOps;
871  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
872  const MachineOperand &MO = MI->getOperand(OpNo);
873  // There may be implicit ops after the fixed operands.
874  if (!MO.isImm())
875  break;
876  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
877  }
878 
879  if (OpNo > MI->getNumOperands())
880  report("Missing operands in last group", MI);
881 
882  // An optional MDNode follows the groups.
883  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
884  ++OpNo;
885 
886  // All trailing operands must be implicit registers.
887  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
888  const MachineOperand &MO = MI->getOperand(OpNo);
889  if (!MO.isReg() || !MO.isImplicit())
890  report("Expected implicit register after groups", &MO, OpNo);
891  }
892 }
893 
894 /// Check that types are consistent when two operands need to have the same
895 /// number of vector elements.
896 /// \return true if the types are valid.
897 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
898  const MachineInstr *MI) {
899  if (Ty0.isVector() != Ty1.isVector()) {
900  report("operand types must be all-vector or all-scalar", MI);
901  // Generally we try to report as many issues as possible at once, but in
902  // this case it's not clear what should we be comparing the size of the
903  // scalar with: the size of the whole vector or its lane. Instead of
904  // making an arbitrary choice and emitting not so helpful message, let's
905  // avoid the extra noise and stop here.
906  return false;
907  }
908 
909  if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
910  report("operand types must preserve number of vector elements", MI);
911  return false;
912  }
913 
914  return true;
915 }
916 
917 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
918  if (isFunctionSelected)
919  report("Unexpected generic instruction in a Selected function", MI);
920 
921  const MCInstrDesc &MCID = MI->getDesc();
922  unsigned NumOps = MI->getNumOperands();
923 
924  // Check types.
925  SmallVector<LLT, 4> Types;
926  for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
927  I != E; ++I) {
928  if (!MCID.OpInfo[I].isGenericType())
929  continue;
930  // Generic instructions specify type equality constraints between some of
931  // their operands. Make sure these are consistent.
932  size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
933  Types.resize(std::max(TypeIdx + 1, Types.size()));
934 
935  const MachineOperand *MO = &MI->getOperand(I);
936  if (!MO->isReg()) {
937  report("generic instruction must use register operands", MI);
938  continue;
939  }
940 
941  LLT OpTy = MRI->getType(MO->getReg());
942  // Don't report a type mismatch if there is no actual mismatch, only a
943  // type missing, to reduce noise:
944  if (OpTy.isValid()) {
945  // Only the first valid type for a type index will be printed: don't
946  // overwrite it later so it's always clear which type was expected:
947  if (!Types[TypeIdx].isValid())
948  Types[TypeIdx] = OpTy;
949  else if (Types[TypeIdx] != OpTy)
950  report("Type mismatch in generic instruction", MO, I, OpTy);
951  } else {
952  // Generic instructions must have types attached to their operands.
953  report("Generic instruction is missing a virtual register type", MO, I);
954  }
955  }
956 
957  // Generic opcodes must not have physical register operands.
958  for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
959  const MachineOperand *MO = &MI->getOperand(I);
960  if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
961  report("Generic instruction cannot have physical register", MO, I);
962  }
963 
964  // Avoid out of bounds in checks below. This was already reported earlier.
965  if (MI->getNumOperands() < MCID.getNumOperands())
966  return;
967 
969  if (!TII->verifyInstruction(*MI, ErrorInfo))
970  report(ErrorInfo.data(), MI);
971 
972  // Verify properties of various specific instruction types
973  switch (MI->getOpcode()) {
974  case TargetOpcode::G_CONSTANT:
975  case TargetOpcode::G_FCONSTANT: {
976  if (MI->getNumOperands() < MCID.getNumOperands())
977  break;
978 
979  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
980  if (DstTy.isVector())
981  report("Instruction cannot use a vector result type", MI);
982 
983  if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
984  if (!MI->getOperand(1).isCImm()) {
985  report("G_CONSTANT operand must be cimm", MI);
986  break;
987  }
988 
989  const ConstantInt *CI = MI->getOperand(1).getCImm();
990  if (CI->getBitWidth() != DstTy.getSizeInBits())
991  report("inconsistent constant size", MI);
992  } else {
993  if (!MI->getOperand(1).isFPImm()) {
994  report("G_FCONSTANT operand must be fpimm", MI);
995  break;
996  }
997  const ConstantFP *CF = MI->getOperand(1).getFPImm();
998 
1000  DstTy.getSizeInBits()) {
1001  report("inconsistent constant size", MI);
1002  }
1003  }
1004 
1005  break;
1006  }
1007  case TargetOpcode::G_LOAD:
1008  case TargetOpcode::G_STORE:
1009  case TargetOpcode::G_ZEXTLOAD:
1010  case TargetOpcode::G_SEXTLOAD: {
1011  LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1012  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1013  if (!PtrTy.isPointer())
1014  report("Generic memory instruction must access a pointer", MI);
1015 
1016  // Generic loads and stores must have a single MachineMemOperand
1017  // describing that access.
1018  if (!MI->hasOneMemOperand()) {
1019  report("Generic instruction accessing memory must have one mem operand",
1020  MI);
1021  } else {
1022  const MachineMemOperand &MMO = **MI->memoperands_begin();
1023  if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1024  MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1025  if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1026  report("Generic extload must have a narrower memory type", MI);
1027  } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1028  if (MMO.getSize() > ValTy.getSizeInBytes())
1029  report("load memory size cannot exceed result size", MI);
1030  } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1031  if (ValTy.getSizeInBytes() < MMO.getSize())
1032  report("store memory size cannot exceed value size", MI);
1033  }
1034  }
1035 
1036  break;
1037  }
1038  case TargetOpcode::G_PHI: {
1039  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1040  if (!DstTy.isValid() ||
1041  !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
1042  [this, &DstTy](const MachineOperand &MO) {
1043  if (!MO.isReg())
1044  return true;
1045  LLT Ty = MRI->getType(MO.getReg());
1046  if (!Ty.isValid() || (Ty != DstTy))
1047  return false;
1048  return true;
1049  }))
1050  report("Generic Instruction G_PHI has operands with incompatible/missing "
1051  "types",
1052  MI);
1053  break;
1054  }
1055  case TargetOpcode::G_BITCAST: {
1056  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1057  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1058  if (!DstTy.isValid() || !SrcTy.isValid())
1059  break;
1060 
1061  if (SrcTy.isPointer() != DstTy.isPointer())
1062  report("bitcast cannot convert between pointers and other types", MI);
1063 
1064  if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1065  report("bitcast sizes must match", MI);
1066  break;
1067  }
1068  case TargetOpcode::G_INTTOPTR:
1069  case TargetOpcode::G_PTRTOINT:
1070  case TargetOpcode::G_ADDRSPACE_CAST: {
1071  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1072  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1073  if (!DstTy.isValid() || !SrcTy.isValid())
1074  break;
1075 
1076  verifyVectorElementMatch(DstTy, SrcTy, MI);
1077 
1078  DstTy = DstTy.getScalarType();
1079  SrcTy = SrcTy.getScalarType();
1080 
1081  if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1082  if (!DstTy.isPointer())
1083  report("inttoptr result type must be a pointer", MI);
1084  if (SrcTy.isPointer())
1085  report("inttoptr source type must not be a pointer", MI);
1086  } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1087  if (!SrcTy.isPointer())
1088  report("ptrtoint source type must be a pointer", MI);
1089  if (DstTy.isPointer())
1090  report("ptrtoint result type must not be a pointer", MI);
1091  } else {
1092  assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1093  if (!SrcTy.isPointer() || !DstTy.isPointer())
1094  report("addrspacecast types must be pointers", MI);
1095  else {
1096  if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1097  report("addrspacecast must convert different address spaces", MI);
1098  }
1099  }
1100 
1101  break;
1102  }
1103  case TargetOpcode::G_GEP: {
1104  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1105  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1106  LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1107  if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1108  break;
1109 
1110  if (!PtrTy.getScalarType().isPointer())
1111  report("gep first operand must be a pointer", MI);
1112 
1113  if (OffsetTy.getScalarType().isPointer())
1114  report("gep offset operand must not be a pointer", MI);
1115 
1116  // TODO: Is the offset allowed to be a scalar with a vector?
1117  break;
1118  }
1119  case TargetOpcode::G_SEXT:
1120  case TargetOpcode::G_ZEXT:
1121  case TargetOpcode::G_ANYEXT:
1122  case TargetOpcode::G_TRUNC:
1123  case TargetOpcode::G_FPEXT:
1124  case TargetOpcode::G_FPTRUNC: {
1125  // Number of operands and presense of types is already checked (and
1126  // reported in case of any issues), so no need to report them again. As
1127  // we're trying to report as many issues as possible at once, however, the
1128  // instructions aren't guaranteed to have the right number of operands or
1129  // types attached to them at this point
1130  assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1131  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1132  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1133  if (!DstTy.isValid() || !SrcTy.isValid())
1134  break;
1135 
1136  LLT DstElTy = DstTy.getScalarType();
1137  LLT SrcElTy = SrcTy.getScalarType();
1138  if (DstElTy.isPointer() || SrcElTy.isPointer())
1139  report("Generic extend/truncate can not operate on pointers", MI);
1140 
1141  verifyVectorElementMatch(DstTy, SrcTy, MI);
1142 
1143  unsigned DstSize = DstElTy.getSizeInBits();
1144  unsigned SrcSize = SrcElTy.getSizeInBits();
1145  switch (MI->getOpcode()) {
1146  default:
1147  if (DstSize <= SrcSize)
1148  report("Generic extend has destination type no larger than source", MI);
1149  break;
1150  case TargetOpcode::G_TRUNC:
1151  case TargetOpcode::G_FPTRUNC:
1152  if (DstSize >= SrcSize)
1153  report("Generic truncate has destination type no smaller than source",
1154  MI);
1155  break;
1156  }
1157  break;
1158  }
1159  case TargetOpcode::G_SELECT: {
1160  LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1161  LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1162  if (!SelTy.isValid() || !CondTy.isValid())
1163  break;
1164 
1165  // Scalar condition select on a vector is valid.
1166  if (CondTy.isVector())
1167  verifyVectorElementMatch(SelTy, CondTy, MI);
1168  break;
1169  }
1170  case TargetOpcode::G_MERGE_VALUES: {
1171  // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1172  // e.g. s2N = MERGE sN, sN
1173  // Merging multiple scalars into a vector is not allowed, should use
1174  // G_BUILD_VECTOR for that.
1175  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1176  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1177  if (DstTy.isVector() || SrcTy.isVector())
1178  report("G_MERGE_VALUES cannot operate on vectors", MI);
1179 
1180  const unsigned NumOps = MI->getNumOperands();
1181  if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1182  report("G_MERGE_VALUES result size is inconsistent", MI);
1183 
1184  for (unsigned I = 2; I != NumOps; ++I) {
1185  if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1186  report("G_MERGE_VALUES source types do not match", MI);
1187  }
1188 
1189  break;
1190  }
1191  case TargetOpcode::G_UNMERGE_VALUES: {
1192  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1193  LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1194  // For now G_UNMERGE can split vectors.
1195  for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
1196  if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1197  report("G_UNMERGE_VALUES destination types do not match", MI);
1198  }
1199  if (SrcTy.getSizeInBits() !=
1200  (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1201  report("G_UNMERGE_VALUES source operand does not cover dest operands",
1202  MI);
1203  }
1204  break;
1205  }
1206  case TargetOpcode::G_BUILD_VECTOR: {
1207  // Source types must be scalars, dest type a vector. Total size of scalars
1208  // must match the dest vector size.
1209  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1210  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1211  if (!DstTy.isVector() || SrcEltTy.isVector()) {
1212  report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1213  break;
1214  }
1215 
1216  if (DstTy.getElementType() != SrcEltTy)
1217  report("G_BUILD_VECTOR result element type must match source type", MI);
1218 
1219  if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1220  report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1221 
1222  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1223  if (MRI->getType(MI->getOperand(1).getReg()) !=
1224  MRI->getType(MI->getOperand(i).getReg()))
1225  report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1226  }
1227 
1228  break;
1229  }
1230  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1231  // Source types must be scalars, dest type a vector. Scalar types must be
1232  // larger than the dest vector elt type, as this is a truncating operation.
1233  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1234  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1235  if (!DstTy.isVector() || SrcEltTy.isVector())
1236  report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1237  MI);
1238  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1239  if (MRI->getType(MI->getOperand(1).getReg()) !=
1240  MRI->getType(MI->getOperand(i).getReg()))
1241  report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1242  MI);
1243  }
1244  if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1245  report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1246  "dest elt type",
1247  MI);
1248  break;
1249  }
1250  case TargetOpcode::G_CONCAT_VECTORS: {
1251  // Source types should be vectors, and total size should match the dest
1252  // vector size.
1253  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1254  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1255  if (!DstTy.isVector() || !SrcTy.isVector())
1256  report("G_CONCAT_VECTOR requires vector source and destination operands",
1257  MI);
1258  for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
1259  if (MRI->getType(MI->getOperand(1).getReg()) !=
1260  MRI->getType(MI->getOperand(i).getReg()))
1261  report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1262  }
1263  if (DstTy.getNumElements() !=
1264  SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1265  report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1266  break;
1267  }
1268  case TargetOpcode::G_ICMP:
1269  case TargetOpcode::G_FCMP: {
1270  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1271  LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1272 
1273  if ((DstTy.isVector() != SrcTy.isVector()) ||
1274  (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1275  report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1276 
1277  break;
1278  }
1279  case TargetOpcode::G_EXTRACT: {
1280  const MachineOperand &SrcOp = MI->getOperand(1);
1281  if (!SrcOp.isReg()) {
1282  report("extract source must be a register", MI);
1283  break;
1284  }
1285 
1286  const MachineOperand &OffsetOp = MI->getOperand(2);
1287  if (!OffsetOp.isImm()) {
1288  report("extract offset must be a constant", MI);
1289  break;
1290  }
1291 
1292  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1293  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1294  if (SrcSize == DstSize)
1295  report("extract source must be larger than result", MI);
1296 
1297  if (DstSize + OffsetOp.getImm() > SrcSize)
1298  report("extract reads past end of register", MI);
1299  break;
1300  }
1301  case TargetOpcode::G_INSERT: {
1302  const MachineOperand &SrcOp = MI->getOperand(2);
1303  if (!SrcOp.isReg()) {
1304  report("insert source must be a register", MI);
1305  break;
1306  }
1307 
1308  const MachineOperand &OffsetOp = MI->getOperand(3);
1309  if (!OffsetOp.isImm()) {
1310  report("insert offset must be a constant", MI);
1311  break;
1312  }
1313 
1314  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1315  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1316 
1317  if (DstSize <= SrcSize)
1318  report("inserted size must be smaller than total register", MI);
1319 
1320  if (SrcSize + OffsetOp.getImm() > DstSize)
1321  report("insert writes past end of register", MI);
1322 
1323  break;
1324  }
1325  case TargetOpcode::G_JUMP_TABLE: {
1326  if (!MI->getOperand(1).isJTI())
1327  report("G_JUMP_TABLE source operand must be a jump table index", MI);
1328  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1329  if (!DstTy.isPointer())
1330  report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1331  break;
1332  }
1333  case TargetOpcode::G_BRJT: {
1334  if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1335  report("G_BRJT src operand 0 must be a pointer type", MI);
1336 
1337  if (!MI->getOperand(1).isJTI())
1338  report("G_BRJT src operand 1 must be a jump table index", MI);
1339 
1340  const auto &IdxOp = MI->getOperand(2);
1341  if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1342  report("G_BRJT src operand 2 must be a scalar reg type", MI);
1343  break;
1344  }
1345  case TargetOpcode::G_INTRINSIC:
1346  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1347  // TODO: Should verify number of def and use operands, but the current
1348  // interface requires passing in IR types for mangling.
1349  const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1350  if (!IntrIDOp.isIntrinsicID()) {
1351  report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1352  break;
1353  }
1354 
1355  bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1356  unsigned IntrID = IntrIDOp.getIntrinsicID();
1357  if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1360  static_cast<Intrinsic::ID>(IntrID));
1361  bool DeclHasSideEffects = !Attrs.hasFnAttribute(Attribute::ReadNone);
1362  if (NoSideEffects && DeclHasSideEffects) {
1363  report("G_INTRINSIC used with intrinsic that accesses memory", MI);
1364  break;
1365  }
1366  if (!NoSideEffects && !DeclHasSideEffects) {
1367  report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
1368  break;
1369  }
1370  }
1371  switch (IntrID) {
1372  case Intrinsic::memcpy:
1373  if (MI->getNumOperands() != 5)
1374  report("Expected memcpy intrinsic to have 5 operands", MI);
1375  break;
1376  case Intrinsic::memmove:
1377  if (MI->getNumOperands() != 5)
1378  report("Expected memmove intrinsic to have 5 operands", MI);
1379  break;
1380  case Intrinsic::memset:
1381  if (MI->getNumOperands() != 5)
1382  report("Expected memset intrinsic to have 5 operands", MI);
1383  break;
1384  }
1385  break;
1386  }
1387  case TargetOpcode::G_SEXT_INREG: {
1388  if (!MI->getOperand(2).isImm()) {
1389  report("G_SEXT_INREG expects an immediate operand #2", MI);
1390  break;
1391  }
1392 
1393  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1394  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1395  verifyVectorElementMatch(DstTy, SrcTy, MI);
1396 
1397  int64_t Imm = MI->getOperand(2).getImm();
1398  if (Imm <= 0)
1399  report("G_SEXT_INREG size must be >= 1", MI);
1400  if (Imm >= SrcTy.getScalarSizeInBits())
1401  report("G_SEXT_INREG size must be less than source bit width", MI);
1402  break;
1403  }
1404  case TargetOpcode::G_SHUFFLE_VECTOR: {
1405  const MachineOperand &MaskOp = MI->getOperand(3);
1406  if (!MaskOp.isShuffleMask()) {
1407  report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1408  break;
1409  }
1410 
1411  const Constant *Mask = MaskOp.getShuffleMask();
1412  auto *MaskVT = dyn_cast<VectorType>(Mask->getType());
1413  if (!MaskVT || !MaskVT->getElementType()->isIntegerTy(32)) {
1414  report("Invalid shufflemask constant type", MI);
1415  break;
1416  }
1417 
1418  if (!Mask->getAggregateElement(0u)) {
1419  report("Invalid shufflemask constant type", MI);
1420  break;
1421  }
1422 
1423  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1424  LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1425  LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1426 
1427  if (Src0Ty != Src1Ty)
1428  report("Source operands must be the same type", MI);
1429 
1430  if (Src0Ty.getScalarType() != DstTy.getScalarType())
1431  report("G_SHUFFLE_VECTOR cannot change element type", MI);
1432 
1433  // Don't check that all operands are vector because scalars are used in
1434  // place of 1 element vectors.
1435  int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1436  int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1437 
1438  SmallVector<int, 32> MaskIdxes;
1439  ShuffleVectorInst::getShuffleMask(Mask, MaskIdxes);
1440 
1441  if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1442  report("Wrong result type for shufflemask", MI);
1443 
1444  for (int Idx : MaskIdxes) {
1445  if (Idx < 0)
1446  continue;
1447 
1448  if (Idx >= 2 * SrcNumElts)
1449  report("Out of bounds shuffle index", MI);
1450  }
1451 
1452  break;
1453  }
1454  case TargetOpcode::G_DYN_STACKALLOC: {
1455  const MachineOperand &DstOp = MI->getOperand(0);
1456  const MachineOperand &AllocOp = MI->getOperand(1);
1457  const MachineOperand &AlignOp = MI->getOperand(2);
1458 
1459  if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1460  report("dst operand 0 must be a pointer type", MI);
1461  break;
1462  }
1463 
1464  if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1465  report("src operand 1 must be a scalar reg type", MI);
1466  break;
1467  }
1468 
1469  if (!AlignOp.isImm()) {
1470  report("src operand 2 must be an immediate type", MI);
1471  break;
1472  }
1473  break;
1474  }
1475  default:
1476  break;
1477  }
1478 }
1479 
1480 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1481  const MCInstrDesc &MCID = MI->getDesc();
1482  if (MI->getNumOperands() < MCID.getNumOperands()) {
1483  report("Too few operands", MI);
1484  errs() << MCID.getNumOperands() << " operands expected, but "
1485  << MI->getNumOperands() << " given.\n";
1486  }
1487 
1488  if (MI->isPHI()) {
1489  if (MF->getProperties().hasProperty(
1491  report("Found PHI instruction with NoPHIs property set", MI);
1492 
1493  if (FirstNonPHI)
1494  report("Found PHI instruction after non-PHI", MI);
1495  } else if (FirstNonPHI == nullptr)
1496  FirstNonPHI = MI;
1497 
1498  // Check the tied operands.
1499  if (MI->isInlineAsm())
1500  verifyInlineAsm(MI);
1501 
1502  // Check the MachineMemOperands for basic consistency.
1504  E = MI->memoperands_end();
1505  I != E; ++I) {
1506  if ((*I)->isLoad() && !MI->mayLoad())
1507  report("Missing mayLoad flag", MI);
1508  if ((*I)->isStore() && !MI->mayStore())
1509  report("Missing mayStore flag", MI);
1510  }
1511 
1512  // Debug values must not have a slot index.
1513  // Other instructions must have one, unless they are inside a bundle.
1514  if (LiveInts) {
1515  bool mapped = !LiveInts->isNotInMIMap(*MI);
1516  if (MI->isDebugInstr()) {
1517  if (mapped)
1518  report("Debug instruction has a slot index", MI);
1519  } else if (MI->isInsideBundle()) {
1520  if (mapped)
1521  report("Instruction inside bundle has a slot index", MI);
1522  } else {
1523  if (!mapped)
1524  report("Missing slot index", MI);
1525  }
1526  }
1527 
1528  if (isPreISelGenericOpcode(MCID.getOpcode())) {
1529  verifyPreISelGenericInstruction(MI);
1530  return;
1531  }
1532 
1534  if (!TII->verifyInstruction(*MI, ErrorInfo))
1535  report(ErrorInfo.data(), MI);
1536 
1537  // Verify properties of various specific instruction types
1538  switch (MI->getOpcode()) {
1539  case TargetOpcode::COPY: {
1540  if (foundErrors)
1541  break;
1542  const MachineOperand &DstOp = MI->getOperand(0);
1543  const MachineOperand &SrcOp = MI->getOperand(1);
1544  LLT DstTy = MRI->getType(DstOp.getReg());
1545  LLT SrcTy = MRI->getType(SrcOp.getReg());
1546  if (SrcTy.isValid() && DstTy.isValid()) {
1547  // If both types are valid, check that the types are the same.
1548  if (SrcTy != DstTy) {
1549  report("Copy Instruction is illegal with mismatching types", MI);
1550  errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1551  }
1552  }
1553  if (SrcTy.isValid() || DstTy.isValid()) {
1554  // If one of them have valid types, let's just check they have the same
1555  // size.
1556  unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
1557  unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
1558  assert(SrcSize && "Expecting size here");
1559  assert(DstSize && "Expecting size here");
1560  if (SrcSize != DstSize)
1561  if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1562  report("Copy Instruction is illegal with mismatching sizes", MI);
1563  errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1564  << "\n";
1565  }
1566  }
1567  break;
1568  }
1569  case TargetOpcode::STATEPOINT:
1570  if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
1573  report("meta operands to STATEPOINT not constant!", MI);
1574  break;
1575 
1576  auto VerifyStackMapConstant = [&](unsigned Offset) {
1577  if (!MI->getOperand(Offset).isImm() ||
1578  MI->getOperand(Offset).getImm() != StackMaps::ConstantOp ||
1579  !MI->getOperand(Offset + 1).isImm())
1580  report("stack map constant to STATEPOINT not well formed!", MI);
1581  };
1582  const unsigned VarStart = StatepointOpers(MI).getVarIdx();
1583  VerifyStackMapConstant(VarStart + StatepointOpers::CCOffset);
1584  VerifyStackMapConstant(VarStart + StatepointOpers::FlagsOffset);
1585  VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
1586 
1587  // TODO: verify we have properly encoded deopt arguments
1588  break;
1589  }
1590 }
1591 
1592 void
1593 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1594  const MachineInstr *MI = MO->getParent();
1595  const MCInstrDesc &MCID = MI->getDesc();
1596  unsigned NumDefs = MCID.getNumDefs();
1597  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1598  NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1599 
1600  // The first MCID.NumDefs operands must be explicit register defines
1601  if (MONum < NumDefs) {
1602  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1603  if (!MO->isReg())
1604  report("Explicit definition must be a register", MO, MONum);
1605  else if (!MO->isDef() && !MCOI.isOptionalDef())
1606  report("Explicit definition marked as use", MO, MONum);
1607  else if (MO->isImplicit())
1608  report("Explicit definition marked as implicit", MO, MONum);
1609  } else if (MONum < MCID.getNumOperands()) {
1610  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1611  // Don't check if it's the last operand in a variadic instruction. See,
1612  // e.g., LDM_RET in the arm back end.
1613  if (MO->isReg() &&
1614  !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
1615  if (MO->isDef() && !MCOI.isOptionalDef())
1616  report("Explicit operand marked as def", MO, MONum);
1617  if (MO->isImplicit())
1618  report("Explicit operand marked as implicit", MO, MONum);
1619  }
1620 
1621  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1622  if (TiedTo != -1) {
1623  if (!MO->isReg())
1624  report("Tied use must be a register", MO, MONum);
1625  else if (!MO->isTied())
1626  report("Operand should be tied", MO, MONum);
1627  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
1628  report("Tied def doesn't match MCInstrDesc", MO, MONum);
1629  else if (Register::isPhysicalRegister(MO->getReg())) {
1630  const MachineOperand &MOTied = MI->getOperand(TiedTo);
1631  if (!MOTied.isReg())
1632  report("Tied counterpart must be a register", &MOTied, TiedTo);
1633  else if (Register::isPhysicalRegister(MOTied.getReg()) &&
1634  MO->getReg() != MOTied.getReg())
1635  report("Tied physical registers must match.", &MOTied, TiedTo);
1636  }
1637  } else if (MO->isReg() && MO->isTied())
1638  report("Explicit operand should not be tied", MO, MONum);
1639  } else {
1640  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1641  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1642  report("Extra explicit operand on non-variadic instruction", MO, MONum);
1643  }
1644 
1645  switch (MO->getType()) {
1647  const Register Reg = MO->getReg();
1648  if (!Reg)
1649  return;
1650  if (MRI->tracksLiveness() && !MI->isDebugValue())
1651  checkLiveness(MO, MONum);
1652 
1653  // Verify the consistency of tied operands.
1654  if (MO->isTied()) {
1655  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
1656  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1657  if (!OtherMO.isReg())
1658  report("Must be tied to a register", MO, MONum);
1659  if (!OtherMO.isTied())
1660  report("Missing tie flags on tied operand", MO, MONum);
1661  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
1662  report("Inconsistent tie links", MO, MONum);
1663  if (MONum < MCID.getNumDefs()) {
1664  if (OtherIdx < MCID.getNumOperands()) {
1665  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
1666  report("Explicit def tied to explicit use without tie constraint",
1667  MO, MONum);
1668  } else {
1669  if (!OtherMO.isImplicit())
1670  report("Explicit def should be tied to implicit use", MO, MONum);
1671  }
1672  }
1673  }
1674 
1675  // Verify two-address constraints after leaving SSA form.
1676  unsigned DefIdx;
1677  if (!MRI->isSSA() && MO->isUse() &&
1678  MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1679  Reg != MI->getOperand(DefIdx).getReg())
1680  report("Two-address instruction operands must be identical", MO, MONum);
1681 
1682  // Check register classes.
1683  unsigned SubIdx = MO->getSubReg();
1684 
1685  if (Register::isPhysicalRegister(Reg)) {
1686  if (SubIdx) {
1687  report("Illegal subregister index for physical register", MO, MONum);
1688  return;
1689  }
1690  if (MONum < MCID.getNumOperands()) {
1691  if (const TargetRegisterClass *DRC =
1692  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1693  if (!DRC->contains(Reg)) {
1694  report("Illegal physical register for instruction", MO, MONum);
1695  errs() << printReg(Reg, TRI) << " is not a "
1696  << TRI->getRegClassName(DRC) << " register.\n";
1697  }
1698  }
1699  }
1700  if (MO->isRenamable()) {
1701  if (MRI->isReserved(Reg)) {
1702  report("isRenamable set on reserved register", MO, MONum);
1703  return;
1704  }
1705  }
1706  if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) {
1707  report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum);
1708  return;
1709  }
1710  } else {
1711  // Virtual register.
1712  const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
1713  if (!RC) {
1714  // This is a generic virtual register.
1715 
1716  // If we're post-Select, we can't have gvregs anymore.
1717  if (isFunctionSelected) {
1718  report("Generic virtual register invalid in a Selected function",
1719  MO, MONum);
1720  return;
1721  }
1722 
1723  // The gvreg must have a type and it must not have a SubIdx.
1724  LLT Ty = MRI->getType(Reg);
1725  if (!Ty.isValid()) {
1726  report("Generic virtual register must have a valid type", MO,
1727  MONum);
1728  return;
1729  }
1730 
1731  const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
1732 
1733  // If we're post-RegBankSelect, the gvreg must have a bank.
1734  if (!RegBank && isFunctionRegBankSelected) {
1735  report("Generic virtual register must have a bank in a "
1736  "RegBankSelected function",
1737  MO, MONum);
1738  return;
1739  }
1740 
1741  // Make sure the register fits into its register bank if any.
1742  if (RegBank && Ty.isValid() &&
1743  RegBank->getSize() < Ty.getSizeInBits()) {
1744  report("Register bank is too small for virtual register", MO,
1745  MONum);
1746  errs() << "Register bank " << RegBank->getName() << " too small("
1747  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
1748  << "-bits\n";
1749  return;
1750  }
1751  if (SubIdx) {
1752  report("Generic virtual register does not allow subregister index", MO,
1753  MONum);
1754  return;
1755  }
1756 
1757  // If this is a target specific instruction and this operand
1758  // has register class constraint, the virtual register must
1759  // comply to it.
1760  if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
1761  MONum < MCID.getNumOperands() &&
1762  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1763  report("Virtual register does not match instruction constraint", MO,
1764  MONum);
1765  errs() << "Expect register class "
1766  << TRI->getRegClassName(
1767  TII->getRegClass(MCID, MONum, TRI, *MF))
1768  << " but got nothing\n";
1769  return;
1770  }
1771 
1772  break;
1773  }
1774  if (SubIdx) {
1775  const TargetRegisterClass *SRC =
1776  TRI->getSubClassWithSubReg(RC, SubIdx);
1777  if (!SRC) {
1778  report("Invalid subregister index for virtual register", MO, MONum);
1779  errs() << "Register class " << TRI->getRegClassName(RC)
1780  << " does not support subreg index " << SubIdx << "\n";
1781  return;
1782  }
1783  if (RC != SRC) {
1784  report("Invalid register class for subregister index", MO, MONum);
1785  errs() << "Register class " << TRI->getRegClassName(RC)
1786  << " does not fully support subreg index " << SubIdx << "\n";
1787  return;
1788  }
1789  }
1790  if (MONum < MCID.getNumOperands()) {
1791  if (const TargetRegisterClass *DRC =
1792  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1793  if (SubIdx) {
1794  const TargetRegisterClass *SuperRC =
1795  TRI->getLargestLegalSuperClass(RC, *MF);
1796  if (!SuperRC) {
1797  report("No largest legal super class exists.", MO, MONum);
1798  return;
1799  }
1800  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
1801  if (!DRC) {
1802  report("No matching super-reg register class.", MO, MONum);
1803  return;
1804  }
1805  }
1806  if (!RC->hasSuperClassEq(DRC)) {
1807  report("Illegal virtual register for instruction", MO, MONum);
1808  errs() << "Expected a " << TRI->getRegClassName(DRC)
1809  << " register, but got a " << TRI->getRegClassName(RC)
1810  << " register\n";
1811  }
1812  }
1813  }
1814  }
1815  break;
1816  }
1817 
1819  regMasks.push_back(MO->getRegMask());
1820  break;
1821 
1823  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
1824  report("PHI operand is not in the CFG", MO, MONum);
1825  break;
1826 
1828  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
1829  LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1830  int FI = MO->getIndex();
1831  LiveInterval &LI = LiveStks->getInterval(FI);
1832  SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
1833 
1834  bool stores = MI->mayStore();
1835  bool loads = MI->mayLoad();
1836  // For a memory-to-memory move, we need to check if the frame
1837  // index is used for storing or loading, by inspecting the
1838  // memory operands.
1839  if (stores && loads) {
1840  for (auto *MMO : MI->memoperands()) {
1841  const PseudoSourceValue *PSV = MMO->getPseudoValue();
1842  if (PSV == nullptr) continue;
1845  if (Value == nullptr) continue;
1846  if (Value->getFrameIndex() != FI) continue;
1847 
1848  if (MMO->isStore())
1849  loads = false;
1850  else
1851  stores = false;
1852  break;
1853  }
1854  if (loads == stores)
1855  report("Missing fixed stack memoperand.", MI);
1856  }
1857  if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
1858  report("Instruction loads from dead spill slot", MO, MONum);
1859  errs() << "Live stack: " << LI << '\n';
1860  }
1861  if (stores && !LI.liveAt(Idx.getRegSlot())) {
1862  report("Instruction stores to dead spill slot", MO, MONum);
1863  errs() << "Live stack: " << LI << '\n';
1864  }
1865  }
1866  break;
1867 
1868  default:
1869  break;
1870  }
1871 }
1872 
1873 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
1874  unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
1875  LaneBitmask LaneMask) {
1876  LiveQueryResult LRQ = LR.Query(UseIdx);
1877  // Check if we have a segment at the use, note however that we only need one
1878  // live subregister range, the others may be dead.
1879  if (!LRQ.valueIn() && LaneMask.none()) {
1880  report("No live segment at use", MO, MONum);
1881  report_context_liverange(LR);
1882  report_context_vreg_regunit(VRegOrUnit);
1883  report_context(UseIdx);
1884  }
1885  if (MO->isKill() && !LRQ.isKill()) {
1886  report("Live range continues after kill flag", MO, MONum);
1887  report_context_liverange(LR);
1888  report_context_vreg_regunit(VRegOrUnit);
1889  if (LaneMask.any())
1890  report_context_lanemask(LaneMask);
1891  report_context(UseIdx);
1892  }
1893 }
1894 
1895 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
1896  unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1897  bool SubRangeCheck, LaneBitmask LaneMask) {
1898  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
1899  assert(VNI && "NULL valno is not allowed");
1900  if (VNI->def != DefIdx) {
1901  report("Inconsistent valno->def", MO, MONum);
1902  report_context_liverange(LR);
1903  report_context_vreg_regunit(VRegOrUnit);
1904  if (LaneMask.any())
1905  report_context_lanemask(LaneMask);
1906  report_context(*VNI);
1907  report_context(DefIdx);
1908  }
1909  } else {
1910  report("No live segment at def", MO, MONum);
1911  report_context_liverange(LR);
1912  report_context_vreg_regunit(VRegOrUnit);
1913  if (LaneMask.any())
1914  report_context_lanemask(LaneMask);
1915  report_context(DefIdx);
1916  }
1917  // Check that, if the dead def flag is present, LiveInts agree.
1918  if (MO->isDead()) {
1919  LiveQueryResult LRQ = LR.Query(DefIdx);
1920  if (!LRQ.isDeadDef()) {
1921  assert(Register::isVirtualRegister(VRegOrUnit) &&
1922  "Expecting a virtual register.");
1923  // A dead subreg def only tells us that the specific subreg is dead. There
1924  // could be other non-dead defs of other subregs, or we could have other
1925  // parts of the register being live through the instruction. So unless we
1926  // are checking liveness for a subrange it is ok for the live range to
1927  // continue, given that we have a dead def of a subregister.
1928  if (SubRangeCheck || MO->getSubReg() == 0) {
1929  report("Live range continues after dead def flag", MO, MONum);
1930  report_context_liverange(LR);
1931  report_context_vreg_regunit(VRegOrUnit);
1932  if (LaneMask.any())
1933  report_context_lanemask(LaneMask);
1934  }
1935  }
1936  }
1937 }
1938 
1939 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
1940  const MachineInstr *MI = MO->getParent();
1941  const unsigned Reg = MO->getReg();
1942 
1943  // Both use and def operands can read a register.
1944  if (MO->readsReg()) {
1945  if (MO->isKill())
1946  addRegWithSubRegs(regsKilled, Reg);
1947 
1948  // Check that LiveVars knows this kill.
1949  if (LiveVars && Register::isVirtualRegister(Reg) && MO->isKill()) {
1950  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1951  if (!is_contained(VI.Kills, MI))
1952  report("Kill missing from LiveVariables", MO, MONum);
1953  }
1954 
1955  // Check LiveInts liveness and kill.
1956  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1957  SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
1958  // Check the cached regunit intervals.
1959  if (Register::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1960  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1961  if (MRI->isReservedRegUnit(*Units))
1962  continue;
1963  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
1964  checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
1965  }
1966  }
1967 
1968  if (Register::isVirtualRegister(Reg)) {
1969  if (LiveInts->hasInterval(Reg)) {
1970  // This is a virtual register interval.
1971  const LiveInterval &LI = LiveInts->getInterval(Reg);
1972  checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
1973 
1974  if (LI.hasSubRanges() && !MO->isDef()) {
1975  unsigned SubRegIdx = MO->getSubReg();
1976  LaneBitmask MOMask = SubRegIdx != 0
1977  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1978  : MRI->getMaxLaneMaskForVReg(Reg);
1979  LaneBitmask LiveInMask;
1980  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1981  if ((MOMask & SR.LaneMask).none())
1982  continue;
1983  checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
1984  LiveQueryResult LRQ = SR.Query(UseIdx);
1985  if (LRQ.valueIn())
1986  LiveInMask |= SR.LaneMask;
1987  }
1988  // At least parts of the register has to be live at the use.
1989  if ((LiveInMask & MOMask).none()) {
1990  report("No live subrange at use", MO, MONum);
1991  report_context(LI);
1992  report_context(UseIdx);
1993  }
1994  }
1995  } else {
1996  report("Virtual register has no live interval", MO, MONum);
1997  }
1998  }
1999  }
2000 
2001  // Use of a dead register.
2002  if (!regsLive.count(Reg)) {
2003  if (Register::isPhysicalRegister(Reg)) {
2004  // Reserved registers may be used even when 'dead'.
2005  bool Bad = !isReserved(Reg);
2006  // We are fine if just any subregister has a defined value.
2007  if (Bad) {
2008  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
2009  ++SubRegs) {
2010  if (regsLive.count(*SubRegs)) {
2011  Bad = false;
2012  break;
2013  }
2014  }
2015  }
2016  // If there is an additional implicit-use of a super register we stop
2017  // here. By definition we are fine if the super register is not
2018  // (completely) dead, if the complete super register is dead we will
2019  // get a report for its operand.
2020  if (Bad) {
2021  for (const MachineOperand &MOP : MI->uses()) {
2022  if (!MOP.isReg() || !MOP.isImplicit())
2023  continue;
2024 
2025  if (!Register::isPhysicalRegister(MOP.getReg()))
2026  continue;
2027 
2028  for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
2029  ++SubRegs) {
2030  if (*SubRegs == Reg) {
2031  Bad = false;
2032  break;
2033  }
2034  }
2035  }
2036  }
2037  if (Bad)
2038  report("Using an undefined physical register", MO, MONum);
2039  } else if (MRI->def_empty(Reg)) {
2040  report("Reading virtual register without a def", MO, MONum);
2041  } else {
2042  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2043  // We don't know which virtual registers are live in, so only complain
2044  // if vreg was killed in this MBB. Otherwise keep track of vregs that
2045  // must be live in. PHI instructions are handled separately.
2046  if (MInfo.regsKilled.count(Reg))
2047  report("Using a killed virtual register", MO, MONum);
2048  else if (!MI->isPHI())
2049  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2050  }
2051  }
2052  }
2053 
2054  if (MO->isDef()) {
2055  // Register defined.
2056  // TODO: verify that earlyclobber ops are not used.
2057  if (MO->isDead())
2058  addRegWithSubRegs(regsDead, Reg);
2059  else
2060  addRegWithSubRegs(regsDefined, Reg);
2061 
2062  // Verify SSA form.
2063  if (MRI->isSSA() && Register::isVirtualRegister(Reg) &&
2064  std::next(MRI->def_begin(Reg)) != MRI->def_end())
2065  report("Multiple virtual register defs in SSA form", MO, MONum);
2066 
2067  // Check LiveInts for a live segment, but only for virtual registers.
2068  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2069  SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2070  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2071 
2072  if (Register::isVirtualRegister(Reg)) {
2073  if (LiveInts->hasInterval(Reg)) {
2074  const LiveInterval &LI = LiveInts->getInterval(Reg);
2075  checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
2076 
2077  if (LI.hasSubRanges()) {
2078  unsigned SubRegIdx = MO->getSubReg();
2079  LaneBitmask MOMask = SubRegIdx != 0
2080  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2081  : MRI->getMaxLaneMaskForVReg(Reg);
2082  for (const LiveInterval::SubRange &SR : LI.subranges()) {
2083  if ((SR.LaneMask & MOMask).none())
2084  continue;
2085  checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2086  }
2087  }
2088  } else {
2089  report("Virtual register has no Live interval", MO, MONum);
2090  }
2091  }
2092  }
2093  }
2094 }
2095 
2096 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
2097 
2098 // This function gets called after visiting all instructions in a bundle. The
2099 // argument points to the bundle header.
2100 // Normal stand-alone instructions are also considered 'bundles', and this
2101 // function is called for all of them.
2102 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2103  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2104  set_union(MInfo.regsKilled, regsKilled);
2105  set_subtract(regsLive, regsKilled); regsKilled.clear();
2106  // Kill any masked registers.
2107  while (!regMasks.empty()) {
2108  const uint32_t *Mask = regMasks.pop_back_val();
2109  for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
2112  regsDead.push_back(*I);
2113  }
2114  set_subtract(regsLive, regsDead); regsDead.clear();
2115  set_union(regsLive, regsDefined); regsDefined.clear();
2116 }
2117 
2118 void
2119 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2120  MBBInfoMap[MBB].regsLiveOut = regsLive;
2121  regsLive.clear();
2122 
2123  if (Indexes) {
2124  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2125  if (!(stop > lastIndex)) {
2126  report("Block ends before last instruction index", MBB);
2127  errs() << "Block ends at " << stop
2128  << " last instruction was at " << lastIndex << '\n';
2129  }
2130  lastIndex = stop;
2131  }
2132 }
2133 
2134 // Calculate the largest possible vregsPassed sets. These are the registers that
2135 // can pass through an MBB live, but may not be live every time. It is assumed
2136 // that all vregsPassed sets are empty before the call.
2137 void MachineVerifier::calcRegsPassed() {
2138  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
2139  // have any vregsPassed.
2141  for (const auto &MBB : *MF) {
2142  BBInfo &MInfo = MBBInfoMap[&MBB];
2143  if (!MInfo.reachable)
2144  continue;
2146  SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
2147  BBInfo &SInfo = MBBInfoMap[*SuI];
2148  if (SInfo.addPassed(MInfo.regsLiveOut))
2149  todo.insert(*SuI);
2150  }
2151  }
2152 
2153  // Iteratively push vregsPassed to successors. This will converge to the same
2154  // final state regardless of DenseSet iteration order.
2155  while (!todo.empty()) {
2156  const MachineBasicBlock *MBB = *todo.begin();
2157  todo.erase(MBB);
2158  BBInfo &MInfo = MBBInfoMap[MBB];
2160  SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
2161  if (*SuI == MBB)
2162  continue;
2163  BBInfo &SInfo = MBBInfoMap[*SuI];
2164  if (SInfo.addPassed(MInfo.vregsPassed))
2165  todo.insert(*SuI);
2166  }
2167  }
2168 }
2169 
2170 // Calculate the set of virtual registers that must be passed through each basic
2171 // block in order to satisfy the requirements of successor blocks. This is very
2172 // similar to calcRegsPassed, only backwards.
2173 void MachineVerifier::calcRegsRequired() {
2174  // First push live-in regs to predecessors' vregsRequired.
2176  for (const auto &MBB : *MF) {
2177  BBInfo &MInfo = MBBInfoMap[&MBB];
2179  PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
2180  BBInfo &PInfo = MBBInfoMap[*PrI];
2181  if (PInfo.addRequired(MInfo.vregsLiveIn))
2182  todo.insert(*PrI);
2183  }
2184  }
2185 
2186  // Iteratively push vregsRequired to predecessors. This will converge to the
2187  // same final state regardless of DenseSet iteration order.
2188  while (!todo.empty()) {
2189  const MachineBasicBlock *MBB = *todo.begin();
2190  todo.erase(MBB);
2191  BBInfo &MInfo = MBBInfoMap[MBB];
2193  PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
2194  if (*PrI == MBB)
2195  continue;
2196  BBInfo &SInfo = MBBInfoMap[*PrI];
2197  if (SInfo.addRequired(MInfo.vregsRequired))
2198  todo.insert(*PrI);
2199  }
2200  }
2201 }
2202 
2203 // Check PHI instructions at the beginning of MBB. It is assumed that
2204 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2205 void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2206  BBInfo &MInfo = MBBInfoMap[&MBB];
2207 
2209  for (const MachineInstr &Phi : MBB) {
2210  if (!Phi.isPHI())
2211  break;
2212  seen.clear();
2213 
2214  const MachineOperand &MODef = Phi.getOperand(0);
2215  if (!MODef.isReg() || !MODef.isDef()) {
2216  report("Expected first PHI operand to be a register def", &MODef, 0);
2217  continue;
2218  }
2219  if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2220  MODef.isEarlyClobber() || MODef.isDebug())
2221  report("Unexpected flag on PHI operand", &MODef, 0);
2222  Register DefReg = MODef.getReg();
2223  if (!Register::isVirtualRegister(DefReg))
2224  report("Expected first PHI operand to be a virtual register", &MODef, 0);
2225 
2226  for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
2227  const MachineOperand &MO0 = Phi.getOperand(I);
2228  if (!MO0.isReg()) {
2229  report("Expected PHI operand to be a register", &MO0, I);
2230  continue;
2231  }
2232  if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2233  MO0.isDebug() || MO0.isTied())
2234  report("Unexpected flag on PHI operand", &MO0, I);
2235 
2236  const MachineOperand &MO1 = Phi.getOperand(I + 1);
2237  if (!MO1.isMBB()) {
2238  report("Expected PHI operand to be a basic block", &MO1, I + 1);
2239  continue;
2240  }
2241 
2242  const MachineBasicBlock &Pre = *MO1.getMBB();
2243  if (!Pre.isSuccessor(&MBB)) {
2244  report("PHI input is not a predecessor block", &MO1, I + 1);
2245  continue;
2246  }
2247 
2248  if (MInfo.reachable) {
2249  seen.insert(&Pre);
2250  BBInfo &PrInfo = MBBInfoMap[&Pre];
2251  if (!MO0.isUndef() && PrInfo.reachable &&
2252  !PrInfo.isLiveOut(MO0.getReg()))
2253  report("PHI operand is not live-out from predecessor", &MO0, I);
2254  }
2255  }
2256 
2257  // Did we see all predecessors?
2258  if (MInfo.reachable) {
2259  for (MachineBasicBlock *Pred : MBB.predecessors()) {
2260  if (!seen.count(Pred)) {
2261  report("Missing PHI operand", &Phi);
2262  errs() << printMBBReference(*Pred)
2263  << " is a predecessor according to the CFG.\n";
2264  }
2265  }
2266  }
2267  }
2268 }
2269 
2270 void MachineVerifier::visitMachineFunctionAfter() {
2271  calcRegsPassed();
2272 
2273  for (const MachineBasicBlock &MBB : *MF)
2274  checkPHIOps(MBB);
2275 
2276  // Now check liveness info if available
2277  calcRegsRequired();
2278 
2279  // Check for killed virtual registers that should be live out.
2280  for (const auto &MBB : *MF) {
2281  BBInfo &MInfo = MBBInfoMap[&MBB];
2282  for (RegSet::iterator
2283  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
2284  ++I)
2285  if (MInfo.regsKilled.count(*I)) {
2286  report("Virtual register killed in block, but needed live out.", &MBB);
2287  errs() << "Virtual register " << printReg(*I)
2288  << " is used after the block.\n";
2289  }
2290  }
2291 
2292  if (!MF->empty()) {
2293  BBInfo &MInfo = MBBInfoMap[&MF->front()];
2294  for (RegSet::iterator
2295  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
2296  ++I) {
2297  report("Virtual register defs don't dominate all uses.", MF);
2298  report_context_vreg(*I);
2299  }
2300  }
2301 
2302  if (LiveVars)
2303  verifyLiveVariables();
2304  if (LiveInts)
2305  verifyLiveIntervals();
2306 
2307  for (auto CSInfo : MF->getCallSitesInfo())
2308  if (!CSInfo.first->isCall())
2309  report("Call site info referencing instruction that is not call", MF);
2310 }
2311 
2312 void MachineVerifier::verifyLiveVariables() {
2313  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
2314  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
2315  unsigned Reg = Register::index2VirtReg(i);
2316  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2317  for (const auto &MBB : *MF) {
2318  BBInfo &MInfo = MBBInfoMap[&MBB];
2319 
2320  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2321  if (MInfo.vregsRequired.count(Reg)) {
2322  if (!VI.AliveBlocks.test(MBB.getNumber())) {
2323  report("LiveVariables: Block missing from AliveBlocks", &MBB);
2324  errs() << "Virtual register " << printReg(Reg)
2325  << " must be live through the block.\n";
2326  }
2327  } else {
2328  if (VI.AliveBlocks.test(MBB.getNumber())) {
2329  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2330  errs() << "Virtual register " << printReg(Reg)
2331  << " is not needed live through the block.\n";
2332  }
2333  }
2334  }
2335  }
2336 }
2337 
2338 void MachineVerifier::verifyLiveIntervals() {
2339  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
2340  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
2341  unsigned Reg = Register::index2VirtReg(i);
2342 
2343  // Spilling and splitting may leave unused registers around. Skip them.
2344  if (MRI->reg_nodbg_empty(Reg))
2345  continue;
2346 
2347  if (!LiveInts->hasInterval(Reg)) {
2348  report("Missing live interval for virtual register", MF);
2349  errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2350  continue;
2351  }
2352 
2353  const LiveInterval &LI = LiveInts->getInterval(Reg);
2354  assert(Reg == LI.reg && "Invalid reg to interval mapping");
2355  verifyLiveInterval(LI);
2356  }
2357 
2358  // Verify all the cached regunit intervals.
2359  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
2360  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2361  verifyLiveRange(*LR, i);
2362 }
2363 
2364 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2365  const VNInfo *VNI, unsigned Reg,
2366  LaneBitmask LaneMask) {
2367  if (VNI->isUnused())
2368  return;
2369 
2370  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2371 
2372  if (!DefVNI) {
2373  report("Value not live at VNInfo def and not marked unused", MF);
2374  report_context(LR, Reg, LaneMask);
2375  report_context(*VNI);
2376  return;
2377  }
2378 
2379  if (DefVNI != VNI) {
2380  report("Live segment at def has different VNInfo", MF);
2381  report_context(LR, Reg, LaneMask);
2382  report_context(*VNI);
2383  return;
2384  }
2385 
2386  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2387  if (!MBB) {
2388  report("Invalid VNInfo definition index", MF);
2389  report_context(LR, Reg, LaneMask);
2390  report_context(*VNI);
2391  return;
2392  }
2393 
2394  if (VNI->isPHIDef()) {
2395  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2396  report("PHIDef VNInfo is not defined at MBB start", MBB);
2397  report_context(LR, Reg, LaneMask);
2398  report_context(*VNI);
2399  }
2400  return;
2401  }
2402 
2403  // Non-PHI def.
2404  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2405  if (!MI) {
2406  report("No instruction at VNInfo def index", MBB);
2407  report_context(LR, Reg, LaneMask);
2408  report_context(*VNI);
2409  return;
2410  }
2411 
2412  if (Reg != 0) {
2413  bool hasDef = false;
2414  bool isEarlyClobber = false;
2415  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2416  if (!MOI->isReg() || !MOI->isDef())
2417  continue;
2418  if (Register::isVirtualRegister(Reg)) {
2419  if (MOI->getReg() != Reg)
2420  continue;
2421  } else {
2422  if (!Register::isPhysicalRegister(MOI->getReg()) ||
2423  !TRI->hasRegUnit(MOI->getReg(), Reg))
2424  continue;
2425  }
2426  if (LaneMask.any() &&
2427  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2428  continue;
2429  hasDef = true;
2430  if (MOI->isEarlyClobber())
2431  isEarlyClobber = true;
2432  }
2433 
2434  if (!hasDef) {
2435  report("Defining instruction does not modify register", MI);
2436  report_context(LR, Reg, LaneMask);
2437  report_context(*VNI);
2438  }
2439 
2440  // Early clobber defs begin at USE slots, but other defs must begin at
2441  // DEF slots.
2442  if (isEarlyClobber) {
2443  if (!VNI->def.isEarlyClobber()) {
2444  report("Early clobber def must be at an early-clobber slot", MBB);
2445  report_context(LR, Reg, LaneMask);
2446  report_context(*VNI);
2447  }
2448  } else if (!VNI->def.isRegister()) {
2449  report("Non-PHI, non-early clobber def must be at a register slot", MBB);
2450  report_context(LR, Reg, LaneMask);
2451  report_context(*VNI);
2452  }
2453  }
2454 }
2455 
2456 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
2458  unsigned Reg, LaneBitmask LaneMask)
2459 {
2460  const LiveRange::Segment &S = *I;
2461  const VNInfo *VNI = S.valno;
2462  assert(VNI && "Live segment has no valno");
2463 
2464  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
2465  report("Foreign valno in live segment", MF);
2466  report_context(LR, Reg, LaneMask);
2467  report_context(S);
2468  report_context(*VNI);
2469  }
2470 
2471  if (VNI->isUnused()) {
2472  report("Live segment valno is marked unused", MF);
2473  report_context(LR, Reg, LaneMask);
2474  report_context(S);
2475  }
2476 
2477  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2478  if (!MBB) {
2479  report("Bad start of live segment, no basic block", MF);
2480  report_context(LR, Reg, LaneMask);
2481  report_context(S);
2482  return;
2483  }
2484  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
2485  if (S.start != MBBStartIdx && S.start != VNI->def) {
2486  report("Live segment must begin at MBB entry or valno def", MBB);
2487  report_context(LR, Reg, LaneMask);
2488  report_context(S);
2489  }
2490 
2491  const MachineBasicBlock *EndMBB =
2492  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
2493  if (!EndMBB) {
2494  report("Bad end of live segment, no basic block", MF);
2495  report_context(LR, Reg, LaneMask);
2496  report_context(S);
2497  return;
2498  }
2499 
2500  // No more checks for live-out segments.
2501  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
2502  return;
2503 
2504  // RegUnit intervals are allowed dead phis.
2505  if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2506  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
2507  return;
2508 
2509  // The live segment is ending inside EndMBB
2510  const MachineInstr *MI =
2511  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
2512  if (!MI) {
2513  report("Live segment doesn't end at a valid instruction", EndMBB);
2514  report_context(LR, Reg, LaneMask);
2515  report_context(S);
2516  return;
2517  }
2518 
2519  // The block slot must refer to a basic block boundary.
2520  if (S.end.isBlock()) {
2521  report("Live segment ends at B slot of an instruction", EndMBB);
2522  report_context(LR, Reg, LaneMask);
2523  report_context(S);
2524  }
2525 
2526  if (S.end.isDead()) {
2527  // Segment ends on the dead slot.
2528  // That means there must be a dead def.
2529  if (!SlotIndex::isSameInstr(S.start, S.end)) {
2530  report("Live segment ending at dead slot spans instructions", EndMBB);
2531  report_context(LR, Reg, LaneMask);
2532  report_context(S);
2533  }
2534  }
2535 
2536  // A live segment can only end at an early-clobber slot if it is being
2537  // redefined by an early-clobber def.
2538  if (S.end.isEarlyClobber()) {
2539  if (I+1 == LR.end() || (I+1)->start != S.end) {
2540  report("Live segment ending at early clobber slot must be "
2541  "redefined by an EC def in the same instruction", EndMBB);
2542  report_context(LR, Reg, LaneMask);
2543  report_context(S);
2544  }
2545  }
2546 
2547  // The following checks only apply to virtual registers. Physreg liveness
2548  // is too weird to check.
2549  if (Register::isVirtualRegister(Reg)) {
2550  // A live segment can end with either a redefinition, a kill flag on a
2551  // use, or a dead flag on a def.
2552  bool hasRead = false;
2553  bool hasSubRegDef = false;
2554  bool hasDeadDef = false;
2555  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2556  if (!MOI->isReg() || MOI->getReg() != Reg)
2557  continue;
2558  unsigned Sub = MOI->getSubReg();
2559  LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
2560  : LaneBitmask::getAll();
2561  if (MOI->isDef()) {
2562  if (Sub != 0) {
2563  hasSubRegDef = true;
2564  // An operand %0:sub0 reads %0:sub1..n. Invert the lane
2565  // mask for subregister defs. Read-undef defs will be handled by
2566  // readsReg below.
2567  SLM = ~SLM;
2568  }
2569  if (MOI->isDead())
2570  hasDeadDef = true;
2571  }
2572  if (LaneMask.any() && (LaneMask & SLM).none())
2573  continue;
2574  if (MOI->readsReg())
2575  hasRead = true;
2576  }
2577  if (S.end.isDead()) {
2578  // Make sure that the corresponding machine operand for a "dead" live
2579  // range has the dead flag. We cannot perform this check for subregister
2580  // liveranges as partially dead values are allowed.
2581  if (LaneMask.none() && !hasDeadDef) {
2582  report("Instruction ending live segment on dead slot has no dead flag",
2583  MI);
2584  report_context(LR, Reg, LaneMask);
2585  report_context(S);
2586  }
2587  } else {
2588  if (!hasRead) {
2589  // When tracking subregister liveness, the main range must start new
2590  // values on partial register writes, even if there is no read.
2591  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
2592  !hasSubRegDef) {
2593  report("Instruction ending live segment doesn't read the register",
2594  MI);
2595  report_context(LR, Reg, LaneMask);
2596  report_context(S);
2597  }
2598  }
2599  }
2600  }
2601 
2602  // Now check all the basic blocks in this live segment.
2604  // Is this live segment the beginning of a non-PHIDef VN?
2605  if (S.start == VNI->def && !VNI->isPHIDef()) {
2606  // Not live-in to any blocks.
2607  if (MBB == EndMBB)
2608  return;
2609  // Skip this block.
2610  ++MFI;
2611  }
2612 
2614  if (LaneMask.any()) {
2615  LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
2616  OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
2617  }
2618 
2619  while (true) {
2620  assert(LiveInts->isLiveInToMBB(LR, &*MFI));
2621  // We don't know how to track physregs into a landing pad.
2622  if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
2623  if (&*MFI == EndMBB)
2624  break;
2625  ++MFI;
2626  continue;
2627  }
2628 
2629  // Is VNI a PHI-def in the current block?
2630  bool IsPHI = VNI->isPHIDef() &&
2631  VNI->def == LiveInts->getMBBStartIdx(&*MFI);
2632 
2633  // Check that VNI is live-out of all predecessors.
2634  for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
2635  PE = MFI->pred_end(); PI != PE; ++PI) {
2636  SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
2637  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
2638 
2639  // All predecessors must have a live-out value. However for a phi
2640  // instruction with subregister intervals
2641  // only one of the subregisters (not necessarily the current one) needs to
2642  // be defined.
2643  if (!PVNI && (LaneMask.none() || !IsPHI)) {
2644  if (LiveRangeCalc::isJointlyDominated(*PI, Undefs, *Indexes))
2645  continue;
2646  report("Register not marked live out of predecessor", *PI);
2647  report_context(LR, Reg, LaneMask);
2648  report_context(*VNI);
2649  errs() << " live into " << printMBBReference(*MFI) << '@'
2650  << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
2651  << PEnd << '\n';
2652  continue;
2653  }
2654 
2655  // Only PHI-defs can take different predecessor values.
2656  if (!IsPHI && PVNI != VNI) {
2657  report("Different value live out of predecessor", *PI);
2658  report_context(LR, Reg, LaneMask);
2659  errs() << "Valno #" << PVNI->id << " live out of "
2660  << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
2661  << VNI->id << " live into " << printMBBReference(*MFI) << '@'
2662  << LiveInts->getMBBStartIdx(&*MFI) << '\n';
2663  }
2664  }
2665  if (&*MFI == EndMBB)
2666  break;
2667  ++MFI;
2668  }
2669 }
2670 
2671 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
2672  LaneBitmask LaneMask) {
2673  for (const VNInfo *VNI : LR.valnos)
2674  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
2675 
2676  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
2677  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
2678 }
2679 
2680 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
2681  unsigned Reg = LI.reg;
2683  verifyLiveRange(LI, Reg);
2684 
2685  LaneBitmask Mask;
2686  LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
2687  for (const LiveInterval::SubRange &SR : LI.subranges()) {
2688  if ((Mask & SR.LaneMask).any()) {
2689  report("Lane masks of sub ranges overlap in live interval", MF);
2690  report_context(LI);
2691  }
2692  if ((SR.LaneMask & ~MaxMask).any()) {
2693  report("Subrange lanemask is invalid", MF);
2694  report_context(LI);
2695  }
2696  if (SR.empty()) {
2697  report("Subrange must not be empty", MF);
2698  report_context(SR, LI.reg, SR.LaneMask);
2699  }
2700  Mask |= SR.LaneMask;
2701  verifyLiveRange(SR, LI.reg, SR.LaneMask);
2702  if (!LI.covers(SR)) {
2703  report("A Subrange is not covered by the main range", MF);
2704  report_context(LI);
2705  }
2706  }
2707 
2708  // Check the LI only has one connected component.
2709  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
2710  unsigned NumComp = ConEQ.Classify(LI);
2711  if (NumComp > 1) {
2712  report("Multiple connected components in live interval", MF);
2713  report_context(LI);
2714  for (unsigned comp = 0; comp != NumComp; ++comp) {
2715  errs() << comp << ": valnos";
2717  E = LI.vni_end(); I!=E; ++I)
2718  if (comp == ConEQ.getEqClass(*I))
2719  errs() << ' ' << (*I)->id;
2720  errs() << '\n';
2721  }
2722  }
2723 }
2724 
2725 namespace {
2726 
2727  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
2728  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
2729  // value is zero.
2730  // We use a bool plus an integer to capture the stack state.
2731  struct StackStateOfBB {
2732  StackStateOfBB() = default;
2733  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
2734  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
2735  ExitIsSetup(ExitSetup) {}
2736 
2737  // Can be negative, which means we are setting up a frame.
2738  int EntryValue = 0;
2739  int ExitValue = 0;
2740  bool EntryIsSetup = false;
2741  bool ExitIsSetup = false;
2742  };
2743 
2744 } // end anonymous namespace
2745 
2746 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
2747 /// by a FrameDestroy <n>, stack adjustments are identical on all
2748 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
2749 void MachineVerifier::verifyStackFrame() {
2750  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
2751  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
2752  if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
2753  return;
2754 
2756  SPState.resize(MF->getNumBlockIDs());
2758 
2759  // Visit the MBBs in DFS order.
2760  for (df_ext_iterator<const MachineFunction *,
2762  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
2763  DFI != DFE; ++DFI) {
2764  const MachineBasicBlock *MBB = *DFI;
2765 
2766  StackStateOfBB BBState;
2767  // Check the exit state of the DFS stack predecessor.
2768  if (DFI.getPathLength() >= 2) {
2769  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
2770  assert(Reachable.count(StackPred) &&
2771  "DFS stack predecessor is already visited.\n");
2772  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
2773  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
2774  BBState.ExitValue = BBState.EntryValue;
2775  BBState.ExitIsSetup = BBState.EntryIsSetup;
2776  }
2777 
2778  // Update stack state by checking contents of MBB.
2779  for (const auto &I : *MBB) {
2780  if (I.getOpcode() == FrameSetupOpcode) {
2781  if (BBState.ExitIsSetup)
2782  report("FrameSetup is after another FrameSetup", &I);
2783  BBState.ExitValue -= TII->getFrameTotalSize(I);
2784  BBState.ExitIsSetup = true;
2785  }
2786 
2787  if (I.getOpcode() == FrameDestroyOpcode) {
2788  int Size = TII->getFrameTotalSize(I);
2789  if (!BBState.ExitIsSetup)
2790  report("FrameDestroy is not after a FrameSetup", &I);
2791  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
2792  BBState.ExitValue;
2793  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
2794  report("FrameDestroy <n> is after FrameSetup <m>", &I);
2795  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
2796  << AbsSPAdj << ">.\n";
2797  }
2798  BBState.ExitValue += Size;
2799  BBState.ExitIsSetup = false;
2800  }
2801  }
2802  SPState[MBB->getNumber()] = BBState;
2803 
2804  // Make sure the exit state of any predecessor is consistent with the entry
2805  // state.
2806  for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
2807  E = MBB->pred_end(); I != E; ++I) {
2808  if (Reachable.count(*I) &&
2809  (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
2810  SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
2811  report("The exit stack state of a predecessor is inconsistent.", MBB);
2812  errs() << "Predecessor " << printMBBReference(*(*I))
2813  << " has exit state (" << SPState[(*I)->getNumber()].ExitValue
2814  << ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
2815  << printMBBReference(*MBB) << " has entry state ("
2816  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
2817  }
2818  }
2819 
2820  // Make sure the entry state of any successor is consistent with the exit
2821  // state.
2822  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
2823  E = MBB->succ_end(); I != E; ++I) {
2824  if (Reachable.count(*I) &&
2825  (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
2826  SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
2827  report("The entry stack state of a successor is inconsistent.", MBB);
2828  errs() << "Successor " << printMBBReference(*(*I))
2829  << " has entry state (" << SPState[(*I)->getNumber()].EntryValue
2830  << ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
2831  << printMBBReference(*MBB) << " has exit state ("
2832  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
2833  }
2834  }
2835 
2836  // Make sure a basic block with return ends with zero stack adjustment.
2837  if (!MBB->empty() && MBB->back().isReturn()) {
2838  if (BBState.ExitIsSetup)
2839  report("A return block ends with a FrameSetup.", MBB);
2840  if (BBState.ExitValue)
2841  report("A return block ends with a nonzero stack adjustment.", MBB);
2842  }
2843  }
2844 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:80
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:77
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:233
mop_iterator operands_end()
Definition: MachineInstr.h:471
A common definition of LaneBitmask for use in TableGen and CodeGen.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const unsigned reg
Definition: LiveInterval.h:708
bool isReserved(Register PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
MachineBasicBlock * getMBB() const
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:60
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:509
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
unsigned getScalarSizeInBits() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID&#39;s allocated.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const MachineFunctionProperties & getProperties() const
Get the function properties.
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
setjmp/longjmp based exceptions
bool isShuffleMask() const
vni_iterator vni_begin()
Definition: LiveInterval.h:223
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:679
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
static bool matchPair(MachineBasicBlock::const_succ_iterator i, const MachineBasicBlock *a, const MachineBasicBlock *b)
unsigned Reg
unsigned getSubReg() const
bool isInlineAsm() const
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:512
bool test(unsigned Idx) const
Definition: BitVector.h:501
LLT getScalarType() const
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:236
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:63
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:116
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:205
A live range for subregisters.
Definition: LiveInterval.h:686
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1165
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:151
MachineBasicBlock reference.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:161
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:78
unsigned const TargetRegisterInfo * TRI
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:93
F(f)
const fltSemantics & getSemantics() const
Definition: APFloat.h:1170
unsigned getCallFrameDestroyOpcode() const
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:83
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.cpp:144
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
VNInfo - Value Number Information.
Definition: LiveInterval.h:52
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void verifyUseLists() const
Verify the use list of all registers.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
unsigned getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:142
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
bool isInternalRead() const
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:156
void initializeMachineVerifierPassPass(PassRegistry &)
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:80
Mask of preserved registers.
bool isEarlyClobber() const
bool isIntrinsicID() const
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
bool test(unsigned Idx) const
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
bool isVector() const
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map...
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:226
A description of a memory reference used in the backend.
Definition: BitVector.h:937
void clear()
clear - Removes all bits from the bitvector. Does not change capacity.
Definition: BitVector.h:366
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:259
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:226
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getVarIdx() const
Get starting index of non call related arguments (calling convention, statepoint flags, vm state and gc state).
Definition: StackMaps.h:172
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
const ConstantFP * getFPImm() const
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
iterator end()
Definition: LiveInterval.h:215
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:764
Result of a LiveRange query.
Definition: LiveInterval.h:89
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:83
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:672
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:390
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:792
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block) ...
Definition: SlotIndexes.h:490
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
def_iterator def_begin(unsigned RegNo) const
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
Definition: LiveVariables.h:83
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:82
LLT getElementType() const
Returns the vector&#39;s element type. Only valid for vector types.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
unsigned getEqClass(const VNInfo *VNI) const
getEqClass - Classify creates equivalence classes numbered 0..N.
Definition: LiveInterval.h:979
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch, catchpad/ret, and cleanuppad/ret.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const
Returns true if Reg contains RegUnit.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
bool isValid() const
isValid - Returns true until all the operands have been visited.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:246
bool hasInterval(Register Reg) const
SlotIndexes pass.
Definition: SlotIndexes.h:314
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:254
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:351
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:111
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn&#39;t...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:104
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:532
TargetInstrInfo - Interface to description of machine instruction set.
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
Definition: Constants.cpp:359
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:412
bool isGenericType() const
Definition: MCInstrDesc.h:101
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:843
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
unsigned const MachineRegisterInfo * MRI
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:221
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:392
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
LLVM_NODISCARD bool empty() const
Definition: SmallPtrSet.h:91
unsigned Classify(const LiveRange &LR)
Classify the values in LR into connected components.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:370
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:385
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:469
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:566
bool isValid() const
constexpr bool none() const
Definition: LaneBitmask.h:51
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
constexpr double e
Definition: MathExtras.h:57
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:507
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:381
self_iterator getIterator()
Definition: ilist_node.h:81
LiveInterval & getInterval(Register Reg)
unsigned getAddressSpace() const
iterator_range< pred_iterator > predecessors()
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:479
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
MCSubRegIterator enumerates all sub-registers of Reg.
size_t size() const
Definition: SmallVector.h:52
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
bool isDebugInstr() const
const Constant * getShuffleMask() const
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
const APFloat & getValueAPF() const
Definition: Constants.h:302
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction&#39;s which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:88
size_type size() const
Definition: SmallPtrSet.h:92
unsigned id
The ID number of this value.
Definition: LiveInterval.h:57
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:203
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
Iterator for intrusive lists based on ilist_node.
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:390
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
Definition: SmallPtrSet.h:377
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:551
Segments::const_iterator const_iterator
Definition: LiveInterval.h:212
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
bool isDebugValue() const
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:966
MachineOperand class - Representation of each machine instruction operand.
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
Intrinsic::ID getIntrinsicID() const
modulo schedule Modulo Schedule test pass
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:241
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:630
This class implements the register bank concept.
Definition: RegisterBank.h:28
int64_t getImm() const
unsigned pred_size() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) FunctionPass *llvm
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
Definition: LiveInterval.h:420
Class to represent vector types.
Definition: DerivedTypes.h:432
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
Special value supplied for machine level alias analysis.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
void setPreservesAll()
Set by analyses that do not transform their input at all.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:229
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Base class for user error types.
Definition: Error.h:344
VNInfoList valnos
Definition: LiveInterval.h:203
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned succ_size() const
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:308
bool isPointer() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
unsigned getNumValNums() const
Definition: LiveInterval.h:304
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:62
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator begin() const
Definition: SmallPtrSet.h:396
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:289
bool isEHPad() const
Returns true if the block is a landing pad.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
#define I(x, y, z)
Definition: MD5.cpp:58
constexpr bool any() const
Definition: LaneBitmask.h:52
MI-level Statepoint operands.
Definition: StackMaps.h:154
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:169
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Abstract Stack Frame Index.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation...
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator begin()
Definition: LiveInterval.h:214
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:136
bool hasFnAttribute(Attribute::AttrKind Kind) const
Equivalent to hasAttribute(AttributeList::FunctionIndex, Kind) but may be faster. ...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:830
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
bool hasInterval(int Slot) const
Definition: LiveStacks.h:77
static def_iterator def_end()
SmallVector< int, 16 > getShuffleMask() const
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
aarch64 promote const
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:30
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:129
LLVM Value Representation.
Definition: Value.h:74
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1465
mop_iterator operands_begin()
Definition: MachineInstr.h:470
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:190
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:593
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:219
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:106
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:663
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index...
ppc ctr loops verify
Register getReg() const
getReg - Returns the register number.
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
const ConstantInt * getCImm() const
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
vni_iterator vni_end()
Definition: LiveInterval.h:224
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:22
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
hexagon widen stores
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:558
bool isImplicit() const
void resize(size_type N)
Definition: SmallVector.h:344
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1224