LLVM 19.0.0git
MachineVerifier.cpp
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1//===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Pass to verify generated machine code. The following is checked:
10//
11// Operand counts: All explicit operands must be present.
12//
13// Register classes: All physical and virtual register operands must be
14// compatible with the register class required by the instruction descriptor.
15//
16// Register live intervals: Registers must be defined only once, and must be
17// defined before use.
18//
19// The machine code verifier is enabled with the command-line option
20// -verify-machineinstrs.
21//===----------------------------------------------------------------------===//
22
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/DenseMap.h"
25#include "llvm/ADT/DenseSet.h"
28#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/StringRef.h"
33#include "llvm/ADT/Twine.h"
62#include "llvm/IR/BasicBlock.h"
63#include "llvm/IR/Constants.h"
65#include "llvm/IR/Function.h"
66#include "llvm/IR/InlineAsm.h"
69#include "llvm/MC/LaneBitmask.h"
70#include "llvm/MC/MCAsmInfo.h"
71#include "llvm/MC/MCDwarf.h"
72#include "llvm/MC/MCInstrDesc.h"
75#include "llvm/Pass.h"
79#include "llvm/Support/ModRef.h"
82#include <algorithm>
83#include <cassert>
84#include <cstddef>
85#include <cstdint>
86#include <iterator>
87#include <string>
88#include <utility>
89
90using namespace llvm;
91
92namespace {
93
94 struct MachineVerifier {
95 MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
96
97 MachineVerifier(const char *b, LiveVariables *LiveVars,
98 LiveIntervals *LiveInts, LiveStacks *LiveStks,
99 SlotIndexes *Indexes)
100 : Banner(b), LiveVars(LiveVars), LiveInts(LiveInts), LiveStks(LiveStks),
101 Indexes(Indexes) {}
102
103 unsigned verify(const MachineFunction &MF);
104
105 Pass *const PASS = nullptr;
106 const char *Banner;
107 const MachineFunction *MF = nullptr;
108 const TargetMachine *TM = nullptr;
109 const TargetInstrInfo *TII = nullptr;
110 const TargetRegisterInfo *TRI = nullptr;
111 const MachineRegisterInfo *MRI = nullptr;
112 const RegisterBankInfo *RBI = nullptr;
113
114 unsigned foundErrors = 0;
115
116 // Avoid querying the MachineFunctionProperties for each operand.
117 bool isFunctionRegBankSelected = false;
118 bool isFunctionSelected = false;
119 bool isFunctionTracksDebugUserValues = false;
120
121 using RegVector = SmallVector<Register, 16>;
122 using RegMaskVector = SmallVector<const uint32_t *, 4>;
123 using RegSet = DenseSet<Register>;
126
127 const MachineInstr *FirstNonPHI = nullptr;
128 const MachineInstr *FirstTerminator = nullptr;
129 BlockSet FunctionBlocks;
130
131 BitVector regsReserved;
132 RegSet regsLive;
133 RegVector regsDefined, regsDead, regsKilled;
134 RegMaskVector regMasks;
135
136 SlotIndex lastIndex;
137
138 // Add Reg and any sub-registers to RV
139 void addRegWithSubRegs(RegVector &RV, Register Reg) {
140 RV.push_back(Reg);
141 if (Reg.isPhysical())
142 append_range(RV, TRI->subregs(Reg.asMCReg()));
143 }
144
145 struct BBInfo {
146 // Is this MBB reachable from the MF entry point?
147 bool reachable = false;
148
149 // Vregs that must be live in because they are used without being
150 // defined. Map value is the user. vregsLiveIn doesn't include regs
151 // that only are used by PHI nodes.
152 RegMap vregsLiveIn;
153
154 // Regs killed in MBB. They may be defined again, and will then be in both
155 // regsKilled and regsLiveOut.
156 RegSet regsKilled;
157
158 // Regs defined in MBB and live out. Note that vregs passing through may
159 // be live out without being mentioned here.
160 RegSet regsLiveOut;
161
162 // Vregs that pass through MBB untouched. This set is disjoint from
163 // regsKilled and regsLiveOut.
164 RegSet vregsPassed;
165
166 // Vregs that must pass through MBB because they are needed by a successor
167 // block. This set is disjoint from regsLiveOut.
168 RegSet vregsRequired;
169
170 // Set versions of block's predecessor and successor lists.
171 BlockSet Preds, Succs;
172
173 BBInfo() = default;
174
175 // Add register to vregsRequired if it belongs there. Return true if
176 // anything changed.
177 bool addRequired(Register Reg) {
178 if (!Reg.isVirtual())
179 return false;
180 if (regsLiveOut.count(Reg))
181 return false;
182 return vregsRequired.insert(Reg).second;
183 }
184
185 // Same for a full set.
186 bool addRequired(const RegSet &RS) {
187 bool Changed = false;
188 for (Register Reg : RS)
189 Changed |= addRequired(Reg);
190 return Changed;
191 }
192
193 // Same for a full map.
194 bool addRequired(const RegMap &RM) {
195 bool Changed = false;
196 for (const auto &I : RM)
197 Changed |= addRequired(I.first);
198 return Changed;
199 }
200
201 // Live-out registers are either in regsLiveOut or vregsPassed.
202 bool isLiveOut(Register Reg) const {
203 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
204 }
205 };
206
207 // Extra register info per MBB.
209
210 bool isReserved(Register Reg) {
211 return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
212 }
213
214 bool isAllocatable(Register Reg) const {
215 return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
216 !regsReserved.test(Reg.id());
217 }
218
219 // Analysis information if available
220 LiveVariables *LiveVars = nullptr;
221 LiveIntervals *LiveInts = nullptr;
222 LiveStacks *LiveStks = nullptr;
223 SlotIndexes *Indexes = nullptr;
224
225 // This is calculated only when trying to verify convergence control tokens.
226 // Similar to the LLVM IR verifier, we calculate this locally instead of
227 // relying on the pass manager.
229
230 void visitMachineFunctionBefore();
231 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
232 void visitMachineBundleBefore(const MachineInstr *MI);
233
234 /// Verify that all of \p MI's virtual register operands are scalars.
235 /// \returns True if all virtual register operands are scalar. False
236 /// otherwise.
237 bool verifyAllRegOpsScalar(const MachineInstr &MI,
238 const MachineRegisterInfo &MRI);
239 bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
240
241 bool verifyGIntrinsicSideEffects(const MachineInstr *MI);
242 bool verifyGIntrinsicConvergence(const MachineInstr *MI);
243 void verifyPreISelGenericInstruction(const MachineInstr *MI);
244
245 void visitMachineInstrBefore(const MachineInstr *MI);
246 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
247 void visitMachineBundleAfter(const MachineInstr *MI);
248 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
249 void visitMachineFunctionAfter();
250
251 void report(const char *msg, const MachineFunction *MF);
252 void report(const char *msg, const MachineBasicBlock *MBB);
253 void report(const char *msg, const MachineInstr *MI);
254 void report(const char *msg, const MachineOperand *MO, unsigned MONum,
255 LLT MOVRegType = LLT{});
256 void report(const Twine &Msg, const MachineInstr *MI);
257
258 void report_context(const LiveInterval &LI) const;
259 void report_context(const LiveRange &LR, Register VRegUnit,
260 LaneBitmask LaneMask) const;
261 void report_context(const LiveRange::Segment &S) const;
262 void report_context(const VNInfo &VNI) const;
263 void report_context(SlotIndex Pos) const;
264 void report_context(MCPhysReg PhysReg) const;
265 void report_context_liverange(const LiveRange &LR) const;
266 void report_context_lanemask(LaneBitmask LaneMask) const;
267 void report_context_vreg(Register VReg) const;
268 void report_context_vreg_regunit(Register VRegOrUnit) const;
269
270 void verifyInlineAsm(const MachineInstr *MI);
271
272 void checkLiveness(const MachineOperand *MO, unsigned MONum);
273 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
274 SlotIndex UseIdx, const LiveRange &LR,
275 Register VRegOrUnit,
276 LaneBitmask LaneMask = LaneBitmask::getNone());
277 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
278 SlotIndex DefIdx, const LiveRange &LR,
279 Register VRegOrUnit, bool SubRangeCheck = false,
280 LaneBitmask LaneMask = LaneBitmask::getNone());
281
282 void markReachable(const MachineBasicBlock *MBB);
283 void calcRegsPassed();
284 void checkPHIOps(const MachineBasicBlock &MBB);
285
286 void calcRegsRequired();
287 void verifyLiveVariables();
288 void verifyLiveIntervals();
289 void verifyLiveInterval(const LiveInterval&);
290 void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
292 void verifyLiveRangeSegment(const LiveRange &,
295 void verifyLiveRange(const LiveRange &, Register,
296 LaneBitmask LaneMask = LaneBitmask::getNone());
297
298 void verifyStackFrame();
299
300 void verifySlotIndexes() const;
301 void verifyProperties(const MachineFunction &MF);
302 };
303
304 struct MachineVerifierPass : public MachineFunctionPass {
305 static char ID; // Pass ID, replacement for typeid
306
307 const std::string Banner;
308
309 MachineVerifierPass(std::string banner = std::string())
310 : MachineFunctionPass(ID), Banner(std::move(banner)) {
312 }
313
314 void getAnalysisUsage(AnalysisUsage &AU) const override {
319 AU.setPreservesAll();
321 }
322
323 bool runOnMachineFunction(MachineFunction &MF) override {
324 // Skip functions that have known verification problems.
325 // FIXME: Remove this mechanism when all problematic passes have been
326 // fixed.
327 if (MF.getProperties().hasProperty(
328 MachineFunctionProperties::Property::FailsVerification))
329 return false;
330
331 unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
332 if (FoundErrors)
333 report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
334 return false;
335 }
336 };
337
338} // end anonymous namespace
339
340char MachineVerifierPass::ID = 0;
341
342INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
343 "Verify generated machine code", false, false)
344
346 return new MachineVerifierPass(Banner);
347}
348
349void llvm::verifyMachineFunction(const std::string &Banner,
350 const MachineFunction &MF) {
351 // TODO: Use MFAM after porting below analyses.
352 // LiveVariables *LiveVars;
353 // LiveIntervals *LiveInts;
354 // LiveStacks *LiveStks;
355 // SlotIndexes *Indexes;
356 unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
357 if (FoundErrors)
358 report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
359}
360
361bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
362 const {
363 MachineFunction &MF = const_cast<MachineFunction&>(*this);
364 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
365 if (AbortOnErrors && FoundErrors)
366 report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
367 return FoundErrors == 0;
368}
369
371 const char *Banner, bool AbortOnErrors) const {
372 MachineFunction &MF = const_cast<MachineFunction &>(*this);
373 unsigned FoundErrors =
374 MachineVerifier(Banner, nullptr, LiveInts, nullptr, Indexes).verify(MF);
375 if (AbortOnErrors && FoundErrors)
376 report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
377 return FoundErrors == 0;
378}
379
380void MachineVerifier::verifySlotIndexes() const {
381 if (Indexes == nullptr)
382 return;
383
384 // Ensure the IdxMBB list is sorted by slot indexes.
387 E = Indexes->MBBIndexEnd(); I != E; ++I) {
388 assert(!Last.isValid() || I->first > Last);
389 Last = I->first;
390 }
391}
392
393void MachineVerifier::verifyProperties(const MachineFunction &MF) {
394 // If a pass has introduced virtual registers without clearing the
395 // NoVRegs property (or set it without allocating the vregs)
396 // then report an error.
397 if (MF.getProperties().hasProperty(
399 MRI->getNumVirtRegs())
400 report("Function has NoVRegs property but there are VReg operands", &MF);
401}
402
403unsigned MachineVerifier::verify(const MachineFunction &MF) {
404 foundErrors = 0;
405
406 this->MF = &MF;
407 TM = &MF.getTarget();
410 RBI = MF.getSubtarget().getRegBankInfo();
411 MRI = &MF.getRegInfo();
412
413 const bool isFunctionFailedISel = MF.getProperties().hasProperty(
415
416 // If we're mid-GlobalISel and we already triggered the fallback path then
417 // it's expected that the MIR is somewhat broken but that's ok since we'll
418 // reset it and clear the FailedISel attribute in ResetMachineFunctions.
419 if (isFunctionFailedISel)
420 return foundErrors;
421
422 isFunctionRegBankSelected = MF.getProperties().hasProperty(
424 isFunctionSelected = MF.getProperties().hasProperty(
426 isFunctionTracksDebugUserValues = MF.getProperties().hasProperty(
428
429 if (PASS) {
430 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
431 // We don't want to verify LiveVariables if LiveIntervals is available.
432 if (!LiveInts)
433 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
434 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
435 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
436 }
437
438 verifySlotIndexes();
439
440 verifyProperties(MF);
441
442 visitMachineFunctionBefore();
443 for (const MachineBasicBlock &MBB : MF) {
444 visitMachineBasicBlockBefore(&MBB);
445 // Keep track of the current bundle header.
446 const MachineInstr *CurBundle = nullptr;
447 // Do we expect the next instruction to be part of the same bundle?
448 bool InBundle = false;
449
450 for (const MachineInstr &MI : MBB.instrs()) {
451 if (MI.getParent() != &MBB) {
452 report("Bad instruction parent pointer", &MBB);
453 errs() << "Instruction: " << MI;
454 continue;
455 }
456
457 // Check for consistent bundle flags.
458 if (InBundle && !MI.isBundledWithPred())
459 report("Missing BundledPred flag, "
460 "BundledSucc was set on predecessor",
461 &MI);
462 if (!InBundle && MI.isBundledWithPred())
463 report("BundledPred flag is set, "
464 "but BundledSucc not set on predecessor",
465 &MI);
466
467 // Is this a bundle header?
468 if (!MI.isInsideBundle()) {
469 if (CurBundle)
470 visitMachineBundleAfter(CurBundle);
471 CurBundle = &MI;
472 visitMachineBundleBefore(CurBundle);
473 } else if (!CurBundle)
474 report("No bundle header", &MI);
475 visitMachineInstrBefore(&MI);
476 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
477 const MachineOperand &Op = MI.getOperand(I);
478 if (Op.getParent() != &MI) {
479 // Make sure to use correct addOperand / removeOperand / ChangeTo
480 // functions when replacing operands of a MachineInstr.
481 report("Instruction has operand with wrong parent set", &MI);
482 }
483
484 visitMachineOperand(&Op, I);
485 }
486
487 // Was this the last bundled instruction?
488 InBundle = MI.isBundledWithSucc();
489 }
490 if (CurBundle)
491 visitMachineBundleAfter(CurBundle);
492 if (InBundle)
493 report("BundledSucc flag set on last instruction in block", &MBB.back());
494 visitMachineBasicBlockAfter(&MBB);
495 }
496 visitMachineFunctionAfter();
497
498 // Clean up.
499 regsLive.clear();
500 regsDefined.clear();
501 regsDead.clear();
502 regsKilled.clear();
503 regMasks.clear();
504 MBBInfoMap.clear();
505
506 return foundErrors;
507}
508
509void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
510 assert(MF);
511 errs() << '\n';
512 if (!foundErrors++) {
513 if (Banner)
514 errs() << "# " << Banner << '\n';
515 if (LiveInts != nullptr)
516 LiveInts->print(errs());
517 else
518 MF->print(errs(), Indexes);
519 }
520 errs() << "*** Bad machine code: " << msg << " ***\n"
521 << "- function: " << MF->getName() << "\n";
522}
523
524void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
525 assert(MBB);
526 report(msg, MBB->getParent());
527 errs() << "- basic block: " << printMBBReference(*MBB) << ' '
528 << MBB->getName() << " (" << (const void *)MBB << ')';
529 if (Indexes)
530 errs() << " [" << Indexes->getMBBStartIdx(MBB)
531 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
532 errs() << '\n';
533}
534
535void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
536 assert(MI);
537 report(msg, MI->getParent());
538 errs() << "- instruction: ";
539 if (Indexes && Indexes->hasIndex(*MI))
540 errs() << Indexes->getInstructionIndex(*MI) << '\t';
541 MI->print(errs(), /*IsStandalone=*/true);
542}
543
544void MachineVerifier::report(const char *msg, const MachineOperand *MO,
545 unsigned MONum, LLT MOVRegType) {
546 assert(MO);
547 report(msg, MO->getParent());
548 errs() << "- operand " << MONum << ": ";
549 MO->print(errs(), MOVRegType, TRI);
550 errs() << "\n";
551}
552
553void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
554 report(Msg.str().c_str(), MI);
555}
556
557void MachineVerifier::report_context(SlotIndex Pos) const {
558 errs() << "- at: " << Pos << '\n';
559}
560
561void MachineVerifier::report_context(const LiveInterval &LI) const {
562 errs() << "- interval: " << LI << '\n';
563}
564
565void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
566 LaneBitmask LaneMask) const {
567 report_context_liverange(LR);
568 report_context_vreg_regunit(VRegUnit);
569 if (LaneMask.any())
570 report_context_lanemask(LaneMask);
571}
572
573void MachineVerifier::report_context(const LiveRange::Segment &S) const {
574 errs() << "- segment: " << S << '\n';
575}
576
577void MachineVerifier::report_context(const VNInfo &VNI) const {
578 errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
579}
580
581void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
582 errs() << "- liverange: " << LR << '\n';
583}
584
585void MachineVerifier::report_context(MCPhysReg PReg) const {
586 errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
587}
588
589void MachineVerifier::report_context_vreg(Register VReg) const {
590 errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
591}
592
593void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
594 if (VRegOrUnit.isVirtual()) {
595 report_context_vreg(VRegOrUnit);
596 } else {
597 errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
598 }
599}
600
601void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
602 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
603}
604
605void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
606 BBInfo &MInfo = MBBInfoMap[MBB];
607 if (!MInfo.reachable) {
608 MInfo.reachable = true;
609 for (const MachineBasicBlock *Succ : MBB->successors())
610 markReachable(Succ);
611 }
612}
613
614void MachineVerifier::visitMachineFunctionBefore() {
615 lastIndex = SlotIndex();
616 regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
617 : TRI->getReservedRegs(*MF);
618
619 if (!MF->empty())
620 markReachable(&MF->front());
621
622 // Build a set of the basic blocks in the function.
623 FunctionBlocks.clear();
624 for (const auto &MBB : *MF) {
625 FunctionBlocks.insert(&MBB);
626 BBInfo &MInfo = MBBInfoMap[&MBB];
627
628 MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
629 if (MInfo.Preds.size() != MBB.pred_size())
630 report("MBB has duplicate entries in its predecessor list.", &MBB);
631
632 MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
633 if (MInfo.Succs.size() != MBB.succ_size())
634 report("MBB has duplicate entries in its successor list.", &MBB);
635 }
636
637 // Check that the register use lists are sane.
638 MRI->verifyUseLists();
639
640 if (!MF->empty())
641 verifyStackFrame();
642}
643
644void
645MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
646 FirstTerminator = nullptr;
647 FirstNonPHI = nullptr;
648
649 if (!MF->getProperties().hasProperty(
650 MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
651 // If this block has allocatable physical registers live-in, check that
652 // it is an entry block or landing pad.
653 for (const auto &LI : MBB->liveins()) {
654 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
655 MBB->getIterator() != MBB->getParent()->begin() &&
657 report("MBB has allocatable live-in, but isn't entry, landing-pad, or "
658 "inlineasm-br-indirect-target.",
659 MBB);
660 report_context(LI.PhysReg);
661 }
662 }
663 }
664
665 if (MBB->isIRBlockAddressTaken()) {
667 report("ir-block-address-taken is associated with basic block not used by "
668 "a blockaddress.",
669 MBB);
670 }
671
672 // Count the number of landing pad successors.
674 for (const auto *succ : MBB->successors()) {
675 if (succ->isEHPad())
676 LandingPadSuccs.insert(succ);
677 if (!FunctionBlocks.count(succ))
678 report("MBB has successor that isn't part of the function.", MBB);
679 if (!MBBInfoMap[succ].Preds.count(MBB)) {
680 report("Inconsistent CFG", MBB);
681 errs() << "MBB is not in the predecessor list of the successor "
682 << printMBBReference(*succ) << ".\n";
683 }
684 }
685
686 // Check the predecessor list.
687 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
688 if (!FunctionBlocks.count(Pred))
689 report("MBB has predecessor that isn't part of the function.", MBB);
690 if (!MBBInfoMap[Pred].Succs.count(MBB)) {
691 report("Inconsistent CFG", MBB);
692 errs() << "MBB is not in the successor list of the predecessor "
693 << printMBBReference(*Pred) << ".\n";
694 }
695 }
696
697 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
698 const BasicBlock *BB = MBB->getBasicBlock();
699 const Function &F = MF->getFunction();
700 if (LandingPadSuccs.size() > 1 &&
701 !(AsmInfo &&
703 BB && isa<SwitchInst>(BB->getTerminator())) &&
704 !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
705 report("MBB has more than one landing pad successor", MBB);
706
707 // Call analyzeBranch. If it succeeds, there several more conditions to check.
708 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
710 if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
711 Cond)) {
712 // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
713 // check whether its answers match up with reality.
714 if (!TBB && !FBB) {
715 // Block falls through to its successor.
716 if (!MBB->empty() && MBB->back().isBarrier() &&
717 !TII->isPredicated(MBB->back())) {
718 report("MBB exits via unconditional fall-through but ends with a "
719 "barrier instruction!", MBB);
720 }
721 if (!Cond.empty()) {
722 report("MBB exits via unconditional fall-through but has a condition!",
723 MBB);
724 }
725 } else if (TBB && !FBB && Cond.empty()) {
726 // Block unconditionally branches somewhere.
727 if (MBB->empty()) {
728 report("MBB exits via unconditional branch but doesn't contain "
729 "any instructions!", MBB);
730 } else if (!MBB->back().isBarrier()) {
731 report("MBB exits via unconditional branch but doesn't end with a "
732 "barrier instruction!", MBB);
733 } else if (!MBB->back().isTerminator()) {
734 report("MBB exits via unconditional branch but the branch isn't a "
735 "terminator instruction!", MBB);
736 }
737 } else if (TBB && !FBB && !Cond.empty()) {
738 // Block conditionally branches somewhere, otherwise falls through.
739 if (MBB->empty()) {
740 report("MBB exits via conditional branch/fall-through but doesn't "
741 "contain any instructions!", MBB);
742 } else if (MBB->back().isBarrier()) {
743 report("MBB exits via conditional branch/fall-through but ends with a "
744 "barrier instruction!", MBB);
745 } else if (!MBB->back().isTerminator()) {
746 report("MBB exits via conditional branch/fall-through but the branch "
747 "isn't a terminator instruction!", MBB);
748 }
749 } else if (TBB && FBB) {
750 // Block conditionally branches somewhere, otherwise branches
751 // somewhere else.
752 if (MBB->empty()) {
753 report("MBB exits via conditional branch/branch but doesn't "
754 "contain any instructions!", MBB);
755 } else if (!MBB->back().isBarrier()) {
756 report("MBB exits via conditional branch/branch but doesn't end with a "
757 "barrier instruction!", MBB);
758 } else if (!MBB->back().isTerminator()) {
759 report("MBB exits via conditional branch/branch but the branch "
760 "isn't a terminator instruction!", MBB);
761 }
762 if (Cond.empty()) {
763 report("MBB exits via conditional branch/branch but there's no "
764 "condition!", MBB);
765 }
766 } else {
767 report("analyzeBranch returned invalid data!", MBB);
768 }
769
770 // Now check that the successors match up with the answers reported by
771 // analyzeBranch.
772 if (TBB && !MBB->isSuccessor(TBB))
773 report("MBB exits via jump or conditional branch, but its target isn't a "
774 "CFG successor!",
775 MBB);
776 if (FBB && !MBB->isSuccessor(FBB))
777 report("MBB exits via conditional branch, but its target isn't a CFG "
778 "successor!",
779 MBB);
780
781 // There might be a fallthrough to the next block if there's either no
782 // unconditional true branch, or if there's a condition, and one of the
783 // branches is missing.
784 bool Fallthrough = !TBB || (!Cond.empty() && !FBB);
785
786 // A conditional fallthrough must be an actual CFG successor, not
787 // unreachable. (Conversely, an unconditional fallthrough might not really
788 // be a successor, because the block might end in unreachable.)
789 if (!Cond.empty() && !FBB) {
791 if (MBBI == MF->end()) {
792 report("MBB conditionally falls through out of function!", MBB);
793 } else if (!MBB->isSuccessor(&*MBBI))
794 report("MBB exits via conditional branch/fall-through but the CFG "
795 "successors don't match the actual successors!",
796 MBB);
797 }
798
799 // Verify that there aren't any extra un-accounted-for successors.
800 for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
801 // If this successor is one of the branch targets, it's okay.
802 if (SuccMBB == TBB || SuccMBB == FBB)
803 continue;
804 // If we might have a fallthrough, and the successor is the fallthrough
805 // block, that's also ok.
806 if (Fallthrough && SuccMBB == MBB->getNextNode())
807 continue;
808 // Also accept successors which are for exception-handling or might be
809 // inlineasm_br targets.
810 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
811 continue;
812 report("MBB has unexpected successors which are not branch targets, "
813 "fallthrough, EHPads, or inlineasm_br targets.",
814 MBB);
815 }
816 }
817
818 regsLive.clear();
819 if (MRI->tracksLiveness()) {
820 for (const auto &LI : MBB->liveins()) {
821 if (!Register::isPhysicalRegister(LI.PhysReg)) {
822 report("MBB live-in list contains non-physical register", MBB);
823 continue;
824 }
825 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
826 regsLive.insert(SubReg);
827 }
828 }
829
830 const MachineFrameInfo &MFI = MF->getFrameInfo();
831 BitVector PR = MFI.getPristineRegs(*MF);
832 for (unsigned I : PR.set_bits()) {
833 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
834 regsLive.insert(SubReg);
835 }
836
837 regsKilled.clear();
838 regsDefined.clear();
839
840 if (Indexes)
841 lastIndex = Indexes->getMBBStartIdx(MBB);
842}
843
844// This function gets called for all bundle headers, including normal
845// stand-alone unbundled instructions.
846void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
847 if (Indexes && Indexes->hasIndex(*MI)) {
848 SlotIndex idx = Indexes->getInstructionIndex(*MI);
849 if (!(idx > lastIndex)) {
850 report("Instruction index out of order", MI);
851 errs() << "Last instruction was at " << lastIndex << '\n';
852 }
853 lastIndex = idx;
854 }
855
856 // Ensure non-terminators don't follow terminators.
857 if (MI->isTerminator()) {
858 if (!FirstTerminator)
859 FirstTerminator = MI;
860 } else if (FirstTerminator) {
861 // For GlobalISel, G_INVOKE_REGION_START is a terminator that we allow to
862 // precede non-terminators.
863 if (FirstTerminator->getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
864 report("Non-terminator instruction after the first terminator", MI);
865 errs() << "First terminator was:\t" << *FirstTerminator;
866 }
867 }
868}
869
870// The operands on an INLINEASM instruction must follow a template.
871// Verify that the flag operands make sense.
872void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
873 // The first two operands on INLINEASM are the asm string and global flags.
874 if (MI->getNumOperands() < 2) {
875 report("Too few operands on inline asm", MI);
876 return;
877 }
878 if (!MI->getOperand(0).isSymbol())
879 report("Asm string must be an external symbol", MI);
880 if (!MI->getOperand(1).isImm())
881 report("Asm flags must be an immediate", MI);
882 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
883 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
884 // and Extra_IsConvergent = 32.
885 if (!isUInt<6>(MI->getOperand(1).getImm()))
886 report("Unknown asm flags", &MI->getOperand(1), 1);
887
888 static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
889
890 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
891 unsigned NumOps;
892 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
893 const MachineOperand &MO = MI->getOperand(OpNo);
894 // There may be implicit ops after the fixed operands.
895 if (!MO.isImm())
896 break;
897 const InlineAsm::Flag F(MO.getImm());
898 NumOps = 1 + F.getNumOperandRegisters();
899 }
900
901 if (OpNo > MI->getNumOperands())
902 report("Missing operands in last group", MI);
903
904 // An optional MDNode follows the groups.
905 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
906 ++OpNo;
907
908 // All trailing operands must be implicit registers.
909 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
910 const MachineOperand &MO = MI->getOperand(OpNo);
911 if (!MO.isReg() || !MO.isImplicit())
912 report("Expected implicit register after groups", &MO, OpNo);
913 }
914
915 if (MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
916 const MachineBasicBlock *MBB = MI->getParent();
917
918 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
919 i != e; ++i) {
920 const MachineOperand &MO = MI->getOperand(i);
921
922 if (!MO.isMBB())
923 continue;
924
925 // Check the successor & predecessor lists look ok, assume they are
926 // not. Find the indirect target without going through the successors.
927 const MachineBasicBlock *IndirectTargetMBB = MO.getMBB();
928 if (!IndirectTargetMBB) {
929 report("INLINEASM_BR indirect target does not exist", &MO, i);
930 break;
931 }
932
933 if (!MBB->isSuccessor(IndirectTargetMBB))
934 report("INLINEASM_BR indirect target missing from successor list", &MO,
935 i);
936
937 if (!IndirectTargetMBB->isPredecessor(MBB))
938 report("INLINEASM_BR indirect target predecessor list missing parent",
939 &MO, i);
940 }
941 }
942}
943
944bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
945 const MachineRegisterInfo &MRI) {
946 if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
947 if (!Op.isReg())
948 return false;
949 const auto Reg = Op.getReg();
950 if (Reg.isPhysical())
951 return false;
952 return !MRI.getType(Reg).isScalar();
953 }))
954 return true;
955 report("All register operands must have scalar types", &MI);
956 return false;
957}
958
959/// Check that types are consistent when two operands need to have the same
960/// number of vector elements.
961/// \return true if the types are valid.
962bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
963 const MachineInstr *MI) {
964 if (Ty0.isVector() != Ty1.isVector()) {
965 report("operand types must be all-vector or all-scalar", MI);
966 // Generally we try to report as many issues as possible at once, but in
967 // this case it's not clear what should we be comparing the size of the
968 // scalar with: the size of the whole vector or its lane. Instead of
969 // making an arbitrary choice and emitting not so helpful message, let's
970 // avoid the extra noise and stop here.
971 return false;
972 }
973
974 if (Ty0.isVector() && Ty0.getElementCount() != Ty1.getElementCount()) {
975 report("operand types must preserve number of vector elements", MI);
976 return false;
977 }
978
979 return true;
980}
981
982bool MachineVerifier::verifyGIntrinsicSideEffects(const MachineInstr *MI) {
983 auto Opcode = MI->getOpcode();
984 bool NoSideEffects = Opcode == TargetOpcode::G_INTRINSIC ||
985 Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
986 unsigned IntrID = cast<GIntrinsic>(MI)->getIntrinsicID();
987 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
989 MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
990 bool DeclHasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();
991 if (NoSideEffects && DeclHasSideEffects) {
992 report(Twine(TII->getName(Opcode),
993 " used with intrinsic that accesses memory"),
994 MI);
995 return false;
996 }
997 if (!NoSideEffects && !DeclHasSideEffects) {
998 report(Twine(TII->getName(Opcode), " used with readnone intrinsic"), MI);
999 return false;
1000 }
1001 }
1002
1003 return true;
1004}
1005
1006bool MachineVerifier::verifyGIntrinsicConvergence(const MachineInstr *MI) {
1007 auto Opcode = MI->getOpcode();
1008 bool NotConvergent = Opcode == TargetOpcode::G_INTRINSIC ||
1009 Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
1010 unsigned IntrID = cast<GIntrinsic>(MI)->getIntrinsicID();
1011 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1013 MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
1014 bool DeclIsConvergent = Attrs.hasFnAttr(Attribute::Convergent);
1015 if (NotConvergent && DeclIsConvergent) {
1016 report(Twine(TII->getName(Opcode), " used with a convergent intrinsic"),
1017 MI);
1018 return false;
1019 }
1020 if (!NotConvergent && !DeclIsConvergent) {
1021 report(
1022 Twine(TII->getName(Opcode), " used with a non-convergent intrinsic"),
1023 MI);
1024 return false;
1025 }
1026 }
1027
1028 return true;
1029}
1030
1031void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
1032 if (isFunctionSelected)
1033 report("Unexpected generic instruction in a Selected function", MI);
1034
1035 const MCInstrDesc &MCID = MI->getDesc();
1036 unsigned NumOps = MI->getNumOperands();
1037
1038 // Branches must reference a basic block if they are not indirect
1039 if (MI->isBranch() && !MI->isIndirectBranch()) {
1040 bool HasMBB = false;
1041 for (const MachineOperand &Op : MI->operands()) {
1042 if (Op.isMBB()) {
1043 HasMBB = true;
1044 break;
1045 }
1046 }
1047
1048 if (!HasMBB) {
1049 report("Branch instruction is missing a basic block operand or "
1050 "isIndirectBranch property",
1051 MI);
1052 }
1053 }
1054
1055 // Check types.
1057 for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
1058 I != E; ++I) {
1059 if (!MCID.operands()[I].isGenericType())
1060 continue;
1061 // Generic instructions specify type equality constraints between some of
1062 // their operands. Make sure these are consistent.
1063 size_t TypeIdx = MCID.operands()[I].getGenericTypeIndex();
1064 Types.resize(std::max(TypeIdx + 1, Types.size()));
1065
1066 const MachineOperand *MO = &MI->getOperand(I);
1067 if (!MO->isReg()) {
1068 report("generic instruction must use register operands", MI);
1069 continue;
1070 }
1071
1072 LLT OpTy = MRI->getType(MO->getReg());
1073 // Don't report a type mismatch if there is no actual mismatch, only a
1074 // type missing, to reduce noise:
1075 if (OpTy.isValid()) {
1076 // Only the first valid type for a type index will be printed: don't
1077 // overwrite it later so it's always clear which type was expected:
1078 if (!Types[TypeIdx].isValid())
1079 Types[TypeIdx] = OpTy;
1080 else if (Types[TypeIdx] != OpTy)
1081 report("Type mismatch in generic instruction", MO, I, OpTy);
1082 } else {
1083 // Generic instructions must have types attached to their operands.
1084 report("Generic instruction is missing a virtual register type", MO, I);
1085 }
1086 }
1087
1088 // Generic opcodes must not have physical register operands.
1089 for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
1090 const MachineOperand *MO = &MI->getOperand(I);
1091 if (MO->isReg() && MO->getReg().isPhysical())
1092 report("Generic instruction cannot have physical register", MO, I);
1093 }
1094
1095 // Avoid out of bounds in checks below. This was already reported earlier.
1096 if (MI->getNumOperands() < MCID.getNumOperands())
1097 return;
1098
1100 if (!TII->verifyInstruction(*MI, ErrorInfo))
1101 report(ErrorInfo.data(), MI);
1102
1103 // Verify properties of various specific instruction types
1104 unsigned Opc = MI->getOpcode();
1105 switch (Opc) {
1106 case TargetOpcode::G_ASSERT_SEXT:
1107 case TargetOpcode::G_ASSERT_ZEXT: {
1108 std::string OpcName =
1109 Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
1110 if (!MI->getOperand(2).isImm()) {
1111 report(Twine(OpcName, " expects an immediate operand #2"), MI);
1112 break;
1113 }
1114
1115 Register Dst = MI->getOperand(0).getReg();
1116 Register Src = MI->getOperand(1).getReg();
1117 LLT SrcTy = MRI->getType(Src);
1118 int64_t Imm = MI->getOperand(2).getImm();
1119 if (Imm <= 0) {
1120 report(Twine(OpcName, " size must be >= 1"), MI);
1121 break;
1122 }
1123
1124 if (Imm >= SrcTy.getScalarSizeInBits()) {
1125 report(Twine(OpcName, " size must be less than source bit width"), MI);
1126 break;
1127 }
1128
1129 const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI);
1130 const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI);
1131
1132 // Allow only the source bank to be set.
1133 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1134 report(Twine(OpcName, " cannot change register bank"), MI);
1135 break;
1136 }
1137
1138 // Don't allow a class change. Do allow member class->regbank.
1139 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst);
1140 if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) {
1141 report(
1142 Twine(OpcName, " source and destination register classes must match"),
1143 MI);
1144 break;
1145 }
1146
1147 break;
1148 }
1149
1150 case TargetOpcode::G_CONSTANT:
1151 case TargetOpcode::G_FCONSTANT: {
1152 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1153 if (DstTy.isVector())
1154 report("Instruction cannot use a vector result type", MI);
1155
1156 if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1157 if (!MI->getOperand(1).isCImm()) {
1158 report("G_CONSTANT operand must be cimm", MI);
1159 break;
1160 }
1161
1162 const ConstantInt *CI = MI->getOperand(1).getCImm();
1163 if (CI->getBitWidth() != DstTy.getSizeInBits())
1164 report("inconsistent constant size", MI);
1165 } else {
1166 if (!MI->getOperand(1).isFPImm()) {
1167 report("G_FCONSTANT operand must be fpimm", MI);
1168 break;
1169 }
1170 const ConstantFP *CF = MI->getOperand(1).getFPImm();
1171
1173 DstTy.getSizeInBits()) {
1174 report("inconsistent constant size", MI);
1175 }
1176 }
1177
1178 break;
1179 }
1180 case TargetOpcode::G_LOAD:
1181 case TargetOpcode::G_STORE:
1182 case TargetOpcode::G_ZEXTLOAD:
1183 case TargetOpcode::G_SEXTLOAD: {
1184 LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1185 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1186 if (!PtrTy.isPointer())
1187 report("Generic memory instruction must access a pointer", MI);
1188
1189 // Generic loads and stores must have a single MachineMemOperand
1190 // describing that access.
1191 if (!MI->hasOneMemOperand()) {
1192 report("Generic instruction accessing memory must have one mem operand",
1193 MI);
1194 } else {
1195 const MachineMemOperand &MMO = **MI->memoperands_begin();
1196 if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1197 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1199 ValTy.getSizeInBits()))
1200 report("Generic extload must have a narrower memory type", MI);
1201 } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1203 ValTy.getSizeInBytes()))
1204 report("load memory size cannot exceed result size", MI);
1205 } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1207 MMO.getSize().getValue()))
1208 report("store memory size cannot exceed value size", MI);
1209 }
1210
1211 const AtomicOrdering Order = MMO.getSuccessOrdering();
1212 if (Opc == TargetOpcode::G_STORE) {
1213 if (Order == AtomicOrdering::Acquire ||
1215 report("atomic store cannot use acquire ordering", MI);
1216
1217 } else {
1218 if (Order == AtomicOrdering::Release ||
1220 report("atomic load cannot use release ordering", MI);
1221 }
1222 }
1223
1224 break;
1225 }
1226 case TargetOpcode::G_PHI: {
1227 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1228 if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1229 [this, &DstTy](const MachineOperand &MO) {
1230 if (!MO.isReg())
1231 return true;
1232 LLT Ty = MRI->getType(MO.getReg());
1233 if (!Ty.isValid() || (Ty != DstTy))
1234 return false;
1235 return true;
1236 }))
1237 report("Generic Instruction G_PHI has operands with incompatible/missing "
1238 "types",
1239 MI);
1240 break;
1241 }
1242 case TargetOpcode::G_BITCAST: {
1243 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1244 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1245 if (!DstTy.isValid() || !SrcTy.isValid())
1246 break;
1247
1248 if (SrcTy.isPointer() != DstTy.isPointer())
1249 report("bitcast cannot convert between pointers and other types", MI);
1250
1251 if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1252 report("bitcast sizes must match", MI);
1253
1254 if (SrcTy == DstTy)
1255 report("bitcast must change the type", MI);
1256
1257 break;
1258 }
1259 case TargetOpcode::G_INTTOPTR:
1260 case TargetOpcode::G_PTRTOINT:
1261 case TargetOpcode::G_ADDRSPACE_CAST: {
1262 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1263 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1264 if (!DstTy.isValid() || !SrcTy.isValid())
1265 break;
1266
1267 verifyVectorElementMatch(DstTy, SrcTy, MI);
1268
1269 DstTy = DstTy.getScalarType();
1270 SrcTy = SrcTy.getScalarType();
1271
1272 if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1273 if (!DstTy.isPointer())
1274 report("inttoptr result type must be a pointer", MI);
1275 if (SrcTy.isPointer())
1276 report("inttoptr source type must not be a pointer", MI);
1277 } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1278 if (!SrcTy.isPointer())
1279 report("ptrtoint source type must be a pointer", MI);
1280 if (DstTy.isPointer())
1281 report("ptrtoint result type must not be a pointer", MI);
1282 } else {
1283 assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1284 if (!SrcTy.isPointer() || !DstTy.isPointer())
1285 report("addrspacecast types must be pointers", MI);
1286 else {
1287 if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1288 report("addrspacecast must convert different address spaces", MI);
1289 }
1290 }
1291
1292 break;
1293 }
1294 case TargetOpcode::G_PTR_ADD: {
1295 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1296 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1297 LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1298 if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1299 break;
1300
1301 if (!PtrTy.isPointerOrPointerVector())
1302 report("gep first operand must be a pointer", MI);
1303
1304 if (OffsetTy.isPointerOrPointerVector())
1305 report("gep offset operand must not be a pointer", MI);
1306
1307 if (PtrTy.isPointerOrPointerVector()) {
1308 const DataLayout &DL = MF->getDataLayout();
1309 unsigned AS = PtrTy.getAddressSpace();
1310 unsigned IndexSizeInBits = DL.getIndexSize(AS) * 8;
1311 if (OffsetTy.getScalarSizeInBits() != IndexSizeInBits) {
1312 report("gep offset operand must match index size for address space",
1313 MI);
1314 }
1315 }
1316
1317 // TODO: Is the offset allowed to be a scalar with a vector?
1318 break;
1319 }
1320 case TargetOpcode::G_PTRMASK: {
1321 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1322 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1323 LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1324 if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
1325 break;
1326
1327 if (!DstTy.isPointerOrPointerVector())
1328 report("ptrmask result type must be a pointer", MI);
1329
1330 if (!MaskTy.getScalarType().isScalar())
1331 report("ptrmask mask type must be an integer", MI);
1332
1333 verifyVectorElementMatch(DstTy, MaskTy, MI);
1334 break;
1335 }
1336 case TargetOpcode::G_SEXT:
1337 case TargetOpcode::G_ZEXT:
1338 case TargetOpcode::G_ANYEXT:
1339 case TargetOpcode::G_TRUNC:
1340 case TargetOpcode::G_FPEXT:
1341 case TargetOpcode::G_FPTRUNC: {
1342 // Number of operands and presense of types is already checked (and
1343 // reported in case of any issues), so no need to report them again. As
1344 // we're trying to report as many issues as possible at once, however, the
1345 // instructions aren't guaranteed to have the right number of operands or
1346 // types attached to them at this point
1347 assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1348 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1349 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1350 if (!DstTy.isValid() || !SrcTy.isValid())
1351 break;
1352
1354 report("Generic extend/truncate can not operate on pointers", MI);
1355
1356 verifyVectorElementMatch(DstTy, SrcTy, MI);
1357
1358 unsigned DstSize = DstTy.getScalarSizeInBits();
1359 unsigned SrcSize = SrcTy.getScalarSizeInBits();
1360 switch (MI->getOpcode()) {
1361 default:
1362 if (DstSize <= SrcSize)
1363 report("Generic extend has destination type no larger than source", MI);
1364 break;
1365 case TargetOpcode::G_TRUNC:
1366 case TargetOpcode::G_FPTRUNC:
1367 if (DstSize >= SrcSize)
1368 report("Generic truncate has destination type no smaller than source",
1369 MI);
1370 break;
1371 }
1372 break;
1373 }
1374 case TargetOpcode::G_SELECT: {
1375 LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1376 LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1377 if (!SelTy.isValid() || !CondTy.isValid())
1378 break;
1379
1380 // Scalar condition select on a vector is valid.
1381 if (CondTy.isVector())
1382 verifyVectorElementMatch(SelTy, CondTy, MI);
1383 break;
1384 }
1385 case TargetOpcode::G_MERGE_VALUES: {
1386 // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1387 // e.g. s2N = MERGE sN, sN
1388 // Merging multiple scalars into a vector is not allowed, should use
1389 // G_BUILD_VECTOR for that.
1390 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1391 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1392 if (DstTy.isVector() || SrcTy.isVector())
1393 report("G_MERGE_VALUES cannot operate on vectors", MI);
1394
1395 const unsigned NumOps = MI->getNumOperands();
1396 if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1397 report("G_MERGE_VALUES result size is inconsistent", MI);
1398
1399 for (unsigned I = 2; I != NumOps; ++I) {
1400 if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1401 report("G_MERGE_VALUES source types do not match", MI);
1402 }
1403
1404 break;
1405 }
1406 case TargetOpcode::G_UNMERGE_VALUES: {
1407 unsigned NumDsts = MI->getNumOperands() - 1;
1408 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1409 for (unsigned i = 1; i < NumDsts; ++i) {
1410 if (MRI->getType(MI->getOperand(i).getReg()) != DstTy) {
1411 report("G_UNMERGE_VALUES destination types do not match", MI);
1412 break;
1413 }
1414 }
1415
1416 LLT SrcTy = MRI->getType(MI->getOperand(NumDsts).getReg());
1417 if (DstTy.isVector()) {
1418 // This case is the converse of G_CONCAT_VECTORS.
1419 if (!SrcTy.isVector() || SrcTy.getScalarType() != DstTy.getScalarType() ||
1420 SrcTy.isScalableVector() != DstTy.isScalableVector() ||
1421 SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits())
1422 report("G_UNMERGE_VALUES source operand does not match vector "
1423 "destination operands",
1424 MI);
1425 } else if (SrcTy.isVector()) {
1426 // This case is the converse of G_BUILD_VECTOR, but relaxed to allow
1427 // mismatched types as long as the total size matches:
1428 // %0:_(s64), %1:_(s64) = G_UNMERGE_VALUES %2:_(<4 x s32>)
1429 if (SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits())
1430 report("G_UNMERGE_VALUES vector source operand does not match scalar "
1431 "destination operands",
1432 MI);
1433 } else {
1434 // This case is the converse of G_MERGE_VALUES.
1435 if (SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits()) {
1436 report("G_UNMERGE_VALUES scalar source operand does not match scalar "
1437 "destination operands",
1438 MI);
1439 }
1440 }
1441 break;
1442 }
1443 case TargetOpcode::G_BUILD_VECTOR: {
1444 // Source types must be scalars, dest type a vector. Total size of scalars
1445 // must match the dest vector size.
1446 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1447 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1448 if (!DstTy.isVector() || SrcEltTy.isVector()) {
1449 report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1450 break;
1451 }
1452
1453 if (DstTy.getElementType() != SrcEltTy)
1454 report("G_BUILD_VECTOR result element type must match source type", MI);
1455
1456 if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1457 report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1458
1459 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1460 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1461 report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1462
1463 break;
1464 }
1465 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1466 // Source types must be scalars, dest type a vector. Scalar types must be
1467 // larger than the dest vector elt type, as this is a truncating operation.
1468 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1469 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1470 if (!DstTy.isVector() || SrcEltTy.isVector())
1471 report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1472 MI);
1473 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1474 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1475 report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1476 MI);
1477 if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1478 report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1479 "dest elt type",
1480 MI);
1481 break;
1482 }
1483 case TargetOpcode::G_CONCAT_VECTORS: {
1484 // Source types should be vectors, and total size should match the dest
1485 // vector size.
1486 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1487 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1488 if (!DstTy.isVector() || !SrcTy.isVector())
1489 report("G_CONCAT_VECTOR requires vector source and destination operands",
1490 MI);
1491
1492 if (MI->getNumOperands() < 3)
1493 report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1494
1495 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1496 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1497 report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1498 if (DstTy.getElementCount() !=
1499 SrcTy.getElementCount() * (MI->getNumOperands() - 1))
1500 report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1501 break;
1502 }
1503 case TargetOpcode::G_ICMP:
1504 case TargetOpcode::G_FCMP: {
1505 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1506 LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1507
1508 if ((DstTy.isVector() != SrcTy.isVector()) ||
1509 (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1510 report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1511
1512 break;
1513 }
1514 case TargetOpcode::G_EXTRACT: {
1515 const MachineOperand &SrcOp = MI->getOperand(1);
1516 if (!SrcOp.isReg()) {
1517 report("extract source must be a register", MI);
1518 break;
1519 }
1520
1521 const MachineOperand &OffsetOp = MI->getOperand(2);
1522 if (!OffsetOp.isImm()) {
1523 report("extract offset must be a constant", MI);
1524 break;
1525 }
1526
1527 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1528 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1529 if (SrcSize == DstSize)
1530 report("extract source must be larger than result", MI);
1531
1532 if (DstSize + OffsetOp.getImm() > SrcSize)
1533 report("extract reads past end of register", MI);
1534 break;
1535 }
1536 case TargetOpcode::G_INSERT: {
1537 const MachineOperand &SrcOp = MI->getOperand(2);
1538 if (!SrcOp.isReg()) {
1539 report("insert source must be a register", MI);
1540 break;
1541 }
1542
1543 const MachineOperand &OffsetOp = MI->getOperand(3);
1544 if (!OffsetOp.isImm()) {
1545 report("insert offset must be a constant", MI);
1546 break;
1547 }
1548
1549 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1550 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1551
1552 if (DstSize <= SrcSize)
1553 report("inserted size must be smaller than total register", MI);
1554
1555 if (SrcSize + OffsetOp.getImm() > DstSize)
1556 report("insert writes past end of register", MI);
1557
1558 break;
1559 }
1560 case TargetOpcode::G_JUMP_TABLE: {
1561 if (!MI->getOperand(1).isJTI())
1562 report("G_JUMP_TABLE source operand must be a jump table index", MI);
1563 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1564 if (!DstTy.isPointer())
1565 report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1566 break;
1567 }
1568 case TargetOpcode::G_BRJT: {
1569 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1570 report("G_BRJT src operand 0 must be a pointer type", MI);
1571
1572 if (!MI->getOperand(1).isJTI())
1573 report("G_BRJT src operand 1 must be a jump table index", MI);
1574
1575 const auto &IdxOp = MI->getOperand(2);
1576 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1577 report("G_BRJT src operand 2 must be a scalar reg type", MI);
1578 break;
1579 }
1580 case TargetOpcode::G_INTRINSIC:
1581 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
1582 case TargetOpcode::G_INTRINSIC_CONVERGENT:
1583 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: {
1584 // TODO: Should verify number of def and use operands, but the current
1585 // interface requires passing in IR types for mangling.
1586 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1587 if (!IntrIDOp.isIntrinsicID()) {
1588 report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1589 break;
1590 }
1591
1592 if (!verifyGIntrinsicSideEffects(MI))
1593 break;
1594 if (!verifyGIntrinsicConvergence(MI))
1595 break;
1596
1597 break;
1598 }
1599 case TargetOpcode::G_SEXT_INREG: {
1600 if (!MI->getOperand(2).isImm()) {
1601 report("G_SEXT_INREG expects an immediate operand #2", MI);
1602 break;
1603 }
1604
1605 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1606 int64_t Imm = MI->getOperand(2).getImm();
1607 if (Imm <= 0)
1608 report("G_SEXT_INREG size must be >= 1", MI);
1609 if (Imm >= SrcTy.getScalarSizeInBits())
1610 report("G_SEXT_INREG size must be less than source bit width", MI);
1611 break;
1612 }
1613 case TargetOpcode::G_BSWAP: {
1614 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1615 if (DstTy.getScalarSizeInBits() % 16 != 0)
1616 report("G_BSWAP size must be a multiple of 16 bits", MI);
1617 break;
1618 }
1619 case TargetOpcode::G_VSCALE: {
1620 if (!MI->getOperand(1).isCImm()) {
1621 report("G_VSCALE operand must be cimm", MI);
1622 break;
1623 }
1624 if (MI->getOperand(1).getCImm()->isZero()) {
1625 report("G_VSCALE immediate cannot be zero", MI);
1626 break;
1627 }
1628 break;
1629 }
1630 case TargetOpcode::G_INSERT_SUBVECTOR: {
1631 const MachineOperand &Src0Op = MI->getOperand(1);
1632 if (!Src0Op.isReg()) {
1633 report("G_INSERT_SUBVECTOR first source must be a register", MI);
1634 break;
1635 }
1636
1637 const MachineOperand &Src1Op = MI->getOperand(2);
1638 if (!Src1Op.isReg()) {
1639 report("G_INSERT_SUBVECTOR second source must be a register", MI);
1640 break;
1641 }
1642
1643 const MachineOperand &IndexOp = MI->getOperand(3);
1644 if (!IndexOp.isImm()) {
1645 report("G_INSERT_SUBVECTOR index must be an immediate", MI);
1646 break;
1647 }
1648
1649 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1650 LLT Src0Ty = MRI->getType(Src0Op.getReg());
1651 LLT Src1Ty = MRI->getType(Src1Op.getReg());
1652
1653 if (!DstTy.isVector()) {
1654 report("Destination type must be a vector", MI);
1655 break;
1656 }
1657
1658 if (!Src0Ty.isVector()) {
1659 report("First source must be a vector", MI);
1660 break;
1661 }
1662
1663 if (!Src1Ty.isVector()) {
1664 report("Second source must be a vector", MI);
1665 break;
1666 }
1667
1668 if (DstTy != Src0Ty) {
1669 report("Destination type must match the first source vector type", MI);
1670 break;
1671 }
1672
1673 if (Src0Ty.getElementType() != Src1Ty.getElementType()) {
1674 report("Element type of source vectors must be the same", MI);
1675 break;
1676 }
1677
1678 if (IndexOp.getImm() != 0 &&
1679 Src1Ty.getElementCount().getKnownMinValue() % IndexOp.getImm() != 0) {
1680 report("Index must be a multiple of the second source vector's "
1681 "minimum vector length",
1682 MI);
1683 break;
1684 }
1685 break;
1686 }
1687 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
1688 const MachineOperand &SrcOp = MI->getOperand(1);
1689 if (!SrcOp.isReg()) {
1690 report("G_EXTRACT_SUBVECTOR first source must be a register", MI);
1691 break;
1692 }
1693
1694 const MachineOperand &IndexOp = MI->getOperand(2);
1695 if (!IndexOp.isImm()) {
1696 report("G_EXTRACT_SUBVECTOR index must be an immediate", MI);
1697 break;
1698 }
1699
1700 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1701 LLT SrcTy = MRI->getType(SrcOp.getReg());
1702
1703 if (!DstTy.isVector()) {
1704 report("Destination type must be a vector", MI);
1705 break;
1706 }
1707
1708 if (!SrcTy.isVector()) {
1709 report("First source must be a vector", MI);
1710 break;
1711 }
1712
1713 if (DstTy.getElementType() != SrcTy.getElementType()) {
1714 report("Element type of vectors must be the same", MI);
1715 break;
1716 }
1717
1718 if (IndexOp.getImm() != 0 &&
1719 SrcTy.getElementCount().getKnownMinValue() % IndexOp.getImm() != 0) {
1720 report("Index must be a multiple of the source vector's minimum vector "
1721 "length",
1722 MI);
1723 break;
1724 }
1725
1726 break;
1727 }
1728 case TargetOpcode::G_SHUFFLE_VECTOR: {
1729 const MachineOperand &MaskOp = MI->getOperand(3);
1730 if (!MaskOp.isShuffleMask()) {
1731 report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1732 break;
1733 }
1734
1735 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1736 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1737 LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1738
1739 if (Src0Ty != Src1Ty)
1740 report("Source operands must be the same type", MI);
1741
1742 if (Src0Ty.getScalarType() != DstTy.getScalarType())
1743 report("G_SHUFFLE_VECTOR cannot change element type", MI);
1744
1745 // Don't check that all operands are vector because scalars are used in
1746 // place of 1 element vectors.
1747 int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1748 int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1749
1750 ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
1751
1752 if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1753 report("Wrong result type for shufflemask", MI);
1754
1755 for (int Idx : MaskIdxes) {
1756 if (Idx < 0)
1757 continue;
1758
1759 if (Idx >= 2 * SrcNumElts)
1760 report("Out of bounds shuffle index", MI);
1761 }
1762
1763 break;
1764 }
1765
1766 case TargetOpcode::G_SPLAT_VECTOR: {
1767 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1768 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1769
1770 if (!DstTy.isScalableVector())
1771 report("Destination type must be a scalable vector", MI);
1772
1773 if (!SrcTy.isScalar())
1774 report("Source type must be a scalar", MI);
1775
1776 if (DstTy.getScalarType() != SrcTy)
1777 report("Element type of the destination must be the same type as the "
1778 "source type",
1779 MI);
1780
1781 break;
1782 }
1783 case TargetOpcode::G_DYN_STACKALLOC: {
1784 const MachineOperand &DstOp = MI->getOperand(0);
1785 const MachineOperand &AllocOp = MI->getOperand(1);
1786 const MachineOperand &AlignOp = MI->getOperand(2);
1787
1788 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1789 report("dst operand 0 must be a pointer type", MI);
1790 break;
1791 }
1792
1793 if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1794 report("src operand 1 must be a scalar reg type", MI);
1795 break;
1796 }
1797
1798 if (!AlignOp.isImm()) {
1799 report("src operand 2 must be an immediate type", MI);
1800 break;
1801 }
1802 break;
1803 }
1804 case TargetOpcode::G_MEMCPY_INLINE:
1805 case TargetOpcode::G_MEMCPY:
1806 case TargetOpcode::G_MEMMOVE: {
1807 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1808 if (MMOs.size() != 2) {
1809 report("memcpy/memmove must have 2 memory operands", MI);
1810 break;
1811 }
1812
1813 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1814 (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1815 report("wrong memory operand types", MI);
1816 break;
1817 }
1818
1819 if (MMOs[0]->getSize() != MMOs[1]->getSize())
1820 report("inconsistent memory operand sizes", MI);
1821
1822 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1823 LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1824
1825 if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
1826 report("memory instruction operand must be a pointer", MI);
1827 break;
1828 }
1829
1830 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1831 report("inconsistent store address space", MI);
1832 if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1833 report("inconsistent load address space", MI);
1834
1835 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1836 if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1837 report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
1838
1839 break;
1840 }
1841 case TargetOpcode::G_BZERO:
1842 case TargetOpcode::G_MEMSET: {
1843 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1844 std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
1845 if (MMOs.size() != 1) {
1846 report(Twine(Name, " must have 1 memory operand"), MI);
1847 break;
1848 }
1849
1850 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1851 report(Twine(Name, " memory operand must be a store"), MI);
1852 break;
1853 }
1854
1855 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1856 if (!DstPtrTy.isPointer()) {
1857 report(Twine(Name, " operand must be a pointer"), MI);
1858 break;
1859 }
1860
1861 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1862 report("inconsistent " + Twine(Name, " address space"), MI);
1863
1864 if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1865 (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1866 report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
1867
1868 break;
1869 }
1870 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1871 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1872 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1873 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1874 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1875 if (!DstTy.isScalar())
1876 report("Vector reduction requires a scalar destination type", MI);
1877 if (!Src1Ty.isScalar())
1878 report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
1879 if (!Src2Ty.isVector())
1880 report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
1881 break;
1882 }
1883 case TargetOpcode::G_VECREDUCE_FADD:
1884 case TargetOpcode::G_VECREDUCE_FMUL:
1885 case TargetOpcode::G_VECREDUCE_FMAX:
1886 case TargetOpcode::G_VECREDUCE_FMIN:
1887 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1888 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1889 case TargetOpcode::G_VECREDUCE_ADD:
1890 case TargetOpcode::G_VECREDUCE_MUL:
1891 case TargetOpcode::G_VECREDUCE_AND:
1892 case TargetOpcode::G_VECREDUCE_OR:
1893 case TargetOpcode::G_VECREDUCE_XOR:
1894 case TargetOpcode::G_VECREDUCE_SMAX:
1895 case TargetOpcode::G_VECREDUCE_SMIN:
1896 case TargetOpcode::G_VECREDUCE_UMAX:
1897 case TargetOpcode::G_VECREDUCE_UMIN: {
1898 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1899 if (!DstTy.isScalar())
1900 report("Vector reduction requires a scalar destination type", MI);
1901 break;
1902 }
1903
1904 case TargetOpcode::G_SBFX:
1905 case TargetOpcode::G_UBFX: {
1906 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1907 if (DstTy.isVector()) {
1908 report("Bitfield extraction is not supported on vectors", MI);
1909 break;
1910 }
1911 break;
1912 }
1913 case TargetOpcode::G_SHL:
1914 case TargetOpcode::G_LSHR:
1915 case TargetOpcode::G_ASHR:
1916 case TargetOpcode::G_ROTR:
1917 case TargetOpcode::G_ROTL: {
1918 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1919 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1920 if (Src1Ty.isVector() != Src2Ty.isVector()) {
1921 report("Shifts and rotates require operands to be either all scalars or "
1922 "all vectors",
1923 MI);
1924 break;
1925 }
1926 break;
1927 }
1928 case TargetOpcode::G_LLROUND:
1929 case TargetOpcode::G_LROUND: {
1930 verifyAllRegOpsScalar(*MI, *MRI);
1931 break;
1932 }
1933 case TargetOpcode::G_IS_FPCLASS: {
1934 LLT DestTy = MRI->getType(MI->getOperand(0).getReg());
1935 LLT DestEltTy = DestTy.getScalarType();
1936 if (!DestEltTy.isScalar()) {
1937 report("Destination must be a scalar or vector of scalars", MI);
1938 break;
1939 }
1940 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1941 LLT SrcEltTy = SrcTy.getScalarType();
1942 if (!SrcEltTy.isScalar()) {
1943 report("Source must be a scalar or vector of scalars", MI);
1944 break;
1945 }
1946 if (!verifyVectorElementMatch(DestTy, SrcTy, MI))
1947 break;
1948 const MachineOperand &TestMO = MI->getOperand(2);
1949 if (!TestMO.isImm()) {
1950 report("floating-point class set (operand 2) must be an immediate", MI);
1951 break;
1952 }
1953 int64_t Test = TestMO.getImm();
1954 if (Test < 0 || Test > fcAllFlags) {
1955 report("Incorrect floating-point class set (operand 2)", MI);
1956 break;
1957 }
1958 break;
1959 }
1960 case TargetOpcode::G_PREFETCH: {
1961 const MachineOperand &AddrOp = MI->getOperand(0);
1962 if (!AddrOp.isReg() || !MRI->getType(AddrOp.getReg()).isPointer()) {
1963 report("addr operand must be a pointer", &AddrOp, 0);
1964 break;
1965 }
1966 const MachineOperand &RWOp = MI->getOperand(1);
1967 if (!RWOp.isImm() || (uint64_t)RWOp.getImm() >= 2) {
1968 report("rw operand must be an immediate 0-1", &RWOp, 1);
1969 break;
1970 }
1971 const MachineOperand &LocalityOp = MI->getOperand(2);
1972 if (!LocalityOp.isImm() || (uint64_t)LocalityOp.getImm() >= 4) {
1973 report("locality operand must be an immediate 0-3", &LocalityOp, 2);
1974 break;
1975 }
1976 const MachineOperand &CacheTypeOp = MI->getOperand(3);
1977 if (!CacheTypeOp.isImm() || (uint64_t)CacheTypeOp.getImm() >= 2) {
1978 report("cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
1979 break;
1980 }
1981 break;
1982 }
1983 case TargetOpcode::G_ASSERT_ALIGN: {
1984 if (MI->getOperand(2).getImm() < 1)
1985 report("alignment immediate must be >= 1", MI);
1986 break;
1987 }
1988 case TargetOpcode::G_CONSTANT_POOL: {
1989 if (!MI->getOperand(1).isCPI())
1990 report("Src operand 1 must be a constant pool index", MI);
1991 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1992 report("Dst operand 0 must be a pointer", MI);
1993 break;
1994 }
1995 default:
1996 break;
1997 }
1998}
1999
2000void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
2001 const MCInstrDesc &MCID = MI->getDesc();
2002 if (MI->getNumOperands() < MCID.getNumOperands()) {
2003 report("Too few operands", MI);
2004 errs() << MCID.getNumOperands() << " operands expected, but "
2005 << MI->getNumOperands() << " given.\n";
2006 }
2007
2008 if (MI->getFlag(MachineInstr::NoConvergent) && !MCID.isConvergent())
2009 report("NoConvergent flag expected only on convergent instructions.", MI);
2010
2011 if (MI->isPHI()) {
2012 if (MF->getProperties().hasProperty(
2014 report("Found PHI instruction with NoPHIs property set", MI);
2015
2016 if (FirstNonPHI)
2017 report("Found PHI instruction after non-PHI", MI);
2018 } else if (FirstNonPHI == nullptr)
2019 FirstNonPHI = MI;
2020
2021 // Check the tied operands.
2022 if (MI->isInlineAsm())
2023 verifyInlineAsm(MI);
2024
2025 // Check that unspillable terminators define a reg and have at most one use.
2026 if (TII->isUnspillableTerminator(MI)) {
2027 if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
2028 report("Unspillable Terminator does not define a reg", MI);
2029 Register Def = MI->getOperand(0).getReg();
2030 if (Def.isVirtual() &&
2031 !MF->getProperties().hasProperty(
2033 std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
2034 report("Unspillable Terminator expected to have at most one use!", MI);
2035 }
2036
2037 // A fully-formed DBG_VALUE must have a location. Ignore partially formed
2038 // DBG_VALUEs: these are convenient to use in tests, but should never get
2039 // generated.
2040 if (MI->isDebugValue() && MI->getNumOperands() == 4)
2041 if (!MI->getDebugLoc())
2042 report("Missing DebugLoc for debug instruction", MI);
2043
2044 // Meta instructions should never be the subject of debug value tracking,
2045 // they don't create a value in the output program at all.
2046 if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
2047 report("Metadata instruction should not have a value tracking number", MI);
2048
2049 // Check the MachineMemOperands for basic consistency.
2050 for (MachineMemOperand *Op : MI->memoperands()) {
2051 if (Op->isLoad() && !MI->mayLoad())
2052 report("Missing mayLoad flag", MI);
2053 if (Op->isStore() && !MI->mayStore())
2054 report("Missing mayStore flag", MI);
2055 }
2056
2057 // Debug values must not have a slot index.
2058 // Other instructions must have one, unless they are inside a bundle.
2059 if (LiveInts) {
2060 bool mapped = !LiveInts->isNotInMIMap(*MI);
2061 if (MI->isDebugOrPseudoInstr()) {
2062 if (mapped)
2063 report("Debug instruction has a slot index", MI);
2064 } else if (MI->isInsideBundle()) {
2065 if (mapped)
2066 report("Instruction inside bundle has a slot index", MI);
2067 } else {
2068 if (!mapped)
2069 report("Missing slot index", MI);
2070 }
2071 }
2072
2073 unsigned Opc = MCID.getOpcode();
2075 verifyPreISelGenericInstruction(MI);
2076 return;
2077 }
2078
2080 if (!TII->verifyInstruction(*MI, ErrorInfo))
2081 report(ErrorInfo.data(), MI);
2082
2083 // Verify properties of various specific instruction types
2084 switch (MI->getOpcode()) {
2085 case TargetOpcode::COPY: {
2086 const MachineOperand &DstOp = MI->getOperand(0);
2087 const MachineOperand &SrcOp = MI->getOperand(1);
2088 const Register SrcReg = SrcOp.getReg();
2089 const Register DstReg = DstOp.getReg();
2090
2091 LLT DstTy = MRI->getType(DstReg);
2092 LLT SrcTy = MRI->getType(SrcReg);
2093 if (SrcTy.isValid() && DstTy.isValid()) {
2094 // If both types are valid, check that the types are the same.
2095 if (SrcTy != DstTy) {
2096 report("Copy Instruction is illegal with mismatching types", MI);
2097 errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
2098 }
2099
2100 break;
2101 }
2102
2103 if (!SrcTy.isValid() && !DstTy.isValid())
2104 break;
2105
2106 // If we have only one valid type, this is likely a copy between a virtual
2107 // and physical register.
2108 TypeSize SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
2109 TypeSize DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
2110 if (SrcReg.isPhysical() && DstTy.isValid()) {
2111 const TargetRegisterClass *SrcRC =
2112 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
2113 if (SrcRC)
2114 SrcSize = TRI->getRegSizeInBits(*SrcRC);
2115 }
2116
2117 if (DstReg.isPhysical() && SrcTy.isValid()) {
2118 const TargetRegisterClass *DstRC =
2119 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
2120 if (DstRC)
2121 DstSize = TRI->getRegSizeInBits(*DstRC);
2122 }
2123
2124 // The next two checks allow COPY between physical and virtual registers,
2125 // when the virtual register has a scalable size and the physical register
2126 // has a fixed size. These checks allow COPY between *potentialy* mismatched
2127 // sizes. However, once RegisterBankSelection occurs, MachineVerifier should
2128 // be able to resolve a fixed size for the scalable vector, and at that
2129 // point this function will know for sure whether the sizes are mismatched
2130 // and correctly report a size mismatch.
2131 if (SrcReg.isPhysical() && DstReg.isVirtual() && DstSize.isScalable() &&
2132 !SrcSize.isScalable())
2133 break;
2134 if (SrcReg.isVirtual() && DstReg.isPhysical() && SrcSize.isScalable() &&
2135 !DstSize.isScalable())
2136 break;
2137
2138 if (SrcSize.isNonZero() && DstSize.isNonZero() && SrcSize != DstSize) {
2139 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
2140 report("Copy Instruction is illegal with mismatching sizes", MI);
2141 errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
2142 << "\n";
2143 }
2144 }
2145 break;
2146 }
2147 case TargetOpcode::STATEPOINT: {
2148 StatepointOpers SO(MI);
2149 if (!MI->getOperand(SO.getIDPos()).isImm() ||
2150 !MI->getOperand(SO.getNBytesPos()).isImm() ||
2151 !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
2152 report("meta operands to STATEPOINT not constant!", MI);
2153 break;
2154 }
2155
2156 auto VerifyStackMapConstant = [&](unsigned Offset) {
2157 if (Offset >= MI->getNumOperands()) {
2158 report("stack map constant to STATEPOINT is out of range!", MI);
2159 return;
2160 }
2161 if (!MI->getOperand(Offset - 1).isImm() ||
2162 MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
2163 !MI->getOperand(Offset).isImm())
2164 report("stack map constant to STATEPOINT not well formed!", MI);
2165 };
2166 VerifyStackMapConstant(SO.getCCIdx());
2167 VerifyStackMapConstant(SO.getFlagsIdx());
2168 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
2169 VerifyStackMapConstant(SO.getNumGCPtrIdx());
2170 VerifyStackMapConstant(SO.getNumAllocaIdx());
2171 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
2172
2173 // Verify that all explicit statepoint defs are tied to gc operands as
2174 // they are expected to be a relocation of gc operands.
2175 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
2176 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2177 for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
2178 unsigned UseOpIdx;
2179 if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
2180 report("STATEPOINT defs expected to be tied", MI);
2181 break;
2182 }
2183 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
2184 report("STATEPOINT def tied to non-gc operand", MI);
2185 break;
2186 }
2187 }
2188
2189 // TODO: verify we have properly encoded deopt arguments
2190 } break;
2191 case TargetOpcode::INSERT_SUBREG: {
2192 unsigned InsertedSize;
2193 if (unsigned SubIdx = MI->getOperand(2).getSubReg())
2194 InsertedSize = TRI->getSubRegIdxSize(SubIdx);
2195 else
2196 InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
2197 unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
2198 if (SubRegSize < InsertedSize) {
2199 report("INSERT_SUBREG expected inserted value to have equal or lesser "
2200 "size than the subreg it was inserted into", MI);
2201 break;
2202 }
2203 } break;
2204 case TargetOpcode::REG_SEQUENCE: {
2205 unsigned NumOps = MI->getNumOperands();
2206 if (!(NumOps & 1)) {
2207 report("Invalid number of operands for REG_SEQUENCE", MI);
2208 break;
2209 }
2210
2211 for (unsigned I = 1; I != NumOps; I += 2) {
2212 const MachineOperand &RegOp = MI->getOperand(I);
2213 const MachineOperand &SubRegOp = MI->getOperand(I + 1);
2214
2215 if (!RegOp.isReg())
2216 report("Invalid register operand for REG_SEQUENCE", &RegOp, I);
2217
2218 if (!SubRegOp.isImm() || SubRegOp.getImm() == 0 ||
2219 SubRegOp.getImm() >= TRI->getNumSubRegIndices()) {
2220 report("Invalid subregister index operand for REG_SEQUENCE",
2221 &SubRegOp, I + 1);
2222 }
2223 }
2224
2225 Register DstReg = MI->getOperand(0).getReg();
2226 if (DstReg.isPhysical())
2227 report("REG_SEQUENCE does not support physical register results", MI);
2228
2229 if (MI->getOperand(0).getSubReg())
2230 report("Invalid subreg result for REG_SEQUENCE", MI);
2231
2232 break;
2233 }
2234 }
2235}
2236
2237void
2238MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
2239 const MachineInstr *MI = MO->getParent();
2240 const MCInstrDesc &MCID = MI->getDesc();
2241 unsigned NumDefs = MCID.getNumDefs();
2242 if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
2243 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
2244
2245 // The first MCID.NumDefs operands must be explicit register defines
2246 if (MONum < NumDefs) {
2247 const MCOperandInfo &MCOI = MCID.operands()[MONum];
2248 if (!MO->isReg())
2249 report("Explicit definition must be a register", MO, MONum);
2250 else if (!MO->isDef() && !MCOI.isOptionalDef())
2251 report("Explicit definition marked as use", MO, MONum);
2252 else if (MO->isImplicit())
2253 report("Explicit definition marked as implicit", MO, MONum);
2254 } else if (MONum < MCID.getNumOperands()) {
2255 const MCOperandInfo &MCOI = MCID.operands()[MONum];
2256 // Don't check if it's the last operand in a variadic instruction. See,
2257 // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
2258 bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
2259 if (!IsOptional) {
2260 if (MO->isReg()) {
2261 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
2262 report("Explicit operand marked as def", MO, MONum);
2263 if (MO->isImplicit())
2264 report("Explicit operand marked as implicit", MO, MONum);
2265 }
2266
2267 // Check that an instruction has register operands only as expected.
2268 if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
2269 !MO->isReg() && !MO->isFI())
2270 report("Expected a register operand.", MO, MONum);
2271 if (MO->isReg()) {
2274 !TII->isPCRelRegisterOperandLegal(*MO)))
2275 report("Expected a non-register operand.", MO, MONum);
2276 }
2277 }
2278
2279 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
2280 if (TiedTo != -1) {
2281 if (!MO->isReg())
2282 report("Tied use must be a register", MO, MONum);
2283 else if (!MO->isTied())
2284 report("Operand should be tied", MO, MONum);
2285 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
2286 report("Tied def doesn't match MCInstrDesc", MO, MONum);
2287 else if (MO->getReg().isPhysical()) {
2288 const MachineOperand &MOTied = MI->getOperand(TiedTo);
2289 if (!MOTied.isReg())
2290 report("Tied counterpart must be a register", &MOTied, TiedTo);
2291 else if (MOTied.getReg().isPhysical() &&
2292 MO->getReg() != MOTied.getReg())
2293 report("Tied physical registers must match.", &MOTied, TiedTo);
2294 }
2295 } else if (MO->isReg() && MO->isTied())
2296 report("Explicit operand should not be tied", MO, MONum);
2297 } else if (!MI->isVariadic()) {
2298 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
2299 if (!MO->isValidExcessOperand())
2300 report("Extra explicit operand on non-variadic instruction", MO, MONum);
2301 }
2302
2303 switch (MO->getType()) {
2305 // Verify debug flag on debug instructions. Check this first because reg0
2306 // indicates an undefined debug value.
2307 if (MI->isDebugInstr() && MO->isUse()) {
2308 if (!MO->isDebug())
2309 report("Register operand must be marked debug", MO, MONum);
2310 } else if (MO->isDebug()) {
2311 report("Register operand must not be marked debug", MO, MONum);
2312 }
2313
2314 const Register Reg = MO->getReg();
2315 if (!Reg)
2316 return;
2317 if (MRI->tracksLiveness() && !MI->isDebugInstr())
2318 checkLiveness(MO, MONum);
2319
2320 if (MO->isDef() && MO->isUndef() && !MO->getSubReg() &&
2321 MO->getReg().isVirtual()) // TODO: Apply to physregs too
2322 report("Undef virtual register def operands require a subregister", MO, MONum);
2323
2324 // Verify the consistency of tied operands.
2325 if (MO->isTied()) {
2326 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
2327 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
2328 if (!OtherMO.isReg())
2329 report("Must be tied to a register", MO, MONum);
2330 if (!OtherMO.isTied())
2331 report("Missing tie flags on tied operand", MO, MONum);
2332 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
2333 report("Inconsistent tie links", MO, MONum);
2334 if (MONum < MCID.getNumDefs()) {
2335 if (OtherIdx < MCID.getNumOperands()) {
2336 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
2337 report("Explicit def tied to explicit use without tie constraint",
2338 MO, MONum);
2339 } else {
2340 if (!OtherMO.isImplicit())
2341 report("Explicit def should be tied to implicit use", MO, MONum);
2342 }
2343 }
2344 }
2345
2346 // Verify two-address constraints after the twoaddressinstruction pass.
2347 // Both twoaddressinstruction pass and phi-node-elimination pass call
2348 // MRI->leaveSSA() to set MF as not IsSSA, we should do the verification
2349 // after twoaddressinstruction pass not after phi-node-elimination pass. So
2350 // we shouldn't use the IsSSA as the condition, we should based on
2351 // TiedOpsRewritten property to verify two-address constraints, this
2352 // property will be set in twoaddressinstruction pass.
2353 unsigned DefIdx;
2354 if (MF->getProperties().hasProperty(
2356 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2357 Reg != MI->getOperand(DefIdx).getReg())
2358 report("Two-address instruction operands must be identical", MO, MONum);
2359
2360 // Check register classes.
2361 unsigned SubIdx = MO->getSubReg();
2362
2363 if (Reg.isPhysical()) {
2364 if (SubIdx) {
2365 report("Illegal subregister index for physical register", MO, MONum);
2366 return;
2367 }
2368 if (MONum < MCID.getNumOperands()) {
2369 if (const TargetRegisterClass *DRC =
2370 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2371 if (!DRC->contains(Reg)) {
2372 report("Illegal physical register for instruction", MO, MONum);
2373 errs() << printReg(Reg, TRI) << " is not a "
2374 << TRI->getRegClassName(DRC) << " register.\n";
2375 }
2376 }
2377 }
2378 if (MO->isRenamable()) {
2379 if (MRI->isReserved(Reg)) {
2380 report("isRenamable set on reserved register", MO, MONum);
2381 return;
2382 }
2383 }
2384 } else {
2385 // Virtual register.
2386 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
2387 if (!RC) {
2388 // This is a generic virtual register.
2389
2390 // Do not allow undef uses for generic virtual registers. This ensures
2391 // getVRegDef can never fail and return null on a generic register.
2392 //
2393 // FIXME: This restriction should probably be broadened to all SSA
2394 // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
2395 // run on the SSA function just before phi elimination.
2396 if (MO->isUndef())
2397 report("Generic virtual register use cannot be undef", MO, MONum);
2398
2399 // Debug value instruction is permitted to use undefined vregs.
2400 // This is a performance measure to skip the overhead of immediately
2401 // pruning unused debug operands. The final undef substitution occurs
2402 // when debug values are allocated in LDVImpl::handleDebugValue, so
2403 // these verifications always apply after this pass.
2404 if (isFunctionTracksDebugUserValues || !MO->isUse() ||
2405 !MI->isDebugValue() || !MRI->def_empty(Reg)) {
2406 // If we're post-Select, we can't have gvregs anymore.
2407 if (isFunctionSelected) {
2408 report("Generic virtual register invalid in a Selected function",
2409 MO, MONum);
2410 return;
2411 }
2412
2413 // The gvreg must have a type and it must not have a SubIdx.
2414 LLT Ty = MRI->getType(Reg);
2415 if (!Ty.isValid()) {
2416 report("Generic virtual register must have a valid type", MO,
2417 MONum);
2418 return;
2419 }
2420
2421 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
2422 const RegisterBankInfo *RBI = MF->getSubtarget().getRegBankInfo();
2423
2424 // If we're post-RegBankSelect, the gvreg must have a bank.
2425 if (!RegBank && isFunctionRegBankSelected) {
2426 report("Generic virtual register must have a bank in a "
2427 "RegBankSelected function",
2428 MO, MONum);
2429 return;
2430 }
2431
2432 // Make sure the register fits into its register bank if any.
2433 if (RegBank && Ty.isValid() && !Ty.isScalableVector() &&
2434 RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) {
2435 report("Register bank is too small for virtual register", MO,
2436 MONum);
2437 errs() << "Register bank " << RegBank->getName() << " too small("
2438 << RBI->getMaximumSize(RegBank->getID()) << ") to fit "
2439 << Ty.getSizeInBits() << "-bits\n";
2440 return;
2441 }
2442 }
2443
2444 if (SubIdx) {
2445 report("Generic virtual register does not allow subregister index", MO,
2446 MONum);
2447 return;
2448 }
2449
2450 // If this is a target specific instruction and this operand
2451 // has register class constraint, the virtual register must
2452 // comply to it.
2453 if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
2454 MONum < MCID.getNumOperands() &&
2455 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2456 report("Virtual register does not match instruction constraint", MO,
2457 MONum);
2458 errs() << "Expect register class "
2459 << TRI->getRegClassName(
2460 TII->getRegClass(MCID, MONum, TRI, *MF))
2461 << " but got nothing\n";
2462 return;
2463 }
2464
2465 break;
2466 }
2467 if (SubIdx) {
2468 const TargetRegisterClass *SRC =
2469 TRI->getSubClassWithSubReg(RC, SubIdx);
2470 if (!SRC) {
2471 report("Invalid subregister index for virtual register", MO, MONum);
2472 errs() << "Register class " << TRI->getRegClassName(RC)
2473 << " does not support subreg index " << SubIdx << "\n";
2474 return;
2475 }
2476 if (RC != SRC) {
2477 report("Invalid register class for subregister index", MO, MONum);
2478 errs() << "Register class " << TRI->getRegClassName(RC)
2479 << " does not fully support subreg index " << SubIdx << "\n";
2480 return;
2481 }
2482 }
2483 if (MONum < MCID.getNumOperands()) {
2484 if (const TargetRegisterClass *DRC =
2485 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2486 if (SubIdx) {
2487 const TargetRegisterClass *SuperRC =
2488 TRI->getLargestLegalSuperClass(RC, *MF);
2489 if (!SuperRC) {
2490 report("No largest legal super class exists.", MO, MONum);
2491 return;
2492 }
2493 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2494 if (!DRC) {
2495 report("No matching super-reg register class.", MO, MONum);
2496 return;
2497 }
2498 }
2499 if (!RC->hasSuperClassEq(DRC)) {
2500 report("Illegal virtual register for instruction", MO, MONum);
2501 errs() << "Expected a " << TRI->getRegClassName(DRC)
2502 << " register, but got a " << TRI->getRegClassName(RC)
2503 << " register\n";
2504 }
2505 }
2506 }
2507 }
2508 break;
2509 }
2510
2512 regMasks.push_back(MO->getRegMask());
2513 break;
2514
2516 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2517 report("PHI operand is not in the CFG", MO, MONum);
2518 break;
2519
2521 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2522 LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2523 int FI = MO->getIndex();
2524 LiveInterval &LI = LiveStks->getInterval(FI);
2525 SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2526
2527 bool stores = MI->mayStore();
2528 bool loads = MI->mayLoad();
2529 // For a memory-to-memory move, we need to check if the frame
2530 // index is used for storing or loading, by inspecting the
2531 // memory operands.
2532 if (stores && loads) {
2533 for (auto *MMO : MI->memoperands()) {
2534 const PseudoSourceValue *PSV = MMO->getPseudoValue();
2535 if (PSV == nullptr) continue;
2537 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2538 if (Value == nullptr) continue;
2539 if (Value->getFrameIndex() != FI) continue;
2540
2541 if (MMO->isStore())
2542 loads = false;
2543 else
2544 stores = false;
2545 break;
2546 }
2547 if (loads == stores)
2548 report("Missing fixed stack memoperand.", MI);
2549 }
2550 if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2551 report("Instruction loads from dead spill slot", MO, MONum);
2552 errs() << "Live stack: " << LI << '\n';
2553 }
2554 if (stores && !LI.liveAt(Idx.getRegSlot())) {
2555 report("Instruction stores to dead spill slot", MO, MONum);
2556 errs() << "Live stack: " << LI << '\n';
2557 }
2558 }
2559 break;
2560
2562 if (MO->getCFIIndex() >= MF->getFrameInstructions().size())
2563 report("CFI instruction has invalid index", MO, MONum);
2564 break;
2565
2566 default:
2567 break;
2568 }
2569}
2570
2571void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2572 unsigned MONum, SlotIndex UseIdx,
2573 const LiveRange &LR,
2574 Register VRegOrUnit,
2575 LaneBitmask LaneMask) {
2576 const MachineInstr *MI = MO->getParent();
2577 LiveQueryResult LRQ = LR.Query(UseIdx);
2578 bool HasValue = LRQ.valueIn() || (MI->isPHI() && LRQ.valueOut());
2579 // Check if we have a segment at the use, note however that we only need one
2580 // live subregister range, the others may be dead.
2581 if (!HasValue && LaneMask.none()) {
2582 report("No live segment at use", MO, MONum);
2583 report_context_liverange(LR);
2584 report_context_vreg_regunit(VRegOrUnit);
2585 report_context(UseIdx);
2586 }
2587 if (MO->isKill() && !LRQ.isKill()) {
2588 report("Live range continues after kill flag", MO, MONum);
2589 report_context_liverange(LR);
2590 report_context_vreg_regunit(VRegOrUnit);
2591 if (LaneMask.any())
2592 report_context_lanemask(LaneMask);
2593 report_context(UseIdx);
2594 }
2595}
2596
2597void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2598 unsigned MONum, SlotIndex DefIdx,
2599 const LiveRange &LR,
2600 Register VRegOrUnit,
2601 bool SubRangeCheck,
2602 LaneBitmask LaneMask) {
2603 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2604 // The LR can correspond to the whole reg and its def slot is not obliged
2605 // to be the same as the MO' def slot. E.g. when we check here "normal"
2606 // subreg MO but there is other EC subreg MO in the same instruction so the
2607 // whole reg has EC def slot and differs from the currently checked MO' def
2608 // slot. For example:
2609 // %0 [16e,32r:0) 0@16e L..3 [16e,32r:0) 0@16e L..C [16r,32r:0) 0@16r
2610 // Check that there is an early-clobber def of the same superregister
2611 // somewhere is performed in visitMachineFunctionAfter()
2612 if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) ||
2613 !SlotIndex::isSameInstr(VNI->def, DefIdx) ||
2614 (VNI->def != DefIdx &&
2615 (!VNI->def.isEarlyClobber() || !DefIdx.isRegister()))) {
2616 report("Inconsistent valno->def", MO, MONum);
2617 report_context_liverange(LR);
2618 report_context_vreg_regunit(VRegOrUnit);
2619 if (LaneMask.any())
2620 report_context_lanemask(LaneMask);
2621 report_context(*VNI);
2622 report_context(DefIdx);
2623 }
2624 } else {
2625 report("No live segment at def", MO, MONum);
2626 report_context_liverange(LR);
2627 report_context_vreg_regunit(VRegOrUnit);
2628 if (LaneMask.any())
2629 report_context_lanemask(LaneMask);
2630 report_context(DefIdx);
2631 }
2632 // Check that, if the dead def flag is present, LiveInts agree.
2633 if (MO->isDead()) {
2634 LiveQueryResult LRQ = LR.Query(DefIdx);
2635 if (!LRQ.isDeadDef()) {
2636 assert(VRegOrUnit.isVirtual() && "Expecting a virtual register.");
2637 // A dead subreg def only tells us that the specific subreg is dead. There
2638 // could be other non-dead defs of other subregs, or we could have other
2639 // parts of the register being live through the instruction. So unless we
2640 // are checking liveness for a subrange it is ok for the live range to
2641 // continue, given that we have a dead def of a subregister.
2642 if (SubRangeCheck || MO->getSubReg() == 0) {
2643 report("Live range continues after dead def flag", MO, MONum);
2644 report_context_liverange(LR);
2645 report_context_vreg_regunit(VRegOrUnit);
2646 if (LaneMask.any())
2647 report_context_lanemask(LaneMask);
2648 }
2649 }
2650 }
2651}
2652
2653void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2654 const MachineInstr *MI = MO->getParent();
2655 const Register Reg = MO->getReg();
2656 const unsigned SubRegIdx = MO->getSubReg();
2657
2658 const LiveInterval *LI = nullptr;
2659 if (LiveInts && Reg.isVirtual()) {
2660 if (LiveInts->hasInterval(Reg)) {
2661 LI = &LiveInts->getInterval(Reg);
2662 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
2663 !LI->hasSubRanges() && MRI->shouldTrackSubRegLiveness(Reg))
2664 report("Live interval for subreg operand has no subranges", MO, MONum);
2665 } else {
2666 report("Virtual register has no live interval", MO, MONum);
2667 }
2668 }
2669
2670 // Both use and def operands can read a register.
2671 if (MO->readsReg()) {
2672 if (MO->isKill())
2673 addRegWithSubRegs(regsKilled, Reg);
2674
2675 // Check that LiveVars knows this kill (unless we are inside a bundle, in
2676 // which case we have already checked that LiveVars knows any kills on the
2677 // bundle header instead).
2678 if (LiveVars && Reg.isVirtual() && MO->isKill() &&
2679 !MI->isBundledWithPred()) {
2680 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2681 if (!is_contained(VI.Kills, MI))
2682 report("Kill missing from LiveVariables", MO, MONum);
2683 }
2684
2685 // Check LiveInts liveness and kill.
2686 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2687 SlotIndex UseIdx;
2688 if (MI->isPHI()) {
2689 // PHI use occurs on the edge, so check for live out here instead.
2690 UseIdx = LiveInts->getMBBEndIdx(
2691 MI->getOperand(MONum + 1).getMBB()).getPrevSlot();
2692 } else {
2693 UseIdx = LiveInts->getInstructionIndex(*MI);
2694 }
2695 // Check the cached regunit intervals.
2696 if (Reg.isPhysical() && !isReserved(Reg)) {
2697 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) {
2698 if (MRI->isReservedRegUnit(Unit))
2699 continue;
2700 if (const LiveRange *LR = LiveInts->getCachedRegUnit(Unit))
2701 checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit);
2702 }
2703 }
2704
2705 if (Reg.isVirtual()) {
2706 // This is a virtual register interval.
2707 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2708
2709 if (LI->hasSubRanges() && !MO->isDef()) {
2710 LaneBitmask MOMask = SubRegIdx != 0
2711 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2712 : MRI->getMaxLaneMaskForVReg(Reg);
2713 LaneBitmask LiveInMask;
2714 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2715 if ((MOMask & SR.LaneMask).none())
2716 continue;
2717 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2718 LiveQueryResult LRQ = SR.Query(UseIdx);
2719 if (LRQ.valueIn() || (MI->isPHI() && LRQ.valueOut()))
2720 LiveInMask |= SR.LaneMask;
2721 }
2722 // At least parts of the register has to be live at the use.
2723 if ((LiveInMask & MOMask).none()) {
2724 report("No live subrange at use", MO, MONum);
2725 report_context(*LI);
2726 report_context(UseIdx);
2727 }
2728 // For PHIs all lanes should be live
2729 if (MI->isPHI() && LiveInMask != MOMask) {
2730 report("Not all lanes of PHI source live at use", MO, MONum);
2731 report_context(*LI);
2732 report_context(UseIdx);
2733 }
2734 }
2735 }
2736 }
2737
2738 // Use of a dead register.
2739 if (!regsLive.count(Reg)) {
2740 if (Reg.isPhysical()) {
2741 // Reserved registers may be used even when 'dead'.
2742 bool Bad = !isReserved(Reg);
2743 // We are fine if just any subregister has a defined value.
2744 if (Bad) {
2745
2746 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2747 if (regsLive.count(SubReg)) {
2748 Bad = false;
2749 break;
2750 }
2751 }
2752 }
2753 // If there is an additional implicit-use of a super register we stop
2754 // here. By definition we are fine if the super register is not
2755 // (completely) dead, if the complete super register is dead we will
2756 // get a report for its operand.
2757 if (Bad) {
2758 for (const MachineOperand &MOP : MI->uses()) {
2759 if (!MOP.isReg() || !MOP.isImplicit())
2760 continue;
2761
2762 if (!MOP.getReg().isPhysical())
2763 continue;
2764
2765 if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2766 Bad = false;
2767 }
2768 }
2769 if (Bad)
2770 report("Using an undefined physical register", MO, MONum);
2771 } else if (MRI->def_empty(Reg)) {
2772 report("Reading virtual register without a def", MO, MONum);
2773 } else {
2774 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2775 // We don't know which virtual registers are live in, so only complain
2776 // if vreg was killed in this MBB. Otherwise keep track of vregs that
2777 // must be live in. PHI instructions are handled separately.
2778 if (MInfo.regsKilled.count(Reg))
2779 report("Using a killed virtual register", MO, MONum);
2780 else if (!MI->isPHI())
2781 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2782 }
2783 }
2784 }
2785
2786 if (MO->isDef()) {
2787 // Register defined.
2788 // TODO: verify that earlyclobber ops are not used.
2789 if (MO->isDead())
2790 addRegWithSubRegs(regsDead, Reg);
2791 else
2792 addRegWithSubRegs(regsDefined, Reg);
2793
2794 // Verify SSA form.
2795 if (MRI->isSSA() && Reg.isVirtual() &&
2796 std::next(MRI->def_begin(Reg)) != MRI->def_end())
2797 report("Multiple virtual register defs in SSA form", MO, MONum);
2798
2799 // Check LiveInts for a live segment, but only for virtual registers.
2800 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2801 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2802 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2803
2804 if (Reg.isVirtual()) {
2805 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2806
2807 if (LI->hasSubRanges()) {
2808 LaneBitmask MOMask = SubRegIdx != 0
2809 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2810 : MRI->getMaxLaneMaskForVReg(Reg);
2811 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2812 if ((SR.LaneMask & MOMask).none())
2813 continue;
2814 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2815 }
2816 }
2817 }
2818 }
2819 }
2820}
2821
2822// This function gets called after visiting all instructions in a bundle. The
2823// argument points to the bundle header.
2824// Normal stand-alone instructions are also considered 'bundles', and this
2825// function is called for all of them.
2826void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2827 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2828 set_union(MInfo.regsKilled, regsKilled);
2829 set_subtract(regsLive, regsKilled); regsKilled.clear();
2830 // Kill any masked registers.
2831 while (!regMasks.empty()) {
2832 const uint32_t *Mask = regMasks.pop_back_val();
2833 for (Register Reg : regsLive)
2834 if (Reg.isPhysical() &&
2835 MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg()))
2836 regsDead.push_back(Reg);
2837 }
2838 set_subtract(regsLive, regsDead); regsDead.clear();
2839 set_union(regsLive, regsDefined); regsDefined.clear();
2840}
2841
2842void
2843MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2844 MBBInfoMap[MBB].regsLiveOut = regsLive;
2845 regsLive.clear();
2846
2847 if (Indexes) {
2848 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2849 if (!(stop > lastIndex)) {
2850 report("Block ends before last instruction index", MBB);
2851 errs() << "Block ends at " << stop
2852 << " last instruction was at " << lastIndex << '\n';
2853 }
2854 lastIndex = stop;
2855 }
2856}
2857
2858namespace {
2859// This implements a set of registers that serves as a filter: can filter other
2860// sets by passing through elements not in the filter and blocking those that
2861// are. Any filter implicitly includes the full set of physical registers upon
2862// creation, thus filtering them all out. The filter itself as a set only grows,
2863// and needs to be as efficient as possible.
2864struct VRegFilter {
2865 // Add elements to the filter itself. \pre Input set \p FromRegSet must have
2866 // no duplicates. Both virtual and physical registers are fine.
2867 template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2868 SmallVector<Register, 0> VRegsBuffer;
2869 filterAndAdd(FromRegSet, VRegsBuffer);
2870 }
2871 // Filter \p FromRegSet through the filter and append passed elements into \p
2872 // ToVRegs. All elements appended are then added to the filter itself.
2873 // \returns true if anything changed.
2874 template <typename RegSetT>
2875 bool filterAndAdd(const RegSetT &FromRegSet,
2876 SmallVectorImpl<Register> &ToVRegs) {
2877 unsigned SparseUniverse = Sparse.size();
2878 unsigned NewSparseUniverse = SparseUniverse;
2879 unsigned NewDenseSize = Dense.size();
2880 size_t Begin = ToVRegs.size();
2881 for (Register Reg : FromRegSet) {
2882 if (!Reg.isVirtual())
2883 continue;
2884 unsigned Index = Register::virtReg2Index(Reg);
2885 if (Index < SparseUniverseMax) {
2886 if (Index < SparseUniverse && Sparse.test(Index))
2887 continue;
2888 NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
2889 } else {
2890 if (Dense.count(Reg))
2891 continue;
2892 ++NewDenseSize;
2893 }
2894 ToVRegs.push_back(Reg);
2895 }
2896 size_t End = ToVRegs.size();
2897 if (Begin == End)
2898 return false;
2899 // Reserving space in sets once performs better than doing so continuously
2900 // and pays easily for double look-ups (even in Dense with SparseUniverseMax
2901 // tuned all the way down) and double iteration (the second one is over a
2902 // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2903 Sparse.resize(NewSparseUniverse);
2904 Dense.reserve(NewDenseSize);
2905 for (unsigned I = Begin; I < End; ++I) {
2906 Register Reg = ToVRegs[I];
2907 unsigned Index = Register::virtReg2Index(Reg);
2908 if (Index < SparseUniverseMax)
2909 Sparse.set(Index);
2910 else
2911 Dense.insert(Reg);
2912 }
2913 return true;
2914 }
2915
2916private:
2917 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2918 // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
2919 // are tracked by Dense. The only purpose of the threashold and the Dense set
2920 // is to have a reasonably growing memory usage in pathological cases (large
2921 // number of very sparse VRegFilter instances live at the same time). In
2922 // practice even in the worst-by-execution time cases having all elements
2923 // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
2924 // space efficient than if tracked by Dense. The threashold is set to keep the
2925 // worst-case memory usage within 2x of figures determined empirically for
2926 // "all Dense" scenario in such worst-by-execution-time cases.
2927 BitVector Sparse;
2929};
2930
2931// Implements both a transfer function and a (binary, in-place) join operator
2932// for a dataflow over register sets with set union join and filtering transfer
2933// (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
2934// Maintains out_b as its state, allowing for O(n) iteration over it at any
2935// time, where n is the size of the set (as opposed to O(U) where U is the
2936// universe). filter_b implicitly contains all physical registers at all times.
2937class FilteringVRegSet {
2938 VRegFilter Filter;
2940
2941public:
2942 // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
2943 // Both virtual and physical registers are fine.
2944 template <typename RegSetT> void addToFilter(const RegSetT &RS) {
2945 Filter.add(RS);
2946 }
2947 // Passes \p RS through the filter_b (transfer function) and adds what's left
2948 // to itself (out_b).
2949 template <typename RegSetT> bool add(const RegSetT &RS) {
2950 // Double-duty the Filter: to maintain VRegs a set (and the join operation
2951 // a set union) just add everything being added here to the Filter as well.
2952 return Filter.filterAndAdd(RS, VRegs);
2953 }
2954 using const_iterator = decltype(VRegs)::const_iterator;
2955 const_iterator begin() const { return VRegs.begin(); }
2956 const_iterator end() const { return VRegs.end(); }
2957 size_t size() const { return VRegs.size(); }
2958};
2959} // namespace
2960
2961// Calculate the largest possible vregsPassed sets. These are the registers that
2962// can pass through an MBB live, but may not be live every time. It is assumed
2963// that all vregsPassed sets are empty before the call.
2964void MachineVerifier::calcRegsPassed() {
2965 if (MF->empty())
2966 // ReversePostOrderTraversal doesn't handle empty functions.
2967 return;
2968
2969 for (const MachineBasicBlock *MB :
2971 FilteringVRegSet VRegs;
2972 BBInfo &Info = MBBInfoMap[MB];
2973 assert(Info.reachable);
2974
2975 VRegs.addToFilter(Info.regsKilled);
2976 VRegs.addToFilter(Info.regsLiveOut);
2977 for (const MachineBasicBlock *Pred : MB->predecessors()) {
2978 const BBInfo &PredInfo = MBBInfoMap[Pred];
2979 if (!PredInfo.reachable)
2980 continue;
2981
2982 VRegs.add(PredInfo.regsLiveOut);
2983 VRegs.add(PredInfo.vregsPassed);
2984 }
2985 Info.vregsPassed.reserve(VRegs.size());
2986 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2987 }
2988}
2989
2990// Calculate the set of virtual registers that must be passed through each basic
2991// block in order to satisfy the requirements of successor blocks. This is very
2992// similar to calcRegsPassed, only backwards.
2993void MachineVerifier::calcRegsRequired() {
2994 // First push live-in regs to predecessors' vregsRequired.
2996 for (const auto &MBB : *MF) {
2997 BBInfo &MInfo = MBBInfoMap[&MBB];
2998 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2999 BBInfo &PInfo = MBBInfoMap[Pred];
3000 if (PInfo.addRequired(MInfo.vregsLiveIn))
3001 todo.insert(Pred);
3002 }
3003
3004 // Handle the PHI node.
3005 for (const MachineInstr &MI : MBB.phis()) {
3006 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
3007 // Skip those Operands which are undef regs or not regs.
3008 if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
3009 continue;
3010
3011 // Get register and predecessor for one PHI edge.
3012 Register Reg = MI.getOperand(i).getReg();
3013 const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
3014
3015 BBInfo &PInfo = MBBInfoMap[Pred];
3016 if (PInfo.addRequired(Reg))
3017 todo.insert(Pred);
3018 }
3019 }
3020 }
3021
3022 // Iteratively push vregsRequired to predecessors. This will converge to the
3023 // same final state regardless of DenseSet iteration order.
3024 while (!todo.empty()) {
3025 const MachineBasicBlock *MBB = *todo.begin();
3026 todo.erase(MBB);
3027 BBInfo &MInfo = MBBInfoMap[MBB];
3028 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3029 if (Pred == MBB)
3030 continue;
3031 BBInfo &SInfo = MBBInfoMap[Pred];
3032 if (SInfo.addRequired(MInfo.vregsRequired))
3033 todo.insert(Pred);
3034 }
3035 }
3036}
3037
3038// Check PHI instructions at the beginning of MBB. It is assumed that
3039// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
3040void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
3041 BBInfo &MInfo = MBBInfoMap[&MBB];
3042
3044 for (const MachineInstr &Phi : MBB) {
3045 if (!Phi.isPHI())
3046 break;
3047 seen.clear();
3048
3049 const MachineOperand &MODef = Phi.getOperand(0);
3050 if (!MODef.isReg() || !MODef.isDef()) {
3051 report("Expected first PHI operand to be a register def", &MODef, 0);
3052 continue;
3053 }
3054 if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
3055 MODef.isEarlyClobber() || MODef.isDebug())
3056 report("Unexpected flag on PHI operand", &MODef, 0);
3057 Register DefReg = MODef.getReg();
3058 if (!DefReg.isVirtual())
3059 report("Expected first PHI operand to be a virtual register", &MODef, 0);
3060
3061 for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
3062 const MachineOperand &MO0 = Phi.getOperand(I);
3063 if (!MO0.isReg()) {
3064 report("Expected PHI operand to be a register", &MO0, I);
3065 continue;
3066 }
3067 if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
3068 MO0.isDebug() || MO0.isTied())
3069 report("Unexpected flag on PHI operand", &MO0, I);
3070
3071 const MachineOperand &MO1 = Phi.getOperand(I + 1);
3072 if (!MO1.isMBB()) {
3073 report("Expected PHI operand to be a basic block", &MO1, I + 1);
3074 continue;
3075 }
3076
3077 const MachineBasicBlock &Pre = *MO1.getMBB();
3078 if (!Pre.isSuccessor(&MBB)) {
3079 report("PHI input is not a predecessor block", &MO1, I + 1);
3080 continue;
3081 }
3082
3083 if (MInfo.reachable) {
3084 seen.insert(&Pre);
3085 BBInfo &PrInfo = MBBInfoMap[&Pre];
3086 if (!MO0.isUndef() && PrInfo.reachable &&
3087 !PrInfo.isLiveOut(MO0.getReg()))
3088 report("PHI operand is not live-out from predecessor", &MO0, I);
3089 }
3090 }
3091
3092 // Did we see all predecessors?
3093 if (MInfo.reachable) {
3094 for (MachineBasicBlock *Pred : MBB.predecessors()) {
3095 if (!seen.count(Pred)) {
3096 report("Missing PHI operand", &Phi);
3097 errs() << printMBBReference(*Pred)
3098 << " is a predecessor according to the CFG.\n";
3099 }
3100 }
3101 }
3102 }
3103}
3104
3105static void
3107 std::function<void(const Twine &Message)> FailureCB) {
3109 CV.initialize(&errs(), FailureCB, MF);
3110
3111 for (const auto &MBB : MF) {
3112 CV.visit(MBB);
3113 for (const auto &MI : MBB.instrs())
3114 CV.visit(MI);
3115 }
3116
3117 if (CV.sawTokens()) {
3118 DT.recalculate(const_cast<MachineFunction &>(MF));
3119 CV.verify(DT);
3120 }
3121}
3122
3123void MachineVerifier::visitMachineFunctionAfter() {
3124 auto FailureCB = [this](const Twine &Message) {
3125 report(Message.str().c_str(), MF);
3126 };
3127 verifyConvergenceControl(*MF, DT, FailureCB);
3128
3129 calcRegsPassed();
3130
3131 for (const MachineBasicBlock &MBB : *MF)
3132 checkPHIOps(MBB);
3133
3134 // Now check liveness info if available
3135 calcRegsRequired();
3136
3137 // Check for killed virtual registers that should be live out.
3138 for (const auto &MBB : *MF) {
3139 BBInfo &MInfo = MBBInfoMap[&MBB];
3140 for (Register VReg : MInfo.vregsRequired)
3141 if (MInfo.regsKilled.count(VReg)) {
3142 report("Virtual register killed in block, but needed live out.", &MBB);
3143 errs() << "Virtual register " << printReg(VReg)
3144 << " is used after the block.\n";
3145 }
3146 }
3147
3148 if (!MF->empty()) {
3149 BBInfo &MInfo = MBBInfoMap[&MF->front()];
3150 for (Register VReg : MInfo.vregsRequired) {
3151 report("Virtual register defs don't dominate all uses.", MF);
3152 report_context_vreg(VReg);
3153 }
3154 }
3155
3156 if (LiveVars)
3157 verifyLiveVariables();
3158 if (LiveInts)
3159 verifyLiveIntervals();
3160
3161 // Check live-in list of each MBB. If a register is live into MBB, check
3162 // that the register is in regsLiveOut of each predecessor block. Since
3163 // this must come from a definition in the predecesssor or its live-in
3164 // list, this will catch a live-through case where the predecessor does not
3165 // have the register in its live-in list. This currently only checks
3166 // registers that have no aliases, are not allocatable and are not
3167 // reserved, which could mean a condition code register for instance.
3168 if (MRI->tracksLiveness())
3169 for (const auto &MBB : *MF)
3171 MCPhysReg LiveInReg = P.PhysReg;
3172 bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
3173 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
3174 continue;
3175 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
3176 BBInfo &PInfo = MBBInfoMap[Pred];
3177 if (!PInfo.regsLiveOut.count(LiveInReg)) {
3178 report("Live in register not found to be live out from predecessor.",
3179 &MBB);
3180 errs() << TRI->getName(LiveInReg)
3181 << " not found to be live out from "
3182 << printMBBReference(*Pred) << "\n";
3183 }
3184 }
3185 }
3186
3187 for (auto CSInfo : MF->getCallSitesInfo())
3188 if (!CSInfo.first->isCall())
3189 report("Call site info referencing instruction that is not call", MF);
3190
3191 // If there's debug-info, check that we don't have any duplicate value
3192 // tracking numbers.
3193 if (MF->getFunction().getSubprogram()) {
3194 DenseSet<unsigned> SeenNumbers;
3195 for (const auto &MBB : *MF) {
3196 for (const auto &MI : MBB) {
3197 if (auto Num = MI.peekDebugInstrNum()) {
3198 auto Result = SeenNumbers.insert((unsigned)Num);
3199 if (!Result.second)
3200 report("Instruction has a duplicated value tracking number", &MI);
3201 }
3202 }
3203 }
3204 }
3205}
3206
3207void MachineVerifier::verifyLiveVariables() {
3208 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
3209 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
3211 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
3212 for (const auto &MBB : *MF) {
3213 BBInfo &MInfo = MBBInfoMap[&MBB];
3214
3215 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
3216 if (MInfo.vregsRequired.count(Reg)) {
3217 if (!VI.AliveBlocks.test(MBB.getNumber())) {
3218 report("LiveVariables: Block missing from AliveBlocks", &MBB);
3219 errs() << "Virtual register " << printReg(Reg)
3220 << " must be live through the block.\n";
3221 }
3222 } else {
3223 if (VI.AliveBlocks.test(MBB.getNumber())) {
3224 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
3225 errs() << "Virtual register " << printReg(Reg)
3226 << " is not needed live through the block.\n";
3227 }
3228 }
3229 }
3230 }
3231}
3232
3233void MachineVerifier::verifyLiveIntervals() {
3234 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
3235 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
3237
3238 // Spilling and splitting may leave unused registers around. Skip them.
3239 if (MRI->reg_nodbg_empty(Reg))
3240 continue;
3241
3242 if (!LiveInts->hasInterval(Reg)) {
3243 report("Missing live interval for virtual register", MF);
3244 errs() << printReg(Reg, TRI) << " still has defs or uses\n";
3245 continue;
3246 }
3247
3248 const LiveInterval &LI = LiveInts->getInterval(Reg);
3249 assert(Reg == LI.reg() && "Invalid reg to interval mapping");
3250 verifyLiveInterval(LI);
3251 }
3252
3253 // Verify all the cached regunit intervals.
3254 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
3255 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
3256 verifyLiveRange(*LR, i);
3257}
3258
3259void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
3260 const VNInfo *VNI, Register Reg,
3261 LaneBitmask LaneMask) {
3262 if (VNI->isUnused())
3263 return;
3264
3265 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
3266
3267 if (!DefVNI) {
3268 report("Value not live at VNInfo def and not marked unused", MF);
3269 report_context(LR, Reg, LaneMask);
3270 report_context(*VNI);
3271 return;
3272 }
3273
3274 if (DefVNI != VNI) {
3275 report("Live segment at def has different VNInfo", MF);
3276 report_context(LR, Reg, LaneMask);
3277 report_context(*VNI);
3278 return;
3279 }
3280
3281 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
3282 if (!MBB) {
3283 report("Invalid VNInfo definition index", MF);
3284 report_context(LR, Reg, LaneMask);
3285 report_context(*VNI);
3286 return;
3287 }
3288
3289 if (VNI->isPHIDef()) {
3290 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
3291 report("PHIDef VNInfo is not defined at MBB start", MBB);
3292 report_context(LR, Reg, LaneMask);
3293 report_context(*VNI);
3294 }
3295 return;
3296 }
3297
3298 // Non-PHI def.
3299 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
3300 if (!MI) {
3301 report("No instruction at VNInfo def index", MBB);
3302 report_context(LR, Reg, LaneMask);
3303 report_context(*VNI);
3304 return;
3305 }
3306
3307 if (Reg != 0) {
3308 bool hasDef = false;
3309 bool isEarlyClobber = false;
3310 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3311 if (!MOI->isReg() || !MOI->isDef())
3312 continue;
3313 if (Reg.isVirtual()) {
3314 if (MOI->getReg() != Reg)
3315 continue;
3316 } else {
3317 if (!MOI->getReg().isPhysical() || !TRI->hasRegUnit(MOI->getReg(), Reg))
3318 continue;
3319 }
3320 if (LaneMask.any() &&
3321 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3322 continue;
3323 hasDef = true;
3324 if (MOI->isEarlyClobber())
3325 isEarlyClobber = true;
3326 }
3327
3328 if (!hasDef) {
3329 report("Defining instruction does not modify register", MI);
3330 report_context(LR, Reg, LaneMask);
3331 report_context(*VNI);
3332 }
3333
3334 // Early clobber defs begin at USE slots, but other defs must begin at
3335 // DEF slots.
3336 if (isEarlyClobber) {
3337 if (!VNI->def.isEarlyClobber()) {
3338 report("Early clobber def must be at an early-clobber slot", MBB);
3339 report_context(LR, Reg, LaneMask);
3340 report_context(*VNI);
3341 }
3342 } else if (!VNI->def.isRegister()) {
3343 report("Non-PHI, non-early clobber def must be at a register slot", MBB);
3344 report_context(LR, Reg, LaneMask);
3345 report_context(*VNI);
3346 }
3347 }
3348}
3349
3350void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
3352 Register Reg,
3353 LaneBitmask LaneMask) {
3354 const LiveRange::Segment &S = *I;
3355 const VNInfo *VNI = S.valno;
3356 assert(VNI && "Live segment has no valno");
3357
3358 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
3359 report("Foreign valno in live segment", MF);
3360 report_context(LR, Reg, LaneMask);
3361 report_context(S);
3362 report_context(*VNI);
3363 }
3364
3365 if (VNI->isUnused()) {
3366 report("Live segment valno is marked unused", MF);
3367 report_context(LR, Reg, LaneMask);
3368 report_context(S);
3369 }
3370
3371 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
3372 if (!MBB) {
3373 report("Bad start of live segment, no basic block", MF);
3374 report_context(LR, Reg, LaneMask);
3375 report_context(S);
3376 return;
3377 }
3378 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
3379 if (S.start != MBBStartIdx && S.start != VNI->def) {
3380 report("Live segment must begin at MBB entry or valno def", MBB);
3381 report_context(LR, Reg, LaneMask);
3382 report_context(S);
3383 }
3384
3385 const MachineBasicBlock *EndMBB =
3386 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
3387 if (!EndMBB) {
3388 report("Bad end of live segment, no basic block", MF);
3389 report_context(LR, Reg, LaneMask);
3390 report_context(S);
3391 return;
3392 }
3393
3394 // Checks for non-live-out segments.
3395 if (S.end != LiveInts->getMBBEndIdx(EndMBB)) {
3396 // RegUnit intervals are allowed dead phis.
3397 if (!Reg.isVirtual() && VNI->isPHIDef() && S.start == VNI->def &&
3398 S.end == VNI->def.getDeadSlot())
3399 return;
3400
3401 // The live segment is ending inside EndMBB
3402 const MachineInstr *MI =
3404 if (!MI) {
3405 report("Live segment doesn't end at a valid instruction", EndMBB);
3406 report_context(LR, Reg, LaneMask);
3407 report_context(S);
3408 return;
3409 }
3410
3411 // The block slot must refer to a basic block boundary.
3412 if (S.end.isBlock()) {
3413 report("Live segment ends at B slot of an instruction", EndMBB);
3414 report_context(LR, Reg, LaneMask);
3415 report_context(S);
3416 }
3417
3418 if (S.end.isDead()) {
3419 // Segment ends on the dead slot.
3420 // That means there must be a dead def.
3421 if (!SlotIndex::isSameInstr(S.start, S.end)) {
3422 report("Live segment ending at dead slot spans instructions", EndMBB);
3423 report_context(LR, Reg, LaneMask);
3424 report_context(S);
3425 }
3426 }
3427
3428 // After tied operands are rewritten, a live segment can only end at an
3429 // early-clobber slot if it is being redefined by an early-clobber def.
3430 // TODO: Before tied operands are rewritten, a live segment can only end at
3431 // an early-clobber slot if the last use is tied to an early-clobber def.
3432 if (MF->getProperties().hasProperty(
3434 S.end.isEarlyClobber()) {
3435 if (I + 1 == LR.end() || (I + 1)->start != S.end) {
3436 report("Live segment ending at early clobber slot must be "
3437 "redefined by an EC def in the same instruction",
3438 EndMBB);
3439 report_context(LR, Reg, LaneMask);
3440 report_context(S);
3441 }
3442 }
3443
3444 // The following checks only apply to virtual registers. Physreg liveness
3445 // is too weird to check.
3446 if (Reg.isVirtual()) {
3447 // A live segment can end with either a redefinition, a kill flag on a
3448 // use, or a dead flag on a def.
3449 bool hasRead = false;
3450 bool hasSubRegDef = false;
3451 bool hasDeadDef = false;
3452 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3453 if (!MOI->isReg() || MOI->getReg() != Reg)
3454 continue;
3455 unsigned Sub = MOI->getSubReg();
3456 LaneBitmask SLM =
3457 Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) : LaneBitmask::getAll();
3458 if (MOI->isDef()) {
3459 if (Sub != 0) {
3460 hasSubRegDef = true;
3461 // An operand %0:sub0 reads %0:sub1..n. Invert the lane
3462 // mask for subregister defs. Read-undef defs will be handled by
3463 // readsReg below.
3464 SLM = ~SLM;
3465 }
3466 if (MOI->isDead())
3467 hasDeadDef = true;
3468 }
3469 if (LaneMask.any() && (LaneMask & SLM).none())
3470 continue;
3471 if (MOI->readsReg())
3472 hasRead = true;
3473 }
3474 if (S.end.isDead()) {
3475 // Make sure that the corresponding machine operand for a "dead" live
3476 // range has the dead flag. We cannot perform this check for subregister
3477 // liveranges as partially dead values are allowed.
3478 if (LaneMask.none() && !hasDeadDef) {
3479 report(
3480 "Instruction ending live segment on dead slot has no dead flag",
3481 MI);
3482 report_context(LR, Reg, LaneMask);
3483 report_context(S);
3484 }
3485 } else {
3486 if (!hasRead) {
3487 // When tracking subregister liveness, the main range must start new
3488 // values on partial register writes, even if there is no read.
3489 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
3490 !hasSubRegDef) {
3491 report("Instruction ending live segment doesn't read the register",
3492 MI);
3493 report_context(LR, Reg, LaneMask);
3494 report_context(S);
3495 }
3496 }
3497 }
3498 }
3499 }
3500
3501 // Now check all the basic blocks in this live segment.
3503 // Is this live segment the beginning of a non-PHIDef VN?
3504 if (S.start == VNI->def && !VNI->isPHIDef()) {
3505 // Not live-in to any blocks.
3506 if (MBB == EndMBB)
3507 return;
3508 // Skip this block.
3509 ++MFI;
3510 }
3511
3513 if (LaneMask.any()) {
3514 LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3515 OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
3516 }
3517
3518 while (true) {
3519 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3520 // We don't know how to track physregs into a landing pad.
3521 if (!Reg.isVirtual() && MFI->isEHPad()) {
3522 if (&*MFI == EndMBB)
3523 break;
3524 ++MFI;
3525 continue;
3526 }
3527
3528 // Is VNI a PHI-def in the current block?
3529 bool IsPHI = VNI->isPHIDef() &&
3530 VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3531
3532 // Check that VNI is live-out of all predecessors.
3533 for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3534 SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3535 // Predecessor of landing pad live-out on last call.
3536 if (MFI->isEHPad()) {
3537 for (const MachineInstr &MI : llvm::reverse(*Pred)) {
3538 if (MI.isCall()) {
3539 PEnd = Indexes->getInstructionIndex(MI).getBoundaryIndex();
3540 break;
3541 }
3542 }
3543 }
3544 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
3545
3546 // All predecessors must have a live-out value. However for a phi
3547 // instruction with subregister intervals
3548 // only one of the subregisters (not necessarily the current one) needs to
3549 // be defined.
3550 if (!PVNI && (LaneMask.none() || !IsPHI)) {
3551 if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
3552 continue;
3553 report("Register not marked live out of predecessor", Pred);
3554 report_context(LR, Reg, LaneMask);
3555 report_context(*VNI);
3556 errs() << " live into " << printMBBReference(*MFI) << '@'
3557 << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3558 << PEnd << '\n';
3559 continue;
3560 }
3561
3562 // Only PHI-defs can take different predecessor values.
3563 if (!IsPHI && PVNI != VNI) {
3564 report("Different value live out of predecessor", Pred);
3565 report_context(LR, Reg, LaneMask);
3566 errs() << "Valno #" << PVNI->id << " live out of "
3567 << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
3568 << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3569 << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3570 }
3571 }
3572 if (&*MFI == EndMBB)
3573 break;
3574 ++MFI;
3575 }
3576}
3577
3578void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
3579 LaneBitmask LaneMask) {
3580 for (const VNInfo *VNI : LR.valnos)
3581 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3582
3583 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
3584 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
3585}
3586
3587void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3588 Register Reg = LI.reg();
3589 assert(Reg.isVirtual());
3590 verifyLiveRange(LI, Reg);
3591
3592 if (LI.hasSubRanges()) {
3594 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
3595 for (const LiveInterval::SubRange &SR : LI.subranges()) {
3596 if ((Mask & SR.LaneMask).any()) {
3597 report("Lane masks of sub ranges overlap in live interval", MF);
3598 report_context(LI);
3599 }
3600 if ((SR.LaneMask & ~MaxMask).any()) {
3601 report("Subrange lanemask is invalid", MF);
3602 report_context(LI);
3603 }
3604 if (SR.empty()) {
3605 report("Subrange must not be empty", MF);
3606 report_context(SR, LI.reg(), SR.LaneMask);
3607 }
3608 Mask |= SR.LaneMask;
3609 verifyLiveRange(SR, LI.reg(), SR.LaneMask);
3610 if (!LI.covers(SR)) {
3611 report("A Subrange is not covered by the main range", MF);
3612 report_context(LI);
3613 }
3614 }
3615 }
3616
3617 // Check the LI only has one connected component.
3618 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
3619 unsigned NumComp = ConEQ.Classify(LI);
3620 if (NumComp > 1) {
3621 report("Multiple connected components in live interval", MF);
3622 report_context(LI);
3623 for (unsigned comp = 0; comp != NumComp; ++comp) {
3624 errs() << comp << ": valnos";
3625 for (const VNInfo *I : LI.valnos)
3626 if (comp == ConEQ.getEqClass(I))
3627 errs() << ' ' << I->id;
3628 errs() << '\n';
3629 }
3630 }
3631}
3632
3633namespace {
3634
3635 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
3636 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
3637 // value is zero.
3638 // We use a bool plus an integer to capture the stack state.
3639 struct StackStateOfBB {
3640 StackStateOfBB() = default;
3641 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
3642 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3643 ExitIsSetup(ExitSetup) {}
3644
3645 // Can be negative, which means we are setting up a frame.
3646 int EntryValue = 0;
3647 int ExitValue = 0;
3648 bool EntryIsSetup = false;
3649 bool ExitIsSetup = false;
3650 };
3651
3652} // end anonymous namespace
3653
3654/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
3655/// by a FrameDestroy <n>, stack adjustments are identical on all
3656/// CFG edges to a merge point, and frame is destroyed at end of a return block.
3657void MachineVerifier::verifyStackFrame() {
3658 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3659 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3660 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3661 return;
3662
3664 SPState.resize(MF->getNumBlockIDs());
3666
3667 // Visit the MBBs in DFS order.
3668 for (df_ext_iterator<const MachineFunction *,
3670 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
3671 DFI != DFE; ++DFI) {
3672 const MachineBasicBlock *MBB = *DFI;
3673
3674 StackStateOfBB BBState;
3675 // Check the exit state of the DFS stack predecessor.
3676 if (DFI.getPathLength() >= 2) {
3677 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3678 assert(Reachable.count(StackPred) &&
3679 "DFS stack predecessor is already visited.\n");
3680 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3681 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3682 BBState.ExitValue = BBState.EntryValue;
3683 BBState.ExitIsSetup = BBState.EntryIsSetup;
3684 }
3685
3686 if ((int)MBB->getCallFrameSize() != -BBState.EntryValue) {
3687 report("Call frame size on entry does not match value computed from "
3688 "predecessor",
3689 MBB);
3690 errs() << "Call frame size on entry " << MBB->getCallFrameSize()
3691 << " does not match value computed from predecessor "
3692 << -BBState.EntryValue << '\n';
3693 }
3694
3695 // Update stack state by checking contents of MBB.
3696 for (const auto &I : *MBB) {
3697 if (I.getOpcode() == FrameSetupOpcode) {
3698 if (BBState.ExitIsSetup)
3699 report("FrameSetup is after another FrameSetup", &I);
3700 BBState.ExitValue -= TII->getFrameTotalSize(I);
3701 BBState.ExitIsSetup = true;
3702 }
3703
3704 if (I.getOpcode() == FrameDestroyOpcode) {
3705 int Size = TII->getFrameTotalSize(I);
3706 if (!BBState.ExitIsSetup)
3707 report("FrameDestroy is not after a FrameSetup", &I);
3708 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3709 BBState.ExitValue;
3710 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
3711 report("FrameDestroy <n> is after FrameSetup <m>", &I);
3712 errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
3713 << AbsSPAdj << ">.\n";
3714 }
3715 BBState.ExitValue += Size;
3716 BBState.ExitIsSetup = false;
3717 }
3718 }
3719 SPState[MBB->getNumber()] = BBState;
3720
3721 // Make sure the exit state of any predecessor is consistent with the entry
3722 // state.
3723 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3724 if (Reachable.count(Pred) &&
3725 (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3726 SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3727 report("The exit stack state of a predecessor is inconsistent.", MBB);
3728 errs() << "Predecessor " << printMBBReference(*Pred)
3729 << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3730 << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3731 << printMBBReference(*MBB) << " has entry state ("
3732 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
3733 }
3734 }
3735
3736 // Make sure the entry state of any successor is consistent with the exit
3737 // state.
3738 for (const MachineBasicBlock *Succ : MBB->successors()) {
3739 if (Reachable.count(Succ) &&
3740 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3741 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3742 report("The entry stack state of a successor is inconsistent.", MBB);
3743 errs() << "Successor " << printMBBReference(*Succ)
3744 << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3745 << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3746 << printMBBReference(*MBB) << " has exit state ("
3747 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
3748 }
3749 }
3750
3751 // Make sure a basic block with return ends with zero stack adjustment.
3752 if (!MBB->empty() && MBB->back().isReturn()) {
3753 if (BBState.ExitIsSetup)
3754 report("A return block ends with a FrameSetup.", MBB);
3755 if (BBState.ExitValue)
3756 report("A return block ends with a nonzero stack adjustment.", MBB);
3757 }
3758 }
3759}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
This file implements the BitVector class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
std::string Name
uint64_t Size
bool End
Definition: ELF_riscv.cpp:480
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
hexagon widen stores
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MIR specialization of the GenericConvergenceVerifier template.
unsigned const TargetRegisterInfo * TRI
unsigned Reg
static void verifyConvergenceControl(const MachineFunction &MF, MachineDomTree &DT, std::function< void(const Twine &Message)> FailureCB)
modulo schedule Modulo Schedule test pass
#define P(N)
ppc ctr loops verify
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file contains some templates that are useful if you are working with the STL at all.
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
Definition: APFloat.h:1303
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
Definition: BasicBlock.h:639
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.h:220
bool test(unsigned Idx) const
Definition: BitVector.h:461
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:335
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:140
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:159
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:267
const APFloat & getValueAPF() const
Definition: Constants.h:310
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
Definition: Constants.h:147
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:220
Implements a dense probed hash-table based set.
Definition: DenseSet.h:271
Core dominator tree base class.
void recalculate(ParentType &Func)
recalculate - compute a dominator tree for the given function
Register getReg() const
Base class for user error types.
Definition: Error.h:352
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
void initialize(raw_ostream *OS, function_ref< void(const Twine &Message)> FailureCB, const FunctionT &F)
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
Definition: LowLevelType.h:182
constexpr unsigned getScalarSizeInBits() const
Definition: LowLevelType.h:267
constexpr bool isScalar() const
Definition: LowLevelType.h:146
constexpr bool isValid() const
Definition: LowLevelType.h:145
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:159
constexpr bool isVector() const
Definition: LowLevelType.h:148
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:193
constexpr bool isPointer() const
Definition: LowLevelType.h:149
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:290
constexpr ElementCount getElementCount() const
Definition: LowLevelType.h:184
constexpr unsigned getAddressSpace() const
Definition: LowLevelType.h:280
constexpr bool isPointerOrPointerVector() const
Definition: LowLevelType.h:153
constexpr LLT getScalarType() const
Definition: LowLevelType.h:208
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelType.h:203
A live range for subregisters.
Definition: LiveInterval.h:694
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
Register reg() const
Definition: LiveInterval.h:718
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:810
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:782
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
Definition: LiveInterval.h:90
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:105
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
Definition: LiveInterval.h:123
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:317
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
bool empty() const
Definition: LiveInterval.h:382
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:542
iterator end()
Definition: LiveInterval.h:216
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
Definition: LiveInterval.h:429
unsigned getNumValNums() const
Definition: LiveInterval.h:313
iterator begin()
Definition: LiveInterval.h:215
VNInfoList valnos
Definition: LiveInterval.h:204
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:68
bool hasInterval(int Slot) const
Definition: LiveStacks.h:82
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TypeSize getValue() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:780
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:248
bool isConvergent() const
Return true if this instruction is convergent.
Definition: MCInstrDesc.h:415
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:418
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:230
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:113
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getCallFrameSize() const
Return the call frame size on entry to this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
BasicBlockListType::const_iterator const_iterator
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:544
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:906
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:940
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:931
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
LocationSize getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
int64_t getImm() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isImplicit() const
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
Definition: RegisterBank.h:28
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:49
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:45
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:68
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:179
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:212
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:245
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:215
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:219
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
Definition: SlotIndexes.h:234
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:275
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:240
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:222
SlotIndexes pass.
Definition: SlotIndexes.h:300
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:462
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:497
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:502
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
Definition: SlotIndexes.h:473
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:371
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:452
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:366
size_type size() const
Definition: SmallPtrSet.h:94
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:356
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:360
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:342
iterator begin() const
Definition: SmallPtrSet.h:380
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:427
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void resize(size_type N)
Definition: SmallVector.h:651
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
Register getReg() const
MI-level Statepoint operands.
Definition: StackMaps.h:158
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
LLVM Value Representation.
Definition: Value.h:74
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
constexpr bool isNonZero() const
Definition: TypeSize.h:158
static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
Definition: TypeSize.h:203
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
Definition: TypeSize.h:210
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
Definition: TypeSize.h:224
self_iterator getIterator()
Definition: ilist_node.h:109
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:316
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:121
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:61
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:60
Reg
All possible values of the reg field in the ModR/M byte.
constexpr double e
Definition: MathExtras.h:31
NodeAddr< PhiNode * > Phi
Definition: RDFGraph.h:390
NodeAddr< DefNode * > Def
Definition: RDFGraph.h:384
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:227
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:236
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:329
@ Offset
Definition: DWP.cpp:456
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1731
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1689
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition: STLExtras.h:2082
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:82
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:92
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
void verifyMachineFunction(const std::string &Banner, const MachineFunction &MF)
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:428
detail::ValueMatchesPoly< M > HasValue(M Matcher)
Definition: Error.h:221
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1745
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:23
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1858
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1888
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:331
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:82
constexpr bool none() const
Definition: LaneBitmask.h:52
constexpr bool any() const
Definition: LaneBitmask.h:53
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:81
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:80
Pair of physical register and lane mask.