LLVM  9.0.0svn
MipsFastISel.cpp
Go to the documentation of this file.
1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file defines the MIPS-specific support for the FastISel class.
12 /// Some of the target-specific code is generated by tablegen in the file
13 /// MipsGenFastISel.inc, which is #included here.
14 ///
15 //===----------------------------------------------------------------------===//
16 
19 #include "MipsCCState.h"
20 #include "MipsISelLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsMachineFunction.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/CodeGen/FastISel.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/CallingConv.h"
44 #include "llvm/IR/Constant.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DataLayout.h"
47 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GlobalValue.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/InstrTypes.h"
52 #include "llvm/IR/Instruction.h"
53 #include "llvm/IR/Instructions.h"
54 #include "llvm/IR/IntrinsicInst.h"
55 #include "llvm/IR/Operator.h"
56 #include "llvm/IR/Type.h"
57 #include "llvm/IR/User.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCContext.h"
60 #include "llvm/MC/MCInstrDesc.h"
61 #include "llvm/MC/MCRegisterInfo.h"
62 #include "llvm/MC/MCSymbol.h"
63 #include "llvm/Support/Casting.h"
64 #include "llvm/Support/Compiler.h"
65 #include "llvm/Support/Debug.h"
70 #include <algorithm>
71 #include <array>
72 #include <cassert>
73 #include <cstdint>
74 
75 #define DEBUG_TYPE "mips-fastisel"
76 
77 using namespace llvm;
78 
80 
81 namespace {
82 
83 class MipsFastISel final : public FastISel {
84 
85  // All possible address modes.
86  class Address {
87  public:
88  using BaseKind = enum { RegBase, FrameIndexBase };
89 
90  private:
91  BaseKind Kind = RegBase;
92  union {
93  unsigned Reg;
94  int FI;
95  } Base;
96 
97  int64_t Offset = 0;
98 
99  const GlobalValue *GV = nullptr;
100 
101  public:
102  // Innocuous defaults for our address.
103  Address() { Base.Reg = 0; }
104 
105  void setKind(BaseKind K) { Kind = K; }
106  BaseKind getKind() const { return Kind; }
107  bool isRegBase() const { return Kind == RegBase; }
108  bool isFIBase() const { return Kind == FrameIndexBase; }
109 
110  void setReg(unsigned Reg) {
111  assert(isRegBase() && "Invalid base register access!");
112  Base.Reg = Reg;
113  }
114 
115  unsigned getReg() const {
116  assert(isRegBase() && "Invalid base register access!");
117  return Base.Reg;
118  }
119 
120  void setFI(unsigned FI) {
121  assert(isFIBase() && "Invalid base frame index access!");
122  Base.FI = FI;
123  }
124 
125  unsigned getFI() const {
126  assert(isFIBase() && "Invalid base frame index access!");
127  return Base.FI;
128  }
129 
130  void setOffset(int64_t Offset_) { Offset = Offset_; }
131  int64_t getOffset() const { return Offset; }
132  void setGlobalValue(const GlobalValue *G) { GV = G; }
133  const GlobalValue *getGlobalValue() { return GV; }
134  };
135 
136  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
137  /// make the right decision when generating code for different targets.
138  const TargetMachine &TM;
139  const MipsSubtarget *Subtarget;
140  const TargetInstrInfo &TII;
141  const TargetLowering &TLI;
142  MipsFunctionInfo *MFI;
143 
144  // Convenience variables to avoid some queries.
146 
147  bool fastLowerArguments() override;
148  bool fastLowerCall(CallLoweringInfo &CLI) override;
149  bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
150 
151  bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
152  // floating point but not reject doing fast-isel in other
153  // situations
154 
155 private:
156  // Selection routines.
157  bool selectLogicalOp(const Instruction *I);
158  bool selectLoad(const Instruction *I);
159  bool selectStore(const Instruction *I);
160  bool selectBranch(const Instruction *I);
161  bool selectSelect(const Instruction *I);
162  bool selectCmp(const Instruction *I);
163  bool selectFPExt(const Instruction *I);
164  bool selectFPTrunc(const Instruction *I);
165  bool selectFPToInt(const Instruction *I, bool IsSigned);
166  bool selectRet(const Instruction *I);
167  bool selectTrunc(const Instruction *I);
168  bool selectIntExt(const Instruction *I);
169  bool selectShift(const Instruction *I);
170  bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
171 
172  // Utility helper routines.
173  bool isTypeLegal(Type *Ty, MVT &VT);
174  bool isTypeSupported(Type *Ty, MVT &VT);
175  bool isLoadTypeLegal(Type *Ty, MVT &VT);
176  bool computeAddress(const Value *Obj, Address &Addr);
177  bool computeCallAddress(const Value *V, Address &Addr);
178  void simplifyAddress(Address &Addr);
179 
180  // Emit helper routines.
181  bool emitCmp(unsigned DestReg, const CmpInst *CI);
182  bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
183  unsigned Alignment = 0);
184  bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
185  MachineMemOperand *MMO = nullptr);
186  bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
187  unsigned Alignment = 0);
188  unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189  bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
190 
191  bool IsZExt);
192  bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 
194  bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
195  bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196  unsigned DestReg);
197  bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
198  unsigned DestReg);
199 
200  unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
201 
202  unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
203  const Value *RHS);
204 
205  unsigned materializeFP(const ConstantFP *CFP, MVT VT);
206  unsigned materializeGV(const GlobalValue *GV, MVT VT);
207  unsigned materializeInt(const Constant *C, MVT VT);
208  unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
209  unsigned materializeExternalCallSym(MCSymbol *Syn);
210 
211  MachineInstrBuilder emitInst(unsigned Opc) {
212  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
213  }
214 
215  MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
216  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
217  DstReg);
218  }
219 
220  MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
221  unsigned MemReg, int64_t MemOffset) {
222  return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
223  }
224 
225  MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
226  unsigned MemReg, int64_t MemOffset) {
227  return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
228  }
229 
230  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
231  const TargetRegisterClass *RC,
232  unsigned Op0, bool Op0IsKill,
233  unsigned Op1, bool Op1IsKill);
234 
235  // for some reason, this default is not generated by tablegen
236  // so we explicitly generate it here.
237  unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
238  unsigned Op0, bool Op0IsKill, uint64_t imm1,
239  uint64_t imm2, unsigned Op3, bool Op3IsKill) {
240  return 0;
241  }
242 
243  // Call handling routines.
244 private:
245  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
246  bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
247  unsigned &NumBytes);
248  bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
249 
250  const MipsABIInfo &getABI() const {
251  return static_cast<const MipsTargetMachine &>(TM).getABI();
252  }
253 
254 public:
255  // Backend specific FastISel code.
256  explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
257  const TargetLibraryInfo *libInfo)
258  : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
259  Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
260  TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
261  MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
262  Context = &funcInfo.Fn->getContext();
263  UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
264  }
265 
266  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
267  unsigned fastMaterializeConstant(const Constant *C) override;
268  bool fastSelectInstruction(const Instruction *I) override;
269 
270 #include "MipsGenFastISel.inc"
271 };
272 
273 } // end anonymous namespace
274 
275 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
276  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
278 
279 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
280  CCValAssign::LocInfo LocInfo,
281  ISD::ArgFlagsTy ArgFlags, CCState &State) {
282  llvm_unreachable("should not be called");
283 }
284 
285 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
286  CCValAssign::LocInfo LocInfo,
287  ISD::ArgFlagsTy ArgFlags, CCState &State) {
288  llvm_unreachable("should not be called");
289 }
290 
291 #include "MipsGenCallingConv.inc"
292 
293 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
294  return CC_MipsO32;
295 }
296 
297 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
298  const Value *LHS, const Value *RHS) {
299  // Canonicalize immediates to the RHS first.
300  if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
301  std::swap(LHS, RHS);
302 
303  unsigned Opc;
304  switch (ISDOpc) {
305  case ISD::AND:
306  Opc = Mips::AND;
307  break;
308  case ISD::OR:
309  Opc = Mips::OR;
310  break;
311  case ISD::XOR:
312  Opc = Mips::XOR;
313  break;
314  default:
315  llvm_unreachable("unexpected opcode");
316  }
317 
318  unsigned LHSReg = getRegForValue(LHS);
319  if (!LHSReg)
320  return 0;
321 
322  unsigned RHSReg;
323  if (const auto *C = dyn_cast<ConstantInt>(RHS))
324  RHSReg = materializeInt(C, MVT::i32);
325  else
326  RHSReg = getRegForValue(RHS);
327  if (!RHSReg)
328  return 0;
329 
330  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
331  if (!ResultReg)
332  return 0;
333 
334  emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
335  return ResultReg;
336 }
337 
338 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
339  assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
340  "Alloca should always return a pointer.");
341 
343  FuncInfo.StaticAllocaMap.find(AI);
344 
345  if (SI != FuncInfo.StaticAllocaMap.end()) {
346  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
347  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
348  ResultReg)
349  .addFrameIndex(SI->second)
350  .addImm(0);
351  return ResultReg;
352  }
353 
354  return 0;
355 }
356 
357 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
358  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
359  return 0;
360  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
361  const ConstantInt *CI = cast<ConstantInt>(C);
362  return materialize32BitInt(CI->getZExtValue(), RC);
363 }
364 
365 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
366  const TargetRegisterClass *RC) {
367  unsigned ResultReg = createResultReg(RC);
368 
369  if (isInt<16>(Imm)) {
370  unsigned Opc = Mips::ADDiu;
371  emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
372  return ResultReg;
373  } else if (isUInt<16>(Imm)) {
374  emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
375  return ResultReg;
376  }
377  unsigned Lo = Imm & 0xFFFF;
378  unsigned Hi = (Imm >> 16) & 0xFFFF;
379  if (Lo) {
380  // Both Lo and Hi have nonzero bits.
381  unsigned TmpReg = createResultReg(RC);
382  emitInst(Mips::LUi, TmpReg).addImm(Hi);
383  emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
384  } else {
385  emitInst(Mips::LUi, ResultReg).addImm(Hi);
386  }
387  return ResultReg;
388 }
389 
390 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
391  if (UnsupportedFPMode)
392  return 0;
393  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
394  if (VT == MVT::f32) {
395  const TargetRegisterClass *RC = &Mips::FGR32RegClass;
396  unsigned DestReg = createResultReg(RC);
397  unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
398  emitInst(Mips::MTC1, DestReg).addReg(TempReg);
399  return DestReg;
400  } else if (VT == MVT::f64) {
401  const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
402  unsigned DestReg = createResultReg(RC);
403  unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
404  unsigned TempReg2 =
405  materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
406  emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
407  return DestReg;
408  }
409  return 0;
410 }
411 
412 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
413  // For now 32-bit only.
414  if (VT != MVT::i32)
415  return 0;
416  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
417  unsigned DestReg = createResultReg(RC);
418  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
419  bool IsThreadLocal = GVar && GVar->isThreadLocal();
420  // TLS not supported at this time.
421  if (IsThreadLocal)
422  return 0;
423  emitInst(Mips::LW, DestReg)
424  .addReg(MFI->getGlobalBaseReg())
425  .addGlobalAddress(GV, 0, MipsII::MO_GOT);
426  if ((GV->hasInternalLinkage() ||
427  (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
428  unsigned TempReg = createResultReg(RC);
429  emitInst(Mips::ADDiu, TempReg)
430  .addReg(DestReg)
431  .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
432  DestReg = TempReg;
433  }
434  return DestReg;
435 }
436 
437 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
438  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
439  unsigned DestReg = createResultReg(RC);
440  emitInst(Mips::LW, DestReg)
441  .addReg(MFI->getGlobalBaseReg())
442  .addSym(Sym, MipsII::MO_GOT);
443  return DestReg;
444 }
445 
446 // Materialize a constant into a register, and return the register
447 // number (or zero if we failed to handle it).
448 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
449  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
450 
451  // Only handle simple types.
452  if (!CEVT.isSimple())
453  return 0;
454  MVT VT = CEVT.getSimpleVT();
455 
456  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
457  return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
458  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
459  return materializeGV(GV, VT);
460  else if (isa<ConstantInt>(C))
461  return materializeInt(C, VT);
462 
463  return 0;
464 }
465 
466 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
467  const User *U = nullptr;
468  unsigned Opcode = Instruction::UserOp1;
469  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
470  // Don't walk into other basic blocks unless the object is an alloca from
471  // another block, otherwise it may not have a virtual register assigned.
472  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
473  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
474  Opcode = I->getOpcode();
475  U = I;
476  }
477  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
478  Opcode = C->getOpcode();
479  U = C;
480  }
481  switch (Opcode) {
482  default:
483  break;
484  case Instruction::BitCast:
485  // Look through bitcasts.
486  return computeAddress(U->getOperand(0), Addr);
487  case Instruction::GetElementPtr: {
488  Address SavedAddr = Addr;
489  int64_t TmpOffset = Addr.getOffset();
490  // Iterate through the GEP folding the constants into offsets where
491  // we can.
493  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
494  ++i, ++GTI) {
495  const Value *Op = *i;
496  if (StructType *STy = GTI.getStructTypeOrNull()) {
497  const StructLayout *SL = DL.getStructLayout(STy);
498  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
499  TmpOffset += SL->getElementOffset(Idx);
500  } else {
501  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
502  while (true) {
503  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
504  // Constant-offset addressing.
505  TmpOffset += CI->getSExtValue() * S;
506  break;
507  }
508  if (canFoldAddIntoGEP(U, Op)) {
509  // A compatible add with a constant operand. Fold the constant.
510  ConstantInt *CI =
511  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
512  TmpOffset += CI->getSExtValue() * S;
513  // Iterate on the other operand.
514  Op = cast<AddOperator>(Op)->getOperand(0);
515  continue;
516  }
517  // Unsupported
518  goto unsupported_gep;
519  }
520  }
521  }
522  // Try to grab the base operand now.
523  Addr.setOffset(TmpOffset);
524  if (computeAddress(U->getOperand(0), Addr))
525  return true;
526  // We failed, restore everything and try the other options.
527  Addr = SavedAddr;
528  unsupported_gep:
529  break;
530  }
531  case Instruction::Alloca: {
532  const AllocaInst *AI = cast<AllocaInst>(Obj);
534  FuncInfo.StaticAllocaMap.find(AI);
535  if (SI != FuncInfo.StaticAllocaMap.end()) {
536  Addr.setKind(Address::FrameIndexBase);
537  Addr.setFI(SI->second);
538  return true;
539  }
540  break;
541  }
542  }
543  Addr.setReg(getRegForValue(Obj));
544  return Addr.getReg() != 0;
545 }
546 
547 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
548  const User *U = nullptr;
549  unsigned Opcode = Instruction::UserOp1;
550 
551  if (const auto *I = dyn_cast<Instruction>(V)) {
552  // Check if the value is defined in the same basic block. This information
553  // is crucial to know whether or not folding an operand is valid.
554  if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
555  Opcode = I->getOpcode();
556  U = I;
557  }
558  } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
559  Opcode = C->getOpcode();
560  U = C;
561  }
562 
563  switch (Opcode) {
564  default:
565  break;
566  case Instruction::BitCast:
567  // Look past bitcasts if its operand is in the same BB.
568  return computeCallAddress(U->getOperand(0), Addr);
569  break;
570  case Instruction::IntToPtr:
571  // Look past no-op inttoptrs if its operand is in the same BB.
572  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
573  TLI.getPointerTy(DL))
574  return computeCallAddress(U->getOperand(0), Addr);
575  break;
576  case Instruction::PtrToInt:
577  // Look past no-op ptrtoints if its operand is in the same BB.
578  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
579  return computeCallAddress(U->getOperand(0), Addr);
580  break;
581  }
582 
583  if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
584  Addr.setGlobalValue(GV);
585  return true;
586  }
587 
588  // If all else fails, try to materialize the value in a register.
589  if (!Addr.getGlobalValue()) {
590  Addr.setReg(getRegForValue(V));
591  return Addr.getReg() != 0;
592  }
593 
594  return false;
595 }
596 
597 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
598  EVT evt = TLI.getValueType(DL, Ty, true);
599  // Only handle simple types.
600  if (evt == MVT::Other || !evt.isSimple())
601  return false;
602  VT = evt.getSimpleVT();
603 
604  // Handle all legal types, i.e. a register that will directly hold this
605  // value.
606  return TLI.isTypeLegal(VT);
607 }
608 
609 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
610  if (Ty->isVectorTy())
611  return false;
612 
613  if (isTypeLegal(Ty, VT))
614  return true;
615 
616  // If this is a type than can be sign or zero-extended to a basic operation
617  // go ahead and accept it now.
618  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
619  return true;
620 
621  return false;
622 }
623 
624 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
625  if (isTypeLegal(Ty, VT))
626  return true;
627  // We will extend this in a later patch:
628  // If this is a type than can be sign or zero-extended to a basic operation
629  // go ahead and accept it now.
630  if (VT == MVT::i8 || VT == MVT::i16)
631  return true;
632  return false;
633 }
634 
635 // Because of how EmitCmp is called with fast-isel, you can
636 // end up with redundant "andi" instructions after the sequences emitted below.
637 // We should try and solve this issue in the future.
638 //
639 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
640  const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
641  bool IsUnsigned = CI->isUnsigned();
642  unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
643  if (LeftReg == 0)
644  return false;
645  unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
646  if (RightReg == 0)
647  return false;
649 
650  switch (P) {
651  default:
652  return false;
653  case CmpInst::ICMP_EQ: {
654  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
655  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
656  emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
657  break;
658  }
659  case CmpInst::ICMP_NE: {
660  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
661  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
662  emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
663  break;
664  }
665  case CmpInst::ICMP_UGT:
666  emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
667  break;
668  case CmpInst::ICMP_ULT:
669  emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
670  break;
671  case CmpInst::ICMP_UGE: {
672  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
673  emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
674  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
675  break;
676  }
677  case CmpInst::ICMP_ULE: {
678  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
679  emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
680  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
681  break;
682  }
683  case CmpInst::ICMP_SGT:
684  emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
685  break;
686  case CmpInst::ICMP_SLT:
687  emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
688  break;
689  case CmpInst::ICMP_SGE: {
690  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
691  emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
692  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
693  break;
694  }
695  case CmpInst::ICMP_SLE: {
696  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
697  emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
698  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
699  break;
700  }
701  case CmpInst::FCMP_OEQ:
702  case CmpInst::FCMP_UNE:
703  case CmpInst::FCMP_OLT:
704  case CmpInst::FCMP_OLE:
705  case CmpInst::FCMP_OGT:
706  case CmpInst::FCMP_OGE: {
707  if (UnsupportedFPMode)
708  return false;
709  bool IsFloat = Left->getType()->isFloatTy();
710  bool IsDouble = Left->getType()->isDoubleTy();
711  if (!IsFloat && !IsDouble)
712  return false;
713  unsigned Opc, CondMovOpc;
714  switch (P) {
715  case CmpInst::FCMP_OEQ:
716  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
717  CondMovOpc = Mips::MOVT_I;
718  break;
719  case CmpInst::FCMP_UNE:
720  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
721  CondMovOpc = Mips::MOVF_I;
722  break;
723  case CmpInst::FCMP_OLT:
724  Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
725  CondMovOpc = Mips::MOVT_I;
726  break;
727  case CmpInst::FCMP_OLE:
728  Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
729  CondMovOpc = Mips::MOVT_I;
730  break;
731  case CmpInst::FCMP_OGT:
732  Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
733  CondMovOpc = Mips::MOVF_I;
734  break;
735  case CmpInst::FCMP_OGE:
736  Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
737  CondMovOpc = Mips::MOVF_I;
738  break;
739  default:
740  llvm_unreachable("Only switching of a subset of CCs.");
741  }
742  unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
743  unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
744  emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
745  emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
746  emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
747  .addReg(RightReg);
748  emitInst(CondMovOpc, ResultReg)
749  .addReg(RegWithOne)
750  .addReg(Mips::FCC0)
751  .addReg(RegWithZero);
752  break;
753  }
754  }
755  return true;
756 }
757 
758 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
759  unsigned Alignment) {
760  //
761  // more cases will be handled here in following patches.
762  //
763  unsigned Opc;
764  switch (VT.SimpleTy) {
765  case MVT::i32:
766  ResultReg = createResultReg(&Mips::GPR32RegClass);
767  Opc = Mips::LW;
768  break;
769  case MVT::i16:
770  ResultReg = createResultReg(&Mips::GPR32RegClass);
771  Opc = Mips::LHu;
772  break;
773  case MVT::i8:
774  ResultReg = createResultReg(&Mips::GPR32RegClass);
775  Opc = Mips::LBu;
776  break;
777  case MVT::f32:
778  if (UnsupportedFPMode)
779  return false;
780  ResultReg = createResultReg(&Mips::FGR32RegClass);
781  Opc = Mips::LWC1;
782  break;
783  case MVT::f64:
784  if (UnsupportedFPMode)
785  return false;
786  ResultReg = createResultReg(&Mips::AFGR64RegClass);
787  Opc = Mips::LDC1;
788  break;
789  default:
790  return false;
791  }
792  if (Addr.isRegBase()) {
793  simplifyAddress(Addr);
794  emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
795  return true;
796  }
797  if (Addr.isFIBase()) {
798  unsigned FI = Addr.getFI();
799  unsigned Align = 4;
800  int64_t Offset = Addr.getOffset();
801  MachineFrameInfo &MFI = MF->getFrameInfo();
802  MachineMemOperand *MMO = MF->getMachineMemOperand(
804  MFI.getObjectSize(FI), Align);
805  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
806  .addFrameIndex(FI)
807  .addImm(Offset)
808  .addMemOperand(MMO);
809  return true;
810  }
811  return false;
812 }
813 
814 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
815  unsigned Alignment) {
816  //
817  // more cases will be handled here in following patches.
818  //
819  unsigned Opc;
820  switch (VT.SimpleTy) {
821  case MVT::i8:
822  Opc = Mips::SB;
823  break;
824  case MVT::i16:
825  Opc = Mips::SH;
826  break;
827  case MVT::i32:
828  Opc = Mips::SW;
829  break;
830  case MVT::f32:
831  if (UnsupportedFPMode)
832  return false;
833  Opc = Mips::SWC1;
834  break;
835  case MVT::f64:
836  if (UnsupportedFPMode)
837  return false;
838  Opc = Mips::SDC1;
839  break;
840  default:
841  return false;
842  }
843  if (Addr.isRegBase()) {
844  simplifyAddress(Addr);
845  emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
846  return true;
847  }
848  if (Addr.isFIBase()) {
849  unsigned FI = Addr.getFI();
850  unsigned Align = 4;
851  int64_t Offset = Addr.getOffset();
852  MachineFrameInfo &MFI = MF->getFrameInfo();
853  MachineMemOperand *MMO = MF->getMachineMemOperand(
855  MFI.getObjectSize(FI), Align);
856  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
857  .addReg(SrcReg)
858  .addFrameIndex(FI)
859  .addImm(Offset)
860  .addMemOperand(MMO);
861  return true;
862  }
863  return false;
864 }
865 
866 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
867  MVT VT;
868  if (!isTypeSupported(I->getType(), VT))
869  return false;
870 
871  unsigned ResultReg;
872  switch (I->getOpcode()) {
873  default:
874  llvm_unreachable("Unexpected instruction.");
875  case Instruction::And:
876  ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
877  break;
878  case Instruction::Or:
879  ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
880  break;
881  case Instruction::Xor:
882  ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
883  break;
884  }
885 
886  if (!ResultReg)
887  return false;
888 
889  updateValueMap(I, ResultReg);
890  return true;
891 }
892 
893 bool MipsFastISel::selectLoad(const Instruction *I) {
894  // Atomic loads need special handling.
895  if (cast<LoadInst>(I)->isAtomic())
896  return false;
897 
898  // Verify we have a legal type before going any further.
899  MVT VT;
900  if (!isLoadTypeLegal(I->getType(), VT))
901  return false;
902 
903  // See if we can handle this address.
904  Address Addr;
905  if (!computeAddress(I->getOperand(0), Addr))
906  return false;
907 
908  unsigned ResultReg;
909  if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
910  return false;
911  updateValueMap(I, ResultReg);
912  return true;
913 }
914 
915 bool MipsFastISel::selectStore(const Instruction *I) {
916  Value *Op0 = I->getOperand(0);
917  unsigned SrcReg = 0;
918 
919  // Atomic stores need special handling.
920  if (cast<StoreInst>(I)->isAtomic())
921  return false;
922 
923  // Verify we have a legal type before going any further.
924  MVT VT;
925  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
926  return false;
927 
928  // Get the value to be stored into a register.
929  SrcReg = getRegForValue(Op0);
930  if (SrcReg == 0)
931  return false;
932 
933  // See if we can handle this address.
934  Address Addr;
935  if (!computeAddress(I->getOperand(1), Addr))
936  return false;
937 
938  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
939  return false;
940  return true;
941 }
942 
943 // This can cause a redundant sltiu to be generated.
944 // FIXME: try and eliminate this in a future patch.
945 bool MipsFastISel::selectBranch(const Instruction *I) {
946  const BranchInst *BI = cast<BranchInst>(I);
947  MachineBasicBlock *BrBB = FuncInfo.MBB;
948  //
949  // TBB is the basic block for the case where the comparison is true.
950  // FBB is the basic block for the case where the comparison is false.
951  // if (cond) goto TBB
952  // goto FBB
953  // TBB:
954  //
955  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
956  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
957  // For now, just try the simplest case where it's fed by a compare.
958  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
959  MVT CIMVT =
960  TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT();
961  if (CIMVT == MVT::i1)
962  return false;
963 
964  unsigned CondReg = getRegForValue(CI);
965  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
966  .addReg(CondReg)
967  .addMBB(TBB);
968  finishCondBranch(BI->getParent(), TBB, FBB);
969  return true;
970  }
971  return false;
972 }
973 
974 bool MipsFastISel::selectCmp(const Instruction *I) {
975  const CmpInst *CI = cast<CmpInst>(I);
976  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
977  if (!emitCmp(ResultReg, CI))
978  return false;
979  updateValueMap(I, ResultReg);
980  return true;
981 }
982 
983 // Attempt to fast-select a floating-point extend instruction.
984 bool MipsFastISel::selectFPExt(const Instruction *I) {
985  if (UnsupportedFPMode)
986  return false;
987  Value *Src = I->getOperand(0);
988  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
989  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
990 
991  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
992  return false;
993 
994  unsigned SrcReg =
995  getRegForValue(Src); // this must be a 32bit floating point register class
996  // maybe we should handle this differently
997  if (!SrcReg)
998  return false;
999 
1000  unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
1001  emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1002  updateValueMap(I, DestReg);
1003  return true;
1004 }
1005 
1006 bool MipsFastISel::selectSelect(const Instruction *I) {
1007  assert(isa<SelectInst>(I) && "Expected a select instruction.");
1008 
1009  LLVM_DEBUG(dbgs() << "selectSelect\n");
1010 
1011  MVT VT;
1012  if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1013  LLVM_DEBUG(
1014  dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1015  return false;
1016  }
1017 
1018  unsigned CondMovOpc;
1019  const TargetRegisterClass *RC;
1020 
1021  if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1022  CondMovOpc = Mips::MOVN_I_I;
1023  RC = &Mips::GPR32RegClass;
1024  } else if (VT == MVT::f32) {
1025  CondMovOpc = Mips::MOVN_I_S;
1026  RC = &Mips::FGR32RegClass;
1027  } else if (VT == MVT::f64) {
1028  CondMovOpc = Mips::MOVN_I_D32;
1029  RC = &Mips::AFGR64RegClass;
1030  } else
1031  return false;
1032 
1033  const SelectInst *SI = cast<SelectInst>(I);
1034  const Value *Cond = SI->getCondition();
1035  unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1036  unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1037  unsigned CondReg = getRegForValue(Cond);
1038 
1039  if (!Src1Reg || !Src2Reg || !CondReg)
1040  return false;
1041 
1042  unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1043  if (!ZExtCondReg)
1044  return false;
1045 
1046  if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1047  return false;
1048 
1049  unsigned ResultReg = createResultReg(RC);
1050  unsigned TempReg = createResultReg(RC);
1051 
1052  if (!ResultReg || !TempReg)
1053  return false;
1054 
1055  emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1056  emitInst(CondMovOpc, ResultReg)
1057  .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1058  updateValueMap(I, ResultReg);
1059  return true;
1060 }
1061 
1062 // Attempt to fast-select a floating-point truncate instruction.
1063 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1064  if (UnsupportedFPMode)
1065  return false;
1066  Value *Src = I->getOperand(0);
1067  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1068  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1069 
1070  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1071  return false;
1072 
1073  unsigned SrcReg = getRegForValue(Src);
1074  if (!SrcReg)
1075  return false;
1076 
1077  unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1078  if (!DestReg)
1079  return false;
1080 
1081  emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1082  updateValueMap(I, DestReg);
1083  return true;
1084 }
1085 
1086 // Attempt to fast-select a floating-point-to-integer conversion.
1087 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1088  if (UnsupportedFPMode)
1089  return false;
1090  MVT DstVT, SrcVT;
1091  if (!IsSigned)
1092  return false; // We don't handle this case yet. There is no native
1093  // instruction for this but it can be synthesized.
1094  Type *DstTy = I->getType();
1095  if (!isTypeLegal(DstTy, DstVT))
1096  return false;
1097 
1098  if (DstVT != MVT::i32)
1099  return false;
1100 
1101  Value *Src = I->getOperand(0);
1102  Type *SrcTy = Src->getType();
1103  if (!isTypeLegal(SrcTy, SrcVT))
1104  return false;
1105 
1106  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1107  return false;
1108 
1109  unsigned SrcReg = getRegForValue(Src);
1110  if (SrcReg == 0)
1111  return false;
1112 
1113  // Determine the opcode for the conversion, which takes place
1114  // entirely within FPRs.
1115  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1116  unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1117  unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1118 
1119  // Generate the convert.
1120  emitInst(Opc, TempReg).addReg(SrcReg);
1121  emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1122 
1123  updateValueMap(I, DestReg);
1124  return true;
1125 }
1126 
1127 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1128  SmallVectorImpl<MVT> &OutVTs,
1129  unsigned &NumBytes) {
1130  CallingConv::ID CC = CLI.CallConv;
1132  CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1133  CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1134  // Get a count of how many bytes are to be pushed on the stack.
1135  NumBytes = CCInfo.getNextStackOffset();
1136  // This is the minimum argument area used for A0-A3.
1137  if (NumBytes < 16)
1138  NumBytes = 16;
1139 
1140  emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1141  // Process the args.
1142  MVT firstMVT;
1143  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1144  CCValAssign &VA = ArgLocs[i];
1145  const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1146  MVT ArgVT = OutVTs[VA.getValNo()];
1147 
1148  if (i == 0) {
1149  firstMVT = ArgVT;
1150  if (ArgVT == MVT::f32) {
1151  VA.convertToReg(Mips::F12);
1152  } else if (ArgVT == MVT::f64) {
1153  VA.convertToReg(Mips::D6);
1154  }
1155  } else if (i == 1) {
1156  if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1157  if (ArgVT == MVT::f32) {
1158  VA.convertToReg(Mips::F14);
1159  } else if (ArgVT == MVT::f64) {
1160  VA.convertToReg(Mips::D7);
1161  }
1162  }
1163  }
1164  if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1165  (ArgVT == MVT::i8)) &&
1166  VA.isMemLoc()) {
1167  switch (VA.getLocMemOffset()) {
1168  case 0:
1169  VA.convertToReg(Mips::A0);
1170  break;
1171  case 4:
1172  VA.convertToReg(Mips::A1);
1173  break;
1174  case 8:
1175  VA.convertToReg(Mips::A2);
1176  break;
1177  case 12:
1178  VA.convertToReg(Mips::A3);
1179  break;
1180  default:
1181  break;
1182  }
1183  }
1184  unsigned ArgReg = getRegForValue(ArgVal);
1185  if (!ArgReg)
1186  return false;
1187 
1188  // Handle arg promotion: SExt, ZExt, AExt.
1189  switch (VA.getLocInfo()) {
1190  case CCValAssign::Full:
1191  break;
1192  case CCValAssign::AExt:
1193  case CCValAssign::SExt: {
1194  MVT DestVT = VA.getLocVT();
1195  MVT SrcVT = ArgVT;
1196  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1197  if (!ArgReg)
1198  return false;
1199  break;
1200  }
1201  case CCValAssign::ZExt: {
1202  MVT DestVT = VA.getLocVT();
1203  MVT SrcVT = ArgVT;
1204  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1205  if (!ArgReg)
1206  return false;
1207  break;
1208  }
1209  default:
1210  llvm_unreachable("Unknown arg promotion!");
1211  }
1212 
1213  // Now copy/store arg to correct locations.
1214  if (VA.isRegLoc() && !VA.needsCustom()) {
1215  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1216  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1217  CLI.OutRegs.push_back(VA.getLocReg());
1218  } else if (VA.needsCustom()) {
1219  llvm_unreachable("Mips does not use custom args.");
1220  return false;
1221  } else {
1222  //
1223  // FIXME: This path will currently return false. It was copied
1224  // from the AArch64 port and should be essentially fine for Mips too.
1225  // The work to finish up this path will be done in a follow-on patch.
1226  //
1227  assert(VA.isMemLoc() && "Assuming store on stack.");
1228  // Don't emit stores for undef values.
1229  if (isa<UndefValue>(ArgVal))
1230  continue;
1231 
1232  // Need to store on the stack.
1233  // FIXME: This alignment is incorrect but this path is disabled
1234  // for now (will return false). We need to determine the right alignment
1235  // based on the normal alignment for the underlying machine type.
1236  //
1237  unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1238 
1239  unsigned BEAlign = 0;
1240  if (ArgSize < 8 && !Subtarget->isLittle())
1241  BEAlign = 8 - ArgSize;
1242 
1243  Address Addr;
1244  Addr.setKind(Address::RegBase);
1245  Addr.setReg(Mips::SP);
1246  Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1247 
1248  unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1249  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1250  MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1251  MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1252  (void)(MMO);
1253  // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1254  return false; // can't store on the stack yet.
1255  }
1256  }
1257 
1258  return true;
1259 }
1260 
1261 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1262  unsigned NumBytes) {
1263  CallingConv::ID CC = CLI.CallConv;
1264  emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1265  if (RetVT != MVT::isVoid) {
1267  MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1268 
1269  CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1270  CLI.Symbol ? CLI.Symbol->getName().data()
1271  : nullptr);
1272 
1273  // Only handle a single return value.
1274  if (RVLocs.size() != 1)
1275  return false;
1276  // Copy all of the result registers out of their specified physreg.
1277  MVT CopyVT = RVLocs[0].getValVT();
1278  // Special handling for extended integers.
1279  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1280  CopyVT = MVT::i32;
1281 
1282  unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1283  if (!ResultReg)
1284  return false;
1285  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1286  TII.get(TargetOpcode::COPY),
1287  ResultReg).addReg(RVLocs[0].getLocReg());
1288  CLI.InRegs.push_back(RVLocs[0].getLocReg());
1289 
1290  CLI.ResultReg = ResultReg;
1291  CLI.NumResultRegs = 1;
1292  }
1293  return true;
1294 }
1295 
1296 bool MipsFastISel::fastLowerArguments() {
1297  LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1298 
1299  if (!FuncInfo.CanLowerReturn) {
1300  LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1301  return false;
1302  }
1303 
1304  const Function *F = FuncInfo.Fn;
1305  if (F->isVarArg()) {
1306  LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1307  return false;
1308  }
1309 
1310  CallingConv::ID CC = F->getCallingConv();
1311  if (CC != CallingConv::C) {
1312  LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1313  return false;
1314  }
1315 
1316  std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1317  Mips::A3}};
1318  std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1319  std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1320  auto NextGPR32 = GPR32ArgRegs.begin();
1321  auto NextFGR32 = FGR32ArgRegs.begin();
1322  auto NextAFGR64 = AFGR64ArgRegs.begin();
1323 
1324  struct AllocatedReg {
1325  const TargetRegisterClass *RC;
1326  unsigned Reg;
1327  AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1328  : RC(RC), Reg(Reg) {}
1329  };
1330 
1331  // Only handle simple cases. i.e. All arguments are directly mapped to
1332  // registers of the appropriate type.
1333  SmallVector<AllocatedReg, 4> Allocation;
1334  for (const auto &FormalArg : F->args()) {
1335  if (FormalArg.hasAttribute(Attribute::InReg) ||
1336  FormalArg.hasAttribute(Attribute::StructRet) ||
1337  FormalArg.hasAttribute(Attribute::ByVal)) {
1338  LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1339  return false;
1340  }
1341 
1342  Type *ArgTy = FormalArg.getType();
1343  if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1344  LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1345  return false;
1346  }
1347 
1348  EVT ArgVT = TLI.getValueType(DL, ArgTy);
1349  LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1350  << ArgVT.getEVTString() << "\n");
1351  if (!ArgVT.isSimple()) {
1352  LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1353  return false;
1354  }
1355 
1356  switch (ArgVT.getSimpleVT().SimpleTy) {
1357  case MVT::i1:
1358  case MVT::i8:
1359  case MVT::i16:
1360  if (!FormalArg.hasAttribute(Attribute::SExt) &&
1361  !FormalArg.hasAttribute(Attribute::ZExt)) {
1362  // It must be any extend, this shouldn't happen for clang-generated IR
1363  // so just fall back on SelectionDAG.
1364  LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1365  return false;
1366  }
1367 
1368  if (NextGPR32 == GPR32ArgRegs.end()) {
1369  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1370  return false;
1371  }
1372 
1373  LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1374  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1375 
1376  // Allocating any GPR32 prohibits further use of floating point arguments.
1377  NextFGR32 = FGR32ArgRegs.end();
1378  NextAFGR64 = AFGR64ArgRegs.end();
1379  break;
1380 
1381  case MVT::i32:
1382  if (FormalArg.hasAttribute(Attribute::ZExt)) {
1383  // The O32 ABI does not permit a zero-extended i32.
1384  LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1385  return false;
1386  }
1387 
1388  if (NextGPR32 == GPR32ArgRegs.end()) {
1389  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1390  return false;
1391  }
1392 
1393  LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1394  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1395 
1396  // Allocating any GPR32 prohibits further use of floating point arguments.
1397  NextFGR32 = FGR32ArgRegs.end();
1398  NextAFGR64 = AFGR64ArgRegs.end();
1399  break;
1400 
1401  case MVT::f32:
1402  if (UnsupportedFPMode) {
1403  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1404  return false;
1405  }
1406  if (NextFGR32 == FGR32ArgRegs.end()) {
1407  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1408  return false;
1409  }
1410  LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1411  Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1412  // Allocating an FGR32 also allocates the super-register AFGR64, and
1413  // ABI rules require us to skip the corresponding GPR32.
1414  if (NextGPR32 != GPR32ArgRegs.end())
1415  NextGPR32++;
1416  if (NextAFGR64 != AFGR64ArgRegs.end())
1417  NextAFGR64++;
1418  break;
1419 
1420  case MVT::f64:
1421  if (UnsupportedFPMode) {
1422  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1423  return false;
1424  }
1425  if (NextAFGR64 == AFGR64ArgRegs.end()) {
1426  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1427  return false;
1428  }
1429  LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1430  Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1431  // Allocating an FGR32 also allocates the super-register AFGR64, and
1432  // ABI rules require us to skip the corresponding GPR32 pair.
1433  if (NextGPR32 != GPR32ArgRegs.end())
1434  NextGPR32++;
1435  if (NextGPR32 != GPR32ArgRegs.end())
1436  NextGPR32++;
1437  if (NextFGR32 != FGR32ArgRegs.end())
1438  NextFGR32++;
1439  break;
1440 
1441  default:
1442  LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1443  return false;
1444  }
1445  }
1446 
1447  for (const auto &FormalArg : F->args()) {
1448  unsigned ArgNo = FormalArg.getArgNo();
1449  unsigned SrcReg = Allocation[ArgNo].Reg;
1450  unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1451  // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1452  // Without this, EmitLiveInCopies may eliminate the livein if its only
1453  // use is a bitcast (which isn't turned into an instruction).
1454  unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1455  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1456  TII.get(TargetOpcode::COPY), ResultReg)
1457  .addReg(DstReg, getKillRegState(true));
1458  updateValueMap(&FormalArg, ResultReg);
1459  }
1460 
1461  // Calculate the size of the incoming arguments area.
1462  // We currently reject all the cases where this would be non-zero.
1463  unsigned IncomingArgSizeInBytes = 0;
1464 
1465  // Account for the reserved argument area on ABI's that have one (O32).
1466  // It seems strange to do this on the caller side but it's necessary in
1467  // SelectionDAG's implementation.
1468  IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1469  IncomingArgSizeInBytes);
1470 
1471  MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1472  false);
1473 
1474  return true;
1475 }
1476 
1477 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1478  CallingConv::ID CC = CLI.CallConv;
1479  bool IsTailCall = CLI.IsTailCall;
1480  bool IsVarArg = CLI.IsVarArg;
1481  const Value *Callee = CLI.Callee;
1482  MCSymbol *Symbol = CLI.Symbol;
1483 
1484  // Do not handle FastCC.
1485  if (CC == CallingConv::Fast)
1486  return false;
1487 
1488  // Allow SelectionDAG isel to handle tail calls.
1489  if (IsTailCall)
1490  return false;
1491 
1492  // Let SDISel handle vararg functions.
1493  if (IsVarArg)
1494  return false;
1495 
1496  // FIXME: Only handle *simple* calls for now.
1497  MVT RetVT;
1498  if (CLI.RetTy->isVoidTy())
1499  RetVT = MVT::isVoid;
1500  else if (!isTypeSupported(CLI.RetTy, RetVT))
1501  return false;
1502 
1503  for (auto Flag : CLI.OutFlags)
1504  if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1505  return false;
1506 
1507  // Set up the argument vectors.
1508  SmallVector<MVT, 16> OutVTs;
1509  OutVTs.reserve(CLI.OutVals.size());
1510 
1511  for (auto *Val : CLI.OutVals) {
1512  MVT VT;
1513  if (!isTypeLegal(Val->getType(), VT) &&
1514  !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1515  return false;
1516 
1517  // We don't handle vector parameters yet.
1518  if (VT.isVector() || VT.getSizeInBits() > 64)
1519  return false;
1520 
1521  OutVTs.push_back(VT);
1522  }
1523 
1524  Address Addr;
1525  if (!computeCallAddress(Callee, Addr))
1526  return false;
1527 
1528  // Handle the arguments now that we've gotten them.
1529  unsigned NumBytes;
1530  if (!processCallArgs(CLI, OutVTs, NumBytes))
1531  return false;
1532 
1533  if (!Addr.getGlobalValue())
1534  return false;
1535 
1536  // Issue the call.
1537  unsigned DestAddress;
1538  if (Symbol)
1539  DestAddress = materializeExternalCallSym(Symbol);
1540  else
1541  DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1542  emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1543  MachineInstrBuilder MIB =
1544  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1545  Mips::RA).addReg(Mips::T9);
1546 
1547  // Add implicit physical register uses to the call.
1548  for (auto Reg : CLI.OutRegs)
1550 
1551  // Add a register mask with the call-preserved registers.
1552  // Proper defs for return values will be added by setPhysRegsDeadExcept().
1553  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1554 
1555  CLI.Call = MIB;
1556 
1557  if (EmitJalrReloc && !Subtarget->inMips16Mode()) {
1558  // Attach callee address to the instruction, let asm printer emit
1559  // .reloc R_MIPS_JALR.
1560  if (Symbol)
1561  MIB.addSym(Symbol, MipsII::MO_JALR);
1562  else
1563  MIB.addSym(FuncInfo.MF->getContext().getOrCreateSymbol(
1564  Addr.getGlobalValue()->getName()), MipsII::MO_JALR);
1565  }
1566 
1567  // Finish off the call including any return values.
1568  return finishCall(CLI, RetVT, NumBytes);
1569 }
1570 
1571 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1572  switch (II->getIntrinsicID()) {
1573  default:
1574  return false;
1575  case Intrinsic::bswap: {
1576  Type *RetTy = II->getCalledFunction()->getReturnType();
1577 
1578  MVT VT;
1579  if (!isTypeSupported(RetTy, VT))
1580  return false;
1581 
1582  unsigned SrcReg = getRegForValue(II->getOperand(0));
1583  if (SrcReg == 0)
1584  return false;
1585  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1586  if (DestReg == 0)
1587  return false;
1588  if (VT == MVT::i16) {
1589  if (Subtarget->hasMips32r2()) {
1590  emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1591  updateValueMap(II, DestReg);
1592  return true;
1593  } else {
1594  unsigned TempReg[3];
1595  for (int i = 0; i < 3; i++) {
1596  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1597  if (TempReg[i] == 0)
1598  return false;
1599  }
1600  emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1601  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1602  emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1603  emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1604  updateValueMap(II, DestReg);
1605  return true;
1606  }
1607  } else if (VT == MVT::i32) {
1608  if (Subtarget->hasMips32r2()) {
1609  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1610  emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1611  emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1612  updateValueMap(II, DestReg);
1613  return true;
1614  } else {
1615  unsigned TempReg[8];
1616  for (int i = 0; i < 8; i++) {
1617  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1618  if (TempReg[i] == 0)
1619  return false;
1620  }
1621 
1622  emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1623  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1624  emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1625  emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1626 
1627  emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1628  emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1629 
1630  emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1631  emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1632  emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1633  updateValueMap(II, DestReg);
1634  return true;
1635  }
1636  }
1637  return false;
1638  }
1639  case Intrinsic::memcpy:
1640  case Intrinsic::memmove: {
1641  const auto *MTI = cast<MemTransferInst>(II);
1642  // Don't handle volatile.
1643  if (MTI->isVolatile())
1644  return false;
1645  if (!MTI->getLength()->getType()->isIntegerTy(32))
1646  return false;
1647  const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1648  return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1649  }
1650  case Intrinsic::memset: {
1651  const MemSetInst *MSI = cast<MemSetInst>(II);
1652  // Don't handle volatile.
1653  if (MSI->isVolatile())
1654  return false;
1655  if (!MSI->getLength()->getType()->isIntegerTy(32))
1656  return false;
1657  return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1658  }
1659  }
1660  return false;
1661 }
1662 
1663 bool MipsFastISel::selectRet(const Instruction *I) {
1664  const Function &F = *I->getParent()->getParent();
1665  const ReturnInst *Ret = cast<ReturnInst>(I);
1666 
1667  LLVM_DEBUG(dbgs() << "selectRet\n");
1668 
1669  if (!FuncInfo.CanLowerReturn)
1670  return false;
1671 
1672  // Build a list of return value registers.
1673  SmallVector<unsigned, 4> RetRegs;
1674 
1675  if (Ret->getNumOperands() > 0) {
1677 
1678  // Do not handle FastCC.
1679  if (CC == CallingConv::Fast)
1680  return false;
1681 
1683  GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1684 
1685  // Analyze operands of the call, assigning locations to each operand.
1687  MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1688  I->getContext());
1689  CCAssignFn *RetCC = RetCC_Mips;
1690  CCInfo.AnalyzeReturn(Outs, RetCC);
1691 
1692  // Only handle a single return value for now.
1693  if (ValLocs.size() != 1)
1694  return false;
1695 
1696  CCValAssign &VA = ValLocs[0];
1697  const Value *RV = Ret->getOperand(0);
1698 
1699  // Don't bother handling odd stuff for now.
1700  if ((VA.getLocInfo() != CCValAssign::Full) &&
1701  (VA.getLocInfo() != CCValAssign::BCvt))
1702  return false;
1703 
1704  // Only handle register returns for now.
1705  if (!VA.isRegLoc())
1706  return false;
1707 
1708  unsigned Reg = getRegForValue(RV);
1709  if (Reg == 0)
1710  return false;
1711 
1712  unsigned SrcReg = Reg + VA.getValNo();
1713  unsigned DestReg = VA.getLocReg();
1714  // Avoid a cross-class copy. This is very unlikely.
1715  if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1716  return false;
1717 
1718  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1719  if (!RVEVT.isSimple())
1720  return false;
1721 
1722  if (RVEVT.isVector())
1723  return false;
1724 
1725  MVT RVVT = RVEVT.getSimpleVT();
1726  if (RVVT == MVT::f128)
1727  return false;
1728 
1729  // Do not handle FGR64 returns for now.
1730  if (RVVT == MVT::f64 && UnsupportedFPMode) {
1731  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1732  return false;
1733  }
1734 
1735  MVT DestVT = VA.getValVT();
1736  // Special handling for extended integers.
1737  if (RVVT != DestVT) {
1738  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1739  return false;
1740 
1741  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1742  bool IsZExt = Outs[0].Flags.isZExt();
1743  SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1744  if (SrcReg == 0)
1745  return false;
1746  }
1747  }
1748 
1749  // Make the copy.
1750  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1751  TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1752 
1753  // Add register to return instruction.
1754  RetRegs.push_back(VA.getLocReg());
1755  }
1756  MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1757  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1758  MIB.addReg(RetRegs[i], RegState::Implicit);
1759  return true;
1760 }
1761 
1762 bool MipsFastISel::selectTrunc(const Instruction *I) {
1763  // The high bits for a type smaller than the register size are assumed to be
1764  // undefined.
1765  Value *Op = I->getOperand(0);
1766 
1767  EVT SrcVT, DestVT;
1768  SrcVT = TLI.getValueType(DL, Op->getType(), true);
1769  DestVT = TLI.getValueType(DL, I->getType(), true);
1770 
1771  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1772  return false;
1773  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1774  return false;
1775 
1776  unsigned SrcReg = getRegForValue(Op);
1777  if (!SrcReg)
1778  return false;
1779 
1780  // Because the high bits are undefined, a truncate doesn't generate
1781  // any code.
1782  updateValueMap(I, SrcReg);
1783  return true;
1784 }
1785 
1786 bool MipsFastISel::selectIntExt(const Instruction *I) {
1787  Type *DestTy = I->getType();
1788  Value *Src = I->getOperand(0);
1789  Type *SrcTy = Src->getType();
1790 
1791  bool isZExt = isa<ZExtInst>(I);
1792  unsigned SrcReg = getRegForValue(Src);
1793  if (!SrcReg)
1794  return false;
1795 
1796  EVT SrcEVT, DestEVT;
1797  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1798  DestEVT = TLI.getValueType(DL, DestTy, true);
1799  if (!SrcEVT.isSimple())
1800  return false;
1801  if (!DestEVT.isSimple())
1802  return false;
1803 
1804  MVT SrcVT = SrcEVT.getSimpleVT();
1805  MVT DestVT = DestEVT.getSimpleVT();
1806  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1807 
1808  if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1809  return false;
1810  updateValueMap(I, ResultReg);
1811  return true;
1812 }
1813 
1814 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1815  unsigned DestReg) {
1816  unsigned ShiftAmt;
1817  switch (SrcVT.SimpleTy) {
1818  default:
1819  return false;
1820  case MVT::i8:
1821  ShiftAmt = 24;
1822  break;
1823  case MVT::i16:
1824  ShiftAmt = 16;
1825  break;
1826  }
1827  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1828  emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1829  emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1830  return true;
1831 }
1832 
1833 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1834  unsigned DestReg) {
1835  switch (SrcVT.SimpleTy) {
1836  default:
1837  return false;
1838  case MVT::i8:
1839  emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1840  break;
1841  case MVT::i16:
1842  emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1843  break;
1844  }
1845  return true;
1846 }
1847 
1848 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1849  unsigned DestReg) {
1850  if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1851  return false;
1852  if (Subtarget->hasMips32r2())
1853  return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1854  return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1855 }
1856 
1857 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1858  unsigned DestReg) {
1859  int64_t Imm;
1860 
1861  switch (SrcVT.SimpleTy) {
1862  default:
1863  return false;
1864  case MVT::i1:
1865  Imm = 1;
1866  break;
1867  case MVT::i8:
1868  Imm = 0xff;
1869  break;
1870  case MVT::i16:
1871  Imm = 0xffff;
1872  break;
1873  }
1874 
1875  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1876  return true;
1877 }
1878 
1879 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1880  unsigned DestReg, bool IsZExt) {
1881  // FastISel does not have plumbing to deal with extensions where the SrcVT or
1882  // DestVT are odd things, so test to make sure that they are both types we can
1883  // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1884  // bail out to SelectionDAG.
1885  if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1886  ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1887  return false;
1888  if (IsZExt)
1889  return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1890  return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1891 }
1892 
1893 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1894  bool isZExt) {
1895  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1896  bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1897  return Success ? DestReg : 0;
1898 }
1899 
1900 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1901  EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1902  if (!DestEVT.isSimple())
1903  return false;
1904 
1905  MVT DestVT = DestEVT.getSimpleVT();
1906  if (DestVT != MVT::i32)
1907  return false;
1908 
1909  unsigned DivOpc;
1910  switch (ISDOpcode) {
1911  default:
1912  return false;
1913  case ISD::SDIV:
1914  case ISD::SREM:
1915  DivOpc = Mips::SDIV;
1916  break;
1917  case ISD::UDIV:
1918  case ISD::UREM:
1919  DivOpc = Mips::UDIV;
1920  break;
1921  }
1922 
1923  unsigned Src0Reg = getRegForValue(I->getOperand(0));
1924  unsigned Src1Reg = getRegForValue(I->getOperand(1));
1925  if (!Src0Reg || !Src1Reg)
1926  return false;
1927 
1928  emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1929  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1930 
1931  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1932  if (!ResultReg)
1933  return false;
1934 
1935  unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1936  ? Mips::MFHI
1937  : Mips::MFLO;
1938  emitInst(MFOpc, ResultReg);
1939 
1940  updateValueMap(I, ResultReg);
1941  return true;
1942 }
1943 
1944 bool MipsFastISel::selectShift(const Instruction *I) {
1945  MVT RetVT;
1946 
1947  if (!isTypeSupported(I->getType(), RetVT))
1948  return false;
1949 
1950  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1951  if (!ResultReg)
1952  return false;
1953 
1954  unsigned Opcode = I->getOpcode();
1955  const Value *Op0 = I->getOperand(0);
1956  unsigned Op0Reg = getRegForValue(Op0);
1957  if (!Op0Reg)
1958  return false;
1959 
1960  // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1961  if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1962  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1963  if (!TempReg)
1964  return false;
1965 
1966  MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1967  bool IsZExt = Opcode == Instruction::LShr;
1968  if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1969  return false;
1970 
1971  Op0Reg = TempReg;
1972  }
1973 
1974  if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1975  uint64_t ShiftVal = C->getZExtValue();
1976 
1977  switch (Opcode) {
1978  default:
1979  llvm_unreachable("Unexpected instruction.");
1980  case Instruction::Shl:
1981  Opcode = Mips::SLL;
1982  break;
1983  case Instruction::AShr:
1984  Opcode = Mips::SRA;
1985  break;
1986  case Instruction::LShr:
1987  Opcode = Mips::SRL;
1988  break;
1989  }
1990 
1991  emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1992  updateValueMap(I, ResultReg);
1993  return true;
1994  }
1995 
1996  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1997  if (!Op1Reg)
1998  return false;
1999 
2000  switch (Opcode) {
2001  default:
2002  llvm_unreachable("Unexpected instruction.");
2003  case Instruction::Shl:
2004  Opcode = Mips::SLLV;
2005  break;
2006  case Instruction::AShr:
2007  Opcode = Mips::SRAV;
2008  break;
2009  case Instruction::LShr:
2010  Opcode = Mips::SRLV;
2011  break;
2012  }
2013 
2014  emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2015  updateValueMap(I, ResultReg);
2016  return true;
2017 }
2018 
2019 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2020  switch (I->getOpcode()) {
2021  default:
2022  break;
2023  case Instruction::Load:
2024  return selectLoad(I);
2025  case Instruction::Store:
2026  return selectStore(I);
2027  case Instruction::SDiv:
2028  if (!selectBinaryOp(I, ISD::SDIV))
2029  return selectDivRem(I, ISD::SDIV);
2030  return true;
2031  case Instruction::UDiv:
2032  if (!selectBinaryOp(I, ISD::UDIV))
2033  return selectDivRem(I, ISD::UDIV);
2034  return true;
2035  case Instruction::SRem:
2036  if (!selectBinaryOp(I, ISD::SREM))
2037  return selectDivRem(I, ISD::SREM);
2038  return true;
2039  case Instruction::URem:
2040  if (!selectBinaryOp(I, ISD::UREM))
2041  return selectDivRem(I, ISD::UREM);
2042  return true;
2043  case Instruction::Shl:
2044  case Instruction::LShr:
2045  case Instruction::AShr:
2046  return selectShift(I);
2047  case Instruction::And:
2048  case Instruction::Or:
2049  case Instruction::Xor:
2050  return selectLogicalOp(I);
2051  case Instruction::Br:
2052  return selectBranch(I);
2053  case Instruction::Ret:
2054  return selectRet(I);
2055  case Instruction::Trunc:
2056  return selectTrunc(I);
2057  case Instruction::ZExt:
2058  case Instruction::SExt:
2059  return selectIntExt(I);
2060  case Instruction::FPTrunc:
2061  return selectFPTrunc(I);
2062  case Instruction::FPExt:
2063  return selectFPExt(I);
2064  case Instruction::FPToSI:
2065  return selectFPToInt(I, /*isSigned*/ true);
2066  case Instruction::FPToUI:
2067  return selectFPToInt(I, /*isSigned*/ false);
2068  case Instruction::ICmp:
2069  case Instruction::FCmp:
2070  return selectCmp(I);
2071  case Instruction::Select:
2072  return selectSelect(I);
2073  }
2074  return false;
2075 }
2076 
2077 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2078  bool IsUnsigned) {
2079  unsigned VReg = getRegForValue(V);
2080  if (VReg == 0)
2081  return 0;
2082  MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2083 
2084  if (VMVT == MVT::i1)
2085  return 0;
2086 
2087  if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2088  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2089  if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2090  return 0;
2091  VReg = TempReg;
2092  }
2093  return VReg;
2094 }
2095 
2096 void MipsFastISel::simplifyAddress(Address &Addr) {
2097  if (!isInt<16>(Addr.getOffset())) {
2098  unsigned TempReg =
2099  materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2100  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2101  emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2102  Addr.setReg(DestReg);
2103  Addr.setOffset(0);
2104  }
2105 }
2106 
2107 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2108  const TargetRegisterClass *RC,
2109  unsigned Op0, bool Op0IsKill,
2110  unsigned Op1, bool Op1IsKill) {
2111  // We treat the MUL instruction in a special way because it clobbers
2112  // the HI0 & LO0 registers. The TableGen definition of this instruction can
2113  // mark these registers only as implicitly defined. As a result, the
2114  // register allocator runs out of registers when this instruction is
2115  // followed by another instruction that defines the same registers too.
2116  // We can fix this by explicitly marking those registers as dead.
2117  if (MachineInstOpcode == Mips::MUL) {
2118  unsigned ResultReg = createResultReg(RC);
2119  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2120  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2121  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2122  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2123  .addReg(Op0, getKillRegState(Op0IsKill))
2124  .addReg(Op1, getKillRegState(Op1IsKill))
2127  return ResultReg;
2128  }
2129 
2130  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2131  Op1IsKill);
2132 }
2133 
2134 namespace llvm {
2135 
2137  const TargetLibraryInfo *libInfo) {
2138  return new MipsFastISel(funcInfo, libInfo);
2139 }
2140 
2141 } // end namespace llvm
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:177
uint64_t CallInst * C
Return a value (possibly void), from a function.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:636
bool hasLocalLinkage() const
Definition: GlobalValue.h:436
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1563
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:24
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
bool isVector() const
Return true if this is a vector value type.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
const MipsInstrInfo * getInstrInfo() const override
const Value * getTrueValue() const
unsigned less or equal
Definition: InstrTypes.h:672
unsigned less than
Definition: InstrTypes.h:671
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:652
unsigned getValNo() const
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:705
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:662
This class wraps the llvm.memset intrinsic.
BasicBlock * getSuccessor(unsigned i) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:685
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
void reserve(size_type N)
Definition: SmallVector.h:376
Value * getLength() const
op_iterator op_begin()
Definition: User.h:230
bool isMemLoc() const
bool needsCustom() const
SI optimize exec mask operations pre RA
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:529
A description of a memory reference used in the backend.
This class represents the LLVM &#39;select&#39; instruction.
const HexagonInstrInfo * TII
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:97
Class to represent struct types.
Definition: DerivedTypes.h:201
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isUnsigned() const
Definition: InstrTypes.h:822
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:653
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getSizeInBits() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:889
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:120
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:224
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
amdgpu Simplify well known AMD library false Value * Callee
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Value * getOperand(unsigned i) const
Definition: User.h:170
unsigned getKillRegState(bool B)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:147
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV)...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:169
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:149
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
op_iterator op_end()
Definition: User.h:232
bool hasInternalLinkage() const
Definition: GlobalValue.h:434
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:160
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:115
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const Value * getCondition() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:193
Extended Value Type.
Definition: ValueTypes.h:34
size_t size() const
Definition: SmallVector.h:53
static bool isAtomic(Instruction *I)
bool isVolatile() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
signed greater than
Definition: InstrTypes.h:673
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:303
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:51
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:650
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
unsigned getNumOperands() const
Definition: User.h:192
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:213
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:675
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Definition: FastISel.cpp:2061
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:226
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:941
signed less or equal
Definition: InstrTypes.h:676
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
This file defines the FastISel class.
const MipsTargetLowering * getTargetLowering() const override
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
const Value * getFalseValue() const
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:721
unsigned getNumArgOperands() const
Definition: InstrTypes.h:1133
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:387
cl::opt< bool > EmitJalrReloc
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:551
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:652
unsigned getLocMemOffset() const
unsigned greater or equal
Definition: InstrTypes.h:670
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1181
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:107
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:346
bool isRegLoc() const
const unsigned Kind
static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:649
LLVM Value Representation.
Definition: Value.h:73
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:247
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned greater than
Definition: InstrTypes.h:669
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:47
APInt bitcastToAPInt() const
Definition: APFloat.h:1094
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
#define LLVM_DEBUG(X)
Definition: Debug.h:123
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:651
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:150
bool isFP64bit() const
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void convertToReg(unsigned RegNo)
iterator_range< arg_iterator > args()
Definition: Function.h:689
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:218
signed greater or equal
Definition: InstrTypes.h:674
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:221
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:67
an instruction to allocate memory on the stack
Definition: Instructions.h:60
Helper operand used to generate R_MIPS_JALR.
Definition: MipsBaseInfo.h:95
gep_type_iterator gep_type_begin(const User *GEP)