LLVM 19.0.0git
MipsISelLowering.cpp
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1//===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Mips uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsISelLowering.h"
18#include "MipsCCState.h"
19#include "MipsInstrInfo.h"
20#include "MipsMachineFunction.h"
21#include "MipsRegisterInfo.h"
22#include "MipsSubtarget.h"
23#include "MipsTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/Statistic.h"
29#include "llvm/ADT/StringRef.h"
51#include "llvm/IR/CallingConv.h"
52#include "llvm/IR/Constants.h"
53#include "llvm/IR/DataLayout.h"
54#include "llvm/IR/DebugLoc.h"
56#include "llvm/IR/Function.h"
57#include "llvm/IR/GlobalValue.h"
58#include "llvm/IR/Type.h"
59#include "llvm/IR/Value.h"
60#include "llvm/MC/MCContext.h"
70#include <algorithm>
71#include <cassert>
72#include <cctype>
73#include <cstdint>
74#include <deque>
75#include <iterator>
76#include <utility>
77#include <vector>
78
79using namespace llvm;
80
81#define DEBUG_TYPE "mips-lower"
82
83STATISTIC(NumTailCalls, "Number of tail calls");
84
85static cl::opt<bool>
86NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
87 cl::desc("MIPS: Don't trap on integer division by zero."),
88 cl::init(false));
89
91
92static const MCPhysReg Mips64DPRegs[8] = {
93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
95};
96
97// The MIPS MSA ABI passes vector arguments in the integer register set.
98// The number of integer registers used is dependant on the ABI used.
101 EVT VT) const {
102 if (!VT.isVector())
103 return getRegisterType(Context, VT);
104
106 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
107 : MVT::i64;
109}
110
113 EVT VT) const {
114 if (VT.isVector()) {
116 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64);
117 return VT.getVectorNumElements() *
119 }
121}
122
124 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
125 unsigned &NumIntermediates, MVT &RegisterVT) const {
126 if (VT.isPow2VectorType()) {
127 IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT);
128 RegisterVT = IntermediateVT.getSimpleVT();
129 NumIntermediates = getNumRegistersForCallingConv(Context, CC, VT);
130 return NumIntermediates;
131 }
132 IntermediateVT = VT.getVectorElementType();
133 NumIntermediates = VT.getVectorNumElements();
134 RegisterVT = getRegisterType(Context, IntermediateVT);
135 return NumIntermediates * getNumRegisters(Context, IntermediateVT);
136}
137
141 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty);
142}
143
144SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
145 SelectionDAG &DAG,
146 unsigned Flag) const {
147 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
148}
149
150SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
151 SelectionDAG &DAG,
152 unsigned Flag) const {
153 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
154}
155
156SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
157 SelectionDAG &DAG,
158 unsigned Flag) const {
159 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
160}
161
162SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
163 SelectionDAG &DAG,
164 unsigned Flag) const {
165 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
166}
167
168SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
169 SelectionDAG &DAG,
170 unsigned Flag) const {
171 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
172 N->getOffset(), Flag);
173}
174
175const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
176 switch ((MipsISD::NodeType)Opcode) {
177 case MipsISD::FIRST_NUMBER: break;
178 case MipsISD::JmpLink: return "MipsISD::JmpLink";
179 case MipsISD::TailCall: return "MipsISD::TailCall";
180 case MipsISD::Highest: return "MipsISD::Highest";
181 case MipsISD::Higher: return "MipsISD::Higher";
182 case MipsISD::Hi: return "MipsISD::Hi";
183 case MipsISD::Lo: return "MipsISD::Lo";
184 case MipsISD::GotHi: return "MipsISD::GotHi";
185 case MipsISD::TlsHi: return "MipsISD::TlsHi";
186 case MipsISD::GPRel: return "MipsISD::GPRel";
187 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
188 case MipsISD::Ret: return "MipsISD::Ret";
189 case MipsISD::ERet: return "MipsISD::ERet";
190 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
191 case MipsISD::FAbs: return "MipsISD::FAbs";
192 case MipsISD::FMS: return "MipsISD::FMS";
193 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
194 case MipsISD::FPCmp: return "MipsISD::FPCmp";
195 case MipsISD::FSELECT: return "MipsISD::FSELECT";
196 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
197 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
198 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
199 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
200 case MipsISD::MFHI: return "MipsISD::MFHI";
201 case MipsISD::MFLO: return "MipsISD::MFLO";
202 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
203 case MipsISD::Mult: return "MipsISD::Mult";
204 case MipsISD::Multu: return "MipsISD::Multu";
205 case MipsISD::MAdd: return "MipsISD::MAdd";
206 case MipsISD::MAddu: return "MipsISD::MAddu";
207 case MipsISD::MSub: return "MipsISD::MSub";
208 case MipsISD::MSubu: return "MipsISD::MSubu";
209 case MipsISD::DivRem: return "MipsISD::DivRem";
210 case MipsISD::DivRemU: return "MipsISD::DivRemU";
211 case MipsISD::DivRem16: return "MipsISD::DivRem16";
212 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
213 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
214 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
215 case MipsISD::Wrapper: return "MipsISD::Wrapper";
216 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
217 case MipsISD::Sync: return "MipsISD::Sync";
218 case MipsISD::Ext: return "MipsISD::Ext";
219 case MipsISD::Ins: return "MipsISD::Ins";
220 case MipsISD::CIns: return "MipsISD::CIns";
221 case MipsISD::LWL: return "MipsISD::LWL";
222 case MipsISD::LWR: return "MipsISD::LWR";
223 case MipsISD::SWL: return "MipsISD::SWL";
224 case MipsISD::SWR: return "MipsISD::SWR";
225 case MipsISD::LDL: return "MipsISD::LDL";
226 case MipsISD::LDR: return "MipsISD::LDR";
227 case MipsISD::SDL: return "MipsISD::SDL";
228 case MipsISD::SDR: return "MipsISD::SDR";
229 case MipsISD::EXTP: return "MipsISD::EXTP";
230 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
231 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
232 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
233 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
234 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
235 case MipsISD::SHILO: return "MipsISD::SHILO";
236 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
237 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
238 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
239 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
240 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
241 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
242 case MipsISD::DOUBLE_SELECT_I: return "MipsISD::DOUBLE_SELECT_I";
243 case MipsISD::DOUBLE_SELECT_I64: return "MipsISD::DOUBLE_SELECT_I64";
244 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
245 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
246 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
247 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
248 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
249 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
250 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
251 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
252 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
253 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
254 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
255 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
256 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
257 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
258 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
259 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
260 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
261 case MipsISD::MULT: return "MipsISD::MULT";
262 case MipsISD::MULTU: return "MipsISD::MULTU";
263 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
264 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
265 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
266 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
267 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
268 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
269 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
270 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
271 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
272 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
273 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
274 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
275 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
276 case MipsISD::VCEQ: return "MipsISD::VCEQ";
277 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
278 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
279 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
280 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
281 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
282 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
283 case MipsISD::VNOR: return "MipsISD::VNOR";
284 case MipsISD::VSHF: return "MipsISD::VSHF";
285 case MipsISD::SHF: return "MipsISD::SHF";
286 case MipsISD::ILVEV: return "MipsISD::ILVEV";
287 case MipsISD::ILVOD: return "MipsISD::ILVOD";
288 case MipsISD::ILVL: return "MipsISD::ILVL";
289 case MipsISD::ILVR: return "MipsISD::ILVR";
290 case MipsISD::PCKEV: return "MipsISD::PCKEV";
291 case MipsISD::PCKOD: return "MipsISD::PCKOD";
292 case MipsISD::INSVE: return "MipsISD::INSVE";
293 }
294 return nullptr;
295}
296
298 const MipsSubtarget &STI)
299 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
300 // Mips does not have i1 type, so use i32 for
301 // setcc operations results (slt, sgt, ...).
304 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
305 // does. Integer booleans still use 0 and 1.
309
310 // Load extented operations for i1 types must be promoted
311 for (MVT VT : MVT::integer_valuetypes()) {
315 }
316
317 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
318 // for f32, f16
319 for (MVT VT : MVT::fp_valuetypes()) {
320 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
321 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
322 }
323
324 // Set LoadExtAction for f16 vectors to Expand
326 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
327 if (F16VT.isValid())
329 }
330
331 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
332 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
333
334 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
335
336 // Used by legalize types to correctly generate the setcc result.
337 // Without this, every float setcc comes with a AND/OR with the result,
338 // we don't want this, since the fpcmp result goes to a flag register,
339 // which is used implicitly by brcond and select operations.
340 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
341
342 // Mips Custom Operations
360
361 if (Subtarget.isGP64bit()) {
374 }
375
376 if (!Subtarget.isGP64bit()) {
380 }
381
383 if (Subtarget.isGP64bit())
385
394
395 // Operations not directly supported by Mips.
409 if (Subtarget.hasCnMips()) {
412 } else {
415 }
422
423 if (!Subtarget.hasMips32r2())
425
426 if (!Subtarget.hasMips64r2())
428
445
446 // Lower f16 conversion operations into library calls
451
453
458
459 // Use the default for now
462
463 if (!Subtarget.isGP64bit()) {
466 }
467
468 if (!Subtarget.hasMips32r2()) {
471 }
472
473 // MIPS16 lacks MIPS32's clz and clo instructions.
476 if (!Subtarget.hasMips64())
478
479 if (!Subtarget.hasMips32r2())
481 if (!Subtarget.hasMips64r2())
483
484 if (Subtarget.isGP64bit()) {
485 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
486 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
487 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
488 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
489 }
490
491 setOperationAction(ISD::TRAP, MVT::Other, Legal);
492
495
496 if (ABI.IsO32()) {
497 // These libcalls are not available in 32-bit.
498 setLibcallName(RTLIB::SHL_I128, nullptr);
499 setLibcallName(RTLIB::SRL_I128, nullptr);
500 setLibcallName(RTLIB::SRA_I128, nullptr);
501 setLibcallName(RTLIB::MUL_I128, nullptr);
502 setLibcallName(RTLIB::MULO_I64, nullptr);
503 setLibcallName(RTLIB::MULO_I128, nullptr);
504 }
505
506 if (Subtarget.isGP64bit())
508 else
510
512
513 // The arguments on the stack are defined in terms of 4-byte slots on O32
514 // and 8-byte slots on N32/N64.
516 : Align(4));
517
518 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
519
521
522 isMicroMips = Subtarget.inMicroMipsMode();
523}
524
525const MipsTargetLowering *
527 const MipsSubtarget &STI) {
528 if (STI.inMips16Mode())
529 return createMips16TargetLowering(TM, STI);
530
531 return createMipsSETargetLowering(TM, STI);
532}
533
534// Create a fast isel object.
535FastISel *
537 const TargetLibraryInfo *libInfo) const {
538 const MipsTargetMachine &TM =
539 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
540
541 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
542 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
545
546 // Disable if either of the following is true:
547 // We do not generate PIC, the ABI is not O32, XGOT is being used.
548 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() ||
550 UseFastISel = false;
551
552 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
553}
554
556 EVT VT) const {
557 if (!VT.isVector())
558 return MVT::i32;
560}
561
564 const MipsSubtarget &Subtarget) {
565 if (DCI.isBeforeLegalizeOps())
566 return SDValue();
567
568 EVT Ty = N->getValueType(0);
569 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
570 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
571 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
573 SDLoc DL(N);
574
575 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
576 N->getOperand(0), N->getOperand(1));
577 SDValue InChain = DAG.getEntryNode();
578 SDValue InGlue = DivRem;
579
580 // insert MFLO
581 if (N->hasAnyUseOfValue(0)) {
582 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
583 InGlue);
584 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
585 InChain = CopyFromLo.getValue(1);
586 InGlue = CopyFromLo.getValue(2);
587 }
588
589 // insert MFHI
590 if (N->hasAnyUseOfValue(1)) {
591 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
592 HI, Ty, InGlue);
593 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
594 }
595
596 return SDValue();
597}
598
600 switch (CC) {
601 default: llvm_unreachable("Unknown fp condition code!");
602 case ISD::SETEQ:
603 case ISD::SETOEQ: return Mips::FCOND_OEQ;
604 case ISD::SETUNE: return Mips::FCOND_UNE;
605 case ISD::SETLT:
606 case ISD::SETOLT: return Mips::FCOND_OLT;
607 case ISD::SETGT:
608 case ISD::SETOGT: return Mips::FCOND_OGT;
609 case ISD::SETLE:
610 case ISD::SETOLE: return Mips::FCOND_OLE;
611 case ISD::SETGE:
612 case ISD::SETOGE: return Mips::FCOND_OGE;
613 case ISD::SETULT: return Mips::FCOND_ULT;
614 case ISD::SETULE: return Mips::FCOND_ULE;
615 case ISD::SETUGT: return Mips::FCOND_UGT;
616 case ISD::SETUGE: return Mips::FCOND_UGE;
617 case ISD::SETUO: return Mips::FCOND_UN;
618 case ISD::SETO: return Mips::FCOND_OR;
619 case ISD::SETNE:
620 case ISD::SETONE: return Mips::FCOND_ONE;
621 case ISD::SETUEQ: return Mips::FCOND_UEQ;
622 }
623}
624
625/// This function returns true if the floating point conditional branches and
626/// conditional moves which use condition code CC should be inverted.
628 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
629 return false;
630
632 "Illegal Condition Code");
633
634 return true;
635}
636
637// Creates and returns an FPCmp node from a setcc node.
638// Returns Op if setcc is not a floating point comparison.
640 // must be a SETCC node
641 if (Op.getOpcode() != ISD::SETCC)
642 return Op;
643
644 SDValue LHS = Op.getOperand(0);
645
646 if (!LHS.getValueType().isFloatingPoint())
647 return Op;
648
649 SDValue RHS = Op.getOperand(1);
650 SDLoc DL(Op);
651
652 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
653 // node if necessary.
654 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
655
656 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
657 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
658}
659
660// Creates and returns a CMovFPT/F node.
662 SDValue False, const SDLoc &DL) {
663 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
664 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
665 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
666
667 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
668 True.getValueType(), True, FCC0, False, Cond);
669}
670
673 const MipsSubtarget &Subtarget) {
674 if (DCI.isBeforeLegalizeOps())
675 return SDValue();
676
677 SDValue SetCC = N->getOperand(0);
678
679 if ((SetCC.getOpcode() != ISD::SETCC) ||
680 !SetCC.getOperand(0).getValueType().isInteger())
681 return SDValue();
682
683 SDValue False = N->getOperand(2);
684 EVT FalseTy = False.getValueType();
685
686 if (!FalseTy.isInteger())
687 return SDValue();
688
689 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
690
691 // If the RHS (False) is 0, we swap the order of the operands
692 // of ISD::SELECT (obviously also inverting the condition) so that we can
693 // take advantage of conditional moves using the $0 register.
694 // Example:
695 // return (a != 0) ? x : 0;
696 // load $reg, x
697 // movz $reg, $0, a
698 if (!FalseC)
699 return SDValue();
700
701 const SDLoc DL(N);
702
703 if (!FalseC->getZExtValue()) {
704 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
705 SDValue True = N->getOperand(1);
706
707 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
708 SetCC.getOperand(1),
710
711 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
712 }
713
714 // If both operands are integer constants there's a possibility that we
715 // can do some interesting optimizations.
716 SDValue True = N->getOperand(1);
717 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
718
719 if (!TrueC || !True.getValueType().isInteger())
720 return SDValue();
721
722 // We'll also ignore MVT::i64 operands as this optimizations proves
723 // to be ineffective because of the required sign extensions as the result
724 // of a SETCC operator is always MVT::i32 for non-vector types.
725 if (True.getValueType() == MVT::i64)
726 return SDValue();
727
728 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
729
730 // 1) (a < x) ? y : y-1
731 // slti $reg1, a, x
732 // addiu $reg2, $reg1, y-1
733 if (Diff == 1)
734 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
735
736 // 2) (a < x) ? y-1 : y
737 // slti $reg1, a, x
738 // xor $reg1, $reg1, 1
739 // addiu $reg2, $reg1, y-1
740 if (Diff == -1) {
741 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
742 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
743 SetCC.getOperand(1),
745 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
746 }
747
748 // Could not optimize.
749 return SDValue();
750}
751
754 const MipsSubtarget &Subtarget) {
755 if (DCI.isBeforeLegalizeOps())
756 return SDValue();
757
758 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
759
760 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
761 if (!FalseC || FalseC->getZExtValue())
762 return SDValue();
763
764 // Since RHS (False) is 0, we swap the order of the True/False operands
765 // (obviously also inverting the condition) so that we can
766 // take advantage of conditional moves using the $0 register.
767 // Example:
768 // return (a != 0) ? x : 0;
769 // load $reg, x
770 // movz $reg, $0, a
771 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
773
774 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
775 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
776 ValueIfFalse, FCC, ValueIfTrue, Glue);
777}
778
781 const MipsSubtarget &Subtarget) {
782 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
783 return SDValue();
784
785 SDValue FirstOperand = N->getOperand(0);
786 unsigned FirstOperandOpc = FirstOperand.getOpcode();
787 SDValue Mask = N->getOperand(1);
788 EVT ValTy = N->getValueType(0);
789 SDLoc DL(N);
790
791 uint64_t Pos = 0;
792 unsigned SMPos, SMSize;
793 ConstantSDNode *CN;
794 SDValue NewOperand;
795 unsigned Opc;
796
797 // Op's second operand must be a shifted mask.
798 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
799 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize))
800 return SDValue();
801
802 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
803 // Pattern match EXT.
804 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
805 // => ext $dst, $src, pos, size
806
807 // The second operand of the shift must be an immediate.
808 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
809 return SDValue();
810
811 Pos = CN->getZExtValue();
812
813 // Return if the shifted mask does not start at bit 0 or the sum of its size
814 // and Pos exceeds the word's size.
815 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
816 return SDValue();
817
818 Opc = MipsISD::Ext;
819 NewOperand = FirstOperand.getOperand(0);
820 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
821 // Pattern match CINS.
822 // $dst = and (shl $src , pos), mask
823 // => cins $dst, $src, pos, size
824 // mask is a shifted mask with consecutive 1's, pos = shift amount,
825 // size = population count.
826
827 // The second operand of the shift must be an immediate.
828 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
829 return SDValue();
830
831 Pos = CN->getZExtValue();
832
833 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
834 Pos + SMSize > ValTy.getSizeInBits())
835 return SDValue();
836
837 NewOperand = FirstOperand.getOperand(0);
838 // SMSize is 'location' (position) in this case, not size.
839 SMSize--;
840 Opc = MipsISD::CIns;
841 } else {
842 // Pattern match EXT.
843 // $dst = and $src, (2**size - 1) , if size > 16
844 // => ext $dst, $src, pos, size , pos = 0
845
846 // If the mask is <= 0xffff, andi can be used instead.
847 if (CN->getZExtValue() <= 0xffff)
848 return SDValue();
849
850 // Return if the mask doesn't start at position 0.
851 if (SMPos)
852 return SDValue();
853
854 Opc = MipsISD::Ext;
855 NewOperand = FirstOperand;
856 }
857 return DAG.getNode(Opc, DL, ValTy, NewOperand,
858 DAG.getConstant(Pos, DL, MVT::i32),
859 DAG.getConstant(SMSize, DL, MVT::i32));
860}
861
864 const MipsSubtarget &Subtarget) {
865 // Pattern match INS.
866 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
867 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
868 // => ins $dst, $src, size, pos, $src1
869 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
870 return SDValue();
871
872 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
873 unsigned SMPos0, SMSize0, SMPos1, SMSize1;
874 ConstantSDNode *CN, *CN1;
875
876 // See if Op's first operand matches (and $src1 , mask0).
877 if (And0.getOpcode() != ISD::AND)
878 return SDValue();
879
880 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
881 !isShiftedMask_64(~CN->getSExtValue(), SMPos0, SMSize0))
882 return SDValue();
883
884 // See if Op's second operand matches (and (shl $src, pos), mask1).
885 if (And1.getOpcode() == ISD::AND &&
886 And1.getOperand(0).getOpcode() == ISD::SHL) {
887
888 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
889 !isShiftedMask_64(CN->getZExtValue(), SMPos1, SMSize1))
890 return SDValue();
891
892 // The shift masks must have the same position and size.
893 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
894 return SDValue();
895
896 SDValue Shl = And1.getOperand(0);
897
898 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
899 return SDValue();
900
901 unsigned Shamt = CN->getZExtValue();
902
903 // Return if the shift amount and the first bit position of mask are not the
904 // same.
905 EVT ValTy = N->getValueType(0);
906 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
907 return SDValue();
908
909 SDLoc DL(N);
910 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
911 DAG.getConstant(SMPos0, DL, MVT::i32),
912 DAG.getConstant(SMSize0, DL, MVT::i32),
913 And0.getOperand(0));
914 } else {
915 // Pattern match DINS.
916 // $dst = or (and $src, mask0), mask1
917 // where mask0 = ((1 << SMSize0) -1) << SMPos0
918 // => dins $dst, $src, pos, size
919 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
920 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
921 (SMSize0 + SMPos0 <= 32))) {
922 // Check if AND instruction has constant as argument
923 bool isConstCase = And1.getOpcode() != ISD::AND;
924 if (And1.getOpcode() == ISD::AND) {
925 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
926 return SDValue();
927 } else {
928 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
929 return SDValue();
930 }
931 // Don't generate INS if constant OR operand doesn't fit into bits
932 // cleared by constant AND operand.
933 if (CN->getSExtValue() & CN1->getSExtValue())
934 return SDValue();
935
936 SDLoc DL(N);
937 EVT ValTy = N->getOperand(0)->getValueType(0);
938 SDValue Const1;
939 SDValue SrlX;
940 if (!isConstCase) {
941 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
942 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
943 }
944 return DAG.getNode(
945 MipsISD::Ins, DL, N->getValueType(0),
946 isConstCase
947 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
948 : SrlX,
949 DAG.getConstant(SMPos0, DL, MVT::i32),
950 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
951 : SMSize0,
952 DL, MVT::i32),
953 And0->getOperand(0));
954
955 }
956 return SDValue();
957 }
958}
959
961 const MipsSubtarget &Subtarget) {
962 // ROOTNode must have a multiplication as an operand for the match to be
963 // successful.
964 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
965 ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
966 return SDValue();
967
968 // In the case where we have a multiplication as the left operand of
969 // of a subtraction, we can't combine into a MipsISD::MSub node as the
970 // the instruction definition of msub(u) places the multiplication on
971 // on the right.
972 if (ROOTNode->getOpcode() == ISD::SUB &&
973 ROOTNode->getOperand(0).getOpcode() == ISD::MUL)
974 return SDValue();
975
976 // We don't handle vector types here.
977 if (ROOTNode->getValueType(0).isVector())
978 return SDValue();
979
980 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
981 // arithmetic. E.g.
982 // (add (mul a b) c) =>
983 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
984 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
985 // or
986 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
987 //
988 // The overhead of setting up the Hi/Lo registers and reassembling the
989 // result makes this a dubious optimzation for MIPS64. The core of the
990 // problem is that Hi/Lo contain the upper and lower 32 bits of the
991 // operand and result.
992 //
993 // It requires a chain of 4 add/mul for MIPS64R2 to get better code
994 // density than doing it naively, 5 for MIPS64. Additionally, using
995 // madd/msub on MIPS64 requires the operands actually be 32 bit sign
996 // extended operands, not true 64 bit values.
997 //
998 // FIXME: For the moment, disable this completely for MIPS64.
999 if (Subtarget.hasMips64())
1000 return SDValue();
1001
1002 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1003 ? ROOTNode->getOperand(0)
1004 : ROOTNode->getOperand(1);
1005
1006 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1007 ? ROOTNode->getOperand(1)
1008 : ROOTNode->getOperand(0);
1009
1010 // Transform this to a MADD only if the user of this node is the add.
1011 // If there are other users of the mul, this function returns here.
1012 if (!Mult.hasOneUse())
1013 return SDValue();
1014
1015 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1016 // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1017 // of the multiply must have 32 or more sign bits, otherwise we cannot
1018 // perform this optimization. We have to check this here as we're performing
1019 // this optimization pre-legalization.
1020 SDValue MultLHS = Mult->getOperand(0);
1021 SDValue MultRHS = Mult->getOperand(1);
1022
1023 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1024 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1025 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1026 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1027
1028 if (!IsSigned && !IsUnsigned)
1029 return SDValue();
1030
1031 // Initialize accumulator.
1032 SDLoc DL(ROOTNode);
1033 SDValue BottomHalf, TopHalf;
1034 std::tie(BottomHalf, TopHalf) =
1035 CurDAG.SplitScalar(AddOperand, DL, MVT::i32, MVT::i32);
1036 SDValue ACCIn =
1037 CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, BottomHalf, TopHalf);
1038
1039 // Create MipsMAdd(u) / MipsMSub(u) node.
1040 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1041 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1042 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1043 SDValue MAddOps[3] = {
1044 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1045 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1046 EVT VTs[2] = {MVT::i32, MVT::i32};
1047 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1048
1049 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1050 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1051 SDValue Combined =
1052 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1053 return Combined;
1054}
1055
1058 const MipsSubtarget &Subtarget) {
1059 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1060 if (DCI.isBeforeLegalizeOps()) {
1061 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1062 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1063 return performMADD_MSUBCombine(N, DAG, Subtarget);
1064
1065 return SDValue();
1066 }
1067
1068 return SDValue();
1069}
1070
1073 const MipsSubtarget &Subtarget) {
1074 // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1075 if (DCI.isBeforeLegalizeOps()) {
1076 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1077 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1078 return performMADD_MSUBCombine(N, DAG, Subtarget);
1079
1080 return SDValue();
1081 }
1082
1083 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1084 SDValue Add = N->getOperand(1);
1085
1086 if (Add.getOpcode() != ISD::ADD)
1087 return SDValue();
1088
1089 SDValue Lo = Add.getOperand(1);
1090
1091 if ((Lo.getOpcode() != MipsISD::Lo) ||
1092 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1093 return SDValue();
1094
1095 EVT ValTy = N->getValueType(0);
1096 SDLoc DL(N);
1097
1098 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1099 Add.getOperand(0));
1100 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1101}
1102
1105 const MipsSubtarget &Subtarget) {
1106 // Pattern match CINS.
1107 // $dst = shl (and $src , imm), pos
1108 // => cins $dst, $src, pos, size
1109
1110 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1111 return SDValue();
1112
1113 SDValue FirstOperand = N->getOperand(0);
1114 unsigned FirstOperandOpc = FirstOperand.getOpcode();
1115 SDValue SecondOperand = N->getOperand(1);
1116 EVT ValTy = N->getValueType(0);
1117 SDLoc DL(N);
1118
1119 uint64_t Pos = 0;
1120 unsigned SMPos, SMSize;
1121 ConstantSDNode *CN;
1122 SDValue NewOperand;
1123
1124 // The second operand of the shift must be an immediate.
1125 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1126 return SDValue();
1127
1128 Pos = CN->getZExtValue();
1129
1130 if (Pos >= ValTy.getSizeInBits())
1131 return SDValue();
1132
1133 if (FirstOperandOpc != ISD::AND)
1134 return SDValue();
1135
1136 // AND's second operand must be a shifted mask.
1137 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1138 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize))
1139 return SDValue();
1140
1141 // Return if the shifted mask does not start at bit 0 or the sum of its size
1142 // and Pos exceeds the word's size.
1143 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1144 return SDValue();
1145
1146 NewOperand = FirstOperand.getOperand(0);
1147 // SMSize is 'location' (position) in this case, not size.
1148 SMSize--;
1149
1150 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1151 DAG.getConstant(Pos, DL, MVT::i32),
1152 DAG.getConstant(SMSize, DL, MVT::i32));
1153}
1154
1156 const {
1157 SelectionDAG &DAG = DCI.DAG;
1158 unsigned Opc = N->getOpcode();
1159
1160 switch (Opc) {
1161 default: break;
1162 case ISD::SDIVREM:
1163 case ISD::UDIVREM:
1164 return performDivRemCombine(N, DAG, DCI, Subtarget);
1165 case ISD::SELECT:
1166 return performSELECTCombine(N, DAG, DCI, Subtarget);
1167 case MipsISD::CMovFP_F:
1168 case MipsISD::CMovFP_T:
1169 return performCMovFPCombine(N, DAG, DCI, Subtarget);
1170 case ISD::AND:
1171 return performANDCombine(N, DAG, DCI, Subtarget);
1172 case ISD::OR:
1173 return performORCombine(N, DAG, DCI, Subtarget);
1174 case ISD::ADD:
1175 return performADDCombine(N, DAG, DCI, Subtarget);
1176 case ISD::SHL:
1177 return performSHLCombine(N, DAG, DCI, Subtarget);
1178 case ISD::SUB:
1179 return performSUBCombine(N, DAG, DCI, Subtarget);
1180 }
1181
1182 return SDValue();
1183}
1184
1186 return Subtarget.hasMips32();
1187}
1188
1190 return Subtarget.hasMips32();
1191}
1192
1194 // We can use ANDI+SLTIU as a bit test. Y contains the bit position.
1195 // For MIPSR2 or later, we may be able to use the `ext` instruction or its'
1196 // double-word variants.
1197 if (auto *C = dyn_cast<ConstantSDNode>(Y))
1198 return C->getAPIntValue().ule(15);
1199
1200 return false;
1201}
1202
1204 const SDNode *N, CombineLevel Level) const {
1205 assert(((N->getOpcode() == ISD::SHL &&
1206 N->getOperand(0).getOpcode() == ISD::SRL) ||
1207 (N->getOpcode() == ISD::SRL &&
1208 N->getOperand(0).getOpcode() == ISD::SHL)) &&
1209 "Expected shift-shift mask");
1210
1211 if (N->getOperand(0).getValueType().isVector())
1212 return false;
1213 return true;
1214}
1215
1216void
1219 SelectionDAG &DAG) const {
1220 return LowerOperationWrapper(N, Results, DAG);
1221}
1222
1225{
1226 switch (Op.getOpcode())
1227 {
1228 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1229 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1230 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1231 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1232 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1233 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1234 case ISD::SELECT: return lowerSELECT(Op, DAG);
1235 case ISD::SETCC: return lowerSETCC(Op, DAG);
1236 case ISD::VASTART: return lowerVASTART(Op, DAG);
1237 case ISD::VAARG: return lowerVAARG(Op, DAG);
1238 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1239 case ISD::FABS: return lowerFABS(Op, DAG);
1240 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1241 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1242 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1243 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1244 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1245 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1246 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1247 case ISD::LOAD: return lowerLOAD(Op, DAG);
1248 case ISD::STORE: return lowerSTORE(Op, DAG);
1249 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1250 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1251 }
1252 return SDValue();
1253}
1254
1255//===----------------------------------------------------------------------===//
1256// Lower helper functions
1257//===----------------------------------------------------------------------===//
1258
1259// addLiveIn - This helper function adds the specified physical register to the
1260// MachineFunction as a live in value. It also creates a corresponding
1261// virtual register for it.
1262static unsigned
1263addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1264{
1266 MF.getRegInfo().addLiveIn(PReg, VReg);
1267 return VReg;
1268}
1269
1272 const TargetInstrInfo &TII,
1273 bool Is64Bit, bool IsMicroMips) {
1274 if (NoZeroDivCheck)
1275 return &MBB;
1276
1277 // Insert instruction "teq $divisor_reg, $zero, 7".
1280 MachineOperand &Divisor = MI.getOperand(2);
1281 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1282 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1283 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1284 .addReg(Mips::ZERO)
1285 .addImm(7);
1286
1287 // Use the 32-bit sub-register if this is a 64-bit division.
1288 if (Is64Bit)
1289 MIB->getOperand(0).setSubReg(Mips::sub_32);
1290
1291 // Clear Divisor's kill flag.
1292 Divisor.setIsKill(false);
1293
1294 // We would normally delete the original instruction here but in this case
1295 // we only needed to inject an additional instruction rather than replace it.
1296
1297 return &MBB;
1298}
1299
1302 MachineBasicBlock *BB) const {
1303 switch (MI.getOpcode()) {
1304 default:
1305 llvm_unreachable("Unexpected instr type to insert");
1306 case Mips::ATOMIC_LOAD_ADD_I8:
1307 return emitAtomicBinaryPartword(MI, BB, 1);
1308 case Mips::ATOMIC_LOAD_ADD_I16:
1309 return emitAtomicBinaryPartword(MI, BB, 2);
1310 case Mips::ATOMIC_LOAD_ADD_I32:
1311 return emitAtomicBinary(MI, BB);
1312 case Mips::ATOMIC_LOAD_ADD_I64:
1313 return emitAtomicBinary(MI, BB);
1314
1315 case Mips::ATOMIC_LOAD_AND_I8:
1316 return emitAtomicBinaryPartword(MI, BB, 1);
1317 case Mips::ATOMIC_LOAD_AND_I16:
1318 return emitAtomicBinaryPartword(MI, BB, 2);
1319 case Mips::ATOMIC_LOAD_AND_I32:
1320 return emitAtomicBinary(MI, BB);
1321 case Mips::ATOMIC_LOAD_AND_I64:
1322 return emitAtomicBinary(MI, BB);
1323
1324 case Mips::ATOMIC_LOAD_OR_I8:
1325 return emitAtomicBinaryPartword(MI, BB, 1);
1326 case Mips::ATOMIC_LOAD_OR_I16:
1327 return emitAtomicBinaryPartword(MI, BB, 2);
1328 case Mips::ATOMIC_LOAD_OR_I32:
1329 return emitAtomicBinary(MI, BB);
1330 case Mips::ATOMIC_LOAD_OR_I64:
1331 return emitAtomicBinary(MI, BB);
1332
1333 case Mips::ATOMIC_LOAD_XOR_I8:
1334 return emitAtomicBinaryPartword(MI, BB, 1);
1335 case Mips::ATOMIC_LOAD_XOR_I16:
1336 return emitAtomicBinaryPartword(MI, BB, 2);
1337 case Mips::ATOMIC_LOAD_XOR_I32:
1338 return emitAtomicBinary(MI, BB);
1339 case Mips::ATOMIC_LOAD_XOR_I64:
1340 return emitAtomicBinary(MI, BB);
1341
1342 case Mips::ATOMIC_LOAD_NAND_I8:
1343 return emitAtomicBinaryPartword(MI, BB, 1);
1344 case Mips::ATOMIC_LOAD_NAND_I16:
1345 return emitAtomicBinaryPartword(MI, BB, 2);
1346 case Mips::ATOMIC_LOAD_NAND_I32:
1347 return emitAtomicBinary(MI, BB);
1348 case Mips::ATOMIC_LOAD_NAND_I64:
1349 return emitAtomicBinary(MI, BB);
1350
1351 case Mips::ATOMIC_LOAD_SUB_I8:
1352 return emitAtomicBinaryPartword(MI, BB, 1);
1353 case Mips::ATOMIC_LOAD_SUB_I16:
1354 return emitAtomicBinaryPartword(MI, BB, 2);
1355 case Mips::ATOMIC_LOAD_SUB_I32:
1356 return emitAtomicBinary(MI, BB);
1357 case Mips::ATOMIC_LOAD_SUB_I64:
1358 return emitAtomicBinary(MI, BB);
1359
1360 case Mips::ATOMIC_SWAP_I8:
1361 return emitAtomicBinaryPartword(MI, BB, 1);
1362 case Mips::ATOMIC_SWAP_I16:
1363 return emitAtomicBinaryPartword(MI, BB, 2);
1364 case Mips::ATOMIC_SWAP_I32:
1365 return emitAtomicBinary(MI, BB);
1366 case Mips::ATOMIC_SWAP_I64:
1367 return emitAtomicBinary(MI, BB);
1368
1369 case Mips::ATOMIC_CMP_SWAP_I8:
1370 return emitAtomicCmpSwapPartword(MI, BB, 1);
1371 case Mips::ATOMIC_CMP_SWAP_I16:
1372 return emitAtomicCmpSwapPartword(MI, BB, 2);
1373 case Mips::ATOMIC_CMP_SWAP_I32:
1374 return emitAtomicCmpSwap(MI, BB);
1375 case Mips::ATOMIC_CMP_SWAP_I64:
1376 return emitAtomicCmpSwap(MI, BB);
1377
1378 case Mips::ATOMIC_LOAD_MIN_I8:
1379 return emitAtomicBinaryPartword(MI, BB, 1);
1380 case Mips::ATOMIC_LOAD_MIN_I16:
1381 return emitAtomicBinaryPartword(MI, BB, 2);
1382 case Mips::ATOMIC_LOAD_MIN_I32:
1383 return emitAtomicBinary(MI, BB);
1384 case Mips::ATOMIC_LOAD_MIN_I64:
1385 return emitAtomicBinary(MI, BB);
1386
1387 case Mips::ATOMIC_LOAD_MAX_I8:
1388 return emitAtomicBinaryPartword(MI, BB, 1);
1389 case Mips::ATOMIC_LOAD_MAX_I16:
1390 return emitAtomicBinaryPartword(MI, BB, 2);
1391 case Mips::ATOMIC_LOAD_MAX_I32:
1392 return emitAtomicBinary(MI, BB);
1393 case Mips::ATOMIC_LOAD_MAX_I64:
1394 return emitAtomicBinary(MI, BB);
1395
1396 case Mips::ATOMIC_LOAD_UMIN_I8:
1397 return emitAtomicBinaryPartword(MI, BB, 1);
1398 case Mips::ATOMIC_LOAD_UMIN_I16:
1399 return emitAtomicBinaryPartword(MI, BB, 2);
1400 case Mips::ATOMIC_LOAD_UMIN_I32:
1401 return emitAtomicBinary(MI, BB);
1402 case Mips::ATOMIC_LOAD_UMIN_I64:
1403 return emitAtomicBinary(MI, BB);
1404
1405 case Mips::ATOMIC_LOAD_UMAX_I8:
1406 return emitAtomicBinaryPartword(MI, BB, 1);
1407 case Mips::ATOMIC_LOAD_UMAX_I16:
1408 return emitAtomicBinaryPartword(MI, BB, 2);
1409 case Mips::ATOMIC_LOAD_UMAX_I32:
1410 return emitAtomicBinary(MI, BB);
1411 case Mips::ATOMIC_LOAD_UMAX_I64:
1412 return emitAtomicBinary(MI, BB);
1413
1414 case Mips::PseudoSDIV:
1415 case Mips::PseudoUDIV:
1416 case Mips::DIV:
1417 case Mips::DIVU:
1418 case Mips::MOD:
1419 case Mips::MODU:
1420 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1421 false);
1422 case Mips::SDIV_MM_Pseudo:
1423 case Mips::UDIV_MM_Pseudo:
1424 case Mips::SDIV_MM:
1425 case Mips::UDIV_MM:
1426 case Mips::DIV_MMR6:
1427 case Mips::DIVU_MMR6:
1428 case Mips::MOD_MMR6:
1429 case Mips::MODU_MMR6:
1430 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1431 case Mips::PseudoDSDIV:
1432 case Mips::PseudoDUDIV:
1433 case Mips::DDIV:
1434 case Mips::DDIVU:
1435 case Mips::DMOD:
1436 case Mips::DMODU:
1437 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1438
1439 case Mips::PseudoSELECT_I:
1440 case Mips::PseudoSELECT_I64:
1441 case Mips::PseudoSELECT_S:
1442 case Mips::PseudoSELECT_D32:
1443 case Mips::PseudoSELECT_D64:
1444 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1445 case Mips::PseudoSELECTFP_F_I:
1446 case Mips::PseudoSELECTFP_F_I64:
1447 case Mips::PseudoSELECTFP_F_S:
1448 case Mips::PseudoSELECTFP_F_D32:
1449 case Mips::PseudoSELECTFP_F_D64:
1450 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1451 case Mips::PseudoSELECTFP_T_I:
1452 case Mips::PseudoSELECTFP_T_I64:
1453 case Mips::PseudoSELECTFP_T_S:
1454 case Mips::PseudoSELECTFP_T_D32:
1455 case Mips::PseudoSELECTFP_T_D64:
1456 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1457 case Mips::PseudoD_SELECT_I:
1458 case Mips::PseudoD_SELECT_I64:
1459 return emitPseudoD_SELECT(MI, BB);
1460 case Mips::LDR_W:
1461 return emitLDR_W(MI, BB);
1462 case Mips::LDR_D:
1463 return emitLDR_D(MI, BB);
1464 case Mips::STR_W:
1465 return emitSTR_W(MI, BB);
1466 case Mips::STR_D:
1467 return emitSTR_D(MI, BB);
1468 }
1469}
1470
1471// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1472// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1474MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1475 MachineBasicBlock *BB) const {
1476
1477 MachineFunction *MF = BB->getParent();
1478 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1480 DebugLoc DL = MI.getDebugLoc();
1481
1482 unsigned AtomicOp;
1483 bool NeedsAdditionalReg = false;
1484 switch (MI.getOpcode()) {
1485 case Mips::ATOMIC_LOAD_ADD_I32:
1486 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1487 break;
1488 case Mips::ATOMIC_LOAD_SUB_I32:
1489 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1490 break;
1491 case Mips::ATOMIC_LOAD_AND_I32:
1492 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1493 break;
1494 case Mips::ATOMIC_LOAD_OR_I32:
1495 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1496 break;
1497 case Mips::ATOMIC_LOAD_XOR_I32:
1498 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1499 break;
1500 case Mips::ATOMIC_LOAD_NAND_I32:
1501 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1502 break;
1503 case Mips::ATOMIC_SWAP_I32:
1504 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1505 break;
1506 case Mips::ATOMIC_LOAD_ADD_I64:
1507 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1508 break;
1509 case Mips::ATOMIC_LOAD_SUB_I64:
1510 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1511 break;
1512 case Mips::ATOMIC_LOAD_AND_I64:
1513 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1514 break;
1515 case Mips::ATOMIC_LOAD_OR_I64:
1516 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1517 break;
1518 case Mips::ATOMIC_LOAD_XOR_I64:
1519 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1520 break;
1521 case Mips::ATOMIC_LOAD_NAND_I64:
1522 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1523 break;
1524 case Mips::ATOMIC_SWAP_I64:
1525 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1526 break;
1527 case Mips::ATOMIC_LOAD_MIN_I32:
1528 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1529 NeedsAdditionalReg = true;
1530 break;
1531 case Mips::ATOMIC_LOAD_MAX_I32:
1532 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1533 NeedsAdditionalReg = true;
1534 break;
1535 case Mips::ATOMIC_LOAD_UMIN_I32:
1536 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1537 NeedsAdditionalReg = true;
1538 break;
1539 case Mips::ATOMIC_LOAD_UMAX_I32:
1540 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1541 NeedsAdditionalReg = true;
1542 break;
1543 case Mips::ATOMIC_LOAD_MIN_I64:
1544 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1545 NeedsAdditionalReg = true;
1546 break;
1547 case Mips::ATOMIC_LOAD_MAX_I64:
1548 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1549 NeedsAdditionalReg = true;
1550 break;
1551 case Mips::ATOMIC_LOAD_UMIN_I64:
1552 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1553 NeedsAdditionalReg = true;
1554 break;
1555 case Mips::ATOMIC_LOAD_UMAX_I64:
1556 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1557 NeedsAdditionalReg = true;
1558 break;
1559 default:
1560 llvm_unreachable("Unknown pseudo atomic for replacement!");
1561 }
1562
1563 Register OldVal = MI.getOperand(0).getReg();
1564 Register Ptr = MI.getOperand(1).getReg();
1565 Register Incr = MI.getOperand(2).getReg();
1566 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1567
1569
1570 // The scratch registers here with the EarlyClobber | Define | Implicit
1571 // flags is used to persuade the register allocator and the machine
1572 // verifier to accept the usage of this register. This has to be a real
1573 // register which has an UNDEF value but is dead after the instruction which
1574 // is unique among the registers chosen for the instruction.
1575
1576 // The EarlyClobber flag has the semantic properties that the operand it is
1577 // attached to is clobbered before the rest of the inputs are read. Hence it
1578 // must be unique among the operands to the instruction.
1579 // The Define flag is needed to coerce the machine verifier that an Undef
1580 // value isn't a problem.
1581 // The Dead flag is needed as the value in scratch isn't used by any other
1582 // instruction. Kill isn't used as Dead is more precise.
1583 // The implicit flag is here due to the interaction between the other flags
1584 // and the machine verifier.
1585
1586 // For correctness purpose, a new pseudo is introduced here. We need this
1587 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1588 // that is spread over >1 basic blocks. A register allocator which
1589 // introduces (or any codegen infact) a store, can violate the expectations
1590 // of the hardware.
1591 //
1592 // An atomic read-modify-write sequence starts with a linked load
1593 // instruction and ends with a store conditional instruction. The atomic
1594 // read-modify-write sequence fails if any of the following conditions
1595 // occur between the execution of ll and sc:
1596 // * A coherent store is completed by another process or coherent I/O
1597 // module into the block of synchronizable physical memory containing
1598 // the word. The size and alignment of the block is
1599 // implementation-dependent.
1600 // * A coherent store is executed between an LL and SC sequence on the
1601 // same processor to the block of synchornizable physical memory
1602 // containing the word.
1603 //
1604
1605 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1606 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1607
1608 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1609 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1610
1612 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1614 .addReg(PtrCopy)
1615 .addReg(IncrCopy)
1618 if (NeedsAdditionalReg) {
1619 Register Scratch2 =
1620 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1623 }
1624
1625 MI.eraseFromParent();
1626
1627 return BB;
1628}
1629
1630MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1631 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1632 unsigned SrcReg) const {
1634 const DebugLoc &DL = MI.getDebugLoc();
1635
1636 if (Subtarget.hasMips32r2() && Size == 1) {
1637 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1638 return BB;
1639 }
1640
1641 if (Subtarget.hasMips32r2() && Size == 2) {
1642 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1643 return BB;
1644 }
1645
1646 MachineFunction *MF = BB->getParent();
1648 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1649 Register ScrReg = RegInfo.createVirtualRegister(RC);
1650
1651 assert(Size < 32);
1652 int64_t ShiftImm = 32 - (Size * 8);
1653
1654 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1655 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1656
1657 return BB;
1658}
1659
1660MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1661 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1662 assert((Size == 1 || Size == 2) &&
1663 "Unsupported size for EmitAtomicBinaryPartial.");
1664
1665 MachineFunction *MF = BB->getParent();
1667 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1668 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1669 const TargetRegisterClass *RCp =
1670 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1672 DebugLoc DL = MI.getDebugLoc();
1673
1674 Register Dest = MI.getOperand(0).getReg();
1675 Register Ptr = MI.getOperand(1).getReg();
1676 Register Incr = MI.getOperand(2).getReg();
1677
1678 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1679 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1680 Register Mask = RegInfo.createVirtualRegister(RC);
1681 Register Mask2 = RegInfo.createVirtualRegister(RC);
1682 Register Incr2 = RegInfo.createVirtualRegister(RC);
1683 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1684 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1685 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1686 Register Scratch = RegInfo.createVirtualRegister(RC);
1687 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1688 Register Scratch3 = RegInfo.createVirtualRegister(RC);
1689
1690 unsigned AtomicOp = 0;
1691 bool NeedsAdditionalReg = false;
1692 switch (MI.getOpcode()) {
1693 case Mips::ATOMIC_LOAD_NAND_I8:
1694 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1695 break;
1696 case Mips::ATOMIC_LOAD_NAND_I16:
1697 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1698 break;
1699 case Mips::ATOMIC_SWAP_I8:
1700 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1701 break;
1702 case Mips::ATOMIC_SWAP_I16:
1703 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1704 break;
1705 case Mips::ATOMIC_LOAD_ADD_I8:
1706 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1707 break;
1708 case Mips::ATOMIC_LOAD_ADD_I16:
1709 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1710 break;
1711 case Mips::ATOMIC_LOAD_SUB_I8:
1712 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1713 break;
1714 case Mips::ATOMIC_LOAD_SUB_I16:
1715 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1716 break;
1717 case Mips::ATOMIC_LOAD_AND_I8:
1718 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1719 break;
1720 case Mips::ATOMIC_LOAD_AND_I16:
1721 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1722 break;
1723 case Mips::ATOMIC_LOAD_OR_I8:
1724 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1725 break;
1726 case Mips::ATOMIC_LOAD_OR_I16:
1727 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1728 break;
1729 case Mips::ATOMIC_LOAD_XOR_I8:
1730 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1731 break;
1732 case Mips::ATOMIC_LOAD_XOR_I16:
1733 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1734 break;
1735 case Mips::ATOMIC_LOAD_MIN_I8:
1736 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1737 NeedsAdditionalReg = true;
1738 break;
1739 case Mips::ATOMIC_LOAD_MIN_I16:
1740 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1741 NeedsAdditionalReg = true;
1742 break;
1743 case Mips::ATOMIC_LOAD_MAX_I8:
1744 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1745 NeedsAdditionalReg = true;
1746 break;
1747 case Mips::ATOMIC_LOAD_MAX_I16:
1748 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1749 NeedsAdditionalReg = true;
1750 break;
1751 case Mips::ATOMIC_LOAD_UMIN_I8:
1752 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1753 NeedsAdditionalReg = true;
1754 break;
1755 case Mips::ATOMIC_LOAD_UMIN_I16:
1756 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1757 NeedsAdditionalReg = true;
1758 break;
1759 case Mips::ATOMIC_LOAD_UMAX_I8:
1760 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1761 NeedsAdditionalReg = true;
1762 break;
1763 case Mips::ATOMIC_LOAD_UMAX_I16:
1764 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1765 NeedsAdditionalReg = true;
1766 break;
1767 default:
1768 llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1769 }
1770
1771 // insert new blocks after the current block
1772 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1773 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1775 MF->insert(It, exitMBB);
1776
1777 // Transfer the remainder of BB and its successor edges to exitMBB.
1778 exitMBB->splice(exitMBB->begin(), BB,
1779 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1781
1783
1784 // thisMBB:
1785 // addiu masklsb2,$0,-4 # 0xfffffffc
1786 // and alignedaddr,ptr,masklsb2
1787 // andi ptrlsb2,ptr,3
1788 // sll shiftamt,ptrlsb2,3
1789 // ori maskupper,$0,255 # 0xff
1790 // sll mask,maskupper,shiftamt
1791 // nor mask2,$0,mask
1792 // sll incr2,incr,shiftamt
1793
1794 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1795 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1796 .addReg(ABI.GetNullPtr()).addImm(-4);
1797 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1798 .addReg(Ptr).addReg(MaskLSB2);
1799 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1800 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1801 if (Subtarget.isLittle()) {
1802 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1803 } else {
1804 Register Off = RegInfo.createVirtualRegister(RC);
1805 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1806 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1807 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1808 }
1809 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1810 .addReg(Mips::ZERO).addImm(MaskImm);
1811 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1812 .addReg(MaskUpper).addReg(ShiftAmt);
1813 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1814 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1815
1816
1817 // The purposes of the flags on the scratch registers is explained in
1818 // emitAtomicBinary. In summary, we need a scratch register which is going to
1819 // be undef, that is unique among registers chosen for the instruction.
1820
1822 BuildMI(BB, DL, TII->get(AtomicOp))
1824 .addReg(AlignedAddr)
1825 .addReg(Incr2)
1826 .addReg(Mask)
1827 .addReg(Mask2)
1828 .addReg(ShiftAmt)
1835 if (NeedsAdditionalReg) {
1836 Register Scratch4 = RegInfo.createVirtualRegister(RC);
1839 }
1840
1841 MI.eraseFromParent(); // The instruction is gone now.
1842
1843 return exitMBB;
1844}
1845
1846// Lower atomic compare and swap to a pseudo instruction, taking care to
1847// define a scratch register for the pseudo instruction's expansion. The
1848// instruction is expanded after the register allocator as to prevent
1849// the insertion of stores between the linked load and the store conditional.
1850
1852MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1853 MachineBasicBlock *BB) const {
1854
1855 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1856 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1857 "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1858
1859 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1860
1861 MachineFunction *MF = BB->getParent();
1865 DebugLoc DL = MI.getDebugLoc();
1866
1867 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1868 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1869 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1870 Register Dest = MI.getOperand(0).getReg();
1871 Register Ptr = MI.getOperand(1).getReg();
1872 Register OldVal = MI.getOperand(2).getReg();
1873 Register NewVal = MI.getOperand(3).getReg();
1874
1875 Register Scratch = MRI.createVirtualRegister(RC);
1877
1878 // We need to create copies of the various registers and kill them at the
1879 // atomic pseudo. If the copies are not made, when the atomic is expanded
1880 // after fast register allocation, the spills will end up outside of the
1881 // blocks that their values are defined in, causing livein errors.
1882
1883 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1884 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1885 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1886
1887 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1888 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1889 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1890
1891 // The purposes of the flags on the scratch registers is explained in
1892 // emitAtomicBinary. In summary, we need a scratch register which is going to
1893 // be undef, that is unique among registers chosen for the instruction.
1894
1895 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1897 .addReg(PtrCopy, RegState::Kill)
1898 .addReg(OldValCopy, RegState::Kill)
1899 .addReg(NewValCopy, RegState::Kill)
1902
1903 MI.eraseFromParent(); // The instruction is gone now.
1904
1905 return BB;
1906}
1907
1908MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1909 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1910 assert((Size == 1 || Size == 2) &&
1911 "Unsupported size for EmitAtomicCmpSwapPartial.");
1912
1913 MachineFunction *MF = BB->getParent();
1915 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1916 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1917 const TargetRegisterClass *RCp =
1918 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1920 DebugLoc DL = MI.getDebugLoc();
1921
1922 Register Dest = MI.getOperand(0).getReg();
1923 Register Ptr = MI.getOperand(1).getReg();
1924 Register CmpVal = MI.getOperand(2).getReg();
1925 Register NewVal = MI.getOperand(3).getReg();
1926
1927 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1928 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1929 Register Mask = RegInfo.createVirtualRegister(RC);
1930 Register Mask2 = RegInfo.createVirtualRegister(RC);
1931 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1932 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1933 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1934 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1935 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1936 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1937 Register MaskedNewVal = RegInfo.createVirtualRegister(RC);
1938 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1939 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1940 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1941
1942 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
1943 // flags are used to coerce the register allocator and the machine verifier to
1944 // accept the usage of these registers.
1945 // The EarlyClobber flag has the semantic properties that the operand it is
1946 // attached to is clobbered before the rest of the inputs are read. Hence it
1947 // must be unique among the operands to the instruction.
1948 // The Define flag is needed to coerce the machine verifier that an Undef
1949 // value isn't a problem.
1950 // The Dead flag is needed as the value in scratch isn't used by any other
1951 // instruction. Kill isn't used as Dead is more precise.
1952 Register Scratch = RegInfo.createVirtualRegister(RC);
1953 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1954
1955 // insert new blocks after the current block
1956 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1957 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1959 MF->insert(It, exitMBB);
1960
1961 // Transfer the remainder of BB and its successor edges to exitMBB.
1962 exitMBB->splice(exitMBB->begin(), BB,
1963 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1965
1967
1968 // thisMBB:
1969 // addiu masklsb2,$0,-4 # 0xfffffffc
1970 // and alignedaddr,ptr,masklsb2
1971 // andi ptrlsb2,ptr,3
1972 // xori ptrlsb2,ptrlsb2,3 # Only for BE
1973 // sll shiftamt,ptrlsb2,3
1974 // ori maskupper,$0,255 # 0xff
1975 // sll mask,maskupper,shiftamt
1976 // nor mask2,$0,mask
1977 // andi maskedcmpval,cmpval,255
1978 // sll shiftedcmpval,maskedcmpval,shiftamt
1979 // andi maskednewval,newval,255
1980 // sll shiftednewval,maskednewval,shiftamt
1981 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1982 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1983 .addReg(ABI.GetNullPtr()).addImm(-4);
1984 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1985 .addReg(Ptr).addReg(MaskLSB2);
1986 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1987 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1988 if (Subtarget.isLittle()) {
1989 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1990 } else {
1991 Register Off = RegInfo.createVirtualRegister(RC);
1992 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1993 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1994 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1995 }
1996 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1997 .addReg(Mips::ZERO).addImm(MaskImm);
1998 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1999 .addReg(MaskUpper).addReg(ShiftAmt);
2000 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
2001 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
2002 .addReg(CmpVal).addImm(MaskImm);
2003 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
2004 .addReg(MaskedCmpVal).addReg(ShiftAmt);
2005 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
2006 .addReg(NewVal).addImm(MaskImm);
2007 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
2008 .addReg(MaskedNewVal).addReg(ShiftAmt);
2009
2010 // The purposes of the flags on the scratch registers are explained in
2011 // emitAtomicBinary. In summary, we need a scratch register which is going to
2012 // be undef, that is unique among the register chosen for the instruction.
2013
2014 BuildMI(BB, DL, TII->get(AtomicOp))
2016 .addReg(AlignedAddr)
2017 .addReg(Mask)
2018 .addReg(ShiftedCmpVal)
2019 .addReg(Mask2)
2020 .addReg(ShiftedNewVal)
2021 .addReg(ShiftAmt)
2026
2027 MI.eraseFromParent(); // The instruction is gone now.
2028
2029 return exitMBB;
2030}
2031
2032SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2033 // The first operand is the chain, the second is the condition, the third is
2034 // the block to branch to if the condition is true.
2035 SDValue Chain = Op.getOperand(0);
2036 SDValue Dest = Op.getOperand(2);
2037 SDLoc DL(Op);
2038
2040 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
2041
2042 // Return if flag is not set by a floating point comparison.
2043 if (CondRes.getOpcode() != MipsISD::FPCmp)
2044 return Op;
2045
2046 SDValue CCNode = CondRes.getOperand(2);
2049 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
2050 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
2051 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
2052 FCC0, Dest, CondRes);
2053}
2054
2055SDValue MipsTargetLowering::
2056lowerSELECT(SDValue Op, SelectionDAG &DAG) const
2057{
2059 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
2060
2061 // Return if flag is not set by a floating point comparison.
2062 if (Cond.getOpcode() != MipsISD::FPCmp)
2063 return Op;
2064
2065 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
2066 SDLoc(Op));
2067}
2068
2069SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2071 SDValue Cond = createFPCmp(DAG, Op);
2072
2073 assert(Cond.getOpcode() == MipsISD::FPCmp &&
2074 "Floating point operand expected.");
2075
2076 SDLoc DL(Op);
2077 SDValue True = DAG.getConstant(1, DL, MVT::i32);
2078 SDValue False = DAG.getConstant(0, DL, MVT::i32);
2079
2080 return createCMovFP(DAG, Cond, True, False, DL);
2081}
2082
2083SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2084 SelectionDAG &DAG) const {
2085 EVT Ty = Op.getValueType();
2086 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2087 const GlobalValue *GV = N->getGlobal();
2088
2089 if (!isPositionIndependent()) {
2090 const MipsTargetObjectFile *TLOF =
2091 static_cast<const MipsTargetObjectFile *>(
2093 const GlobalObject *GO = GV->getAliaseeObject();
2094 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2095 // %gp_rel relocation
2096 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2097
2098 // %hi/%lo relocation
2099 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2100 // %highest/%higher/%hi/%lo relocation
2101 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2102 }
2103
2104 // Every other architecture would use shouldAssumeDSOLocal in here, but
2105 // mips is special.
2106 // * In PIC code mips requires got loads even for local statics!
2107 // * To save on got entries, for local statics the got entry contains the
2108 // page and an additional add instruction takes care of the low bits.
2109 // * It is legal to access a hidden symbol with a non hidden undefined,
2110 // so one cannot guarantee that all access to a hidden symbol will know
2111 // it is hidden.
2112 // * Mips linkers don't support creating a page and a full got entry for
2113 // the same symbol.
2114 // * Given all that, we have to use a full got entry for hidden symbols :-(
2115 if (GV->hasLocalLinkage())
2116 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2117
2118 if (Subtarget.useXGOT())
2119 return getAddrGlobalLargeGOT(
2121 DAG.getEntryNode(),
2122 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2123
2124 return getAddrGlobal(
2125 N, SDLoc(N), Ty, DAG,
2127 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2128}
2129
2130SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2131 SelectionDAG &DAG) const {
2132 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2133 EVT Ty = Op.getValueType();
2134
2135 if (!isPositionIndependent())
2136 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2137 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2138
2139 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2140}
2141
2142SDValue MipsTargetLowering::
2143lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2144{
2145 // If the relocation model is PIC, use the General Dynamic TLS Model or
2146 // Local Dynamic TLS model, otherwise use the Initial Exec or
2147 // Local Exec TLS Model.
2148
2149 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2150 if (DAG.getTarget().useEmulatedTLS())
2151 return LowerToTLSEmulatedModel(GA, DAG);
2152
2153 SDLoc DL(GA);
2154 const GlobalValue *GV = GA->getGlobal();
2155 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2156
2158
2159 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2160 // General Dynamic and Local Dynamic TLS Model.
2161 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2163
2164 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2166 getGlobalReg(DAG, PtrVT), TGA);
2167 unsigned PtrSize = PtrVT.getSizeInBits();
2168 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2169
2170 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2171
2173 ArgListEntry Entry;
2174 Entry.Node = Argument;
2175 Entry.Ty = PtrTy;
2176 Args.push_back(Entry);
2177
2179 CLI.setDebugLoc(DL)
2180 .setChain(DAG.getEntryNode())
2181 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2182 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2183
2184 SDValue Ret = CallResult.first;
2185
2186 if (model != TLSModel::LocalDynamic)
2187 return Ret;
2188
2189 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2191 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2192 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2194 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2195 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2196 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2197 }
2198
2200 if (model == TLSModel::InitialExec) {
2201 // Initial Exec TLS Model
2202 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2204 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2205 TGA);
2206 Offset =
2207 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2208 } else {
2209 // Local Exec TLS Model
2210 assert(model == TLSModel::LocalExec);
2211 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2213 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2215 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2216 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2217 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2218 }
2219
2221 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2222}
2223
2224SDValue MipsTargetLowering::
2225lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2226{
2227 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2228 EVT Ty = Op.getValueType();
2229
2230 if (!isPositionIndependent())
2231 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2232 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2233
2234 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2235}
2236
2237SDValue MipsTargetLowering::
2238lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2239{
2240 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2241 EVT Ty = Op.getValueType();
2242
2243 if (!isPositionIndependent()) {
2244 const MipsTargetObjectFile *TLOF =
2245 static_cast<const MipsTargetObjectFile *>(
2247
2248 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2250 // %gp_rel relocation
2251 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2252
2253 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2254 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2255 }
2256
2257 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2258}
2259
2260SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2262 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2263
2264 SDLoc DL(Op);
2265 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2267
2268 // vastart just stores the address of the VarArgsFrameIndex slot into the
2269 // memory location argument.
2270 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2271 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2272 MachinePointerInfo(SV));
2273}
2274
2275SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2276 SDNode *Node = Op.getNode();
2277 EVT VT = Node->getValueType(0);
2278 SDValue Chain = Node->getOperand(0);
2279 SDValue VAListPtr = Node->getOperand(1);
2280 const Align Align =
2281 llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne();
2282 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2283 SDLoc DL(Node);
2284 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2285
2286 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2287 VAListPtr, MachinePointerInfo(SV));
2288 SDValue VAList = VAListLoad;
2289
2290 // Re-align the pointer if necessary.
2291 // It should only ever be necessary for 64-bit types on O32 since the minimum
2292 // argument alignment is the same as the maximum type alignment for N32/N64.
2293 //
2294 // FIXME: We currently align too often. The code generator doesn't notice
2295 // when the pointer is still aligned from the last va_arg (or pair of
2296 // va_args for the i64 on O32 case).
2298 VAList = DAG.getNode(
2299 ISD::ADD, DL, VAList.getValueType(), VAList,
2300 DAG.getConstant(Align.value() - 1, DL, VAList.getValueType()));
2301
2302 VAList = DAG.getNode(
2303 ISD::AND, DL, VAList.getValueType(), VAList,
2304 DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType()));
2305 }
2306
2307 // Increment the pointer, VAList, to the next vaarg.
2308 auto &TD = DAG.getDataLayout();
2309 unsigned ArgSizeInBytes =
2311 SDValue Tmp3 =
2312 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2313 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2314 DL, VAList.getValueType()));
2315 // Store the incremented VAList to the legalized pointer
2316 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2317 MachinePointerInfo(SV));
2318
2319 // In big-endian mode we must adjust the pointer when the load size is smaller
2320 // than the argument slot size. We must also reduce the known alignment to
2321 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2322 // the correct half of the slot, and reduce the alignment from 8 (slot
2323 // alignment) down to 4 (type alignment).
2324 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2325 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2326 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2327 DAG.getIntPtrConstant(Adjustment, DL));
2328 }
2329 // Load the actual argument out of the pointer VAList
2330 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2331}
2332
2334 bool HasExtractInsert) {
2335 EVT TyX = Op.getOperand(0).getValueType();
2336 EVT TyY = Op.getOperand(1).getValueType();
2337 SDLoc DL(Op);
2338 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2339 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2340 SDValue Res;
2341
2342 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2343 // to i32.
2344 SDValue X = (TyX == MVT::f32) ?
2345 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2346 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2347 Const1);
2348 SDValue Y = (TyY == MVT::f32) ?
2349 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2350 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2351 Const1);
2352
2353 if (HasExtractInsert) {
2354 // ext E, Y, 31, 1 ; extract bit31 of Y
2355 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2356 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2357 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2358 } else {
2359 // sll SllX, X, 1
2360 // srl SrlX, SllX, 1
2361 // srl SrlY, Y, 31
2362 // sll SllY, SrlX, 31
2363 // or Or, SrlX, SllY
2364 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2365 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2366 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2367 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2368 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2369 }
2370
2371 if (TyX == MVT::f32)
2372 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2373
2374 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2375 Op.getOperand(0),
2376 DAG.getConstant(0, DL, MVT::i32));
2377 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2378}
2379
2381 bool HasExtractInsert) {
2382 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2383 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2384 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2385 SDLoc DL(Op);
2386 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2387
2388 // Bitcast to integer nodes.
2389 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2390 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2391
2392 if (HasExtractInsert) {
2393 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2394 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2395 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2396 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2397
2398 if (WidthX > WidthY)
2399 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2400 else if (WidthY > WidthX)
2401 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2402
2403 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2404 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2405 X);
2406 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2407 }
2408
2409 // (d)sll SllX, X, 1
2410 // (d)srl SrlX, SllX, 1
2411 // (d)srl SrlY, Y, width(Y)-1
2412 // (d)sll SllY, SrlX, width(Y)-1
2413 // or Or, SrlX, SllY
2414 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2415 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2416 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2417 DAG.getConstant(WidthY - 1, DL, MVT::i32));
2418
2419 if (WidthX > WidthY)
2420 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2421 else if (WidthY > WidthX)
2422 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2423
2424 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2425 DAG.getConstant(WidthX - 1, DL, MVT::i32));
2426 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2427 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2428}
2429
2430SDValue
2431MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2432 if (Subtarget.isGP64bit())
2434
2436}
2437
2438SDValue MipsTargetLowering::lowerFABS32(SDValue Op, SelectionDAG &DAG,
2439 bool HasExtractInsert) const {
2440 SDLoc DL(Op);
2441 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2442
2444 return DAG.getNode(MipsISD::FAbs, DL, Op.getValueType(), Op.getOperand(0));
2445
2446 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2447 // to i32.
2448 SDValue X = (Op.getValueType() == MVT::f32)
2449 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))
2450 : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2451 Op.getOperand(0), Const1);
2452
2453 // Clear MSB.
2454 if (HasExtractInsert)
2455 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2456 DAG.getRegister(Mips::ZERO, MVT::i32),
2457 DAG.getConstant(31, DL, MVT::i32), Const1, X);
2458 else {
2459 // TODO: Provide DAG patterns which transform (and x, cst)
2460 // back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2461 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2462 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2463 }
2464
2465 if (Op.getValueType() == MVT::f32)
2466 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2467
2468 // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2469 // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2470 // should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2471 // place.
2472 SDValue LowX =
2473 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2474 DAG.getConstant(0, DL, MVT::i32));
2475 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2476}
2477
2478SDValue MipsTargetLowering::lowerFABS64(SDValue Op, SelectionDAG &DAG,
2479 bool HasExtractInsert) const {
2480 SDLoc DL(Op);
2481 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2482
2484 return DAG.getNode(MipsISD::FAbs, DL, Op.getValueType(), Op.getOperand(0));
2485
2486 // Bitcast to integer node.
2487 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2488
2489 // Clear MSB.
2490 if (HasExtractInsert)
2491 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2492 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2493 DAG.getConstant(63, DL, MVT::i32), Const1, X);
2494 else {
2495 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2496 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2497 }
2498
2499 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2500}
2501
2502SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2503 if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64))
2504 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
2505
2506 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
2507}
2508
2509SDValue MipsTargetLowering::
2510lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2511 // check the depth
2512 if (Op.getConstantOperandVal(0) != 0) {
2513 DAG.getContext()->emitError(
2514 "return address can be determined only for current frame");
2515 return SDValue();
2516 }
2517
2519 MFI.setFrameAddressIsTaken(true);
2520 EVT VT = Op.getValueType();
2521 SDLoc DL(Op);
2522 SDValue FrameAddr = DAG.getCopyFromReg(
2523 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2524 return FrameAddr;
2525}
2526
2527SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2528 SelectionDAG &DAG) const {
2530 return SDValue();
2531
2532 // check the depth
2533 if (Op.getConstantOperandVal(0) != 0) {
2534 DAG.getContext()->emitError(
2535 "return address can be determined only for current frame");
2536 return SDValue();
2537 }
2538
2540 MachineFrameInfo &MFI = MF.getFrameInfo();
2541 MVT VT = Op.getSimpleValueType();
2542 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2543 MFI.setReturnAddressIsTaken(true);
2544
2545 // Return RA, which contains the return address. Mark it an implicit live-in.
2547 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2548}
2549
2550// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2551// generated from __builtin_eh_return (offset, handler)
2552// The effect of this is to adjust the stack pointer by "offset"
2553// and then branch to "handler".
2554SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2555 const {
2558
2559 MipsFI->setCallsEhReturn();
2560 SDValue Chain = Op.getOperand(0);
2561 SDValue Offset = Op.getOperand(1);
2562 SDValue Handler = Op.getOperand(2);
2563 SDLoc DL(Op);
2564 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2565
2566 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2567 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2568 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2569 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2570 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2571 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2572 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2573 DAG.getRegister(OffsetReg, Ty),
2574 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2575 Chain.getValue(1));
2576}
2577
2578SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2579 SelectionDAG &DAG) const {
2580 // FIXME: Need pseudo-fence for 'singlethread' fences
2581 // FIXME: Set SType for weaker fences where supported/appropriate.
2582 unsigned SType = 0;
2583 SDLoc DL(Op);
2584 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2585 DAG.getConstant(SType, DL, MVT::i32));
2586}
2587
2588SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2589 SelectionDAG &DAG) const {
2590 SDLoc DL(Op);
2591 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2592
2593 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2594 SDValue Shamt = Op.getOperand(2);
2595 // if shamt < (VT.bits):
2596 // lo = (shl lo, shamt)
2597 // hi = (or (shl hi, shamt) (srl (srl lo, 1), (xor shamt, (VT.bits-1))))
2598 // else:
2599 // lo = 0
2600 // hi = (shl lo, shamt[4:0])
2601 SDValue Not =
2602 DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2603 DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32));
2604 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2605 DAG.getConstant(1, DL, VT));
2606 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2607 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2608 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2609 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2610 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2611 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2612 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2613 DAG.getConstant(0, DL, VT), ShiftLeftLo);
2614 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2615
2616 SDValue Ops[2] = {Lo, Hi};
2617 return DAG.getMergeValues(Ops, DL);
2618}
2619
2620SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2621 bool IsSRA) const {
2622 SDLoc DL(Op);
2623 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2624 SDValue Shamt = Op.getOperand(2);
2625 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2626
2627 // if shamt < (VT.bits):
2628 // lo = (or (shl (shl hi, 1), (xor shamt, (VT.bits-1))) (srl lo, shamt))
2629 // if isSRA:
2630 // hi = (sra hi, shamt)
2631 // else:
2632 // hi = (srl hi, shamt)
2633 // else:
2634 // if isSRA:
2635 // lo = (sra hi, shamt[4:0])
2636 // hi = (sra hi, 31)
2637 // else:
2638 // lo = (srl hi, shamt[4:0])
2639 // hi = 0
2640 SDValue Not =
2641 DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2642 DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32));
2643 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2644 DAG.getConstant(1, DL, VT));
2645 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2646 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2647 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2648 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2649 DL, VT, Hi, Shamt);
2650 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2651 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2652 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2653 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2654
2655 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
2656 SDVTList VTList = DAG.getVTList(VT, VT);
2659 DL, VTList, Cond, ShiftRightHi,
2660 IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or,
2661 ShiftRightHi);
2662 }
2663
2664 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2665 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2666 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2667
2668 SDValue Ops[2] = {Lo, Hi};
2669 return DAG.getMergeValues(Ops, DL);
2670}
2671
2672static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2673 SDValue Chain, SDValue Src, unsigned Offset) {
2674 SDValue Ptr = LD->getBasePtr();
2675 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2676 EVT BasePtrVT = Ptr.getValueType();
2677 SDLoc DL(LD);
2678 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2679
2680 if (Offset)
2681 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2682 DAG.getConstant(Offset, DL, BasePtrVT));
2683
2684 SDValue Ops[] = { Chain, Ptr, Src };
2685 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2686 LD->getMemOperand());
2687}
2688
2689// Expand an unaligned 32 or 64-bit integer load node.
2691 LoadSDNode *LD = cast<LoadSDNode>(Op);
2692 EVT MemVT = LD->getMemoryVT();
2693
2695 return Op;
2696
2697 // Return if load is aligned or if MemVT is neither i32 nor i64.
2698 if ((LD->getAlign().value() >= (MemVT.getSizeInBits() / 8)) ||
2699 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2700 return SDValue();
2701
2702 bool IsLittle = Subtarget.isLittle();
2703 EVT VT = Op.getValueType();
2704 ISD::LoadExtType ExtType = LD->getExtensionType();
2705 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2706
2707 assert((VT == MVT::i32) || (VT == MVT::i64));
2708
2709 // Expand
2710 // (set dst, (i64 (load baseptr)))
2711 // to
2712 // (set tmp, (ldl (add baseptr, 7), undef))
2713 // (set dst, (ldr baseptr, tmp))
2714 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2715 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2716 IsLittle ? 7 : 0);
2717 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2718 IsLittle ? 0 : 7);
2719 }
2720
2721 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2722 IsLittle ? 3 : 0);
2723 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2724 IsLittle ? 0 : 3);
2725
2726 // Expand
2727 // (set dst, (i32 (load baseptr))) or
2728 // (set dst, (i64 (sextload baseptr))) or
2729 // (set dst, (i64 (extload baseptr)))
2730 // to
2731 // (set tmp, (lwl (add baseptr, 3), undef))
2732 // (set dst, (lwr baseptr, tmp))
2733 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2734 (ExtType == ISD::EXTLOAD))
2735 return LWR;
2736
2737 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2738
2739 // Expand
2740 // (set dst, (i64 (zextload baseptr)))
2741 // to
2742 // (set tmp0, (lwl (add baseptr, 3), undef))
2743 // (set tmp1, (lwr baseptr, tmp0))
2744 // (set tmp2, (shl tmp1, 32))
2745 // (set dst, (srl tmp2, 32))
2746 SDLoc DL(LD);
2747 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2748 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2749 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2750 SDValue Ops[] = { SRL, LWR.getValue(1) };
2751 return DAG.getMergeValues(Ops, DL);
2752}
2753
2754static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2755 SDValue Chain, unsigned Offset) {
2756 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2757 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2758 SDLoc DL(SD);
2759 SDVTList VTList = DAG.getVTList(MVT::Other);
2760
2761 if (Offset)
2762 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2763 DAG.getConstant(Offset, DL, BasePtrVT));
2764
2765 SDValue Ops[] = { Chain, Value, Ptr };
2766 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2767 SD->getMemOperand());
2768}
2769
2770// Expand an unaligned 32 or 64-bit integer store node.
2772 bool IsLittle) {
2773 SDValue Value = SD->getValue(), Chain = SD->getChain();
2774 EVT VT = Value.getValueType();
2775
2776 // Expand
2777 // (store val, baseptr) or
2778 // (truncstore val, baseptr)
2779 // to
2780 // (swl val, (add baseptr, 3))
2781 // (swr val, baseptr)
2782 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2783 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2784 IsLittle ? 3 : 0);
2785 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2786 }
2787
2788 assert(VT == MVT::i64);
2789
2790 // Expand
2791 // (store val, baseptr)
2792 // to
2793 // (sdl val, (add baseptr, 7))
2794 // (sdr val, baseptr)
2795 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2796 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2797}
2798
2799// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2801 bool SingleFloat) {
2802 SDValue Val = SD->getValue();
2803
2804 if (Val.getOpcode() != ISD::FP_TO_SINT ||
2805 (Val.getValueSizeInBits() > 32 && SingleFloat))
2806 return SDValue();
2807
2809 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2810 Val.getOperand(0));
2811 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2812 SD->getPointerInfo(), SD->getAlign(),
2813 SD->getMemOperand()->getFlags());
2814}
2815
2817 StoreSDNode *SD = cast<StoreSDNode>(Op);
2818 EVT MemVT = SD->getMemoryVT();
2819
2820 // Lower unaligned integer stores.
2822 (SD->getAlign().value() < (MemVT.getSizeInBits() / 8)) &&
2823 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2824 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2825
2827}
2828
2829SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2830 SelectionDAG &DAG) const {
2831
2832 // Return a fixed StackObject with offset 0 which points to the old stack
2833 // pointer.
2835 EVT ValTy = Op->getValueType(0);
2836 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2837 return DAG.getFrameIndex(FI, ValTy);
2838}
2839
2840SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2841 SelectionDAG &DAG) const {
2842 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat())
2843 return SDValue();
2844
2845 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2846 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2847 Op.getOperand(0));
2848 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2849}
2850
2851//===----------------------------------------------------------------------===//
2852// Calling Convention Implementation
2853//===----------------------------------------------------------------------===//
2854
2855//===----------------------------------------------------------------------===//
2856// TODO: Implement a generic logic using tblgen that can support this.
2857// Mips O32 ABI rules:
2858// ---
2859// i32 - Passed in A0, A1, A2, A3 and stack
2860// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2861// an argument. Otherwise, passed in A1, A2, A3 and stack.
2862// f64 - Only passed in two aliased f32 registers if no int reg has been used
2863// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2864// not used, it must be shadowed. If only A3 is available, shadow it and
2865// go to stack.
2866// vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2867// vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2868// with the remainder spilled to the stack.
2869// vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2870// spilling the remainder to the stack.
2871//
2872// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2873//===----------------------------------------------------------------------===//
2874
2875static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2876 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2877 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2878 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2880
2881 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2882
2883 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2884
2885 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2886
2887 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2888
2889 // Do not process byval args here.
2890 if (ArgFlags.isByVal())
2891 return true;
2892
2893 // Promote i8 and i16
2894 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2895 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2896 LocVT = MVT::i32;
2897 if (ArgFlags.isSExt())
2898 LocInfo = CCValAssign::SExtUpper;
2899 else if (ArgFlags.isZExt())
2900 LocInfo = CCValAssign::ZExtUpper;
2901 else
2902 LocInfo = CCValAssign::AExtUpper;
2903 }
2904 }
2905
2906 // Promote i8 and i16
2907 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2908 LocVT = MVT::i32;
2909 if (ArgFlags.isSExt())
2910 LocInfo = CCValAssign::SExt;
2911 else if (ArgFlags.isZExt())
2912 LocInfo = CCValAssign::ZExt;
2913 else
2914 LocInfo = CCValAssign::AExt;
2915 }
2916
2917 unsigned Reg;
2918
2919 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2920 // is true: function is vararg, argument is 3rd or higher, there is previous
2921 // argument which is not f32 or f64.
2922 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2923 State.getFirstUnallocated(F32Regs) != ValNo;
2924 Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
2925 bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8));
2926 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2927
2928 // The MIPS vector ABI for floats passes them in a pair of registers
2929 if (ValVT == MVT::i32 && isVectorFloat) {
2930 // This is the start of an vector that was scalarized into an unknown number
2931 // of components. It doesn't matter how many there are. Allocate one of the
2932 // notional 8 byte aligned registers which map onto the argument stack, and
2933 // shadow the register lost to alignment requirements.
2934 if (ArgFlags.isSplit()) {
2935 Reg = State.AllocateReg(FloatVectorIntRegs);
2936 if (Reg == Mips::A2)
2937 State.AllocateReg(Mips::A1);
2938 else if (Reg == 0)
2939 State.AllocateReg(Mips::A3);
2940 } else {
2941 // If we're an intermediate component of the split, we can just attempt to
2942 // allocate a register directly.
2943 Reg = State.AllocateReg(IntRegs);
2944 }
2945 } else if (ValVT == MVT::i32 ||
2946 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2947 Reg = State.AllocateReg(IntRegs);
2948 // If this is the first part of an i64 arg,
2949 // the allocated register must be either A0 or A2.
2950 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2951 Reg = State.AllocateReg(IntRegs);
2952 LocVT = MVT::i32;
2953 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2954 // Allocate int register and shadow next int register. If first
2955 // available register is Mips::A1 or Mips::A3, shadow it too.
2956 Reg = State.AllocateReg(IntRegs);
2957 if (Reg == Mips::A1 || Reg == Mips::A3)
2958 Reg = State.AllocateReg(IntRegs);
2959
2960 if (Reg) {
2961 LocVT = MVT::i32;
2962
2963 State.addLoc(
2964 CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2965 MCRegister HiReg = State.AllocateReg(IntRegs);
2966 assert(HiReg);
2967 State.addLoc(
2968 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo));
2969 return false;
2970 }
2971 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2972 // we are guaranteed to find an available float register
2973 if (ValVT == MVT::f32) {
2974 Reg = State.AllocateReg(F32Regs);
2975 // Shadow int register
2976 State.AllocateReg(IntRegs);
2977 } else {
2978 Reg = State.AllocateReg(F64Regs);
2979 // Shadow int registers
2980 unsigned Reg2 = State.AllocateReg(IntRegs);
2981 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2982 State.AllocateReg(IntRegs);
2983 State.AllocateReg(IntRegs);
2984 }
2985 } else
2986 llvm_unreachable("Cannot handle this ValVT.");
2987
2988 if (!Reg) {
2989 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2990 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2991 } else
2992 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2993
2994 return false;
2995}
2996
2997static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2998 MVT LocVT, CCValAssign::LocInfo LocInfo,
2999 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3000 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
3001
3002 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3003}
3004
3005static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
3006 MVT LocVT, CCValAssign::LocInfo LocInfo,
3007 ISD::ArgFlagsTy ArgFlags, CCState &State) {
3008 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3009
3010 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3011}
3012
3013static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
3014 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
3016
3017#include "MipsGenCallingConv.inc"
3018
3020 return CC_Mips_FixedArg;
3021 }
3022
3024 return RetCC_Mips;
3025 }
3026//===----------------------------------------------------------------------===//
3027// Call Calling Convention Implementation
3028//===----------------------------------------------------------------------===//
3029
3030SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3031 SDValue Chain, SDValue Arg,
3032 const SDLoc &DL, bool IsTailCall,
3033 SelectionDAG &DAG) const {
3034 if (!IsTailCall) {
3035 SDValue PtrOff =
3036 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
3038 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
3039 }
3040
3042 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
3043 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3044 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(),
3046}
3047
3050 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3051 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
3052 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
3053 SDValue Chain) const {
3054 // Insert node "GP copy globalreg" before call to function.
3055 //
3056 // R_MIPS_CALL* operators (emitted when non-internal functions are called
3057 // in PIC mode) allow symbols to be resolved via lazy binding.
3058 // The lazy binding stub requires GP to point to the GOT.
3059 // Note that we don't need GP to point to the GOT for indirect calls
3060 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
3061 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
3062 // used for the function (that is, Mips linker doesn't generate lazy binding
3063 // stub for a function whose address is taken in the program).
3064 if (IsPICCall && !InternalLinkage && IsCallReloc) {
3065 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
3066 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
3067 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
3068 }
3069
3070 // Build a sequence of copy-to-reg nodes chained together with token
3071 // chain and flag operands which copy the outgoing args into registers.
3072 // The InGlue in necessary since all emitted instructions must be
3073 // stuck together.
3074 SDValue InGlue;
3075
3076 for (auto &R : RegsToPass) {
3077 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InGlue);
3078 InGlue = Chain.getValue(1);
3079 }
3080
3081 // Add argument registers to the end of the list so that they are
3082 // known live into the call.
3083 for (auto &R : RegsToPass)
3084 Ops.push_back(CLI.DAG.getRegister(R.first, R.second.getValueType()));
3085
3086 // Add a register mask operand representing the call-preserved registers.
3088 const uint32_t *Mask =
3089 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
3090 assert(Mask && "Missing call preserved mask for calling convention");
3092 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
3093 StringRef Sym = G->getGlobal()->getName();
3094 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3095 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
3097 }
3098 }
3099 }
3100 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
3101
3102 if (InGlue.getNode())
3103 Ops.push_back(InGlue);
3104}
3105
3107 SDNode *Node) const {
3108 switch (MI.getOpcode()) {
3109 default:
3110 return;
3111 case Mips::JALR:
3112 case Mips::JALRPseudo:
3113 case Mips::JALR64:
3114 case Mips::JALR64Pseudo:
3115 case Mips::JALR16_MM:
3116 case Mips::JALRC16_MMR6:
3117 case Mips::TAILCALLREG:
3118 case Mips::TAILCALLREG64:
3119 case Mips::TAILCALLR6REG:
3120 case Mips::TAILCALL64R6REG:
3121 case Mips::TAILCALLREG_MM:
3122 case Mips::TAILCALLREG_MMR6: {
3123 if (!EmitJalrReloc ||
3126 Node->getNumOperands() < 1 ||
3127 Node->getOperand(0).getNumOperands() < 2) {
3128 return;
3129 }
3130 // We are after the callee address, set by LowerCall().
3131 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
3132 // symbol.
3133 const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
3134 StringRef Sym;
3135 if (const GlobalAddressSDNode *G =
3136 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3137 // We must not emit the R_MIPS_JALR relocation against data symbols
3138 // since this will cause run-time crashes if the linker replaces the
3139 // call instruction with a relative branch to the data symbol.
3140 if (!isa<Function>(G->getGlobal())) {
3141 LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol "
3142 << G->getGlobal()->getName() << "\n");
3143 return;
3144 }
3145 Sym = G->getGlobal()->getName();
3146 }
3147 else if (const ExternalSymbolSDNode *ES =
3148 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3149 Sym = ES->getSymbol();
3150 }
3151
3152 if (Sym.empty())
3153 return;
3154
3155 MachineFunction *MF = MI.getParent()->getParent();
3157 LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n");
3159 }
3160 }
3161}
3162
3163/// LowerCall - functions arguments are copied from virtual regs to
3164/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3165SDValue
3166MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3167 SmallVectorImpl<SDValue> &InVals) const {
3168 SelectionDAG &DAG = CLI.DAG;
3169 SDLoc DL = CLI.DL;
3171 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3173 SDValue Chain = CLI.Chain;
3174 SDValue Callee = CLI.Callee;
3175 bool &IsTailCall = CLI.IsTailCall;
3176 CallingConv::ID CallConv = CLI.CallConv;
3177 bool IsVarArg = CLI.IsVarArg;
3178
3180 MachineFrameInfo &MFI = MF.getFrameInfo();
3182 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
3183 bool IsPIC = isPositionIndependent();
3184
3185 // Analyze operands of the call, assigning locations to each operand.
3187 MipsCCState CCInfo(
3188 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3190
3191 const ExternalSymbolSDNode *ES =
3192 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3193
3194 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
3195 // is during the lowering of a call with a byval argument which produces
3196 // a call to memcpy. For the O32 case, this causes the caller to allocate
3197 // stack space for the reserved argument area for the callee, then recursively
3198 // again for the memcpy call. In the NEWABI case, this doesn't occur as those
3199 // ABIs mandate that the callee allocates the reserved argument area. We do
3200 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
3201 //
3202 // If the callee has a byval argument and memcpy is used, we are mandated
3203 // to already have produced a reserved argument area for the callee for O32.
3204 // Therefore, the reserved argument area can be reused for both calls.
3205 //
3206 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
3207 // present, as we have yet to hook that node onto the chain.
3208 //
3209 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
3210 // case. GCC does a similar trick, in that wherever possible, it calculates
3211 // the maximum out going argument area (including the reserved area), and
3212 // preallocates the stack space on entrance to the caller.
3213 //
3214 // FIXME: We should do the same for efficiency and space.
3215
3216 // Note: The check on the calling convention below must match
3217 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
3218 bool MemcpyInByVal = ES &&
3219 StringRef(ES->getSymbol()) == StringRef("memcpy") &&
3220 CallConv != CallingConv::Fast &&
3221 Chain.getOpcode() == ISD::CALLSEQ_START;
3222
3223 // Allocate the reserved argument area. It seems strange to do this from the
3224 // caller side but removing it breaks the frame size calculation.
3225 unsigned ReservedArgArea =
3226 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
3227 CCInfo.AllocateStack(ReservedArgArea, Align(1));
3228
3229 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3230 ES ? ES->getSymbol() : nullptr);
3231
3232 // Get a count of how many bytes are to be pushed on the stack.
3233 unsigned StackSize = CCInfo.getStackSize();
3234
3235 // Call site info for function parameters tracking.
3237
3238 // Check if it's really possible to do a tail call. Restrict it to functions
3239 // that are part of this compilation unit.
3240 bool InternalLinkage = false;
3241 if (IsTailCall) {
3242 IsTailCall = isEligibleForTailCallOptimization(
3243 CCInfo, StackSize, *MF.getInfo<MipsFunctionInfo>());
3244 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3245 InternalLinkage = G->getGlobal()->hasInternalLinkage();
3246 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3247 G->getGlobal()->hasPrivateLinkage() ||
3248 G->getGlobal()->hasHiddenVisibility() ||
3249 G->getGlobal()->hasProtectedVisibility());
3250 }
3251 }
3252 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall())
3253 report_fatal_error("failed to perform tail call elimination on a call "
3254 "site marked musttail");
3255
3256 if (IsTailCall)
3257 ++NumTailCalls;
3258
3259 // Chain is the output chain of the last Load/Store or CopyToReg node.
3260 // ByValChain is the output chain of the last Memcpy node created for copying
3261 // byval arguments to the stack.
3262 unsigned StackAlignment = TFL->getStackAlignment();
3263 StackSize = alignTo(StackSize, StackAlignment);
3264
3265 if (!(IsTailCall || MemcpyInByVal))
3266 Chain = DAG.getCALLSEQ_START(Chain, StackSize, 0, DL);
3267
3269 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3271
3272 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3273 SmallVector<SDValue, 8> MemOpChains;
3274
3275 CCInfo.rewindByValRegsInfo();
3276
3277 // Walk the register/memloc assignments, inserting copies/loads.
3278 for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3279 SDValue Arg = OutVals[OutIdx];
3280 CCValAssign &VA = ArgLocs[i];
3281 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3282 ISD::ArgFlagsTy Flags = Outs[OutIdx].Flags;
3283 bool UseUpperBits = false;
3284
3285 // ByVal Arg.
3286 if (Flags.isByVal()) {
3287 unsigned FirstByValReg, LastByValReg;
3288 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3289 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3290
3291 assert(Flags.getByValSize() &&
3292 "ByVal args of size 0 should have been ignored by front-end.");
3293 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3294 assert(!IsTailCall &&
3295 "Do not tail-call optimize if there is a byval argument.");
3296 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3297 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3298 VA);
3299 CCInfo.nextInRegsParam();
3300 continue;
3301 }
3302
3303 // Promote the value if needed.
3304 switch (VA.getLocInfo()) {
3305 default:
3306 llvm_unreachable("Unknown loc info!");
3307 case CCValAssign::Full:
3308 if (VA.isRegLoc()) {
3309 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3310 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3311 (ValVT == MVT::i64 && LocVT == MVT::f64))
3312 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3313 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3315 Arg, DAG.getConstant(0, DL, MVT::i32));
3317 Arg, DAG.getConstant(1, DL, MVT::i32));
3318 if (!Subtarget.isLittle())
3319 std::swap(Lo, Hi);
3320
3321 assert(VA.needsCustom());
3322
3323 Register LocRegLo = VA.getLocReg();
3324 Register LocRegHigh = ArgLocs[++i].getLocReg();
3325 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3326 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3327 continue;
3328 }
3329 }
3330 break;
3331 case CCValAssign::BCvt:
3332 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3333 break;
3335 UseUpperBits = true;
3336 [[fallthrough]];
3337 case CCValAssign::SExt:
3338 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3339 break;
3341 UseUpperBits = true;
3342 [[fallthrough]];
3343 case CCValAssign::ZExt:
3344 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3345 break;
3347 UseUpperBits = true;
3348 [[fallthrough]];
3349 case CCValAssign::AExt:
3350 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3351 break;
3352 }
3353
3354 if (UseUpperBits) {
3355 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3356 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3357 Arg = DAG.getNode(
3358 ISD::SHL, DL, VA.getLocVT(), Arg,
3359 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3360 }
3361
3362 // Arguments that can be passed on register must be kept at
3363 // RegsToPass vector
3364 if (VA.isRegLoc()) {
3365 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3366
3367 // If the parameter is passed through reg $D, which splits into
3368 // two physical registers, avoid creating call site info.
3369 if (Mips::AFGR64RegClass.contains(VA.getLocReg()))
3370 continue;
3371
3372 // Collect CSInfo about which register passes which parameter.
3373 const TargetOptions &Options = DAG.getTarget().Options;
3374 if (Options.SupportsDebugEntryValues)
3375 CSInfo.emplace_back(VA.getLocReg(), i);
3376
3377 continue;
3378 }
3379
3380 // Register can't get to this point...
3381 assert(VA.isMemLoc());
3382
3383 // emit ISD::STORE whichs stores the
3384 // parameter value to a stack Location
3385 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3386 Chain, Arg, DL, IsTailCall, DAG));
3387 }
3388
3389 // Transform all store nodes into one single node because all store
3390 // nodes are independent of each other.
3391 if (!MemOpChains.empty())
3392 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3393
3394 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3395 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3396 // node so that legalize doesn't hack it.
3397
3398 EVT Ty = Callee.getValueType();
3399 bool GlobalOrExternal = false, IsCallReloc = false;
3400
3401 // The long-calls feature is ignored in case of PIC.
3402 // While we do not support -mshared / -mno-shared properly,
3403 // ignore long-calls in case of -mabicalls too.
3404 if (!Subtarget.isABICalls() && !IsPIC) {
3405 // If the function should be called using "long call",
3406 // get its address into a register to prevent using
3407 // of the `jal` instruction for the direct call.
3408 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3409 if (Subtarget.useLongCalls())
3411 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3412 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3413 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3414 bool UseLongCalls = Subtarget.useLongCalls();
3415 // If the function has long-call/far/near attribute
3416 // it overrides command line switch pased to the backend.
3417 if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3418 if (F->hasFnAttribute("long-call"))
3419 UseLongCalls = true;
3420 else if (F->hasFnAttribute("short-call"))
3421 UseLongCalls = false;
3422 }
3423 if (UseLongCalls)
3425 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3426 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3427 }
3428 }
3429
3430 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3431 if (IsPIC) {
3432 const GlobalValue *Val = G->getGlobal();
3433 InternalLinkage = Val->hasInternalLinkage();
3434
3435 if (InternalLinkage)
3436 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3437 else if (Subtarget.useXGOT()) {
3439 MipsII::MO_CALL_LO16, Chain,
3440 FuncInfo->callPtrInfo(MF, Val));
3441 IsCallReloc = true;
3442 } else {
3443 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3444 FuncInfo->callPtrInfo(MF, Val));
3445 IsCallReloc = true;
3446 }
3447 } else
3448 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3449 getPointerTy(DAG.getDataLayout()), 0,
3451 GlobalOrExternal = true;
3452 }
3453 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3454 const char *Sym = S->getSymbol();
3455
3456 if (!IsPIC) // static
3459 else if (Subtarget.useXGOT()) {
3461 MipsII::MO_CALL_LO16, Chain,
3462 FuncInfo->callPtrInfo(MF, Sym));
3463 IsCallReloc = true;
3464 } else { // PIC
3465 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3466 FuncInfo->callPtrInfo(MF, Sym));
3467 IsCallReloc = true;
3468 }
3469
3470 GlobalOrExternal = true;
3471 }
3472
3473 SmallVector<SDValue, 8> Ops(1, Chain);
3474 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3475
3476 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3477 IsCallReloc, CLI, Callee, Chain);
3478
3479 if (IsTailCall) {
3481 SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3482 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
3483 return Ret;
3484 }
3485
3486 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3487 SDValue InGlue = Chain.getValue(1);
3488
3489 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
3490
3491 // Create the CALLSEQ_END node in the case of where it is not a call to
3492 // memcpy.
3493 if (!(MemcpyInByVal)) {
3494 Chain = DAG.getCALLSEQ_END(Chain, StackSize, 0, InGlue, DL);
3495 InGlue = Chain.getValue(1);
3496 }
3497
3498 // Handle result values, copying them out of physregs into vregs that we
3499 // return.
3500 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG,
3501 InVals, CLI);
3502}
3503
3504/// LowerCallResult - Lower the result values of a call into the
3505/// appropriate copies out of appropriate physical registers.
3506SDValue MipsTargetLowering::LowerCallResult(
3507 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool IsVarArg,
3508 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3511 // Assign locations to each value returned by this call.
3513 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3514 *DAG.getContext());
3515
3516 const ExternalSymbolSDNode *ES =
3517 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3518 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3519 ES ? ES->getSymbol() : nullptr);
3520
3521 // Copy all of the result registers out of their specified physreg.
3522 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3523 CCValAssign &VA = RVLocs[i];
3524 assert(VA.isRegLoc() && "Can only return in registers!");
3525
3526 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3527 RVLocs[i].getLocVT(), InGlue);
3528 Chain = Val.getValue(1);
3529 InGlue = Val.getValue(2);
3530
3531 if (VA.isUpperBitsInLoc()) {
3532 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3533 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3534 unsigned Shift =
3536 Val = DAG.getNode(
3537 Shift, DL, VA.getLocVT(), Val,
3538 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3539 }
3540
3541 switch (VA.getLocInfo()) {
3542 default:
3543 llvm_unreachable("Unknown loc info!");
3544 case CCValAssign::Full:
3545 break;
3546 case CCValAssign::BCvt:
3547 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3548 break;
3549 case CCValAssign::AExt:
3551 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3552 break;
3553 case CCValAssign::ZExt:
3555 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3556 DAG.getValueType(VA.getValVT()));
3557 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3558 break;
3559 case CCValAssign::SExt:
3561 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3562 DAG.getValueType(VA.getValVT()));
3563 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3564 break;
3565 }
3566
3567 InVals.push_back(Val);
3568 }
3569
3570 return Chain;
3571}
3572
3574 EVT ArgVT, const SDLoc &DL,
3575 SelectionDAG &DAG) {
3576 MVT LocVT = VA.getLocVT();
3577 EVT ValVT = VA.getValVT();
3578
3579 // Shift into the upper bits if necessary.
3580 switch (VA.getLocInfo()) {
3581 default:
3582 break;
3586 unsigned ValSizeInBits = ArgVT.getSizeInBits();
3587 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3588 unsigned Opcode =
3590 Val = DAG.getNode(
3591 Opcode, DL, VA.getLocVT(), Val,
3592 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3593 break;
3594 }
3595 }
3596
3597 // If this is an value smaller than the argument slot size (32-bit for O32,
3598 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3599 // size. Extract the value and insert any appropriate assertions regarding
3600 // sign/zero extension.
3601 switch (VA.getLocInfo()) {
3602 default:
3603 llvm_unreachable("Unknown loc info!");
3604 case CCValAssign::Full:
3605 break;
3607 case CCValAssign::AExt:
3608 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3609 break;
3611 case CCValAssign::SExt:
3612 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3613 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3614 break;
3616 case CCValAssign::ZExt:
3617 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3618 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3619 break;
3620 case CCValAssign::BCvt:
3621 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3622 break;
3623 }
3624
3625 return Val;
3626}
3627
3628//===----------------------------------------------------------------------===//
3629// Formal Arguments Calling Convention Implementation
3630//===----------------------------------------------------------------------===//
3631/// LowerFormalArguments - transform physical registers into virtual registers
3632/// and generate load operations for arguments places on the stack.
3633SDValue MipsTargetLowering::LowerFormalArguments(
3634 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3635 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3636 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3638 MachineFrameInfo &MFI = MF.getFrameInfo();
3640
3641 MipsFI->setVarArgsFrameIndex(0);
3642
3643 // Used with vargs to acumulate store chains.
3644 std::vector<SDValue> OutChains;
3645
3646 // Assign locations to all of the incoming arguments.
3648 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3649 *DAG.getContext());
3650 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1));
3652 Function::const_arg_iterator FuncArg = Func.arg_begin();
3653
3654 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3656 "Functions with the interrupt attribute cannot have arguments!");
3657
3658 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3659 MipsFI->setFormalArgInfo(CCInfo.getStackSize(),
3660 CCInfo.getInRegsParamsCount() > 0);
3661
3662 unsigned CurArgIdx = 0;
3663 CCInfo.rewindByValRegsInfo();
3664
3665 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3666 CCValAssign &VA = ArgLocs[i];
3667 if (Ins[InsIdx].isOrigArg()) {
3668 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3669 CurArgIdx = Ins[InsIdx].getOrigArgIndex();
3670 }
3671 EVT ValVT = VA.getValVT();
3672 ISD::ArgFlagsTy Flags = Ins[InsIdx].Flags;
3673 bool IsRegLoc = VA.isRegLoc();
3674
3675 if (Flags.isByVal()) {
3676 assert(Ins[InsIdx].isOrigArg() && "Byval arguments cannot be implicit");
3677 unsigned FirstByValReg, LastByValReg;
3678 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3679 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3680
3681 assert(Flags.getByValSize() &&
3682 "ByVal args of size 0 should have been ignored by front-end.");
3683 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3684 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3685 FirstByValReg, LastByValReg, VA, CCInfo);
3686 CCInfo.nextInRegsParam();
3687 continue;
3688 }
3689
3690 // Arguments stored on registers
3691 if (IsRegLoc) {
3692 MVT RegVT = VA.getLocVT();
3693 Register ArgReg = VA.getLocReg();
3694 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3695
3696 // Transform the arguments stored on
3697 // physical registers into virtual ones
3698 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3699 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3700
3701 ArgValue =
3702 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG);
3703
3704 // Handle floating point arguments passed in integer registers and
3705 // long double arguments passed in floating point registers.
3706 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3707 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3708 (RegVT == MVT::f64 && ValVT == MVT::i64))
3709 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3710 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3711 ValVT == MVT::f64) {
3712 assert(VA.needsCustom() && "Expected custom argument for f64 split");
3713 CCValAssign &NextVA = ArgLocs[++i];
3714 unsigned Reg2 =
3715 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC);
3716 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3717 if (!Subtarget.isLittle())
3718 std::swap(ArgValue, ArgValue2);
3719 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3720 ArgValue, ArgValue2);
3721 }
3722
3723 InVals.push_back(ArgValue);
3724 } else { // VA.isRegLoc()
3725 MVT LocVT = VA.getLocVT();
3726
3727 assert(!VA.needsCustom() && "unexpected custom memory argument");
3728
3729 // Only arguments pased on the stack should make it here.
3730 assert(VA.isMemLoc());
3731
3732 // The stack pointer offset is relative to the caller stack frame.
3733 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3734 VA.getLocMemOffset(), true);
3735
3736 // Create load nodes to retrieve arguments from the stack
3737 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3738 SDValue ArgValue = DAG.getLoad(
3739 LocVT, DL, Chain, FIN,
3741 OutChains.push_back(ArgValue.getValue(1));
3742
3743 ArgValue =
3744 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG);
3745
3746 InVals.push_back(ArgValue);
3747 }
3748 }
3749
3750 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3751
3752 if (ArgLocs[i].needsCustom()) {
3753 ++i;
3754 continue;
3755 }
3756
3757 // The mips ABIs for returning structs by value requires that we copy
3758 // the sret argument into $v0 for the return. Save the argument into
3759 // a virtual register so that we can access it from the return points.
3760 if (Ins[InsIdx].Flags.isSRet()) {
3761 unsigned Reg = MipsFI->getSRetReturnReg();
3762 if (!Reg) {
3764 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3765 MipsFI->setSRetReturnReg(Reg);
3766 }
3767 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3768 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3769 break;
3770 }
3771 }
3772
3773 if (IsVarArg)
3774 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3775
3776 // All stores are grouped in one node to allow the matching between
3777 // the size of Ins and InVals. This only happens when on varg functions
3778 if (!OutChains.empty()) {
3779 OutChains.push_back(Chain);
3780 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3781 }
3782
3783 return Chain;
3784}
3785
3786//===----------------------------------------------------------------------===//
3787// Return Value Calling Convention Implementation
3788//===----------------------------------------------------------------------===//
3789
3790bool
3791MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3792 MachineFunction &MF, bool IsVarArg,
3794 LLVMContext &Context) const {
3796 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3797 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3798}
3799
3800bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type,
3801 bool IsSigned) const {
3802 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3803 return true;
3804
3805 return IsSigned;
3806}
3807
3808SDValue
3809MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3810 const SDLoc &DL,
3811 SelectionDAG &DAG) const {
3814
3815 MipsFI->setISR();
3816
3817 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3818}
3819
3820SDValue
3821MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3822 bool IsVarArg,
3824 const SmallVectorImpl<SDValue> &OutVals,
3825 const SDLoc &DL, SelectionDAG &DAG) const {
3826 // CCValAssign - represent the assignment of
3827 // the return value to a location
3830
3831 // CCState - Info about the registers and stack slot.
3832 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3833
3834 // Analyze return values.
3835 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3836
3837 SDValue Glue;
3838 SmallVector<SDValue, 4> RetOps(1, Chain);
3839
3840 // Copy the result values into the output registers.
3841 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3842 SDValue Val = OutVals[i];
3843 CCValAssign &VA = RVLocs[i];
3844 assert(VA.isRegLoc() && "Can only return in registers!");
3845 bool UseUpperBits = false;
3846
3847 switch (VA.getLocInfo()) {
3848 default:
3849 llvm_unreachable("Unknown loc info!");
3850 case CCValAssign::Full:
3851 break;
3852 case CCValAssign::BCvt:
3853 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3854 break;
3856 UseUpperBits = true;
3857 [[fallthrough]];
3858 case CCValAssign::AExt:
3859 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3860 break;
3862 UseUpperBits = true;
3863 [[fallthrough]];
3864 case CCValAssign::ZExt:
3865 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3866 break;
3868 UseUpperBits = true;
3869 [[fallthrough]];
3870 case CCValAssign::SExt:
3871 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3872 break;
3873 }
3874
3875 if (UseUpperBits) {
3876 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3877 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3878 Val = DAG.getNode(
3879 ISD::SHL, DL, VA.getLocVT(), Val,
3880 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3881 }
3882
3883 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
3884
3885 // Guarantee that all emitted copies are stuck together with flags.
3886 Glue = Chain.getValue(1);
3887 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3888 }
3889
3890 // The mips ABIs for returning structs by value requires that we copy
3891 // the sret argument into $v0 for the return. We saved the argument into
3892 // a virtual register in the entry block, so now we copy the value out
3893 // and into $v0.
3894 if (MF.getFunction().hasStructRetAttr()) {
3896 unsigned Reg = MipsFI->getSRetReturnReg();
3897
3898 if (!Reg)
3899 llvm_unreachable("sret virtual register not created in the entry block");
3900 SDValue Val =
3901 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3902 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3903
3904 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Glue);
3905 Glue = Chain.getValue(1);
3906 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3907 }
3908
3909 RetOps[0] = Chain; // Update chain.
3910
3911 // Add the glue if we have it.
3912 if (Glue.getNode())
3913 RetOps.push_back(Glue);
3914
3915 // ISRs must use "eret".
3916 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3917 return LowerInterruptReturn(RetOps, DL, DAG);
3918
3919 // Standard return on Mips is a "jr $ra"
3920 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3921}
3922
3923//===----------------------------------------------------------------------===//
3924// Mips Inline Assembly Support
3925//===----------------------------------------------------------------------===//
3926
3927/// getConstraintType - Given a constraint letter, return the type of
3928/// constraint it is for this target.
3930MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3931 // Mips specific constraints
3932 // GCC config/mips/constraints.md
3933 //
3934 // 'd' : An address register. Equivalent to r
3935 // unless generating MIPS16 code.
3936 // 'y' : Equivalent to r; retained for
3937 // backwards compatibility.
3938 // 'c' : A register suitable for use in an indirect
3939 // jump. This will always be $25 for -mabicalls.
3940 // 'l' : The lo register. 1 word storage.
3941 // 'x' : The hilo register pair. Double word storage.
3942 if (Constraint.size() == 1) {
3943 switch (Constraint[0]) {
3944 default : break;
3945 case 'd':
3946 case 'y':
3947 case 'f':
3948 case 'c':
3949 case 'l':
3950 case 'x':
3951 return C_RegisterClass;
3952 case 'R':
3953 return C_Memory;
3954 }
3955 }
3956
3957 if (Constraint == "ZC")
3958 return C_Memory;
3959
3960 return TargetLowering::getConstraintType(Constraint);
3961}
3962
3963/// Examine constraint type and operand type and determine a weight value.
3964/// This object must already have been set up with the operand type
3965/// and the current alternative constraint selected.
3967MipsTargetLowering::getSingleConstraintMatchWeight(
3968 AsmOperandInfo &info, const char *constraint) const {
3970 Value *CallOperandVal = info.CallOperandVal;
3971 // If we don't have a value, we can't do a match,
3972 // but allow it at the lowest weight.
3973 if (!CallOperandVal)
3974 return CW_Default;
3975 Type *type = CallOperandVal->getType();
3976 // Look at the constraint type.
3977 switch (*constraint) {
3978 default:
3980 break;
3981 case 'd':
3982 case 'y':
3983 if (type->isIntegerTy())
3984 weight = CW_Register;
3985 break;
3986 case 'f': // FPU or MSA register
3987 if (Subtarget.hasMSA() && type->isVectorTy() &&
3988 type->getPrimitiveSizeInBits().getFixedValue() == 128)
3989 weight = CW_Register;
3990 else if (type->isFloatTy())
3991 weight = CW_Register;
3992 break;
3993 case 'c': // $25 for indirect jumps
3994 case 'l': // lo register
3995 case 'x': // hilo register pair
3996 if (type->isIntegerTy())
3997 weight = CW_SpecificReg;
3998 break;
3999 case 'I': // signed 16 bit immediate
4000 case 'J': // integer zero
4001 case 'K': // unsigned 16 bit immediate
4002 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4003 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4004 case 'O': // signed 15 bit immediate (+- 16383)
4005 case 'P': // immediate in the range of 65535 to 1 (inclusive)
4006 if (isa<ConstantInt>(CallOperandVal))
4007 weight = CW_Constant;
4008 break;
4009 case 'R':
4010 weight = CW_Memory;
4011 break;
4012 }
4013 return weight;
4014}
4015
4016/// This is a helper function to parse a physical register string and split it
4017/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
4018/// that is returned indicates whether parsing was successful. The second flag
4019/// is true if the numeric part exists.
4020static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
4021 unsigned long long &Reg) {
4022 if (C.front() != '{' || C.back() != '}')
4023 return std::make_pair(false, false);
4024
4025 // Search for the first numeric character.
4026 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
4027 I = std::find_if(B, E, isdigit);
4028
4029 Prefix = StringRef(B, I - B);
4030
4031 // The second flag is set to false if no numeric characters were found.
4032 if (I == E)
4033 return std::make_pair(true, false);
4034
4035 // Parse the numeric characters.
4036 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
4037 true);
4038}
4039
4041 ISD::NodeType) const {
4042 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
4043 EVT MinVT = getRegisterType(Cond ? MVT::i64 : MVT::i32);
4044 return VT.bitsLT(MinVT) ? MinVT : VT;
4045}
4046
4047std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4048parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
4049 const TargetRegisterInfo *TRI =
4051 const TargetRegisterClass *RC;
4052 StringRef Prefix;
4053 unsigned long long Reg;
4054
4055 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
4056
4057 if (!R.first)
4058 return std::make_pair(0U, nullptr);
4059
4060 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
4061 // No numeric characters follow "hi" or "lo".
4062 if (R.second)
4063 return std::make_pair(0U, nullptr);
4064
4065 RC = TRI->getRegClass(Prefix == "hi" ?
4066 Mips::HI32RegClassID : Mips::LO32RegClassID);
4067 return std::make_pair(*(RC->begin()), RC);
4068 } else if (Prefix.starts_with("$msa")) {
4069 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
4070
4071 // No numeric characters follow the name.
4072 if (R.second)
4073 return std::make_pair(0U, nullptr);
4074
4076 .Case("$msair", Mips::MSAIR)
4077 .Case("$msacsr", Mips::MSACSR)
4078 .Case("$msaaccess", Mips::MSAAccess)
4079 .Case("$msasave", Mips::MSASave)
4080 .Case("$msamodify", Mips::MSAModify)
4081 .Case("$msarequest", Mips::MSARequest)
4082 .Case("$msamap", Mips::MSAMap)
4083 .Case("$msaunmap", Mips::MSAUnmap)
4084 .Default(0);
4085
4086 if (!Reg)
4087 return std::make_pair(0U, nullptr);
4088
4089 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
4090 return std::make_pair(Reg, RC);
4091 }
4092
4093 if (!R.second)
4094 return std::make_pair(0U, nullptr);
4095
4096 if (Prefix == "$f") { // Parse $f0-$f31.
4097 // If the size of FP registers is 64-bit or Reg is an even number, select
4098 // the 64-bit register class. Otherwise, select the 32-bit register class.
4099 if (VT == MVT::Other)
4100 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
4101
4102 RC = getRegClassFor(VT);
4103
4104 if (RC == &Mips::AFGR64RegClass) {
4105 assert(Reg % 2 == 0);
4106 Reg >>= 1;
4107 }
4108 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
4109 RC = TRI->getRegClass(Mips::FCCRegClassID);
4110 else if (Prefix == "$w") { // Parse $w0-$w31.
4111 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
4112 } else { // Parse $0-$31.
4113 assert(Prefix == "$");
4114 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
4115 }
4116
4117 assert(Reg < RC->getNumRegs());
4118 return std::make_pair(*(RC->begin() + Reg), RC);
4119}
4120
4121/// Given a register class constraint, like 'r', if this corresponds directly
4122/// to an LLVM register class, return a register of 0 and the register class
4123/// pointer.
4124std::pair<unsigned, const TargetRegisterClass *>
4125MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
4126 StringRef Constraint,
4127 MVT VT) const {
4128 if (Constraint.size() == 1) {
4129 switch (Constraint[0]) {
4130 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
4131 case 'y': // Same as 'r'. Exists for compatibility.
4132 case 'r':
4133 if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
4134 VT == MVT::i1) ||
4135 (VT == MVT::f32 && Subtarget.useSoftFloat())) {
4136 if (Subtarget.inMips16Mode())
4137 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4138 return std::make_pair(0U, &Mips::GPR32RegClass);
4139 }
4140 if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
4142 return std::make_pair(0U, &Mips::GPR32RegClass);
4143 if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
4145 return std::make_pair(0U, &Mips::GPR64RegClass);
4146 // This will generate an error message
4147 return std::make_pair(0U, nullptr);
4148 case 'f': // FPU or MSA register
4149 if (VT == MVT::v16i8)
4150 return std::make_pair(0U, &Mips::MSA128BRegClass);
4151 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
4152 return std::make_pair(0U, &Mips::MSA128HRegClass);
4153 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
4154 return std::make_pair(0U, &Mips::MSA128WRegClass);
4155 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
4156 return std::make_pair(0U, &Mips::MSA128DRegClass);
4157 else if (VT == MVT::f32)
4158 return std::make_pair(0U, &Mips::FGR32RegClass);
4159 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
4160 if (Subtarget.isFP64bit())
4161 return std::make_pair(0U, &Mips::FGR64RegClass);
4162 return std::make_pair(0U, &Mips::AFGR64RegClass);
4163 }
4164 break;
4165 case 'c': // register suitable for indirect jump
4166 if (VT == MVT::i32)
4167 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
4168 if (VT == MVT::i64)
4169 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4170 // This will generate an error message
4171 return std::make_pair(0U, nullptr);
4172 case 'l': // use the `lo` register to store values
4173 // that are no bigger than a word
4174 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4175 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
4176 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4177 case 'x': // use the concatenated `hi` and `lo` registers
4178 // to store doubleword values
4179 // Fixme: Not triggering the use of both hi and low
4180 // This will generate an error message
4181 return std::make_pair(0U, nullptr);
4182 }
4183 }
4184
4185 if (!Constraint.empty()) {
4186 std::pair<unsigned, const TargetRegisterClass *> R;
4187 R = parseRegForInlineAsmConstraint(Constraint, VT);
4188
4189 if (R.second)
4190 return R;
4191 }
4192
4193 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4194}
4195
4196/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4197/// vector. If it is invalid, don't add anything to Ops.
4198void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4199 StringRef Constraint,
4200 std::vector<SDValue> &Ops,
4201 SelectionDAG &DAG) const {
4202 SDLoc DL(Op);
4204
4205 // Only support length 1 constraints for now.
4206 if (Constraint.size() > 1)
4207 return;
4208
4209 char ConstraintLetter = Constraint[0];
4210 switch (ConstraintLetter) {
4211 default: break; // This will fall through to the generic implementation
4212 case 'I': // Signed 16 bit constant
4213 // If this fails, the parent routine will give an error
4214 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4215 EVT Type = Op.getValueType();
4216 int64_t Val = C->getSExtValue();
4217 if (isInt<16>(Val)) {
4218 Result = DAG.getTargetConstant(Val, DL, Type);
4219 break;
4220 }
4221 }
4222 return;
4223 case 'J': // integer zero
4224 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4225 EVT Type = Op.getValueType();
4226 int64_t Val = C->getZExtValue();
4227 if (Val == 0) {
4228 Result = DAG.getTargetConstant(0, DL, Type);
4229 break;
4230 }
4231 }
4232 return;
4233 case 'K': // unsigned 16 bit immediate
4234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4235 EVT Type = Op.getValueType();
4236 uint64_t Val = (uint64_t)C->getZExtValue();
4237 if (isUInt<16>(Val)) {
4238 Result = DAG.getTargetConstant(Val, DL, Type);
4239 break;
4240 }
4241 }
4242 return;
4243 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4245 EVT Type = Op.getValueType();
4246 int64_t Val = C->getSExtValue();
4247 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4248 Result = DAG.getTargetConstant(Val, DL, Type);
4249 break;
4250 }
4251 }
4252 return;
4253 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4255 EVT Type = Op.getValueType();
4256 int64_t Val = C->getSExtValue();
4257 if ((Val >= -65535) && (Val <= -1)) {
4258 Result = DAG.getTargetConstant(Val, DL, Type);
4259 break;
4260 }
4261 }
4262 return;
4263 case 'O': // signed 15 bit immediate
4264 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4265 EVT Type = Op.getValueType();
4266 int64_t Val = C->getSExtValue();
4267 if ((isInt<15>(Val))) {
4268 Result = DAG.getTargetConstant(Val, DL, Type);
4269 break;
4270 }
4271 }
4272 return;
4273 case 'P': // immediate in the range of 1 to 65535 (inclusive)
4274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4275 EVT Type = Op.getValueType();
4276 int64_t Val = C->getSExtValue();
4277 if ((Val <= 65535) && (Val >= 1)) {
4278 Result = DAG.getTargetConstant(Val, DL, Type);
4279 break;
4280 }
4281 }
4282 return;
4283 }
4284
4285 if (Result.getNode()) {
4286 Ops.push_back(Result);
4287 return;
4288 }
4289
4290 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4291}
4292
4293bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4294 const AddrMode &AM, Type *Ty,
4295 unsigned AS,
4296 Instruction *I) const {
4297 // No global is ever allowed as a base.
4298 if (AM.BaseGV)
4299 return false;
4300
4301 switch (AM.Scale) {
4302 case 0: // "r+i" or just "i", depending on HasBaseReg.
4303 break;
4304 case 1:
4305 if (!AM.HasBaseReg) // allow "r+i".
4306 break;
4307 return false; // disallow "r+r" or "r+r+i".
4308 default:
4309 return false;
4310 }
4311
4312 return true;
4313}
4314
4315bool
4316MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4317 // The Mips target isn't yet aware of offsets.
4318 return false;
4319}
4320
4321EVT MipsTargetLowering::getOptimalMemOpType(
4322 const MemOp &Op, const AttributeList &FuncAttributes) const {
4323 if (Subtarget.hasMips64())
4324 return MVT::i64;
4325
4326 return MVT::i32;
4327}
4328
4329bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
4330 bool ForCodeSize) const {
4331 if (VT != MVT::f32 && VT != MVT::f64)
4332 return false;
4333 if (Imm.isNegZero())
4334 return false;
4335 return Imm.isZero();
4336}
4337
4338unsigned MipsTargetLowering::getJumpTableEncoding() const {
4339
4340 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4341 if (ABI.IsN64() && isPositionIndependent())
4343
4345}
4346
4347bool MipsTargetLowering::useSoftFloat() const {
4348 return Subtarget.useSoftFloat();
4349}
4350
4351void MipsTargetLowering::copyByValRegs(
4352 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4353 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4354 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4355 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4356 MipsCCState &State) const {
4358 MachineFrameInfo &MFI = MF.getFrameInfo();
4359 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4360 unsigned NumRegs = LastReg - FirstReg;
4361 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4362 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4363 int FrameObjOffset;
4364 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4365
4366 if (RegAreaSize)
4367 FrameObjOffset =
4369 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4370 else
4371 FrameObjOffset = VA.getLocMemOffset();
4372
4373 // Create frame object.
4374 EVT PtrTy = getPointerTy(DAG.getDataLayout());
4375 // Make the fixed object stored to mutable so that the load instructions
4376 // referencing it have their memory dependencies added.
4377 // Set the frame object as isAliased which clears the underlying objects
4378 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4379 // stores as dependencies for loads referencing this fixed object.
4380 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
4381 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4382 InVals.push_back(FIN);
4383
4384 if (!NumRegs)
4385 return;
4386
4387 // Copy arg registers.
4388 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4389 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4390
4391 for (unsigned I = 0; I < NumRegs; ++I) {
4392 unsigned ArgReg = ByValArgRegs[FirstReg + I];
4393 unsigned VReg = addLiveIn(MF, ArgReg, RC);
4394 unsigned Offset = I * GPRSizeInBytes;
4395 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4396 DAG.getConstant(Offset, DL, PtrTy));
4397 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4398 StorePtr, MachinePointerInfo(FuncArg, Offset));
4399 OutChains.push_back(Store);
4400 }
4401}
4402
4403// Copy byVal arg to registers and stack.
4404void MipsTargetLowering::passByValArg(
4405 SDValue Chain, const SDLoc &DL,
4406 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4407 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4408 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4409 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4410 const CCValAssign &VA) const {
4411 unsigned ByValSizeInBytes = Flags.getByValSize();
4412 unsigned OffsetInBytes = 0; // From beginning of struct
4413 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4414 Align Alignment =
4415 std::min(Flags.getNonZeroByValAlign(), Align(RegSizeInBytes));
4416 EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4417 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4418 unsigned NumRegs = LastReg - FirstReg;
4419
4420 if (NumRegs) {
4422 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4423 unsigned I = 0;
4424
4425 // Copy words to registers.
4426 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4427 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4428 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4429 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4430 MachinePointerInfo(), Alignment);
4431 MemOpChains.push_back(LoadVal.getValue(1));
4432 unsigned ArgReg = ArgRegs[FirstReg + I];
4433 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4434 }
4435
4436 // Return if the struct has been fully copied.
4437 if (ByValSizeInBytes == OffsetInBytes)
4438 return;
4439
4440 // Copy the remainder of the byval argument with sub-word loads and shifts.
4441 if (LeftoverBytes) {
4442 SDValue Val;
4443
4444 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4445 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4446 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4447
4448 if (RemainingSizeInBytes < LoadSizeInBytes)
4449 continue;
4450
4451 // Load subword.
4452 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4453 DAG.getConstant(OffsetInBytes, DL,
4454 PtrTy));
4455 SDValue LoadVal = DAG.getExtLoad(
4456 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4457 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4458 MemOpChains.push_back(LoadVal.getValue(1));
4459
4460 // Shift the loaded value.
4461 unsigned Shamt;
4462
4463 if (isLittle)
4464 Shamt = TotalBytesLoaded * 8;
4465 else
4466 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4467
4468 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4469 DAG.getConstant(Shamt, DL, MVT::i32));
4470
4471 if (Val.getNode())
4472 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4473 else
4474 Val = Shift;
4475
4476 OffsetInBytes += LoadSizeInBytes;
4477 TotalBytesLoaded += LoadSizeInBytes;
4478 Alignment = std::min(Alignment, Align(LoadSizeInBytes));
4479 }
4480
4481 unsigned ArgReg = ArgRegs[FirstReg + I];
4482 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4483 return;
4484 }
4485 }
4486
4487 // Copy remainder of byval arg to it with memcpy.
4488 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4489 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4490 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4491 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4493 Chain = DAG.getMemcpy(
4494 Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy),
4495 Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false,
4496 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
4497 MemOpChains.push_back(Chain);
4498}
4499
4500void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4501 SDValue Chain, const SDLoc &DL,
4502 SelectionDAG &DAG,
4503 CCState &State) const {
4505 unsigned Idx = State.getFirstUnallocated(ArgRegs);
4506 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4507 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4508 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4510 MachineFrameInfo &MFI = MF.getFrameInfo();
4512
4513 // Offset of the first variable argument from stack pointer.
4514 int VaArgOffset;
4515
4516 if (ArgRegs.size() == Idx)
4517 VaArgOffset = alignTo(State.getStackSize(), RegSizeInBytes);
4518 else {
4519 VaArgOffset =
4521 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4522 }
4523
4524 // Record the frame index of the first variable argument
4525 // which is a value necessary to VASTART.
4526 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4527 MipsFI->setVarArgsFrameIndex(FI);
4528
4529 // Copy the integer registers that have not been used for argument passing
4530 // to the argument register save area. For O32, the save area is allocated
4531 // in the caller's stack frame, while for N32/64, it is allocated in the
4532 // callee's stack frame.
4533 for (unsigned I = Idx; I < ArgRegs.size();
4534 ++I, VaArgOffset += RegSizeInBytes) {
4535 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4536 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4537 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4538 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4539 SDValue Store =
4540 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4541 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4542 (Value *)nullptr);
4543 OutChains.push_back(Store);
4544 }
4545}
4546
4548 Align Alignment) const {
4550
4551 assert(Size && "Byval argument's size shouldn't be 0.");
4552
4553 Alignment = std::min(Alignment, TFL->getStackAlign());
4554
4555 unsigned FirstReg = 0;
4556 unsigned NumRegs = 0;
4557
4558 if (State->getCallingConv() != CallingConv::Fast) {
4559 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4561 // FIXME: The O32 case actually describes no shadow registers.
4562 const MCPhysReg *ShadowRegs =
4563 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4564
4565 // We used to check the size as well but we can't do that anymore since
4566 // CCState::HandleByVal() rounds up the size after calling this function.
4567 assert(
4568 Alignment >= Align(RegSizeInBytes) &&
4569 "Byval argument's alignment should be a multiple of RegSizeInBytes.");
4570
4571 FirstReg = State->getFirstUnallocated(IntArgRegs);
4572
4573 // If Alignment > RegSizeInBytes, the first arg register must be even.
4574 // FIXME: This condition happens to do the right thing but it's not the
4575 // right way to test it. We want to check that the stack frame offset
4576 // of the register is aligned.
4577 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) {
4578 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4579 ++FirstReg;
4580 }
4581
4582 // Mark the registers allocated.
4583 Size = alignTo(Size, RegSizeInBytes);
4584 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4585 Size -= RegSizeInBytes, ++I, ++NumRegs)
4586 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4587 }
4588
4589 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4590}
4591
4592MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4594 bool isFPCmp,
4595 unsigned Opc) const {
4597 "Subtarget already supports SELECT nodes with the use of"
4598 "conditional-move instructions.");
4599
4600 const TargetInstrInfo *TII =
4602 DebugLoc DL = MI.getDebugLoc();
4603
4604 // To "insert" a SELECT instruction, we actually have to insert the
4605 // diamond control-flow pattern. The incoming instruction knows the
4606 // destination vreg to set, the condition code register to branch on, the
4607 // true/false values to select between, and a branch opcode to use.
4608 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4610
4611 // thisMBB:
4612 // ...
4613 // TrueVal = ...
4614 // setcc r1, r2, r3
4615 // bNE r1, r0, copy1MBB
4616 // fallthrough --> copy0MBB
4617 MachineBasicBlock *thisMBB = BB;
4618 MachineFunction *F = BB->getParent();
4619 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4620 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4621 F->insert(It, copy0MBB);
4622 F->insert(It, sinkMBB);
4623
4624 // Transfer the remainder of BB and its successor edges to sinkMBB.
4625 sinkMBB->splice(sinkMBB->begin(), BB,
4626 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4628
4629 // Next, add the true and fallthrough blocks as its successors.
4630 BB->addSuccessor(copy0MBB);
4631 BB->addSuccessor(sinkMBB);
4632
4633 if (isFPCmp) {
4634 // bc1[tf] cc, sinkMBB
4635 BuildMI(BB, DL, TII->get(Opc))
4636 .addReg(MI.getOperand(1).getReg())
4637 .addMBB(sinkMBB);
4638 } else {
4639 // bne rs, $0, sinkMBB
4640 BuildMI(BB, DL, TII->get(Opc))
4641 .addReg(MI.getOperand(1).getReg())
4642 .addReg(Mips::ZERO)
4643 .addMBB(sinkMBB);
4644 }
4645
4646 // copy0MBB:
4647 // %FalseValue = ...
4648 // # fallthrough to sinkMBB
4649 BB = copy0MBB;
4650
4651 // Update machine-CFG edges
4652 BB->addSuccessor(sinkMBB);
4653
4654 // sinkMBB:
4655 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4656 // ...
4657 BB = sinkMBB;
4658
4659 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4660 .addReg(MI.getOperand(2).getReg())
4661 .addMBB(thisMBB)
4662 .addReg(MI.getOperand(3).getReg())
4663 .addMBB(copy0MBB);
4664
4665 MI.eraseFromParent(); // The pseudo instruction is gone now.
4666
4667 return BB;
4668}
4669
4671MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
4672 MachineBasicBlock *BB) const {
4674 "Subtarget already supports SELECT nodes with the use of"
4675 "conditional-move instructions.");
4676
4678 DebugLoc DL = MI.getDebugLoc();
4679
4680 // D_SELECT substitutes two SELECT nodes that goes one after another and
4681 // have the same condition operand. On machines which don't have
4682 // conditional-move instruction, it reduces unnecessary branch instructions
4683 // which are result of using two diamond patterns that are result of two
4684 // SELECT pseudo instructions.
4685 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4687
4688 // thisMBB:
4689 // ...
4690 // TrueVal = ...
4691 // setcc r1, r2, r3
4692 // bNE r1, r0, copy1MBB
4693 // fallthrough --> copy0MBB
4694 MachineBasicBlock *thisMBB = BB;
4695 MachineFunction *F = BB->getParent();
4696 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4697 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4698 F->insert(It, copy0MBB);
4699 F->insert(It, sinkMBB);
4700
4701 // Transfer the remainder of BB and its successor edges to sinkMBB.
4702 sinkMBB->splice(sinkMBB->begin(), BB,
4703 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4705
4706 // Next, add the true and fallthrough blocks as its successors.
4707 BB->addSuccessor(copy0MBB);
4708 BB->addSuccessor(sinkMBB);
4709
4710 // bne rs, $0, sinkMBB
4711 BuildMI(BB, DL, TII->get(Mips::BNE))
4712 .addReg(MI.getOperand(2).getReg())
4713 .addReg(Mips::ZERO)
4714 .addMBB(sinkMBB);
4715
4716 // copy0MBB:
4717 // %FalseValue = ...
4718 // # fallthrough to sinkMBB
4719 BB = copy0MBB;
4720
4721 // Update machine-CFG edges
4722 BB->addSuccessor(sinkMBB);
4723
4724 // sinkMBB:
4725 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4726 // ...
4727 BB = sinkMBB;
4728
4729 // Use two PHI nodes to select two reults
4730 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4731 .addReg(MI.getOperand(3).getReg())
4732 .addMBB(thisMBB)
4733 .addReg(MI.getOperand(5).getReg())
4734 .addMBB(copy0MBB);
4735 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
4736 .addReg(MI.getOperand(4).getReg())
4737 .addMBB(thisMBB)
4738 .addReg(MI.getOperand(6).getReg())
4739 .addMBB(copy0MBB);
4740
4741 MI.eraseFromParent(); // The pseudo instruction is gone now.
4742
4743 return BB;
4744}
4745
4746// FIXME? Maybe this could be a TableGen attribute on some registers and
4747// this table could be generated automatically from RegInfo.
4750 const MachineFunction &MF) const {
4751 // The Linux kernel uses $28 and sp.
4752 if (Subtarget.isGP64bit()) {
4754 .Case("$28", Mips::GP_64)
4755 .Case("sp", Mips::SP_64)
4756 .Default(Register());
4757 if (Reg)
4758 return Reg;
4759 } else {
4761 .Case("$28", Mips::GP)
4762 .Case("sp", Mips::SP)
4763 .Default(Register());
4764 if (Reg)
4765 return Reg;
4766 }
4767 report_fatal_error("Invalid register name global variable");
4768}
4769
4770MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,
4771 MachineBasicBlock *BB) const {
4772 MachineFunction *MF = BB->getParent();
4775 const bool IsLittle = Subtarget.isLittle();
4776 DebugLoc DL = MI.getDebugLoc();
4777
4778 Register Dest = MI.getOperand(0).getReg();
4779 Register Address = MI.getOperand(1).getReg();
4780 unsigned Imm = MI.getOperand(2).getImm();
4781
4783
4785 // Mips release 6 can load from adress that is not naturally-aligned.
4786 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4787 BuildMI(*BB, I, DL, TII->get(Mips::LW))
4788 .addDef(Temp)
4789 .addUse(Address)
4790 .addImm(Imm);
4791 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp);
4792 } else {
4793 // Mips release 5 needs to use instructions that can load from an unaligned
4794 // memory address.
4795 Register LoadHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4796 Register LoadFull = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4797 Register Undef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4798 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef);
4799 BuildMI(*BB, I, DL, TII->get(Mips::LWR))
4800 .addDef(LoadHalf)
4801 .addUse(Address)
4802 .addImm(Imm + (IsLittle ? 0 : 3))
4803 .addUse(Undef);
4804 BuildMI(*BB, I, DL, TII->get(Mips::LWL))
4805 .addDef(LoadFull)
4806 .addUse(Address)
4807 .addImm(Imm + (IsLittle ? 3 : 0))
4808 .addUse(LoadHalf);
4809 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull);
4810 }
4811
4812 MI.eraseFromParent();
4813 return BB;
4814}
4815
4816MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI,
4817 MachineBasicBlock *BB) const {
4818 MachineFunction *MF = BB->getParent();
4821 const bool IsLittle = Subtarget.isLittle();
4822 DebugLoc DL = MI.getDebugLoc();
4823
4824 Register Dest = MI.getOperand(0).getReg();
4825 Register Address = MI.getOperand(1).getReg();
4826 unsigned Imm = MI.getOperand(2).getImm();
4827
4829
4831 // Mips release 6 can load from adress that is not naturally-aligned.
4832 if (Subtarget.isGP64bit()) {
4833 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass);
4834 BuildMI(*BB, I, DL, TII->get(Mips::LD))
4835 .addDef(Temp)
4836 .addUse(Address)
4837 .addImm(Imm);
4838 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp);
4839 } else {
4840 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4841 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4842 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4843 BuildMI(*BB, I, DL, TII->get(Mips::LW))
4844 .addDef(Lo)
4845 .addUse(Address)
4846 .addImm(Imm + (IsLittle ? 0 : 4));
4847 BuildMI(*BB, I, DL, TII->get(Mips::LW))
4848 .addDef(Hi)
4849 .addUse(Address)
4850 .addImm(Imm + (IsLittle ? 4 : 0));
4851 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(Lo);
4852 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest)
4853 .addUse(Wtemp)
4854 .addUse(Hi)
4855 .addImm(1);
4856 }
4857 } else {
4858 // Mips release 5 needs to use instructions that can load from an unaligned
4859 // memory address.
4860 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4861 Register LoFull = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4862 Register LoUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4863 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4864 Register HiFull = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4865 Register HiUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4866 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4867 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(LoUndef);
4868 BuildMI(*BB, I, DL, TII->get(Mips::LWR))
4869 .addDef(LoHalf)
4870 .addUse(Address)
4871 .addImm(Imm + (IsLittle ? 0 : 7))
4872 .addUse(LoUndef);
4873 BuildMI(*BB, I, DL, TII->get(Mips::LWL))
4874 .addDef(LoFull)
4875 .addUse(Address)
4876 .addImm(Imm + (IsLittle ? 3 : 4))
4877 .addUse(LoHalf);
4878 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(HiUndef);
4879 BuildMI(*BB, I, DL, TII->get(Mips::LWR))
4880 .addDef(HiHalf)
4881 .addUse(Address)
4882 .addImm(Imm + (IsLittle ? 4 : 3))
4883 .addUse(HiUndef);
4884 BuildMI(*BB, I, DL, TII->get(Mips::LWL))
4885 .addDef(HiFull)
4886 .addUse(Address)
4887 .addImm(Imm + (IsLittle ? 7 : 0))
4888 .addUse(HiHalf);
4889 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(LoFull);
4890 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest)
4891 .addUse(Wtemp)
4892 .addUse(HiFull)
4893 .addImm(1);
4894 }
4895
4896 MI.eraseFromParent();
4897 return BB;
4898}
4899
4900MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI,
4901 MachineBasicBlock *BB) const {
4902 MachineFunction *MF = BB->getParent();
4905 const bool IsLittle = Subtarget.isLittle();
4906 DebugLoc DL = MI.getDebugLoc();
4907
4908 Register StoreVal = MI.getOperand(0).getReg();
4909 Register Address = MI.getOperand(1).getReg();
4910 unsigned Imm = MI.getOperand(2).getImm();
4911
4913
4915 // Mips release 6 can store to adress that is not naturally-aligned.
4916 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4917 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4918 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(BitcastW).addUse(StoreVal);
4919 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
4920 .addDef(Tmp)
4921 .addUse(BitcastW)
4922 .addImm(0);
4923 BuildMI(*BB, I, DL, TII->get(Mips::SW))
4924 .addUse(Tmp)
4925 .addUse(Address)
4926 .addImm(Imm);
4927 } else {
4928 // Mips release 5 needs to use instructions that can store to an unaligned
4929 // memory address.
4930 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4931 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
4932 .addDef(Tmp)
4933 .addUse(StoreVal)
4934 .addImm(0);
4935 BuildMI(*BB, I, DL, TII->get(Mips::SWR))
4936 .addUse(Tmp)
4937 .addUse(Address)
4938 .addImm(Imm + (IsLittle ? 0 : 3));
4939 BuildMI(*BB, I, DL, TII->get(Mips::SWL))
4940 .addUse(Tmp)
4941 .addUse(Address)
4942 .addImm(Imm + (IsLittle ? 3 : 0));
4943 }
4944
4945 MI.eraseFromParent();
4946
4947 return BB;
4948}
4949
4950MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI,
4951 MachineBasicBlock *BB) const {
4952 MachineFunction *MF = BB->getParent();
4955 const bool IsLittle = Subtarget.isLittle();
4956 DebugLoc DL = MI.getDebugLoc();
4957
4958 Register StoreVal = MI.getOperand(0).getReg();
4959 Register Address = MI.getOperand(1).getReg();
4960 unsigned Imm = MI.getOperand(2).getImm();
4961
4963
4965 // Mips release 6 can store to adress that is not naturally-aligned.
4966 if (Subtarget.isGP64bit()) {
4967 Register BitcastD = MRI.createVirtualRegister(&Mips::MSA128DRegClass);
4968 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass);
4969 BuildMI(*BB, I, DL, TII->get(Mips::COPY))
4970 .addDef(BitcastD)
4971 .addUse(StoreVal);
4972 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_D))
4973 .addDef(Lo)
4974 .addUse(BitcastD)
4975 .addImm(0);
4976 BuildMI(*BB, I, DL, TII->get(Mips::SD))
4977 .addUse(Lo)
4978 .addUse(Address)
4979 .addImm(Imm);
4980 } else {
4981 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4982 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4983 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4984 BuildMI(*BB, I, DL, TII->get(Mips::COPY))
4985 .addDef(BitcastW)
4986 .addUse(StoreVal);
4987 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
4988 .addDef(Lo)
4989 .addUse(BitcastW)
4990 .addImm(0);
4991 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
4992 .addDef(Hi)
4993 .addUse(BitcastW)
4994 .addImm(1);
4995 BuildMI(*BB, I, DL, TII->get(Mips::SW))
4996 .addUse(Lo)
4997 .addUse(Address)
4998 .addImm(Imm + (IsLittle ? 0 : 4));
4999 BuildMI(*BB, I, DL, TII->get(Mips::SW))
5000 .addUse(Hi)
5001 .addUse(Address)
5002 .addImm(Imm + (IsLittle ? 4 : 0));
5003 }
5004 } else {
5005 // Mips release 5 needs to use instructions that can store to an unaligned
5006 // memory address.
5007 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5008 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5009 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass);
5010 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal);
5011 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
5012 .addDef(Lo)
5013 .addUse(Bitcast)
5014 .addImm(0);
5015 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W))
5016 .addDef(Hi)
5017 .addUse(Bitcast)
5018 .addImm(1);
5019 BuildMI(*BB, I, DL, TII->get(Mips::SWR))
5020 .addUse(Lo)
5021 .addUse(Address)
5022 .addImm(Imm + (IsLittle ? 0 : 3));
5023 BuildMI(*BB, I, DL, TII->get(Mips::SWL))
5024 .addUse(Lo)
5025 .addUse(Address)
5026 .addImm(Imm + (IsLittle ? 3 : 0));
5027 BuildMI(*BB, I, DL, TII->get(Mips::SWR))
5028 .addUse(Hi)
5029 .addUse(Address)
5030 .addImm(Imm + (IsLittle ? 4 : 7));
5031 BuildMI(*BB, I, DL, TII->get(Mips::SWL))
5032 .addUse(Hi)
5033 .addUse(Address)
5034 .addImm(Imm + (IsLittle ? 7 : 4));
5035 }
5036
5037 MI.eraseFromParent();
5038 return BB;
5039}
unsigned const MachineRegisterInfo * MRI
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:203
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
Symbol * Sym
Definition: ELF_riscv.cpp:479
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
static LVOptions Options
Definition: LVOptions.cpp:25
lazy value info
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
cl::opt< bool > EmitJalrReloc
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget)
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat)
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static const MCPhysReg Mips64DPRegs[8]
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
cl::opt< bool > EmitJalrReloc
static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
LLVMContext & Context
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file defines the SmallVector class.
static const MCPhysReg IntRegs[32]
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static const MCPhysReg F32Regs[64]
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
Value * RHS
Value * LHS
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
const T * data() const
Definition: ArrayRef.h:162
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
static BranchProbability getOne()
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
CallingConv::ID getCallingConv() const
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
bool isVarArg() const
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
bool isUpperBitsInLoc() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
bool needsCustom() const
bool isMemLoc() const
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
int64_t getLocMemOffset() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:504
A debug info location.
Definition: DebugLoc.h:33
const char * getSymbol() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:661
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:669
const GlobalValue * getGlobal() const
bool hasLocalLinkage() const
Definition: GlobalValue.h:527
const GlobalObject * getAliaseeObject() const
Definition: Globals.cpp:368
bool hasInternalLinkage() const
Definition: GlobalValue.h:525
Class to represent integer types.
Definition: DerivedTypes.h:40
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This class is used to represent ISD::LOAD nodes.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:200
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Machine Value Type.
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
static auto fp_fixedlen_vector_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:554
@ EK_GPRel64BlockAddress
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative,...
@ MOVolatile
The memory access is volatile.
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Align getAlign() const
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
bool IsN64() const
Definition: MipsABIInfo.h:42
ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
Definition: MipsABIInfo.cpp:41
bool ArePtrs64bit() const
Definition: MipsABIInfo.h:73
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
Definition: MipsABIInfo.cpp:49
unsigned GetPtrAddiuOp() const
unsigned GetPtrAndOp() const
ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
Definition: MipsABIInfo.cpp:33
unsigned GetNullPtr() const
Definition: MipsABIInfo.cpp:90
bool IsN32() const
Definition: MipsABIInfo.h:41
bool IsO32() const
Definition: MipsABIInfo.h:40
bool WasOriginalArgVectorFloat(unsigned ValNo) const
Definition: MipsCCState.h:198
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
Definition: MipsCCState.cpp:70
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
void setVarArgsFrameIndex(int Index)
unsigned getSRetReturnReg() const
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
Register getGlobalBaseReg(MachineFunction &MF)
void setSRetReturnReg(unsigned Reg)
void setFormalArgInfo(unsigned Size, bool HasByval)
static const uint32_t * getMips16RetHelperMask()
bool hasMips32r6() const
bool hasMips4() const
bool hasMips64r2() const
bool isFP64bit() const
bool isLittle() const
bool inMicroMipsMode() const
bool useSoftFloat() const
const MipsInstrInfo * getInstrInfo() const override
bool hasMips64r6() const
bool inMips16Mode() const
bool hasMips64() const
bool hasMips32() const
bool hasSym32() const
bool useXGOT() const
bool inAbs2008Mode() const
const MipsRegisterInfo * getRegisterInfo() const override
bool isABICalls() const
bool hasCnMips() const
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool isGP64bit() const
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool hasMips32r2() const
bool hasMSA() const
bool isSingleFloat() const
bool isABI_O32() const
bool useLongCalls() const
unsigned getGPRSizeInBytes() const
bool inMips16HardFloat() const
const TargetFrameLowering * getFrameLowering() const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
const MipsABIInfo & ABI
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:722
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:732
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:472
void addCallSiteInfo(const SDNode *Node, CallSiteInfoImpl &&CallInfo)
Set CallSiteInfo to be associated with Node.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:473
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:773
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:676
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:768
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:469
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:799
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
Definition: SelectionDAG.h:485
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:739
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:554
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:950
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getValue() const
bool isTruncatingStore() const
Return true if the op does a truncation before store.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual TargetLoweringObjectFile * getObjFileLowering() const
TargetOptions Options
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:265
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:154
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:228
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:187
self_iterator getIterator()
Definition: ilist_node.h:109
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:121
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:750
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1126
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1122
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:714
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1155
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Definition: ISDOpcodes.h:1241
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:1031
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:783
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:483
@ RETURNADDR
Definition: ISDOpcodes.h:95
@ GlobalAddress
Definition: ISDOpcodes.h:78
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1233
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:913
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:903
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:229
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:135
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
@ TargetJumpTable
Definition: ISDOpcodes.h:167
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:988
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1077
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:1056
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:727
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
Definition: ISDOpcodes.h:1237
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1151
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:705
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:780
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:742
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:1041
@ ConstantPool
Definition: ISDOpcodes.h:82
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:798
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
Definition: ISDOpcodes.h:129
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:836
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:680
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1208
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:786
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1146
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1070
@ BlockAddress
Definition: ISDOpcodes.h:84
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:763
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:493
@ AssertZext
Definition: ISDOpcodes.h:62
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
Definition: ISDOpcodes.h:1140
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1523
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1503
@ Bitcast
Perform the operation on a different, but equivalently sized type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:148
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
Definition: MipsBaseInfo.h:95
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:69
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
Definition: MipsBaseInfo.h:89
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:63
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Dead
Unused definition.
@ Define
Register definition.
@ Kill
The last use of a register.
@ EarlyClobber
Register definition happens before uses.
@ GeneralDynamic
Definition: CodeGen.h:46
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
NodeAddr< FuncNode * > Func
Definition: RDFGraph.h:393
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:417
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
Definition: MathExtras.h:258
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
@ Or
Bitwise or logical OR of integers.
@ Add
Sum of integers.
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
DWARFExpression::Operation Op
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
Definition: StringRef.cpp:486
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Extended Value Type.
Definition: ValueTypes.h:34
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:93
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:290
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:358
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:455
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:306
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
Definition: ValueTypes.h:58
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:167
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
bool isRound() const
Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:238
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:318
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:326
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:151
Align getNonZeroOrigAlign() const
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:141
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals