81#define DEBUG_TYPE "mips-lower"
87 cl::desc(
"MIPS: Don't trap on integer division by zero."),
93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
125 unsigned &NumIntermediates,
MVT &RegisterVT)
const {
130 return NumIntermediates;
146 unsigned Flag)
const {
152 unsigned Flag)
const {
158 unsigned Flag)
const {
164 unsigned Flag)
const {
170 unsigned Flag)
const {
172 N->getOffset(), Flag);
548 if (!
TM.isPositionIndependent() || !
TM.getABI().IsO32() ||
568 EVT Ty =
N->getValueType(0);
569 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
570 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
576 N->getOperand(0),
N->getOperand(1));
581 if (
N->hasAnyUseOfValue(0)) {
590 if (
N->hasAnyUseOfValue(1)) {
632 "Illegal Condition Code");
646 if (!
LHS.getValueType().isFloatingPoint())
758 SDValue ValueIfTrue =
N->getOperand(0), ValueIfFalse =
N->getOperand(2);
774 SDValue FCC =
N->getOperand(1), Glue =
N->getOperand(3);
775 return DAG.
getNode(Opc,
SDLoc(
N), ValueIfFalse.getValueType(),
776 ValueIfFalse, FCC, ValueIfTrue, Glue);
785 SDValue FirstOperand =
N->getOperand(0);
786 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
788 EVT ValTy =
N->getValueType(0);
792 unsigned SMPos, SMSize;
798 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
808 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
828 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
833 if (SMPos != Pos || Pos >= ValTy.
getSizeInBits() || SMSize >= 32 ||
855 NewOperand = FirstOperand;
857 return DAG.
getNode(Opc,
DL, ValTy, NewOperand,
872 SDValue And0 =
N->getOperand(0), And1 =
N->getOperand(1);
873 unsigned SMPos0, SMSize0, SMPos1, SMSize1;
880 if (!(CN = dyn_cast<ConstantSDNode>(And0.
getOperand(1))) ||
886 And1.getOperand(0).getOpcode() ==
ISD::SHL) {
888 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
893 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
898 if (!(CN = dyn_cast<ConstantSDNode>(Shl.
getOperand(1))))
905 EVT ValTy =
N->getValueType(0);
906 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.
getSizeInBits()))
919 if (~CN->
getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
920 ((SMSize0 + SMPos0 <= 64 && Subtarget.
hasMips64r2()) ||
921 (SMSize0 + SMPos0 <= 32))) {
925 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
928 if (!(CN1 = dyn_cast<ConstantSDNode>(
N->getOperand(1))))
937 EVT ValTy =
N->getOperand(0)->getValueType(0);
1012 if (!Mult.hasOneUse())
1020 SDValue MultLHS = Mult->getOperand(0);
1021 SDValue MultRHS = Mult->getOperand(1);
1028 if (!IsSigned && !IsUnsigned)
1034 std::tie(BottomHalf, TopHalf) =
1046 EVT VTs[2] = {MVT::i32, MVT::i32};
1062 !Subtarget.
inMips16Mode() &&
N->getValueType(0) == MVT::i64)
1077 !Subtarget.
inMips16Mode() &&
N->getValueType(0) == MVT::i64)
1095 EVT ValTy =
N->getValueType(0);
1113 SDValue FirstOperand =
N->getOperand(0);
1114 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
1115 SDValue SecondOperand =
N->getOperand(1);
1116 EVT ValTy =
N->getValueType(0);
1120 unsigned SMPos, SMSize;
1125 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1137 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
1143 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.
getSizeInBits())
1158 unsigned Opc =
N->getOpcode();
1197 if (
auto *
C = dyn_cast<ConstantSDNode>(
Y))
1198 return C->getAPIntValue().ule(15);
1206 N->getOperand(0).getOpcode() ==
ISD::SRL) ||
1208 N->getOperand(0).getOpcode() ==
ISD::SHL)) &&
1209 "Expected shift-shift mask");
1211 if (
N->getOperand(0).getValueType().isVector())
1226 switch (
Op.getOpcode())
1273 bool Is64Bit,
bool IsMicroMips) {
1282 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1303 switch (
MI.getOpcode()) {
1306 case Mips::ATOMIC_LOAD_ADD_I8:
1307 return emitAtomicBinaryPartword(
MI, BB, 1);
1308 case Mips::ATOMIC_LOAD_ADD_I16:
1309 return emitAtomicBinaryPartword(
MI, BB, 2);
1310 case Mips::ATOMIC_LOAD_ADD_I32:
1311 return emitAtomicBinary(
MI, BB);
1312 case Mips::ATOMIC_LOAD_ADD_I64:
1313 return emitAtomicBinary(
MI, BB);
1315 case Mips::ATOMIC_LOAD_AND_I8:
1316 return emitAtomicBinaryPartword(
MI, BB, 1);
1317 case Mips::ATOMIC_LOAD_AND_I16:
1318 return emitAtomicBinaryPartword(
MI, BB, 2);
1319 case Mips::ATOMIC_LOAD_AND_I32:
1320 return emitAtomicBinary(
MI, BB);
1321 case Mips::ATOMIC_LOAD_AND_I64:
1322 return emitAtomicBinary(
MI, BB);
1324 case Mips::ATOMIC_LOAD_OR_I8:
1325 return emitAtomicBinaryPartword(
MI, BB, 1);
1326 case Mips::ATOMIC_LOAD_OR_I16:
1327 return emitAtomicBinaryPartword(
MI, BB, 2);
1328 case Mips::ATOMIC_LOAD_OR_I32:
1329 return emitAtomicBinary(
MI, BB);
1330 case Mips::ATOMIC_LOAD_OR_I64:
1331 return emitAtomicBinary(
MI, BB);
1333 case Mips::ATOMIC_LOAD_XOR_I8:
1334 return emitAtomicBinaryPartword(
MI, BB, 1);
1335 case Mips::ATOMIC_LOAD_XOR_I16:
1336 return emitAtomicBinaryPartword(
MI, BB, 2);
1337 case Mips::ATOMIC_LOAD_XOR_I32:
1338 return emitAtomicBinary(
MI, BB);
1339 case Mips::ATOMIC_LOAD_XOR_I64:
1340 return emitAtomicBinary(
MI, BB);
1342 case Mips::ATOMIC_LOAD_NAND_I8:
1343 return emitAtomicBinaryPartword(
MI, BB, 1);
1344 case Mips::ATOMIC_LOAD_NAND_I16:
1345 return emitAtomicBinaryPartword(
MI, BB, 2);
1346 case Mips::ATOMIC_LOAD_NAND_I32:
1347 return emitAtomicBinary(
MI, BB);
1348 case Mips::ATOMIC_LOAD_NAND_I64:
1349 return emitAtomicBinary(
MI, BB);
1351 case Mips::ATOMIC_LOAD_SUB_I8:
1352 return emitAtomicBinaryPartword(
MI, BB, 1);
1353 case Mips::ATOMIC_LOAD_SUB_I16:
1354 return emitAtomicBinaryPartword(
MI, BB, 2);
1355 case Mips::ATOMIC_LOAD_SUB_I32:
1356 return emitAtomicBinary(
MI, BB);
1357 case Mips::ATOMIC_LOAD_SUB_I64:
1358 return emitAtomicBinary(
MI, BB);
1360 case Mips::ATOMIC_SWAP_I8:
1361 return emitAtomicBinaryPartword(
MI, BB, 1);
1362 case Mips::ATOMIC_SWAP_I16:
1363 return emitAtomicBinaryPartword(
MI, BB, 2);
1364 case Mips::ATOMIC_SWAP_I32:
1365 return emitAtomicBinary(
MI, BB);
1366 case Mips::ATOMIC_SWAP_I64:
1367 return emitAtomicBinary(
MI, BB);
1369 case Mips::ATOMIC_CMP_SWAP_I8:
1370 return emitAtomicCmpSwapPartword(
MI, BB, 1);
1371 case Mips::ATOMIC_CMP_SWAP_I16:
1372 return emitAtomicCmpSwapPartword(
MI, BB, 2);
1373 case Mips::ATOMIC_CMP_SWAP_I32:
1374 return emitAtomicCmpSwap(
MI, BB);
1375 case Mips::ATOMIC_CMP_SWAP_I64:
1376 return emitAtomicCmpSwap(
MI, BB);
1378 case Mips::ATOMIC_LOAD_MIN_I8:
1379 return emitAtomicBinaryPartword(
MI, BB, 1);
1380 case Mips::ATOMIC_LOAD_MIN_I16:
1381 return emitAtomicBinaryPartword(
MI, BB, 2);
1382 case Mips::ATOMIC_LOAD_MIN_I32:
1383 return emitAtomicBinary(
MI, BB);
1384 case Mips::ATOMIC_LOAD_MIN_I64:
1385 return emitAtomicBinary(
MI, BB);
1387 case Mips::ATOMIC_LOAD_MAX_I8:
1388 return emitAtomicBinaryPartword(
MI, BB, 1);
1389 case Mips::ATOMIC_LOAD_MAX_I16:
1390 return emitAtomicBinaryPartword(
MI, BB, 2);
1391 case Mips::ATOMIC_LOAD_MAX_I32:
1392 return emitAtomicBinary(
MI, BB);
1393 case Mips::ATOMIC_LOAD_MAX_I64:
1394 return emitAtomicBinary(
MI, BB);
1396 case Mips::ATOMIC_LOAD_UMIN_I8:
1397 return emitAtomicBinaryPartword(
MI, BB, 1);
1398 case Mips::ATOMIC_LOAD_UMIN_I16:
1399 return emitAtomicBinaryPartword(
MI, BB, 2);
1400 case Mips::ATOMIC_LOAD_UMIN_I32:
1401 return emitAtomicBinary(
MI, BB);
1402 case Mips::ATOMIC_LOAD_UMIN_I64:
1403 return emitAtomicBinary(
MI, BB);
1405 case Mips::ATOMIC_LOAD_UMAX_I8:
1406 return emitAtomicBinaryPartword(
MI, BB, 1);
1407 case Mips::ATOMIC_LOAD_UMAX_I16:
1408 return emitAtomicBinaryPartword(
MI, BB, 2);
1409 case Mips::ATOMIC_LOAD_UMAX_I32:
1410 return emitAtomicBinary(
MI, BB);
1411 case Mips::ATOMIC_LOAD_UMAX_I64:
1412 return emitAtomicBinary(
MI, BB);
1414 case Mips::PseudoSDIV:
1415 case Mips::PseudoUDIV:
1422 case Mips::SDIV_MM_Pseudo:
1423 case Mips::UDIV_MM_Pseudo:
1426 case Mips::DIV_MMR6:
1427 case Mips::DIVU_MMR6:
1428 case Mips::MOD_MMR6:
1429 case Mips::MODU_MMR6:
1431 case Mips::PseudoDSDIV:
1432 case Mips::PseudoDUDIV:
1439 case Mips::PseudoSELECT_I:
1440 case Mips::PseudoSELECT_I64:
1441 case Mips::PseudoSELECT_S:
1442 case Mips::PseudoSELECT_D32:
1443 case Mips::PseudoSELECT_D64:
1444 return emitPseudoSELECT(
MI, BB,
false, Mips::BNE);
1445 case Mips::PseudoSELECTFP_F_I:
1446 case Mips::PseudoSELECTFP_F_I64:
1447 case Mips::PseudoSELECTFP_F_S:
1448 case Mips::PseudoSELECTFP_F_D32:
1449 case Mips::PseudoSELECTFP_F_D64:
1450 return emitPseudoSELECT(
MI, BB,
true, Mips::BC1F);
1451 case Mips::PseudoSELECTFP_T_I:
1452 case Mips::PseudoSELECTFP_T_I64:
1453 case Mips::PseudoSELECTFP_T_S:
1454 case Mips::PseudoSELECTFP_T_D32:
1455 case Mips::PseudoSELECTFP_T_D64:
1456 return emitPseudoSELECT(
MI, BB,
true, Mips::BC1T);
1457 case Mips::PseudoD_SELECT_I:
1458 case Mips::PseudoD_SELECT_I64:
1459 return emitPseudoD_SELECT(
MI, BB);
1461 return emitLDR_W(
MI, BB);
1463 return emitLDR_D(
MI, BB);
1465 return emitSTR_W(
MI, BB);
1467 return emitSTR_D(
MI, BB);
1483 bool NeedsAdditionalReg =
false;
1484 switch (
MI.getOpcode()) {
1485 case Mips::ATOMIC_LOAD_ADD_I32:
1486 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1488 case Mips::ATOMIC_LOAD_SUB_I32:
1489 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1491 case Mips::ATOMIC_LOAD_AND_I32:
1492 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1494 case Mips::ATOMIC_LOAD_OR_I32:
1495 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1497 case Mips::ATOMIC_LOAD_XOR_I32:
1498 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1500 case Mips::ATOMIC_LOAD_NAND_I32:
1501 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1503 case Mips::ATOMIC_SWAP_I32:
1504 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1506 case Mips::ATOMIC_LOAD_ADD_I64:
1507 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1509 case Mips::ATOMIC_LOAD_SUB_I64:
1510 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1512 case Mips::ATOMIC_LOAD_AND_I64:
1513 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1515 case Mips::ATOMIC_LOAD_OR_I64:
1516 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1518 case Mips::ATOMIC_LOAD_XOR_I64:
1519 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1521 case Mips::ATOMIC_LOAD_NAND_I64:
1522 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1524 case Mips::ATOMIC_SWAP_I64:
1525 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1527 case Mips::ATOMIC_LOAD_MIN_I32:
1528 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1529 NeedsAdditionalReg =
true;
1531 case Mips::ATOMIC_LOAD_MAX_I32:
1532 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1533 NeedsAdditionalReg =
true;
1535 case Mips::ATOMIC_LOAD_UMIN_I32:
1536 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1537 NeedsAdditionalReg =
true;
1539 case Mips::ATOMIC_LOAD_UMAX_I32:
1540 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1541 NeedsAdditionalReg =
true;
1543 case Mips::ATOMIC_LOAD_MIN_I64:
1544 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1545 NeedsAdditionalReg =
true;
1547 case Mips::ATOMIC_LOAD_MAX_I64:
1548 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1549 NeedsAdditionalReg =
true;
1551 case Mips::ATOMIC_LOAD_UMIN_I64:
1552 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1553 NeedsAdditionalReg =
true;
1555 case Mips::ATOMIC_LOAD_UMAX_I64:
1556 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1557 NeedsAdditionalReg =
true;
1618 if (NeedsAdditionalReg) {
1625 MI.eraseFromParent();
1632 unsigned SrcReg)
const {
1652 int64_t ShiftImm = 32 - (
Size * 8);
1663 "Unsupported size for EmitAtomicBinaryPartial.");
1690 unsigned AtomicOp = 0;
1691 bool NeedsAdditionalReg =
false;
1692 switch (
MI.getOpcode()) {
1693 case Mips::ATOMIC_LOAD_NAND_I8:
1694 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1696 case Mips::ATOMIC_LOAD_NAND_I16:
1697 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1699 case Mips::ATOMIC_SWAP_I8:
1700 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1702 case Mips::ATOMIC_SWAP_I16:
1703 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1705 case Mips::ATOMIC_LOAD_ADD_I8:
1706 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1708 case Mips::ATOMIC_LOAD_ADD_I16:
1709 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1711 case Mips::ATOMIC_LOAD_SUB_I8:
1712 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1714 case Mips::ATOMIC_LOAD_SUB_I16:
1715 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1717 case Mips::ATOMIC_LOAD_AND_I8:
1718 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1720 case Mips::ATOMIC_LOAD_AND_I16:
1721 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1723 case Mips::ATOMIC_LOAD_OR_I8:
1724 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1726 case Mips::ATOMIC_LOAD_OR_I16:
1727 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1729 case Mips::ATOMIC_LOAD_XOR_I8:
1730 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1732 case Mips::ATOMIC_LOAD_XOR_I16:
1733 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1735 case Mips::ATOMIC_LOAD_MIN_I8:
1736 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1737 NeedsAdditionalReg =
true;
1739 case Mips::ATOMIC_LOAD_MIN_I16:
1740 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1741 NeedsAdditionalReg =
true;
1743 case Mips::ATOMIC_LOAD_MAX_I8:
1744 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1745 NeedsAdditionalReg =
true;
1747 case Mips::ATOMIC_LOAD_MAX_I16:
1748 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1749 NeedsAdditionalReg =
true;
1751 case Mips::ATOMIC_LOAD_UMIN_I8:
1752 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1753 NeedsAdditionalReg =
true;
1755 case Mips::ATOMIC_LOAD_UMIN_I16:
1756 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1757 NeedsAdditionalReg =
true;
1759 case Mips::ATOMIC_LOAD_UMAX_I8:
1760 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1761 NeedsAdditionalReg =
true;
1763 case Mips::ATOMIC_LOAD_UMAX_I16:
1764 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1765 NeedsAdditionalReg =
true;
1794 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
1835 if (NeedsAdditionalReg) {
1841 MI.eraseFromParent();
1855 assert((
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1856 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1857 "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1859 const unsigned Size =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1867 unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1868 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1869 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1884 Register OldValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(OldVal));
1885 Register NewValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(NewVal));
1903 MI.eraseFromParent();
1911 "Unsupported size for EmitAtomicCmpSwapPartial.");
1938 unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1939 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1940 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1981 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
1982 BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1984 BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
2027 MI.eraseFromParent();
2052 FCC0, Dest, CondRes);
2074 "Floating point operand expected.");
2085 EVT Ty =
Op.getValueType();
2133 EVT Ty =
Op.getValueType();
2176 Args.push_back(Entry);
2181 .setLibCallee(
CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2182 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
2228 EVT Ty =
Op.getValueType();
2241 EVT Ty =
Op.getValueType();
2270 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
2277 EVT VT =
Node->getValueType(0);
2282 const Value *SV = cast<SrcValueSDNode>(
Node->getOperand(2))->getValue();
2309 unsigned ArgSizeInBytes =
2325 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2334 bool HasExtractInsert) {
2335 EVT TyX =
Op.getOperand(0).getValueType();
2336 EVT TyY =
Op.getOperand(1).getValueType();
2353 if (HasExtractInsert) {
2371 if (TyX == MVT::f32)
2381 bool HasExtractInsert) {
2382 unsigned WidthX =
Op.getOperand(0).getValueSizeInBits();
2383 unsigned WidthY =
Op.getOperand(1).getValueSizeInBits();
2392 if (HasExtractInsert) {
2398 if (WidthX > WidthY)
2400 else if (WidthY > WidthX)
2419 if (WidthX > WidthY)
2421 else if (WidthY > WidthX)
2439 bool HasExtractInsert)
const {
2451 Op.getOperand(0), Const1);
2454 if (HasExtractInsert)
2465 if (
Op.getValueType() == MVT::f32)
2479 bool HasExtractInsert)
const {
2490 if (HasExtractInsert)
2512 if (
Op.getConstantOperandVal(0) != 0) {
2514 "return address can be determined only for current frame");
2520 EVT VT =
Op.getValueType();
2533 if (
Op.getConstantOperandVal(0) != 0) {
2535 "return address can be determined only for current frame");
2541 MVT VT =
Op.getSimpleValueType();
2542 unsigned RA =
ABI.
IsN64() ? Mips::RA_64 : Mips::RA;
2568 unsigned OffsetReg =
ABI.
IsN64() ? Mips::V1_64 : Mips::V1;
2569 unsigned AddrReg =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
2659 DL, VTList,
Cond, ShiftRightHi,
2675 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2676 EVT BasePtrVT =
Ptr.getValueType();
2686 LD->getMemOperand());
2692 EVT MemVT = LD->getMemoryVT();
2698 if ((LD->getAlign().value() >= (MemVT.
getSizeInBits() / 8)) ||
2699 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2703 EVT VT =
Op.getValueType();
2707 assert((VT == MVT::i32) || (VT == MVT::i64));
2750 SDValue Ops[] = { SRL, LWR.getValue(1) };
2823 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2835 EVT ValTy =
Op->getValueType(0);
2881 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2887 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2895 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2899 else if (ArgFlags.
isZExt())
2907 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2911 else if (ArgFlags.
isZExt())
2922 bool AllocateFloatsInIntReg = State.
isVarArg() || ValNo > 1 ||
2925 bool isI64 = (ValVT == MVT::i32 && OrigAlign ==
Align(8));
2929 if (ValVT == MVT::i32 && isVectorFloat) {
2936 if (Reg == Mips::A2)
2945 }
else if (ValVT == MVT::i32 ||
2946 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2950 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2953 }
else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2957 if (Reg == Mips::A1 || Reg == Mips::A3)
2973 if (ValVT == MVT::f32) {
2981 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3000 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
3002 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3008 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3010 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3017#include "MipsGenCallingConv.inc"
3020 return CC_Mips_FixedArg;
3032 const SDLoc &
DL,
bool IsTailCall,
3050 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3051 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
3064 if (IsPICCall && !InternalLinkage && IsCallReloc) {
3065 unsigned GPReg =
ABI.
IsN64() ? Mips::GP_64 : Mips::GP;
3067 RegsToPass.push_back(std::make_pair(GPReg,
getGlobalReg(CLI.
DAG, Ty)));
3076 for (
auto &R : RegsToPass) {
3083 for (
auto &R : RegsToPass)
3090 assert(Mask &&
"Missing call preserved mask for calling convention");
3094 Function *
F =
G->getGlobal()->getParent()->getFunction(
Sym);
3095 if (
F &&
F->hasFnAttribute(
"__Mips16RetHelper")) {
3108 switch (
MI.getOpcode()) {
3112 case Mips::JALRPseudo:
3114 case Mips::JALR64Pseudo:
3115 case Mips::JALR16_MM:
3116 case Mips::JALRC16_MMR6:
3117 case Mips::TAILCALLREG:
3118 case Mips::TAILCALLREG64:
3119 case Mips::TAILCALLR6REG:
3120 case Mips::TAILCALL64R6REG:
3121 case Mips::TAILCALLREG_MM:
3122 case Mips::TAILCALLREG_MMR6: {
3126 Node->getNumOperands() < 1 ||
3127 Node->getOperand(0).getNumOperands() < 2) {
3133 const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
3136 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3140 if (!isa<Function>(
G->getGlobal())) {
3141 LLVM_DEBUG(
dbgs() <<
"Not adding R_MIPS_JALR against data symbol "
3142 <<
G->getGlobal()->getName() <<
"\n");
3145 Sym =
G->getGlobal()->getName();
3148 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3149 Sym = ES->getSymbol();
3192 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3218 bool MemcpyInByVal = ES &&
3225 unsigned ReservedArgArea =
3227 CCInfo.AllocateStack(ReservedArgArea,
Align(1));
3233 unsigned StackSize = CCInfo.getStackSize();
3240 bool InternalLinkage =
false;
3242 IsTailCall = isEligibleForTailCallOptimization(
3245 InternalLinkage =
G->getGlobal()->hasInternalLinkage();
3246 IsTailCall &= (InternalLinkage ||
G->getGlobal()->hasLocalLinkage() ||
3247 G->getGlobal()->hasPrivateLinkage() ||
3248 G->getGlobal()->hasHiddenVisibility() ||
3249 G->getGlobal()->hasProtectedVisibility());
3254 "site marked musttail");
3263 StackSize =
alignTo(StackSize, StackAlignment);
3265 if (!(IsTailCall || MemcpyInByVal))
3272 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3275 CCInfo.rewindByValRegsInfo();
3278 for (
unsigned i = 0, e = ArgLocs.
size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3279 SDValue Arg = OutVals[OutIdx];
3283 bool UseUpperBits =
false;
3286 if (
Flags.isByVal()) {
3287 unsigned FirstByValReg, LastByValReg;
3288 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3289 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3292 "ByVal args of size 0 should have been ignored by front-end.");
3293 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3295 "Do not tail-call optimize if there is a byval argument.");
3296 passByValArg(Chain,
DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3299 CCInfo.nextInRegsParam();
3309 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3310 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3311 (ValVT == MVT::i64 && LocVT == MVT::f64))
3313 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3324 Register LocRegHigh = ArgLocs[++i].getLocReg();
3325 RegsToPass.
push_back(std::make_pair(LocRegLo,
Lo));
3326 RegsToPass.push_back(std::make_pair(LocRegHigh,
Hi));
3335 UseUpperBits =
true;
3341 UseUpperBits =
true;
3347 UseUpperBits =
true;
3355 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3365 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), Arg));
3374 if (
Options.SupportsDebugEntryValues)
3386 Chain, Arg,
DL, IsTailCall, DAG));
3391 if (!MemOpChains.
empty())
3399 bool GlobalOrExternal =
false, IsCallReloc =
false;
3408 if (
auto *
N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3413 }
else if (
auto *
N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3417 if (
auto *
F = dyn_cast<Function>(
N->getGlobal())) {
3418 if (
F->hasFnAttribute(
"long-call"))
3419 UseLongCalls =
true;
3420 else if (
F->hasFnAttribute(
"short-call"))
3421 UseLongCalls =
false;
3435 if (InternalLinkage)
3451 GlobalOrExternal =
true;
3454 const char *
Sym = S->getSymbol();
3470 GlobalOrExternal =
true;
3476 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3477 IsCallReloc, CLI, Callee, Chain);
3493 if (!(MemcpyInByVal)) {
3500 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins,
DL, DAG,
3506SDValue MipsTargetLowering::LowerCallResult(
3517 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.
Callee.
getNode());
3518 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.
RetTy,
3522 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3527 RVLocs[i].getLocVT(), InGlue);
3532 unsigned ValSizeInBits =
Ins[i].ArgVT.getSizeInBits();
3633SDValue MipsTargetLowering::LowerFormalArguments(
3644 std::vector<SDValue> OutChains;
3654 if (
Func.hasFnAttribute(
"interrupt") && !
Func.arg_empty())
3656 "Functions with the interrupt attribute cannot have arguments!");
3658 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3660 CCInfo.getInRegsParamsCount() > 0);
3662 unsigned CurArgIdx = 0;
3663 CCInfo.rewindByValRegsInfo();
3665 for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3667 if (Ins[InsIdx].isOrigArg()) {
3668 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3669 CurArgIdx =
Ins[InsIdx].getOrigArgIndex();
3675 if (
Flags.isByVal()) {
3676 assert(Ins[InsIdx].isOrigArg() &&
"Byval arguments cannot be implicit");
3677 unsigned FirstByValReg, LastByValReg;
3678 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3679 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3682 "ByVal args of size 0 should have been ignored by front-end.");
3683 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3684 copyByValRegs(Chain,
DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3685 FirstByValReg, LastByValReg, VA, CCInfo);
3686 CCInfo.nextInRegsParam();
3706 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3707 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3708 (RegVT == MVT::f64 && ValVT == MVT::i64))
3710 else if (
ABI.
IsO32() && RegVT == MVT::i32 &&
3711 ValVT == MVT::f64) {
3720 ArgValue, ArgValue2);
3739 LocVT,
DL, Chain, FIN,
3741 OutChains.push_back(ArgValue.
getValue(1));
3750 for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3752 if (ArgLocs[i].needsCustom()) {
3760 if (Ins[InsIdx].
Flags.isSRet()) {
3774 writeVarArgRegs(OutChains, Chain,
DL, DAG, CCInfo);
3778 if (!OutChains.empty()) {
3779 OutChains.push_back(Chain);
3796 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3797 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3800bool MipsTargetLowering::shouldSignExtendTypeInLibCall(
EVT Type,
3801 bool IsSigned)
const {
3835 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3841 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3845 bool UseUpperBits =
false;
3856 UseUpperBits =
true;
3862 UseUpperBits =
true;
3868 UseUpperBits =
true;
3876 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3902 unsigned V0 =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
3917 return LowerInterruptReturn(RetOps,
DL, DAG);
3930MipsTargetLowering::getConstraintType(
StringRef Constraint)
const {
3942 if (Constraint.
size() == 1) {
3943 switch (Constraint[0]) {
3957 if (Constraint ==
"ZC")
3967MipsTargetLowering::getSingleConstraintMatchWeight(
3968 AsmOperandInfo &
info,
const char *constraint)
const {
3970 Value *CallOperandVal =
info.CallOperandVal;
3973 if (!CallOperandVal)
3977 switch (*constraint) {
4006 if (isa<ConstantInt>(CallOperandVal))
4021 unsigned long long &Reg) {
4022 if (
C.front() !=
'{' ||
C.back() !=
'}')
4023 return std::make_pair(
false,
false);
4027 I = std::find_if(
B,
E, isdigit);
4033 return std::make_pair(
true,
false);
4044 return VT.
bitsLT(MinVT) ? MinVT : VT;
4047std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4053 unsigned long long Reg;
4058 return std::make_pair(0U,
nullptr);
4060 if ((Prefix ==
"hi" || Prefix ==
"lo")) {
4063 return std::make_pair(0U,
nullptr);
4065 RC =
TRI->getRegClass(Prefix ==
"hi" ?
4066 Mips::HI32RegClassID : Mips::LO32RegClassID);
4067 return std::make_pair(*(RC->
begin()), RC);
4068 }
else if (Prefix.starts_with(
"$msa")) {
4073 return std::make_pair(0U,
nullptr);
4076 .
Case(
"$msair", Mips::MSAIR)
4077 .
Case(
"$msacsr", Mips::MSACSR)
4078 .
Case(
"$msaaccess", Mips::MSAAccess)
4079 .
Case(
"$msasave", Mips::MSASave)
4080 .
Case(
"$msamodify", Mips::MSAModify)
4081 .
Case(
"$msarequest", Mips::MSARequest)
4082 .
Case(
"$msamap", Mips::MSAMap)
4083 .
Case(
"$msaunmap", Mips::MSAUnmap)
4087 return std::make_pair(0U,
nullptr);
4089 RC =
TRI->getRegClass(Mips::MSACtrlRegClassID);
4090 return std::make_pair(Reg, RC);
4094 return std::make_pair(0U,
nullptr);
4096 if (Prefix ==
"$f") {
4099 if (VT == MVT::Other)
4104 if (RC == &Mips::AFGR64RegClass) {
4108 }
else if (Prefix ==
"$fcc")
4109 RC =
TRI->getRegClass(Mips::FCCRegClassID);
4110 else if (Prefix ==
"$w") {
4117 assert(Reg < RC->getNumRegs());
4118 return std::make_pair(*(RC->
begin() + Reg), RC);
4124std::pair<unsigned, const TargetRegisterClass *>
4128 if (Constraint.
size() == 1) {
4129 switch (Constraint[0]) {
4133 if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
4137 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4138 return std::make_pair(0U, &Mips::GPR32RegClass);
4142 return std::make_pair(0U, &Mips::GPR32RegClass);
4145 return std::make_pair(0U, &Mips::GPR64RegClass);
4147 return std::make_pair(0U,
nullptr);
4149 if (VT == MVT::v16i8)
4150 return std::make_pair(0U, &Mips::MSA128BRegClass);
4151 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
4152 return std::make_pair(0U, &Mips::MSA128HRegClass);
4153 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
4154 return std::make_pair(0U, &Mips::MSA128WRegClass);
4155 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
4156 return std::make_pair(0U, &Mips::MSA128DRegClass);
4157 else if (VT == MVT::f32)
4158 return std::make_pair(0U, &Mips::FGR32RegClass);
4161 return std::make_pair(0U, &Mips::FGR64RegClass);
4162 return std::make_pair(0U, &Mips::AFGR64RegClass);
4167 return std::make_pair((
unsigned)Mips::T9, &Mips::GPR32RegClass);
4169 return std::make_pair((
unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4171 return std::make_pair(0U,
nullptr);
4174 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4175 return std::make_pair((
unsigned)Mips::LO0, &Mips::LO32RegClass);
4176 return std::make_pair((
unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4181 return std::make_pair(0U,
nullptr);
4185 if (!Constraint.
empty()) {
4186 std::pair<unsigned, const TargetRegisterClass *>
R;
4187 R = parseRegForInlineAsmConstraint(Constraint, VT);
4198void MipsTargetLowering::LowerAsmOperandForConstraint(
SDValue Op,
4200 std::vector<SDValue> &Ops,
4206 if (Constraint.
size() > 1)
4209 char ConstraintLetter = Constraint[0];
4210 switch (ConstraintLetter) {
4216 int64_t Val =
C->getSExtValue();
4217 if (isInt<16>(Val)) {
4226 int64_t Val =
C->getZExtValue();
4237 if (isUInt<16>(Val)) {
4246 int64_t Val =
C->getSExtValue();
4247 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4256 int64_t Val =
C->getSExtValue();
4257 if ((Val >= -65535) && (Val <= -1)) {
4266 int64_t Val =
C->getSExtValue();
4267 if ((isInt<15>(Val))) {
4276 int64_t Val =
C->getSExtValue();
4277 if ((Val <= 65535) && (Val >= 1)) {
4286 Ops.push_back(Result);
4293bool MipsTargetLowering::isLegalAddressingMode(
const DataLayout &
DL,
4321EVT MipsTargetLowering::getOptimalMemOpType(
4329bool MipsTargetLowering::isFPImmLegal(
const APFloat &Imm,
EVT VT,
4330 bool ForCodeSize)
const {
4331 if (VT != MVT::f32 && VT != MVT::f64)
4333 if (
Imm.isNegZero())
4335 return Imm.isZero();
4338unsigned MipsTargetLowering::getJumpTableEncoding()
const {
4347bool MipsTargetLowering::useSoftFloat()
const {
4351void MipsTargetLowering::copyByValRegs(
4355 unsigned FirstReg,
unsigned LastReg,
const CCValAssign &VA,
4360 unsigned NumRegs = LastReg - FirstReg;
4361 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4362 unsigned FrameObjSize = std::max(
Flags.getByValSize(), RegAreaSize);
4369 (
int)((ByValArgRegs.
size() - FirstReg) * GPRSizeInBytes);
4391 for (
unsigned I = 0;
I < NumRegs; ++
I) {
4392 unsigned ArgReg = ByValArgRegs[FirstReg +
I];
4393 unsigned VReg =
addLiveIn(MF, ArgReg, RC);
4394 unsigned Offset =
I * GPRSizeInBytes;
4399 OutChains.push_back(Store);
4404void MipsTargetLowering::passByValArg(
4406 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4411 unsigned ByValSizeInBytes =
Flags.getByValSize();
4412 unsigned OffsetInBytes = 0;
4415 std::min(
Flags.getNonZeroByValAlign(),
Align(RegSizeInBytes));
4418 unsigned NumRegs = LastReg - FirstReg;
4422 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4426 for (;
I < NumRegs - LeftoverBytes; ++
I, OffsetInBytes += RegSizeInBytes) {
4432 unsigned ArgReg = ArgRegs[FirstReg +
I];
4433 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4437 if (ByValSizeInBytes == OffsetInBytes)
4441 if (LeftoverBytes) {
4444 for (
unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4445 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4446 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4448 if (RemainingSizeInBytes < LoadSizeInBytes)
4464 Shamt = TotalBytesLoaded * 8;
4466 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4476 OffsetInBytes += LoadSizeInBytes;
4477 TotalBytesLoaded += LoadSizeInBytes;
4478 Alignment = std::min(Alignment,
Align(LoadSizeInBytes));
4481 unsigned ArgReg = ArgRegs[FirstReg +
I];
4482 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4488 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4495 Align(Alignment),
false,
false,
4500void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4521 (
int)(RegSizeInBytes * (ArgRegs.
size() -
Idx));
4533 for (
unsigned I =
Idx;
I < ArgRegs.
size();
4534 ++
I, VaArgOffset += RegSizeInBytes) {
4541 cast<StoreSDNode>(
Store.getNode())->getMemOperand()->setValue(
4543 OutChains.push_back(Store);
4548 Align Alignment)
const {
4551 assert(
Size &&
"Byval argument's size shouldn't be 0.");
4555 unsigned FirstReg = 0;
4556 unsigned NumRegs = 0;
4568 Alignment >=
Align(RegSizeInBytes) &&
4569 "Byval argument's alignment should be a multiple of RegSizeInBytes.");
4577 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) {
4578 State->
AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4584 for (
unsigned I = FirstReg;
Size > 0 && (
I < IntArgRegs.
size());
4585 Size -= RegSizeInBytes, ++
I, ++NumRegs)
4595 unsigned Opc)
const {
4597 "Subtarget already supports SELECT nodes with the use of"
4598 "conditional-move instructions.");
4621 F->insert(It, copy0MBB);
4622 F->insert(It, sinkMBB);
4665 MI.eraseFromParent();
4674 "Subtarget already supports SELECT nodes with the use of"
4675 "conditional-move instructions.");
4698 F->insert(It, copy0MBB);
4699 F->insert(It, sinkMBB);
4741 MI.eraseFromParent();
4754 .
Case(
"$28", Mips::GP_64)
4755 .
Case(
"sp", Mips::SP_64)
4761 .
Case(
"$28", Mips::GP)
4762 .
Case(
"sp", Mips::SP)
4780 unsigned Imm =
MI.getOperand(2).getImm();
4786 Register Temp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4795 Register LoadHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4796 Register LoadFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4797 Register Undef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4802 .
addImm(Imm + (IsLittle ? 0 : 3))
4807 .
addImm(Imm + (IsLittle ? 3 : 0))
4812 MI.eraseFromParent();
4826 unsigned Imm =
MI.getOperand(2).getImm();
4833 Register Temp =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
4840 Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4841 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4842 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4846 .
addImm(Imm + (IsLittle ? 0 : 4));
4850 .
addImm(Imm + (IsLittle ? 4 : 0));
4860 Register LoHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4861 Register LoFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4862 Register LoUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4863 Register HiHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4864 Register HiFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4865 Register HiUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4866 Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4871 .
addImm(Imm + (IsLittle ? 0 : 7))
4876 .
addImm(Imm + (IsLittle ? 3 : 4))
4882 .
addImm(Imm + (IsLittle ? 4 : 3))
4887 .
addImm(Imm + (IsLittle ? 7 : 0))
4896 MI.eraseFromParent();
4908 Register StoreVal =
MI.getOperand(0).getReg();
4910 unsigned Imm =
MI.getOperand(2).getImm();
4916 Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4917 Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4930 Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4938 .
addImm(Imm + (IsLittle ? 0 : 3));
4942 .
addImm(Imm + (IsLittle ? 3 : 0));
4945 MI.eraseFromParent();
4958 Register StoreVal =
MI.getOperand(0).getReg();
4960 unsigned Imm =
MI.getOperand(2).getImm();
4967 Register BitcastD =
MRI.createVirtualRegister(&Mips::MSA128DRegClass);
4968 Register Lo =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
4981 Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4982 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4983 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4998 .
addImm(Imm + (IsLittle ? 0 : 4));
5002 .
addImm(Imm + (IsLittle ? 4 : 0));
5008 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5009 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5022 .
addImm(Imm + (IsLittle ? 0 : 3));
5026 .
addImm(Imm + (IsLittle ? 3 : 0));
5030 .
addImm(Imm + (IsLittle ? 4 : 7));
5034 .
addImm(Imm + (IsLittle ? 7 : 4));
5037 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
unsigned const TargetRegisterInfo * TRI
cl::opt< bool > EmitJalrReloc
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget)
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat)
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static const MCPhysReg Mips64DPRegs[8]
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
cl::opt< bool > EmitJalrReloc
static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file defines the SmallVector class.
static const MCPhysReg IntRegs[32]
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static const MCPhysReg F32Regs[64]
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
static BranchProbability getOne()
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
CallingConv::ID getCallingConv() const
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
bool isUpperBitsInLoc() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
int64_t getLocMemOffset() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
const char * getSymbol() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalValue * getGlobal() const
bool hasLocalLinkage() const
const GlobalObject * getAliaseeObject() const
bool hasInternalLinkage() const
Class to represent integer types.
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This class is used to represent ISD::LOAD nodes.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
static auto fp_fixedlen_vector_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
@ EK_GPRel64BlockAddress
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative,...
@ MOVolatile
The memory access is volatile.
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
bool ArePtrs64bit() const
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
unsigned GetPtrAddiuOp() const
unsigned GetPtrAndOp() const
ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
unsigned GetNullPtr() const
bool WasOriginalArgVectorFloat(unsigned ValNo) const
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
void setVarArgsFrameIndex(int Index)
unsigned getSRetReturnReg() const
int getVarArgsFrameIndex() const
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
Register getGlobalBaseReg(MachineFunction &MF)
void setSRetReturnReg(unsigned Reg)
void setFormalArgInfo(unsigned Size, bool HasByval)
static const uint32_t * getMips16RetHelperMask()
bool inMicroMipsMode() const
bool useSoftFloat() const
const MipsInstrInfo * getInstrInfo() const override
bool inMips16Mode() const
bool inAbs2008Mode() const
const MipsRegisterInfo * getRegisterInfo() const override
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool isSingleFloat() const
bool useLongCalls() const
unsigned getGPRSizeInBytes() const
bool inMips16HardFloat() const
const TargetFrameLowering * getFrameLowering() const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
const DataLayout & getDataLayout() const
void addCallSiteInfo(const SDNode *Node, CallSiteInfoImpl &&CallInfo)
Set CallSiteInfo to be associated with Node.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getValue() const
bool isTruncatingStore() const
Return true if the op does a truncation before store.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual TargetLoweringObjectFile * getObjFileLowering() const
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
constexpr ScalarTy getFixedValue() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ Bitcast
Perform the operation on a different, but equivalently sized type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ EarlyClobber
Register definition happens before uses.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
@ Or
Bitwise or logical OR of integers.
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
bool isVector() const
Return true if this is a vector value type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isRound() const
Return true if the size is a power-of-two number of bytes.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Align getNonZeroOrigAlign() const
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalizeOps() const