LLVM 19.0.0git
MipsMachineFunction.cpp
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1//===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "MipsSubtarget.h"
12#include "MipsTargetMachine.h"
19
20using namespace llvm;
21
22static cl::opt<bool>
23FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
24 cl::desc("Always use $gp as the global base register."));
25
29 &Src2DstMBB) const {
30 return DestMF.cloneInfo<MipsFunctionInfo>(*this);
31}
32
34
36 return GlobalBaseReg;
37}
38
40 auto &STI = MF.getSubtarget<MipsSubtarget>();
41 auto &TM = static_cast<const MipsTargetMachine &>(MF.getTarget());
42
43 if (STI.inMips16Mode())
44 return Mips::CPU16RegsRegClass;
45
46 if (STI.inMicroMipsMode())
47 return Mips::GPRMM16RegClass;
48
49 if (TM.getABI().IsN64())
50 return Mips::GPR64RegClass;
51
52 return Mips::GPR32RegClass;
53}
54
56 if (!GlobalBaseReg)
57 GlobalBaseReg =
59 return GlobalBaseReg;
60}
61
63 if (!GlobalBaseReg) {
66 }
67 return GlobalBaseReg;
68}
69
71 if (!GlobalBaseReg)
72 return;
73
76 MachineRegisterInfo &RegInfo = MF.getRegInfo();
79 const TargetRegisterClass *RC;
80 const MipsABIInfo &ABI =
81 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
82 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
83
84 Register V0 = RegInfo.createVirtualRegister(RC);
85 Register V1 = RegInfo.createVirtualRegister(RC);
86
87 if (ABI.IsN64()) {
88 MF.getRegInfo().addLiveIn(Mips::T9_64);
89 MBB.addLiveIn(Mips::T9_64);
90
91 // lui $v0, %hi(%neg(%gp_rel(fname)))
92 // daddu $v1, $v0, $t9
93 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
94 const GlobalValue *FName = &MF.getFunction();
95 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
97 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
98 .addReg(Mips::T9_64);
99 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
101 return;
102 }
103
104 if (!MF.getTarget().isPositionIndependent()) {
105 // Set global register to __gnu_local_gp.
106 //
107 // lui $v0, %hi(__gnu_local_gp)
108 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
109 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
110 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
111 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
112 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
113 return;
114 }
115
116 MF.getRegInfo().addLiveIn(Mips::T9);
117 MBB.addLiveIn(Mips::T9);
118
119 if (ABI.IsN32()) {
120 // lui $v0, %hi(%neg(%gp_rel(fname)))
121 // addu $v1, $v0, $t9
122 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
123 const GlobalValue *FName = &MF.getFunction();
124 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
126 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
127 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
129 return;
130 }
131
132 assert(ABI.IsO32());
133
134 // For O32 ABI, the following instruction sequence is emitted to initialize
135 // the global base register:
136 //
137 // 0. lui $2, %hi(_gp_disp)
138 // 1. addiu $2, $2, %lo(_gp_disp)
139 // 2. addu $globalbasereg, $2, $t9
140 //
141 // We emit only the last instruction here.
142 //
143 // GNU linker requires that the first two instructions appear at the beginning
144 // of a function and no instructions be inserted before or between them.
145 // The two instructions are emitted during lowering to MC layer in order to
146 // avoid any reordering.
147 //
148 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
149 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
150 // reads it.
151 MF.getRegInfo().addLiveIn(Mips::V0);
152 MBB.addLiveIn(Mips::V0);
153 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
154 .addReg(Mips::V0).addReg(Mips::T9);
155}
156
159 for (int &I : EhDataRegFI) {
160 const TargetRegisterClass &RC =
161 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
162 ? Mips::GPR64RegClass
163 : Mips::GPR32RegClass;
164
165 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
166 TRI.getSpillAlign(RC), false);
167 }
168}
169
171 // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
172 // The current implementation only supports Mips32r2+ not Mips64rX. Status
173 // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
174 // however Mips32r2+ is the supported architecture.
175 const TargetRegisterClass &RC = Mips::GPR32RegClass;
177
178 for (int &I : ISRDataRegFI)
179 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
180 TRI.getSpillAlign(RC), false);
181}
182
184 return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
185 || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
186}
187
189 return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
190}
192 const char *ES) {
194}
195
197 const GlobalValue *GV) {
199}
200
202 const TargetRegisterClass *RC) {
204 if (MoveF64ViaSpillFI == -1) {
205 MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
206 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false);
207 }
208 return MoveF64ViaSpillFI;
209}
210
211void MipsFunctionInfo::anchor() {}
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static cl::opt< bool > FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), cl::desc("Always use $gp as the global base register."))
static const TargetRegisterClass & getGlobalBaseRegClass(MachineFunction &MF)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
A debug info location.
Definition: DebugLoc.h:33
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
PseudoSourceValueManager & getPSVManager() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * cloneInfo(const Ty &Old)
const MachineBasicBlock & front() const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Register getGlobalBaseRegForGlobalISel(MachineFunction &MF)
bool isISRRegFI(int FI) const
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
int getMoveF64ViaSpillFI(MachineFunction &MF, const TargetRegisterClass *RC)
Register getGlobalBaseReg(MachineFunction &MF)
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool isEhDataRegFI(int FI) const
void createEhDataRegsFI(MachineFunction &MF)
void initGlobalBaseReg(MachineFunction &MF)
~MipsFunctionInfo() override
void createISRRegFI(MachineFunction &MF)
const PseudoSourceValue * getExternalSymbolCallEntry(const char *ES)
const PseudoSourceValue * getGlobalValueCallEntry(const GlobalValue *GV)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetInstrInfo - Interface to description of machine instruction set.
bool isPositionIndependent() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
This class contains a discriminated union of information about pointers in memory operands,...