LLVM  9.0.0svn
MipsSEISelLowering.cpp
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1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsTargetLowering specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelLowering.h"
14 #include "MipsMachineFunction.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Triple.h"
35 #include "llvm/IR/DebugLoc.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/Casting.h"
39 #include "llvm/Support/Debug.h"
44 #include <algorithm>
45 #include <cassert>
46 #include <cstdint>
47 #include <iterator>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "mips-isel"
53 
54 static cl::opt<bool>
55 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
56  cl::desc("MIPS: permit tail calls."), cl::init(false));
57 
58 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
59  cl::desc("Expand double precision loads and "
60  "stores to their single precision "
61  "counterparts"));
62 
64  const MipsSubtarget &STI)
65  : MipsTargetLowering(TM, STI) {
66  // Set up the register classes
67  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
68 
69  if (Subtarget.isGP64bit())
70  addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
71 
72  if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
73  // Expand all truncating stores and extending loads.
74  for (MVT VT0 : MVT::vector_valuetypes()) {
75  for (MVT VT1 : MVT::vector_valuetypes()) {
76  setTruncStoreAction(VT0, VT1, Expand);
80  }
81  }
82  }
83 
84  if (Subtarget.hasDSP()) {
86 
87  for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
88  addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
89 
90  // Expand all builtin opcodes.
91  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
92  setOperationAction(Opc, VecTys[i], Expand);
93 
94  setOperationAction(ISD::ADD, VecTys[i], Legal);
95  setOperationAction(ISD::SUB, VecTys[i], Legal);
96  setOperationAction(ISD::LOAD, VecTys[i], Legal);
97  setOperationAction(ISD::STORE, VecTys[i], Legal);
99  }
100 
106 
107  if (Subtarget.hasMips32r2()) {
110  }
111  }
112 
113  if (Subtarget.hasDSPR2())
115 
116  if (Subtarget.hasMSA()) {
117  addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
118  addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
119  addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
120  addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
121  addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
122  addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
123  addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
124 
125  // f16 is a storage-only type, always promote it to f32.
126  addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
162 
168  }
169 
170  if (!Subtarget.useSoftFloat()) {
171  addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
172 
173  // When dealing with single precision only, use libcalls
174  if (!Subtarget.isSingleFloat()) {
175  if (Subtarget.isFP64bit())
176  addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
177  else
178  addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
179  }
180  }
181 
186 
187  if (Subtarget.hasCnMips())
189  else if (Subtarget.isGP64bit())
191 
192  if (Subtarget.isGP64bit()) {
199  }
200 
203 
209 
211 
215 
217  !Subtarget.hasMips64()) {
219  }
220 
221  if (NoDPLoadStore) {
224  }
225 
226  if (Subtarget.hasMips32r6()) {
227  // MIPS32r6 replaces the accumulator-based multiplies with a three register
228  // instruction
234 
235  // MIPS32r6 replaces the accumulator-based division/remainder with separate
236  // three register division and remainder instructions.
243 
244  // MIPS32r6 replaces conditional moves with an equivalent that removes the
245  // need for three GPR read ports.
249 
253 
254  assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
258 
260 
261  // Floating point > and >= are supported via < and <=
266 
271  }
272 
273  if (Subtarget.hasMips64r6()) {
274  // MIPS64r6 replaces the accumulator-based multiplies with a three register
275  // instruction
281 
282  // MIPS32r6 replaces the accumulator-based division/remainder with separate
283  // three register division and remainder instructions.
290 
291  // MIPS64r6 replaces conditional moves with an equivalent that removes the
292  // need for three GPR read ports.
296  }
297 
299 }
300 
301 const MipsTargetLowering *
303  const MipsSubtarget &STI) {
304  return new MipsSETargetLowering(TM, STI);
305 }
306 
307 const TargetRegisterClass *
309  if (VT == MVT::Untyped)
310  return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
311 
313 }
314 
315 // Enable MSA support for the given integer type and Register class.
318  addRegisterClass(Ty, RC);
319 
320  // Expand all builtin opcodes.
321  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
322  setOperationAction(Opc, Ty, Expand);
323 
330 
352 
353  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
358  }
359 
366 }
367 
368 // Enable MSA support for the given floating-point type and Register class.
371  addRegisterClass(Ty, RC);
372 
373  // Expand all builtin opcodes.
374  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
375  setOperationAction(Opc, Ty, Expand);
376 
383 
384  if (Ty != MVT::v8f16) {
396 
404  }
405 }
406 
407 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
408  if(!Subtarget.hasMips32r6())
409  return MipsTargetLowering::LowerOperation(Op, DAG);
410 
411  EVT ResTy = Op->getValueType(0);
412  SDLoc DL(Op);
413 
414  // Although MTC1_D64 takes an i32 and writes an f64, the upper 32 bits of the
415  // floating point register are undefined. Not really an issue as sel.d, which
416  // is produced from an FSELECT node, only looks at bit 0.
417  SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
418  return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
419  Op->getOperand(2));
420 }
421 
422 bool
424  unsigned,
425  unsigned,
426  bool *Fast) const {
428 
430  // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
431  // implementation defined whether this is handled by hardware, software, or
432  // a hybrid of the two but it's expected that most implementations will
433  // handle the majority of cases in hardware.
434  if (Fast)
435  *Fast = true;
436  return true;
437  }
438 
439  switch (SVT) {
440  case MVT::i64:
441  case MVT::i32:
442  if (Fast)
443  *Fast = true;
444  return true;
445  default:
446  return false;
447  }
448 }
449 
451  SelectionDAG &DAG) const {
452  switch(Op.getOpcode()) {
453  case ISD::LOAD: return lowerLOAD(Op, DAG);
454  case ISD::STORE: return lowerSTORE(Op, DAG);
455  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
456  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
457  case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
458  case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
459  case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
460  case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
461  case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
462  DAG);
463  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
464  case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
465  case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
466  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
467  case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
468  case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
469  case ISD::SELECT: return lowerSELECT(Op, DAG);
470  case ISD::BITCAST: return lowerBITCAST(Op, DAG);
471  }
472 
473  return MipsTargetLowering::LowerOperation(Op, DAG);
474 }
475 
476 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
477 //
478 // Performs the following transformations:
479 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
480 // sign/zero-extension is completely overwritten by the new one performed by
481 // the ISD::AND.
482 // - Removes redundant zero extensions performed by an ISD::AND.
485  const MipsSubtarget &Subtarget) {
486  if (!Subtarget.hasMSA())
487  return SDValue();
488 
489  SDValue Op0 = N->getOperand(0);
490  SDValue Op1 = N->getOperand(1);
491  unsigned Op0Opcode = Op0->getOpcode();
492 
493  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
494  // where $d + 1 == 2^n and n == 32
495  // or $d + 1 == 2^n and n <= 32 and ZExt
496  // -> (MipsVExtractZExt $a, $b, $c)
497  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
498  Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
500 
501  if (!Mask)
502  return SDValue();
503 
504  int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
505 
506  if (Log2IfPositive <= 0)
507  return SDValue(); // Mask+1 is not a power of 2
508 
509  SDValue Op0Op2 = Op0->getOperand(2);
510  EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
511  unsigned ExtendTySize = ExtendTy.getSizeInBits();
512  unsigned Log2 = Log2IfPositive;
513 
514  if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
515  Log2 == ExtendTySize) {
516  SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
517  return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
518  Op0->getVTList(),
519  makeArrayRef(Ops, Op0->getNumOperands()));
520  }
521  }
522 
523  return SDValue();
524 }
525 
526 // Determine if the specified node is a constant vector splat.
527 //
528 // Returns true and sets Imm if:
529 // * N is a ISD::BUILD_VECTOR representing a constant splat
530 //
531 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
532 // differences are that it assumes the MSA has already been checked and the
533 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
534 // must not be in order for binsri.d to be selectable).
535 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
537 
538  if (!Node)
539  return false;
540 
541  APInt SplatValue, SplatUndef;
542  unsigned SplatBitSize;
543  bool HasAnyUndefs;
544 
545  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
546  8, !IsLittleEndian))
547  return false;
548 
549  Imm = SplatValue;
550 
551  return true;
552 }
553 
554 // Test whether the given node is an all-ones build_vector.
555 static bool isVectorAllOnes(SDValue N) {
556  // Look through bitcasts. Endianness doesn't matter because we are looking
557  // for an all-ones value.
558  if (N->getOpcode() == ISD::BITCAST)
559  N = N->getOperand(0);
560 
562 
563  if (!BVN)
564  return false;
565 
566  APInt SplatValue, SplatUndef;
567  unsigned SplatBitSize;
568  bool HasAnyUndefs;
569 
570  // Endianness doesn't matter in this context because we are looking for
571  // an all-ones value.
572  if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
573  return SplatValue.isAllOnesValue();
574 
575  return false;
576 }
577 
578 // Test whether N is the bitwise inverse of OfNode.
579 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
580  if (N->getOpcode() != ISD::XOR)
581  return false;
582 
583  if (isVectorAllOnes(N->getOperand(0)))
584  return N->getOperand(1) == OfNode;
585 
586  if (isVectorAllOnes(N->getOperand(1)))
587  return N->getOperand(0) == OfNode;
588 
589  return false;
590 }
591 
592 // Perform combines where ISD::OR is the root node.
593 //
594 // Performs the following transformations:
595 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
596 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
597 // vector type.
600  const MipsSubtarget &Subtarget) {
601  if (!Subtarget.hasMSA())
602  return SDValue();
603 
604  EVT Ty = N->getValueType(0);
605 
606  if (!Ty.is128BitVector())
607  return SDValue();
608 
609  SDValue Op0 = N->getOperand(0);
610  SDValue Op1 = N->getOperand(1);
611 
612  if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
613  SDValue Op0Op0 = Op0->getOperand(0);
614  SDValue Op0Op1 = Op0->getOperand(1);
615  SDValue Op1Op0 = Op1->getOperand(0);
616  SDValue Op1Op1 = Op1->getOperand(1);
617  bool IsLittleEndian = !Subtarget.isLittle();
618 
619  SDValue IfSet, IfClr, Cond;
620  bool IsConstantMask = false;
621  APInt Mask, InvMask;
622 
623  // If Op0Op0 is an appropriate mask, try to find it's inverse in either
624  // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
625  // looking.
626  // IfClr will be set if we find a valid match.
627  if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
628  Cond = Op0Op0;
629  IfSet = Op0Op1;
630 
631  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
632  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
633  IfClr = Op1Op1;
634  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
635  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
636  IfClr = Op1Op0;
637 
638  IsConstantMask = true;
639  }
640 
641  // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
642  // thing again using this mask.
643  // IfClr will be set if we find a valid match.
644  if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
645  Cond = Op0Op1;
646  IfSet = Op0Op0;
647 
648  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
649  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
650  IfClr = Op1Op1;
651  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
652  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
653  IfClr = Op1Op0;
654 
655  IsConstantMask = true;
656  }
657 
658  // If IfClr is not yet set, try looking for a non-constant match.
659  // IfClr will be set if we find a valid match amongst the eight
660  // possibilities.
661  if (!IfClr.getNode()) {
662  if (isBitwiseInverse(Op0Op0, Op1Op0)) {
663  Cond = Op1Op0;
664  IfSet = Op1Op1;
665  IfClr = Op0Op1;
666  } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
667  Cond = Op1Op0;
668  IfSet = Op1Op1;
669  IfClr = Op0Op0;
670  } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
671  Cond = Op1Op1;
672  IfSet = Op1Op0;
673  IfClr = Op0Op1;
674  } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
675  Cond = Op1Op1;
676  IfSet = Op1Op0;
677  IfClr = Op0Op0;
678  } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
679  Cond = Op0Op0;
680  IfSet = Op0Op1;
681  IfClr = Op1Op1;
682  } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
683  Cond = Op0Op0;
684  IfSet = Op0Op1;
685  IfClr = Op1Op0;
686  } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
687  Cond = Op0Op1;
688  IfSet = Op0Op0;
689  IfClr = Op1Op1;
690  } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
691  Cond = Op0Op1;
692  IfSet = Op0Op0;
693  IfClr = Op1Op0;
694  }
695  }
696 
697  // At this point, IfClr will be set if we have a valid match.
698  if (!IfClr.getNode())
699  return SDValue();
700 
701  assert(Cond.getNode() && IfSet.getNode());
702 
703  // Fold degenerate cases.
704  if (IsConstantMask) {
705  if (Mask.isAllOnesValue())
706  return IfSet;
707  else if (Mask == 0)
708  return IfClr;
709  }
710 
711  // Transform the DAG into an equivalent VSELECT.
712  return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
713  }
714 
715  return SDValue();
716 }
717 
719  SelectionDAG &DAG,
720  const MipsSubtarget &Subtarget) {
721  // Estimate the number of operations the below transform will turn a
722  // constant multiply into. The number is approximately how many powers
723  // of two summed together that the constant can be broken down into.
724 
725  SmallVector<APInt, 16> WorkStack(1, C);
726  unsigned Steps = 0;
727  unsigned BitWidth = C.getBitWidth();
728 
729  while (!WorkStack.empty()) {
730  APInt Val = WorkStack.pop_back_val();
731 
732  if (Val == 0 || Val == 1)
733  continue;
734 
735  if (Val.isPowerOf2()) {
736  ++Steps;
737  continue;
738  }
739 
740  APInt Floor = APInt(BitWidth, 1) << Val.logBase2();
741  APInt Ceil = Val.isNegative() ? APInt(BitWidth, 0)
742  : APInt(BitWidth, 1) << C.ceilLogBase2();
743 
744  if ((Val - Floor).ule(Ceil - Val)) {
745  WorkStack.push_back(Floor);
746  WorkStack.push_back(Val - Floor);
747  ++Steps;
748  continue;
749  }
750 
751  WorkStack.push_back(Ceil);
752  WorkStack.push_back(Ceil - Val);
753  ++Steps;
754 
755  // If we have taken more than 12[1] / 8[2] steps to attempt the
756  // optimization for a native sized value, it is more than likely that this
757  // optimization will make things worse.
758  //
759  // [1] MIPS64 requires 6 instructions at most to materialize any constant,
760  // multiplication requires at least 4 cycles, but another cycle (or two)
761  // to retrieve the result from the HI/LO registers.
762  //
763  // [2] For MIPS32, more than 8 steps is expensive as the constant could be
764  // materialized in 2 instructions, multiplication requires at least 4
765  // cycles, but another cycle (or two) to retrieve the result from the
766  // HI/LO registers.
767 
768  if (Steps > 12 && (Subtarget.isABI_N32() || Subtarget.isABI_N64()))
769  return false;
770 
771  if (Steps > 8 && Subtarget.isABI_O32())
772  return false;
773  }
774 
775  // If the value being multiplied is not supported natively, we have to pay
776  // an additional legalization cost, conservatively assume an increase in the
777  // cost of 3 instructions per step. This values for this heuristic were
778  // determined experimentally.
779  unsigned RegisterSize = DAG.getTargetLoweringInfo()
780  .getRegisterType(*DAG.getContext(), VT)
781  .getSizeInBits();
782  Steps *= (VT.getSizeInBits() != RegisterSize) * 3;
783  if (Steps > 27)
784  return false;
785 
786  return true;
787 }
788 
789 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT,
790  EVT ShiftTy, SelectionDAG &DAG) {
791  // Return 0.
792  if (C == 0)
793  return DAG.getConstant(0, DL, VT);
794 
795  // Return x.
796  if (C == 1)
797  return X;
798 
799  // If c is power of 2, return (shl x, log2(c)).
800  if (C.isPowerOf2())
801  return DAG.getNode(ISD::SHL, DL, VT, X,
802  DAG.getConstant(C.logBase2(), DL, ShiftTy));
803 
804  unsigned BitWidth = C.getBitWidth();
805  APInt Floor = APInt(BitWidth, 1) << C.logBase2();
806  APInt Ceil = C.isNegative() ? APInt(BitWidth, 0) :
807  APInt(BitWidth, 1) << C.ceilLogBase2();
808 
809  // If |c - floor_c| <= |c - ceil_c|,
810  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
811  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
812  if ((C - Floor).ule(Ceil - C)) {
813  SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
814  SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
815  return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
816  }
817 
818  // If |c - floor_c| > |c - ceil_c|,
819  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
820  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
821  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
822  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
823 }
824 
827  const MipsSETargetLowering *TL,
828  const MipsSubtarget &Subtarget) {
829  EVT VT = N->getValueType(0);
830 
831  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
833  C->getAPIntValue(), VT, DAG, Subtarget))
834  return genConstMult(N->getOperand(0), C->getAPIntValue(), SDLoc(N), VT,
835  TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
836  DAG);
837 
838  return SDValue(N, 0);
839 }
840 
841 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
842  SelectionDAG &DAG,
843  const MipsSubtarget &Subtarget) {
844  // See if this is a vector splat immediate node.
845  APInt SplatValue, SplatUndef;
846  unsigned SplatBitSize;
847  bool HasAnyUndefs;
848  unsigned EltSize = Ty.getScalarSizeInBits();
850 
851  if (!Subtarget.hasDSP())
852  return SDValue();
853 
854  if (!BV ||
855  !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
856  EltSize, !Subtarget.isLittle()) ||
857  (SplatBitSize != EltSize) ||
858  (SplatValue.getZExtValue() >= EltSize))
859  return SDValue();
860 
861  SDLoc DL(N);
862  return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
863  DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
864 }
865 
868  const MipsSubtarget &Subtarget) {
869  EVT Ty = N->getValueType(0);
870 
871  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
872  return SDValue();
873 
874  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
875 }
876 
877 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
878 // constant splats into MipsISD::SHRA_DSP for DSPr2.
879 //
880 // Performs the following transformations:
881 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
882 // sign/zero-extension is completely overwritten by the new one performed by
883 // the ISD::SRA and ISD::SHL nodes.
884 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
885 // sequence.
886 //
887 // See performDSPShiftCombine for more information about the transformation
888 // used for DSPr2.
891  const MipsSubtarget &Subtarget) {
892  EVT Ty = N->getValueType(0);
893 
894  if (Subtarget.hasMSA()) {
895  SDValue Op0 = N->getOperand(0);
896  SDValue Op1 = N->getOperand(1);
897 
898  // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
899  // where $d + sizeof($c) == 32
900  // or $d + sizeof($c) <= 32 and SExt
901  // -> (MipsVExtractSExt $a, $b, $c)
902  if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
903  SDValue Op0Op0 = Op0->getOperand(0);
904  ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
905 
906  if (!ShAmount)
907  return SDValue();
908 
909  if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
911  return SDValue();
912 
913  EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
914  unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
915 
916  if (TotalBits == 32 ||
917  (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
918  TotalBits <= 32)) {
919  SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
920  Op0Op0->getOperand(2) };
921  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
922  Op0Op0->getVTList(),
923  makeArrayRef(Ops, Op0Op0->getNumOperands()));
924  }
925  }
926  }
927 
928  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
929  return SDValue();
930 
931  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
932 }
933 
934 
937  const MipsSubtarget &Subtarget) {
938  EVT Ty = N->getValueType(0);
939 
940  if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
941  return SDValue();
942 
943  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
944 }
945 
946 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
947  bool IsV216 = (Ty == MVT::v2i16);
948 
949  switch (CC) {
950  case ISD::SETEQ:
951  case ISD::SETNE: return true;
952  case ISD::SETLT:
953  case ISD::SETLE:
954  case ISD::SETGT:
955  case ISD::SETGE: return IsV216;
956  case ISD::SETULT:
957  case ISD::SETULE:
958  case ISD::SETUGT:
959  case ISD::SETUGE: return !IsV216;
960  default: return false;
961  }
962 }
963 
965  EVT Ty = N->getValueType(0);
966 
967  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
968  return SDValue();
969 
970  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
971  return SDValue();
972 
973  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
974  N->getOperand(1), N->getOperand(2));
975 }
976 
978  EVT Ty = N->getValueType(0);
979 
980  if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
981  SDValue SetCC = N->getOperand(0);
982 
983  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
984  return SDValue();
985 
986  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
987  SetCC.getOperand(0), SetCC.getOperand(1),
988  N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
989  }
990 
991  return SDValue();
992 }
993 
995  const MipsSubtarget &Subtarget) {
996  EVT Ty = N->getValueType(0);
997 
998  if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
999  // Try the following combines:
1000  // (xor (or $a, $b), (build_vector allones))
1001  // (xor (or $a, $b), (bitcast (build_vector allones)))
1002  SDValue Op0 = N->getOperand(0);
1003  SDValue Op1 = N->getOperand(1);
1004  SDValue NotOp;
1005 
1007  NotOp = Op1;
1008  else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1009  NotOp = Op0;
1010  else
1011  return SDValue();
1012 
1013  if (NotOp->getOpcode() == ISD::OR)
1014  return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1015  NotOp->getOperand(1));
1016  }
1017 
1018  return SDValue();
1019 }
1020 
1021 SDValue
1023  SelectionDAG &DAG = DCI.DAG;
1024  SDValue Val;
1025 
1026  switch (N->getOpcode()) {
1027  case ISD::AND:
1028  Val = performANDCombine(N, DAG, DCI, Subtarget);
1029  break;
1030  case ISD::OR:
1031  Val = performORCombine(N, DAG, DCI, Subtarget);
1032  break;
1033  case ISD::MUL:
1034  return performMULCombine(N, DAG, DCI, this, Subtarget);
1035  case ISD::SHL:
1036  Val = performSHLCombine(N, DAG, DCI, Subtarget);
1037  break;
1038  case ISD::SRA:
1039  return performSRACombine(N, DAG, DCI, Subtarget);
1040  case ISD::SRL:
1041  return performSRLCombine(N, DAG, DCI, Subtarget);
1042  case ISD::VSELECT:
1043  return performVSELECTCombine(N, DAG);
1044  case ISD::XOR:
1045  Val = performXORCombine(N, DAG, Subtarget);
1046  break;
1047  case ISD::SETCC:
1048  Val = performSETCCCombine(N, DAG);
1049  break;
1050  }
1051 
1052  if (Val.getNode()) {
1053  LLVM_DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1054  N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n";
1055  Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n");
1056  return Val;
1057  }
1058 
1060 }
1061 
1064  MachineBasicBlock *BB) const {
1065  switch (MI.getOpcode()) {
1066  default:
1068  case Mips::BPOSGE32_PSEUDO:
1069  return emitBPOSGE32(MI, BB);
1070  case Mips::SNZ_B_PSEUDO:
1071  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1072  case Mips::SNZ_H_PSEUDO:
1073  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1074  case Mips::SNZ_W_PSEUDO:
1075  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1076  case Mips::SNZ_D_PSEUDO:
1077  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1078  case Mips::SNZ_V_PSEUDO:
1079  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1080  case Mips::SZ_B_PSEUDO:
1081  return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1082  case Mips::SZ_H_PSEUDO:
1083  return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1084  case Mips::SZ_W_PSEUDO:
1085  return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1086  case Mips::SZ_D_PSEUDO:
1087  return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1088  case Mips::SZ_V_PSEUDO:
1089  return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1090  case Mips::COPY_FW_PSEUDO:
1091  return emitCOPY_FW(MI, BB);
1092  case Mips::COPY_FD_PSEUDO:
1093  return emitCOPY_FD(MI, BB);
1094  case Mips::INSERT_FW_PSEUDO:
1095  return emitINSERT_FW(MI, BB);
1096  case Mips::INSERT_FD_PSEUDO:
1097  return emitINSERT_FD(MI, BB);
1098  case Mips::INSERT_B_VIDX_PSEUDO:
1099  case Mips::INSERT_B_VIDX64_PSEUDO:
1100  return emitINSERT_DF_VIDX(MI, BB, 1, false);
1101  case Mips::INSERT_H_VIDX_PSEUDO:
1102  case Mips::INSERT_H_VIDX64_PSEUDO:
1103  return emitINSERT_DF_VIDX(MI, BB, 2, false);
1104  case Mips::INSERT_W_VIDX_PSEUDO:
1105  case Mips::INSERT_W_VIDX64_PSEUDO:
1106  return emitINSERT_DF_VIDX(MI, BB, 4, false);
1107  case Mips::INSERT_D_VIDX_PSEUDO:
1108  case Mips::INSERT_D_VIDX64_PSEUDO:
1109  return emitINSERT_DF_VIDX(MI, BB, 8, false);
1110  case Mips::INSERT_FW_VIDX_PSEUDO:
1111  case Mips::INSERT_FW_VIDX64_PSEUDO:
1112  return emitINSERT_DF_VIDX(MI, BB, 4, true);
1113  case Mips::INSERT_FD_VIDX_PSEUDO:
1114  case Mips::INSERT_FD_VIDX64_PSEUDO:
1115  return emitINSERT_DF_VIDX(MI, BB, 8, true);
1116  case Mips::FILL_FW_PSEUDO:
1117  return emitFILL_FW(MI, BB);
1118  case Mips::FILL_FD_PSEUDO:
1119  return emitFILL_FD(MI, BB);
1120  case Mips::FEXP2_W_1_PSEUDO:
1121  return emitFEXP2_W_1(MI, BB);
1122  case Mips::FEXP2_D_1_PSEUDO:
1123  return emitFEXP2_D_1(MI, BB);
1124  case Mips::ST_F16:
1125  return emitST_F16_PSEUDO(MI, BB);
1126  case Mips::LD_F16:
1127  return emitLD_F16_PSEUDO(MI, BB);
1128  case Mips::MSA_FP_EXTEND_W_PSEUDO:
1129  return emitFPEXTEND_PSEUDO(MI, BB, false);
1130  case Mips::MSA_FP_ROUND_W_PSEUDO:
1131  return emitFPROUND_PSEUDO(MI, BB, false);
1132  case Mips::MSA_FP_EXTEND_D_PSEUDO:
1133  return emitFPEXTEND_PSEUDO(MI, BB, true);
1134  case Mips::MSA_FP_ROUND_D_PSEUDO:
1135  return emitFPROUND_PSEUDO(MI, BB, true);
1136  }
1137 }
1138 
1139 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1140  const CCState &CCInfo, unsigned NextStackOffset,
1141  const MipsFunctionInfo &FI) const {
1142  if (!UseMipsTailCalls)
1143  return false;
1144 
1145  // Exception has to be cleared with eret.
1146  if (FI.isISR())
1147  return false;
1148 
1149  // Return false if either the callee or caller has a byval argument.
1150  if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1151  return false;
1152 
1153  // Return true if the callee's argument area is no larger than the
1154  // caller's.
1155  return NextStackOffset <= FI.getIncomingArgSize();
1156 }
1157 
1158 void MipsSETargetLowering::
1159 getOpndList(SmallVectorImpl<SDValue> &Ops,
1160  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1161  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1162  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1163  SDValue Chain) const {
1164  Ops.push_back(Callee);
1165  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1166  InternalLinkage, IsCallReloc, CLI, Callee,
1167  Chain);
1168 }
1169 
1170 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1171  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1172 
1173  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1174  return MipsTargetLowering::lowerLOAD(Op, DAG);
1175 
1176  // Replace a double precision load with two i32 loads and a buildpair64.
1177  SDLoc DL(Op);
1178  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1179  EVT PtrVT = Ptr.getValueType();
1180 
1181  // i32 load from lower address.
1182  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1183  Nd.getAlignment(), Nd.getMemOperand()->getFlags());
1184 
1185  // i32 load from higher address.
1186  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1187  SDValue Hi = DAG.getLoad(
1188  MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1189  std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
1190 
1191  if (!Subtarget.isLittle())
1192  std::swap(Lo, Hi);
1193 
1194  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1195  SDValue Ops[2] = {BP, Hi.getValue(1)};
1196  return DAG.getMergeValues(Ops, DL);
1197 }
1198 
1199 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1200  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1201 
1202  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1203  return MipsTargetLowering::lowerSTORE(Op, DAG);
1204 
1205  // Replace a double precision store with two extractelement64s and i32 stores.
1206  SDLoc DL(Op);
1207  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1208  EVT PtrVT = Ptr.getValueType();
1210  Val, DAG.getConstant(0, DL, MVT::i32));
1212  Val, DAG.getConstant(1, DL, MVT::i32));
1213 
1214  if (!Subtarget.isLittle())
1215  std::swap(Lo, Hi);
1216 
1217  // i32 store to lower address.
1218  Chain =
1219  DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1220  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1221 
1222  // i32 store to higher address.
1223  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1224  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1225  std::min(Nd.getAlignment(), 4U),
1226  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1227 }
1228 
1229 SDValue MipsSETargetLowering::lowerBITCAST(SDValue Op,
1230  SelectionDAG &DAG) const {
1231  SDLoc DL(Op);
1232  MVT Src = Op.getOperand(0).getValueType().getSimpleVT();
1233  MVT Dest = Op.getValueType().getSimpleVT();
1234 
1235  // Bitcast i64 to double.
1236  if (Src == MVT::i64 && Dest == MVT::f64) {
1238  Op.getOperand(0), DAG.getIntPtrConstant(0, DL));
1240  Op.getOperand(0), DAG.getIntPtrConstant(1, DL));
1241  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1242  }
1243 
1244  // Bitcast double to i64.
1245  if (Src == MVT::f64 && Dest == MVT::i64) {
1246  SDValue Lo =
1248  DAG.getConstant(0, DL, MVT::i32));
1249  SDValue Hi =
1251  DAG.getConstant(1, DL, MVT::i32));
1252  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1253  }
1254 
1255  // Skip other cases of bitcast and use default lowering.
1256  return SDValue();
1257 }
1258 
1259 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1260  bool HasLo, bool HasHi,
1261  SelectionDAG &DAG) const {
1262  // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1264 
1265  EVT Ty = Op.getOperand(0).getValueType();
1266  SDLoc DL(Op);
1267  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1268  Op.getOperand(0), Op.getOperand(1));
1269  SDValue Lo, Hi;
1270 
1271  if (HasLo)
1272  Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1273  if (HasHi)
1274  Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1275 
1276  if (!HasLo || !HasHi)
1277  return HasLo ? Lo : Hi;
1278 
1279  SDValue Vals[] = { Lo, Hi };
1280  return DAG.getMergeValues(Vals, DL);
1281 }
1282 
1284  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1285  DAG.getConstant(0, DL, MVT::i32));
1286  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1287  DAG.getConstant(1, DL, MVT::i32));
1288  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1289 }
1290 
1291 static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) {
1292  SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1293  SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1294  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1295 }
1296 
1297 // This function expands mips intrinsic nodes which have 64-bit input operands
1298 // or output values.
1299 //
1300 // out64 = intrinsic-node in64
1301 // =>
1302 // lo = copy (extract-element (in64, 0))
1303 // hi = copy (extract-element (in64, 1))
1304 // mips-specific-node
1305 // v0 = copy lo
1306 // v1 = copy hi
1307 // out64 = merge-values (v0, v1)
1308 //
1309 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1310  SDLoc DL(Op);
1311  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1313  unsigned OpNo = 0;
1314 
1315  // See if Op has a chain input.
1316  if (HasChainIn)
1317  Ops.push_back(Op->getOperand(OpNo++));
1318 
1319  // The next operand is the intrinsic opcode.
1321 
1322  // See if the next operand has type i64.
1323  SDValue Opnd = Op->getOperand(++OpNo), In64;
1324 
1325  if (Opnd.getValueType() == MVT::i64)
1326  In64 = initAccumulator(Opnd, DL, DAG);
1327  else
1328  Ops.push_back(Opnd);
1329 
1330  // Push the remaining operands.
1331  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1332  Ops.push_back(Op->getOperand(OpNo));
1333 
1334  // Add In64 to the end of the list.
1335  if (In64.getNode())
1336  Ops.push_back(In64);
1337 
1338  // Scan output.
1339  SmallVector<EVT, 2> ResTys;
1340 
1341  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1342  I != E; ++I)
1343  ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1344 
1345  // Create node.
1346  SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1347  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1348 
1349  if (!HasChainIn)
1350  return Out;
1351 
1352  assert(Val->getValueType(1) == MVT::Other);
1353  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1354  return DAG.getMergeValues(Vals, DL);
1355 }
1356 
1357 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1358 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1359  SDLoc DL(Op);
1360  SDValue Vec = Op->getOperand(1);
1361  SDValue Idx = Op->getOperand(2);
1362  EVT ResTy = Op->getValueType(0);
1363  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1364 
1365  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1366  DAG.getValueType(EltTy));
1367 
1368  return Result;
1369 }
1370 
1371 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1372  EVT ResVecTy = Op->getValueType(0);
1373  EVT ViaVecTy = ResVecTy;
1374  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1375  SDLoc DL(Op);
1376 
1377  // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1378  // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1379  // lanes.
1380  SDValue LaneA = Op->getOperand(OpNr);
1381  SDValue LaneB;
1382 
1383  if (ResVecTy == MVT::v2i64) {
1384  // In case of the index being passed as an immediate value, set the upper
1385  // lane to 0 so that the splati.d instruction can be matched.
1386  if (isa<ConstantSDNode>(LaneA))
1387  LaneB = DAG.getConstant(0, DL, MVT::i32);
1388  // Having the index passed in a register, set the upper lane to the same
1389  // value as the lower - this results in the BUILD_VECTOR node not being
1390  // expanded through stack. This way we are able to pattern match the set of
1391  // nodes created here to splat.d.
1392  else
1393  LaneB = LaneA;
1394  ViaVecTy = MVT::v4i32;
1395  if(BigEndian)
1396  std::swap(LaneA, LaneB);
1397  } else
1398  LaneB = LaneA;
1399 
1400  SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1401  LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1402 
1403  SDValue Result = DAG.getBuildVector(
1404  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1405 
1406  if (ViaVecTy != ResVecTy) {
1407  SDValue One = DAG.getConstant(1, DL, ViaVecTy);
1408  Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy,
1409  DAG.getNode(ISD::AND, DL, ViaVecTy, Result, One));
1410  }
1411 
1412  return Result;
1413 }
1414 
1415 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG,
1416  bool IsSigned = false) {
1417  auto *CImm = cast<ConstantSDNode>(Op->getOperand(ImmOp));
1418  return DAG.getConstant(
1420  IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),
1421  SDLoc(Op), Op->getValueType(0));
1422 }
1423 
1424 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1425  bool BigEndian, SelectionDAG &DAG) {
1426  EVT ViaVecTy = VecTy;
1427  SDValue SplatValueA = SplatValue;
1428  SDValue SplatValueB = SplatValue;
1429  SDLoc DL(SplatValue);
1430 
1431  if (VecTy == MVT::v2i64) {
1432  // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1433  ViaVecTy = MVT::v4i32;
1434 
1435  SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1436  SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1437  DAG.getConstant(32, DL, MVT::i32));
1438  SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1439  }
1440 
1441  // We currently hold the parts in little endian order. Swap them if
1442  // necessary.
1443  if (BigEndian)
1444  std::swap(SplatValueA, SplatValueB);
1445 
1446  SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1447  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1448  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1449  SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1450 
1451  SDValue Result = DAG.getBuildVector(
1452  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1453 
1454  if (VecTy != ViaVecTy)
1455  Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1456 
1457  return Result;
1458 }
1459 
1461  unsigned Opc, SDValue Imm,
1462  bool BigEndian) {
1463  EVT VecTy = Op->getValueType(0);
1464  SDValue Exp2Imm;
1465  SDLoc DL(Op);
1466 
1467  // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1468  // here for now.
1469  if (VecTy == MVT::v2i64) {
1470  if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1471  APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1472 
1473  SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1474  MVT::i32);
1475  SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
1476 
1477  if (BigEndian)
1478  std::swap(BitImmLoOp, BitImmHiOp);
1479 
1480  Exp2Imm = DAG.getNode(
1481  ISD::BITCAST, DL, MVT::v2i64,
1482  DAG.getBuildVector(MVT::v4i32, DL,
1483  {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1484  }
1485  }
1486 
1487  if (!Exp2Imm.getNode()) {
1488  // We couldnt constant fold, do a vector shift instead
1489 
1490  // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1491  // only values 0-63 are valid.
1492  if (VecTy == MVT::v2i64)
1493  Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1494 
1495  Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1496 
1497  Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1498  Exp2Imm);
1499  }
1500 
1501  return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1502 }
1503 
1505  SDLoc DL(Op);
1506  EVT ResTy = Op->getValueType(0);
1507  SDValue Vec = Op->getOperand(2);
1508  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1509  MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1510  SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
1511  DL, ResEltTy);
1512  SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1513 
1514  return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1515 }
1516 
1518  EVT ResTy = Op->getValueType(0);
1519  SDLoc DL(Op);
1520  SDValue One = DAG.getConstant(1, DL, ResTy);
1521  SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1522 
1523  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1524  DAG.getNOT(DL, Bit, ResTy));
1525 }
1526 
1528  SDLoc DL(Op);
1529  EVT ResTy = Op->getValueType(0);
1530  APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1531  << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1532  SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1533 
1534  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1535 }
1536 
1537 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1538  SelectionDAG &DAG) const {
1539  SDLoc DL(Op);
1540  unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1541  switch (Intrinsic) {
1542  default:
1543  return SDValue();
1544  case Intrinsic::mips_shilo:
1545  return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1546  case Intrinsic::mips_dpau_h_qbl:
1547  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1548  case Intrinsic::mips_dpau_h_qbr:
1549  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1550  case Intrinsic::mips_dpsu_h_qbl:
1551  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1552  case Intrinsic::mips_dpsu_h_qbr:
1553  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1554  case Intrinsic::mips_dpa_w_ph:
1555  return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1556  case Intrinsic::mips_dps_w_ph:
1557  return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1558  case Intrinsic::mips_dpax_w_ph:
1559  return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1560  case Intrinsic::mips_dpsx_w_ph:
1561  return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1562  case Intrinsic::mips_mulsa_w_ph:
1563  return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1564  case Intrinsic::mips_mult:
1565  return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1566  case Intrinsic::mips_multu:
1567  return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1568  case Intrinsic::mips_madd:
1569  return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1570  case Intrinsic::mips_maddu:
1571  return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1572  case Intrinsic::mips_msub:
1573  return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1574  case Intrinsic::mips_msubu:
1575  return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1576  case Intrinsic::mips_addv_b:
1577  case Intrinsic::mips_addv_h:
1578  case Intrinsic::mips_addv_w:
1579  case Intrinsic::mips_addv_d:
1580  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1581  Op->getOperand(2));
1582  case Intrinsic::mips_addvi_b:
1583  case Intrinsic::mips_addvi_h:
1584  case Intrinsic::mips_addvi_w:
1585  case Intrinsic::mips_addvi_d:
1586  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1587  lowerMSASplatImm(Op, 2, DAG));
1588  case Intrinsic::mips_and_v:
1589  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1590  Op->getOperand(2));
1591  case Intrinsic::mips_andi_b:
1592  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1593  lowerMSASplatImm(Op, 2, DAG));
1594  case Intrinsic::mips_bclr_b:
1595  case Intrinsic::mips_bclr_h:
1596  case Intrinsic::mips_bclr_w:
1597  case Intrinsic::mips_bclr_d:
1598  return lowerMSABitClear(Op, DAG);
1599  case Intrinsic::mips_bclri_b:
1600  case Intrinsic::mips_bclri_h:
1601  case Intrinsic::mips_bclri_w:
1602  case Intrinsic::mips_bclri_d:
1603  return lowerMSABitClearImm(Op, DAG);
1604  case Intrinsic::mips_binsli_b:
1605  case Intrinsic::mips_binsli_h:
1606  case Intrinsic::mips_binsli_w:
1607  case Intrinsic::mips_binsli_d: {
1608  // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1609  EVT VecTy = Op->getValueType(0);
1610  EVT EltTy = VecTy.getVectorElementType();
1611  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1612  report_fatal_error("Immediate out of range");
1614  Op->getConstantOperandVal(3) + 1);
1615  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1616  DAG.getConstant(Mask, DL, VecTy, true),
1617  Op->getOperand(2), Op->getOperand(1));
1618  }
1619  case Intrinsic::mips_binsri_b:
1620  case Intrinsic::mips_binsri_h:
1621  case Intrinsic::mips_binsri_w:
1622  case Intrinsic::mips_binsri_d: {
1623  // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1624  EVT VecTy = Op->getValueType(0);
1625  EVT EltTy = VecTy.getVectorElementType();
1626  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1627  report_fatal_error("Immediate out of range");
1629  Op->getConstantOperandVal(3) + 1);
1630  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1631  DAG.getConstant(Mask, DL, VecTy, true),
1632  Op->getOperand(2), Op->getOperand(1));
1633  }
1634  case Intrinsic::mips_bmnz_v:
1635  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1636  Op->getOperand(2), Op->getOperand(1));
1637  case Intrinsic::mips_bmnzi_b:
1638  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1639  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1640  Op->getOperand(1));
1641  case Intrinsic::mips_bmz_v:
1642  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1643  Op->getOperand(1), Op->getOperand(2));
1644  case Intrinsic::mips_bmzi_b:
1645  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1646  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1647  Op->getOperand(2));
1648  case Intrinsic::mips_bneg_b:
1649  case Intrinsic::mips_bneg_h:
1650  case Intrinsic::mips_bneg_w:
1651  case Intrinsic::mips_bneg_d: {
1652  EVT VecTy = Op->getValueType(0);
1653  SDValue One = DAG.getConstant(1, DL, VecTy);
1654 
1655  return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1656  DAG.getNode(ISD::SHL, DL, VecTy, One,
1657  truncateVecElts(Op, DAG)));
1658  }
1659  case Intrinsic::mips_bnegi_b:
1660  case Intrinsic::mips_bnegi_h:
1661  case Intrinsic::mips_bnegi_w:
1662  case Intrinsic::mips_bnegi_d:
1663  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1664  !Subtarget.isLittle());
1665  case Intrinsic::mips_bnz_b:
1666  case Intrinsic::mips_bnz_h:
1667  case Intrinsic::mips_bnz_w:
1668  case Intrinsic::mips_bnz_d:
1669  return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1670  Op->getOperand(1));
1671  case Intrinsic::mips_bnz_v:
1672  return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1673  Op->getOperand(1));
1674  case Intrinsic::mips_bsel_v:
1675  // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1676  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1677  Op->getOperand(1), Op->getOperand(3),
1678  Op->getOperand(2));
1679  case Intrinsic::mips_bseli_b:
1680  // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1681  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1682  Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1683  Op->getOperand(2));
1684  case Intrinsic::mips_bset_b:
1685  case Intrinsic::mips_bset_h:
1686  case Intrinsic::mips_bset_w:
1687  case Intrinsic::mips_bset_d: {
1688  EVT VecTy = Op->getValueType(0);
1689  SDValue One = DAG.getConstant(1, DL, VecTy);
1690 
1691  return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1692  DAG.getNode(ISD::SHL, DL, VecTy, One,
1693  truncateVecElts(Op, DAG)));
1694  }
1695  case Intrinsic::mips_bseti_b:
1696  case Intrinsic::mips_bseti_h:
1697  case Intrinsic::mips_bseti_w:
1698  case Intrinsic::mips_bseti_d:
1699  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1700  !Subtarget.isLittle());
1701  case Intrinsic::mips_bz_b:
1702  case Intrinsic::mips_bz_h:
1703  case Intrinsic::mips_bz_w:
1704  case Intrinsic::mips_bz_d:
1705  return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1706  Op->getOperand(1));
1707  case Intrinsic::mips_bz_v:
1708  return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1709  Op->getOperand(1));
1710  case Intrinsic::mips_ceq_b:
1711  case Intrinsic::mips_ceq_h:
1712  case Intrinsic::mips_ceq_w:
1713  case Intrinsic::mips_ceq_d:
1714  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1715  Op->getOperand(2), ISD::SETEQ);
1716  case Intrinsic::mips_ceqi_b:
1717  case Intrinsic::mips_ceqi_h:
1718  case Intrinsic::mips_ceqi_w:
1719  case Intrinsic::mips_ceqi_d:
1720  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1721  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
1722  case Intrinsic::mips_cle_s_b:
1723  case Intrinsic::mips_cle_s_h:
1724  case Intrinsic::mips_cle_s_w:
1725  case Intrinsic::mips_cle_s_d:
1726  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1727  Op->getOperand(2), ISD::SETLE);
1728  case Intrinsic::mips_clei_s_b:
1729  case Intrinsic::mips_clei_s_h:
1730  case Intrinsic::mips_clei_s_w:
1731  case Intrinsic::mips_clei_s_d:
1732  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1733  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
1734  case Intrinsic::mips_cle_u_b:
1735  case Intrinsic::mips_cle_u_h:
1736  case Intrinsic::mips_cle_u_w:
1737  case Intrinsic::mips_cle_u_d:
1738  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1739  Op->getOperand(2), ISD::SETULE);
1740  case Intrinsic::mips_clei_u_b:
1741  case Intrinsic::mips_clei_u_h:
1742  case Intrinsic::mips_clei_u_w:
1743  case Intrinsic::mips_clei_u_d:
1744  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1745  lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1746  case Intrinsic::mips_clt_s_b:
1747  case Intrinsic::mips_clt_s_h:
1748  case Intrinsic::mips_clt_s_w:
1749  case Intrinsic::mips_clt_s_d:
1750  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1751  Op->getOperand(2), ISD::SETLT);
1752  case Intrinsic::mips_clti_s_b:
1753  case Intrinsic::mips_clti_s_h:
1754  case Intrinsic::mips_clti_s_w:
1755  case Intrinsic::mips_clti_s_d:
1756  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1757  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
1758  case Intrinsic::mips_clt_u_b:
1759  case Intrinsic::mips_clt_u_h:
1760  case Intrinsic::mips_clt_u_w:
1761  case Intrinsic::mips_clt_u_d:
1762  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1763  Op->getOperand(2), ISD::SETULT);
1764  case Intrinsic::mips_clti_u_b:
1765  case Intrinsic::mips_clti_u_h:
1766  case Intrinsic::mips_clti_u_w:
1767  case Intrinsic::mips_clti_u_d:
1768  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1769  lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1770  case Intrinsic::mips_copy_s_b:
1771  case Intrinsic::mips_copy_s_h:
1772  case Intrinsic::mips_copy_s_w:
1774  case Intrinsic::mips_copy_s_d:
1775  if (Subtarget.hasMips64())
1776  // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1778  else {
1779  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1780  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1781  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1782  Op->getValueType(0), Op->getOperand(1),
1783  Op->getOperand(2));
1784  }
1785  case Intrinsic::mips_copy_u_b:
1786  case Intrinsic::mips_copy_u_h:
1787  case Intrinsic::mips_copy_u_w:
1789  case Intrinsic::mips_copy_u_d:
1790  if (Subtarget.hasMips64())
1791  // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1793  else {
1794  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1795  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1796  // Note: When i64 is illegal, this results in copy_s.w instructions
1797  // instead of copy_u.w instructions. This makes no difference to the
1798  // behaviour since i64 is only illegal when the register file is 32-bit.
1799  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1800  Op->getValueType(0), Op->getOperand(1),
1801  Op->getOperand(2));
1802  }
1803  case Intrinsic::mips_div_s_b:
1804  case Intrinsic::mips_div_s_h:
1805  case Intrinsic::mips_div_s_w:
1806  case Intrinsic::mips_div_s_d:
1807  return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1808  Op->getOperand(2));
1809  case Intrinsic::mips_div_u_b:
1810  case Intrinsic::mips_div_u_h:
1811  case Intrinsic::mips_div_u_w:
1812  case Intrinsic::mips_div_u_d:
1813  return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1814  Op->getOperand(2));
1815  case Intrinsic::mips_fadd_w:
1816  case Intrinsic::mips_fadd_d:
1817  // TODO: If intrinsics have fast-math-flags, propagate them.
1818  return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1819  Op->getOperand(2));
1820  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1821  case Intrinsic::mips_fceq_w:
1822  case Intrinsic::mips_fceq_d:
1823  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1824  Op->getOperand(2), ISD::SETOEQ);
1825  case Intrinsic::mips_fcle_w:
1826  case Intrinsic::mips_fcle_d:
1827  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1828  Op->getOperand(2), ISD::SETOLE);
1829  case Intrinsic::mips_fclt_w:
1830  case Intrinsic::mips_fclt_d:
1831  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1832  Op->getOperand(2), ISD::SETOLT);
1833  case Intrinsic::mips_fcne_w:
1834  case Intrinsic::mips_fcne_d:
1835  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1836  Op->getOperand(2), ISD::SETONE);
1837  case Intrinsic::mips_fcor_w:
1838  case Intrinsic::mips_fcor_d:
1839  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1840  Op->getOperand(2), ISD::SETO);
1841  case Intrinsic::mips_fcueq_w:
1842  case Intrinsic::mips_fcueq_d:
1843  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1844  Op->getOperand(2), ISD::SETUEQ);
1845  case Intrinsic::mips_fcule_w:
1846  case Intrinsic::mips_fcule_d:
1847  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1848  Op->getOperand(2), ISD::SETULE);
1849  case Intrinsic::mips_fcult_w:
1850  case Intrinsic::mips_fcult_d:
1851  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1852  Op->getOperand(2), ISD::SETULT);
1853  case Intrinsic::mips_fcun_w:
1854  case Intrinsic::mips_fcun_d:
1855  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1856  Op->getOperand(2), ISD::SETUO);
1857  case Intrinsic::mips_fcune_w:
1858  case Intrinsic::mips_fcune_d:
1859  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1860  Op->getOperand(2), ISD::SETUNE);
1861  case Intrinsic::mips_fdiv_w:
1862  case Intrinsic::mips_fdiv_d:
1863  // TODO: If intrinsics have fast-math-flags, propagate them.
1864  return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1865  Op->getOperand(2));
1866  case Intrinsic::mips_ffint_u_w:
1867  case Intrinsic::mips_ffint_u_d:
1868  return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1869  Op->getOperand(1));
1870  case Intrinsic::mips_ffint_s_w:
1871  case Intrinsic::mips_ffint_s_d:
1872  return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1873  Op->getOperand(1));
1874  case Intrinsic::mips_fill_b:
1875  case Intrinsic::mips_fill_h:
1876  case Intrinsic::mips_fill_w:
1877  case Intrinsic::mips_fill_d: {
1878  EVT ResTy = Op->getValueType(0);
1880  Op->getOperand(1));
1881 
1882  // If ResTy is v2i64 then the type legalizer will break this node down into
1883  // an equivalent v4i32.
1884  return DAG.getBuildVector(ResTy, DL, Ops);
1885  }
1886  case Intrinsic::mips_fexp2_w:
1887  case Intrinsic::mips_fexp2_d: {
1888  // TODO: If intrinsics have fast-math-flags, propagate them.
1889  EVT ResTy = Op->getValueType(0);
1890  return DAG.getNode(
1891  ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1892  DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1893  }
1894  case Intrinsic::mips_flog2_w:
1895  case Intrinsic::mips_flog2_d:
1896  return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1897  case Intrinsic::mips_fmadd_w:
1898  case Intrinsic::mips_fmadd_d:
1899  return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1900  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1901  case Intrinsic::mips_fmul_w:
1902  case Intrinsic::mips_fmul_d:
1903  // TODO: If intrinsics have fast-math-flags, propagate them.
1904  return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1905  Op->getOperand(2));
1906  case Intrinsic::mips_fmsub_w:
1907  case Intrinsic::mips_fmsub_d: {
1908  // TODO: If intrinsics have fast-math-flags, propagate them.
1909  return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0),
1910  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1911  }
1912  case Intrinsic::mips_frint_w:
1913  case Intrinsic::mips_frint_d:
1914  return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1915  case Intrinsic::mips_fsqrt_w:
1916  case Intrinsic::mips_fsqrt_d:
1917  return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1918  case Intrinsic::mips_fsub_w:
1919  case Intrinsic::mips_fsub_d:
1920  // TODO: If intrinsics have fast-math-flags, propagate them.
1921  return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1922  Op->getOperand(2));
1923  case Intrinsic::mips_ftrunc_u_w:
1924  case Intrinsic::mips_ftrunc_u_d:
1925  return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1926  Op->getOperand(1));
1927  case Intrinsic::mips_ftrunc_s_w:
1928  case Intrinsic::mips_ftrunc_s_d:
1929  return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1930  Op->getOperand(1));
1931  case Intrinsic::mips_ilvev_b:
1932  case Intrinsic::mips_ilvev_h:
1933  case Intrinsic::mips_ilvev_w:
1934  case Intrinsic::mips_ilvev_d:
1935  return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1936  Op->getOperand(1), Op->getOperand(2));
1937  case Intrinsic::mips_ilvl_b:
1938  case Intrinsic::mips_ilvl_h:
1939  case Intrinsic::mips_ilvl_w:
1940  case Intrinsic::mips_ilvl_d:
1941  return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1942  Op->getOperand(1), Op->getOperand(2));
1943  case Intrinsic::mips_ilvod_b:
1944  case Intrinsic::mips_ilvod_h:
1945  case Intrinsic::mips_ilvod_w:
1946  case Intrinsic::mips_ilvod_d:
1947  return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1948  Op->getOperand(1), Op->getOperand(2));
1949  case Intrinsic::mips_ilvr_b:
1950  case Intrinsic::mips_ilvr_h:
1951  case Intrinsic::mips_ilvr_w:
1952  case Intrinsic::mips_ilvr_d:
1953  return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1954  Op->getOperand(1), Op->getOperand(2));
1955  case Intrinsic::mips_insert_b:
1956  case Intrinsic::mips_insert_h:
1957  case Intrinsic::mips_insert_w:
1958  case Intrinsic::mips_insert_d:
1959  return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1960  Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1961  case Intrinsic::mips_insve_b:
1962  case Intrinsic::mips_insve_h:
1963  case Intrinsic::mips_insve_w:
1964  case Intrinsic::mips_insve_d: {
1965  // Report an error for out of range values.
1966  int64_t Max;
1967  switch (Intrinsic) {
1968  case Intrinsic::mips_insve_b: Max = 15; break;
1969  case Intrinsic::mips_insve_h: Max = 7; break;
1970  case Intrinsic::mips_insve_w: Max = 3; break;
1971  case Intrinsic::mips_insve_d: Max = 1; break;
1972  default: llvm_unreachable("Unmatched intrinsic");
1973  }
1974  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
1975  if (Value < 0 || Value > Max)
1976  report_fatal_error("Immediate out of range");
1977  return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1978  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1979  DAG.getConstant(0, DL, MVT::i32));
1980  }
1981  case Intrinsic::mips_ldi_b:
1982  case Intrinsic::mips_ldi_h:
1983  case Intrinsic::mips_ldi_w:
1984  case Intrinsic::mips_ldi_d:
1985  return lowerMSASplatImm(Op, 1, DAG, true);
1986  case Intrinsic::mips_lsa:
1987  case Intrinsic::mips_dlsa: {
1988  EVT ResTy = Op->getValueType(0);
1989  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1990  DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1991  Op->getOperand(2), Op->getOperand(3)));
1992  }
1993  case Intrinsic::mips_maddv_b:
1994  case Intrinsic::mips_maddv_h:
1995  case Intrinsic::mips_maddv_w:
1996  case Intrinsic::mips_maddv_d: {
1997  EVT ResTy = Op->getValueType(0);
1998  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1999  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2000  Op->getOperand(2), Op->getOperand(3)));
2001  }
2002  case Intrinsic::mips_max_s_b:
2003  case Intrinsic::mips_max_s_h:
2004  case Intrinsic::mips_max_s_w:
2005  case Intrinsic::mips_max_s_d:
2006  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2007  Op->getOperand(1), Op->getOperand(2));
2008  case Intrinsic::mips_max_u_b:
2009  case Intrinsic::mips_max_u_h:
2010  case Intrinsic::mips_max_u_w:
2011  case Intrinsic::mips_max_u_d:
2012  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2013  Op->getOperand(1), Op->getOperand(2));
2014  case Intrinsic::mips_maxi_s_b:
2015  case Intrinsic::mips_maxi_s_h:
2016  case Intrinsic::mips_maxi_s_w:
2017  case Intrinsic::mips_maxi_s_d:
2018  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2019  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2020  case Intrinsic::mips_maxi_u_b:
2021  case Intrinsic::mips_maxi_u_h:
2022  case Intrinsic::mips_maxi_u_w:
2023  case Intrinsic::mips_maxi_u_d:
2024  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2025  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2026  case Intrinsic::mips_min_s_b:
2027  case Intrinsic::mips_min_s_h:
2028  case Intrinsic::mips_min_s_w:
2029  case Intrinsic::mips_min_s_d:
2030  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2031  Op->getOperand(1), Op->getOperand(2));
2032  case Intrinsic::mips_min_u_b:
2033  case Intrinsic::mips_min_u_h:
2034  case Intrinsic::mips_min_u_w:
2035  case Intrinsic::mips_min_u_d:
2036  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2037  Op->getOperand(1), Op->getOperand(2));
2038  case Intrinsic::mips_mini_s_b:
2039  case Intrinsic::mips_mini_s_h:
2040  case Intrinsic::mips_mini_s_w:
2041  case Intrinsic::mips_mini_s_d:
2042  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2043  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2044  case Intrinsic::mips_mini_u_b:
2045  case Intrinsic::mips_mini_u_h:
2046  case Intrinsic::mips_mini_u_w:
2047  case Intrinsic::mips_mini_u_d:
2048  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2049  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2050  case Intrinsic::mips_mod_s_b:
2051  case Intrinsic::mips_mod_s_h:
2052  case Intrinsic::mips_mod_s_w:
2053  case Intrinsic::mips_mod_s_d:
2054  return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2055  Op->getOperand(2));
2056  case Intrinsic::mips_mod_u_b:
2057  case Intrinsic::mips_mod_u_h:
2058  case Intrinsic::mips_mod_u_w:
2059  case Intrinsic::mips_mod_u_d:
2060  return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2061  Op->getOperand(2));
2062  case Intrinsic::mips_mulv_b:
2063  case Intrinsic::mips_mulv_h:
2064  case Intrinsic::mips_mulv_w:
2065  case Intrinsic::mips_mulv_d:
2066  return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2067  Op->getOperand(2));
2068  case Intrinsic::mips_msubv_b:
2069  case Intrinsic::mips_msubv_h:
2070  case Intrinsic::mips_msubv_w:
2071  case Intrinsic::mips_msubv_d: {
2072  EVT ResTy = Op->getValueType(0);
2073  return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2074  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2075  Op->getOperand(2), Op->getOperand(3)));
2076  }
2077  case Intrinsic::mips_nlzc_b:
2078  case Intrinsic::mips_nlzc_h:
2079  case Intrinsic::mips_nlzc_w:
2080  case Intrinsic::mips_nlzc_d:
2081  return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2082  case Intrinsic::mips_nor_v: {
2083  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2084  Op->getOperand(1), Op->getOperand(2));
2085  return DAG.getNOT(DL, Res, Res->getValueType(0));
2086  }
2087  case Intrinsic::mips_nori_b: {
2088  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2089  Op->getOperand(1),
2090  lowerMSASplatImm(Op, 2, DAG));
2091  return DAG.getNOT(DL, Res, Res->getValueType(0));
2092  }
2093  case Intrinsic::mips_or_v:
2094  return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2095  Op->getOperand(2));
2096  case Intrinsic::mips_ori_b:
2097  return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2098  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2099  case Intrinsic::mips_pckev_b:
2100  case Intrinsic::mips_pckev_h:
2101  case Intrinsic::mips_pckev_w:
2102  case Intrinsic::mips_pckev_d:
2103  return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2104  Op->getOperand(1), Op->getOperand(2));
2105  case Intrinsic::mips_pckod_b:
2106  case Intrinsic::mips_pckod_h:
2107  case Intrinsic::mips_pckod_w:
2108  case Intrinsic::mips_pckod_d:
2109  return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2110  Op->getOperand(1), Op->getOperand(2));
2111  case Intrinsic::mips_pcnt_b:
2112  case Intrinsic::mips_pcnt_h:
2113  case Intrinsic::mips_pcnt_w:
2114  case Intrinsic::mips_pcnt_d:
2115  return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2116  case Intrinsic::mips_sat_s_b:
2117  case Intrinsic::mips_sat_s_h:
2118  case Intrinsic::mips_sat_s_w:
2119  case Intrinsic::mips_sat_s_d:
2120  case Intrinsic::mips_sat_u_b:
2121  case Intrinsic::mips_sat_u_h:
2122  case Intrinsic::mips_sat_u_w:
2123  case Intrinsic::mips_sat_u_d: {
2124  // Report an error for out of range values.
2125  int64_t Max;
2126  switch (Intrinsic) {
2127  case Intrinsic::mips_sat_s_b:
2128  case Intrinsic::mips_sat_u_b: Max = 7; break;
2129  case Intrinsic::mips_sat_s_h:
2130  case Intrinsic::mips_sat_u_h: Max = 15; break;
2131  case Intrinsic::mips_sat_s_w:
2132  case Intrinsic::mips_sat_u_w: Max = 31; break;
2133  case Intrinsic::mips_sat_s_d:
2134  case Intrinsic::mips_sat_u_d: Max = 63; break;
2135  default: llvm_unreachable("Unmatched intrinsic");
2136  }
2137  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2138  if (Value < 0 || Value > Max)
2139  report_fatal_error("Immediate out of range");
2140  return SDValue();
2141  }
2142  case Intrinsic::mips_shf_b:
2143  case Intrinsic::mips_shf_h:
2144  case Intrinsic::mips_shf_w: {
2145  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2146  if (Value < 0 || Value > 255)
2147  report_fatal_error("Immediate out of range");
2148  return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2149  Op->getOperand(2), Op->getOperand(1));
2150  }
2151  case Intrinsic::mips_sldi_b:
2152  case Intrinsic::mips_sldi_h:
2153  case Intrinsic::mips_sldi_w:
2154  case Intrinsic::mips_sldi_d: {
2155  // Report an error for out of range values.
2156  int64_t Max;
2157  switch (Intrinsic) {
2158  case Intrinsic::mips_sldi_b: Max = 15; break;
2159  case Intrinsic::mips_sldi_h: Max = 7; break;
2160  case Intrinsic::mips_sldi_w: Max = 3; break;
2161  case Intrinsic::mips_sldi_d: Max = 1; break;
2162  default: llvm_unreachable("Unmatched intrinsic");
2163  }
2164  int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2165  if (Value < 0 || Value > Max)
2166  report_fatal_error("Immediate out of range");
2167  return SDValue();
2168  }
2169  case Intrinsic::mips_sll_b:
2170  case Intrinsic::mips_sll_h:
2171  case Intrinsic::mips_sll_w:
2172  case Intrinsic::mips_sll_d:
2173  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2174  truncateVecElts(Op, DAG));
2175  case Intrinsic::mips_slli_b:
2176  case Intrinsic::mips_slli_h:
2177  case Intrinsic::mips_slli_w:
2178  case Intrinsic::mips_slli_d:
2179  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2180  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2181  case Intrinsic::mips_splat_b:
2182  case Intrinsic::mips_splat_h:
2183  case Intrinsic::mips_splat_w:
2184  case Intrinsic::mips_splat_d:
2185  // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2186  // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2187  // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2188  // Instead we lower to MipsISD::VSHF and match from there.
2189  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2190  lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2191  Op->getOperand(1));
2192  case Intrinsic::mips_splati_b:
2193  case Intrinsic::mips_splati_h:
2194  case Intrinsic::mips_splati_w:
2195  case Intrinsic::mips_splati_d:
2196  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2197  lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2198  Op->getOperand(1));
2199  case Intrinsic::mips_sra_b:
2200  case Intrinsic::mips_sra_h:
2201  case Intrinsic::mips_sra_w:
2202  case Intrinsic::mips_sra_d:
2203  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2204  truncateVecElts(Op, DAG));
2205  case Intrinsic::mips_srai_b:
2206  case Intrinsic::mips_srai_h:
2207  case Intrinsic::mips_srai_w:
2208  case Intrinsic::mips_srai_d:
2209  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2210  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2211  case Intrinsic::mips_srari_b:
2212  case Intrinsic::mips_srari_h:
2213  case Intrinsic::mips_srari_w:
2214  case Intrinsic::mips_srari_d: {
2215  // Report an error for out of range values.
2216  int64_t Max;
2217  switch (Intrinsic) {
2218  case Intrinsic::mips_srari_b: Max = 7; break;
2219  case Intrinsic::mips_srari_h: Max = 15; break;
2220  case Intrinsic::mips_srari_w: Max = 31; break;
2221  case Intrinsic::mips_srari_d: Max = 63; break;
2222  default: llvm_unreachable("Unmatched intrinsic");
2223  }
2224  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2225  if (Value < 0 || Value > Max)
2226  report_fatal_error("Immediate out of range");
2227  return SDValue();
2228  }
2229  case Intrinsic::mips_srl_b:
2230  case Intrinsic::mips_srl_h:
2231  case Intrinsic::mips_srl_w:
2232  case Intrinsic::mips_srl_d:
2233  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2234  truncateVecElts(Op, DAG));
2235  case Intrinsic::mips_srli_b:
2236  case Intrinsic::mips_srli_h:
2237  case Intrinsic::mips_srli_w:
2238  case Intrinsic::mips_srli_d:
2239  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2240  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2241  case Intrinsic::mips_srlri_b:
2242  case Intrinsic::mips_srlri_h:
2243  case Intrinsic::mips_srlri_w:
2244  case Intrinsic::mips_srlri_d: {
2245  // Report an error for out of range values.
2246  int64_t Max;
2247  switch (Intrinsic) {
2248  case Intrinsic::mips_srlri_b: Max = 7; break;
2249  case Intrinsic::mips_srlri_h: Max = 15; break;
2250  case Intrinsic::mips_srlri_w: Max = 31; break;
2251  case Intrinsic::mips_srlri_d: Max = 63; break;
2252  default: llvm_unreachable("Unmatched intrinsic");
2253  }
2254  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2255  if (Value < 0 || Value > Max)
2256  report_fatal_error("Immediate out of range");
2257  return SDValue();
2258  }
2259  case Intrinsic::mips_subv_b:
2260  case Intrinsic::mips_subv_h:
2261  case Intrinsic::mips_subv_w:
2262  case Intrinsic::mips_subv_d:
2263  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2264  Op->getOperand(2));
2265  case Intrinsic::mips_subvi_b:
2266  case Intrinsic::mips_subvi_h:
2267  case Intrinsic::mips_subvi_w:
2268  case Intrinsic::mips_subvi_d:
2269  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2270  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2271  case Intrinsic::mips_vshf_b:
2272  case Intrinsic::mips_vshf_h:
2273  case Intrinsic::mips_vshf_w:
2274  case Intrinsic::mips_vshf_d:
2275  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2276  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2277  case Intrinsic::mips_xor_v:
2278  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2279  Op->getOperand(2));
2280  case Intrinsic::mips_xori_b:
2281  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2282  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2283  case Intrinsic::thread_pointer: {
2284  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2285  return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2286  }
2287  }
2288 }
2289 
2291  const MipsSubtarget &Subtarget) {
2292  SDLoc DL(Op);
2293  SDValue ChainIn = Op->getOperand(0);
2294  SDValue Address = Op->getOperand(2);
2295  SDValue Offset = Op->getOperand(3);
2296  EVT ResTy = Op->getValueType(0);
2297  EVT PtrTy = Address->getValueType(0);
2298 
2299  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2300  // however takes an i32 signed constant offset. The actual type of the
2301  // intrinsic is a scaled signed i10.
2302  if (Subtarget.isABI_N64())
2303  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2304 
2305  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2306  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2307  /* Alignment = */ 16);
2308 }
2309 
2310 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2311  SelectionDAG &DAG) const {
2312  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2313  switch (Intr) {
2314  default:
2315  return SDValue();
2316  case Intrinsic::mips_extp:
2317  return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2318  case Intrinsic::mips_extpdp:
2319  return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2320  case Intrinsic::mips_extr_w:
2321  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2322  case Intrinsic::mips_extr_r_w:
2323  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2324  case Intrinsic::mips_extr_rs_w:
2325  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2326  case Intrinsic::mips_extr_s_h:
2327  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2328  case Intrinsic::mips_mthlip:
2329  return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2330  case Intrinsic::mips_mulsaq_s_w_ph:
2331  return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2332  case Intrinsic::mips_maq_s_w_phl:
2333  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2334  case Intrinsic::mips_maq_s_w_phr:
2335  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2336  case Intrinsic::mips_maq_sa_w_phl:
2337  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2338  case Intrinsic::mips_maq_sa_w_phr:
2339  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2340  case Intrinsic::mips_dpaq_s_w_ph:
2341  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2342  case Intrinsic::mips_dpsq_s_w_ph:
2343  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2344  case Intrinsic::mips_dpaq_sa_l_w:
2345  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2346  case Intrinsic::mips_dpsq_sa_l_w:
2347  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2348  case Intrinsic::mips_dpaqx_s_w_ph:
2349  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2350  case Intrinsic::mips_dpaqx_sa_w_ph:
2351  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2352  case Intrinsic::mips_dpsqx_s_w_ph:
2353  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2354  case Intrinsic::mips_dpsqx_sa_w_ph:
2355  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2356  case Intrinsic::mips_ld_b:
2357  case Intrinsic::mips_ld_h:
2358  case Intrinsic::mips_ld_w:
2359  case Intrinsic::mips_ld_d:
2360  return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
2361  }
2362 }
2363 
2365  const MipsSubtarget &Subtarget) {
2366  SDLoc DL(Op);
2367  SDValue ChainIn = Op->getOperand(0);
2368  SDValue Value = Op->getOperand(2);
2369  SDValue Address = Op->getOperand(3);
2370  SDValue Offset = Op->getOperand(4);
2371  EVT PtrTy = Address->getValueType(0);
2372 
2373  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2374  // however takes an i32 signed constant offset. The actual type of the
2375  // intrinsic is a scaled signed i10.
2376  if (Subtarget.isABI_N64())
2377  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2378 
2379  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2380 
2381  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2382  /* Alignment = */ 16);
2383 }
2384 
2385 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2386  SelectionDAG &DAG) const {
2387  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2388  switch (Intr) {
2389  default:
2390  return SDValue();
2391  case Intrinsic::mips_st_b:
2392  case Intrinsic::mips_st_h:
2393  case Intrinsic::mips_st_w:
2394  case Intrinsic::mips_st_d:
2395  return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
2396  }
2397 }
2398 
2399 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2400 //
2401 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2402 // choose to sign-extend but we could have equally chosen zero-extend. The
2403 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2404 // result into this node later (possibly changing it to a zero-extend in the
2405 // process).
2406 SDValue MipsSETargetLowering::
2407 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2408  SDLoc DL(Op);
2409  EVT ResTy = Op->getValueType(0);
2410  SDValue Op0 = Op->getOperand(0);
2411  EVT VecTy = Op0->getValueType(0);
2412 
2413  if (!VecTy.is128BitVector())
2414  return SDValue();
2415 
2416  if (ResTy.isInteger()) {
2417  SDValue Op1 = Op->getOperand(1);
2418  EVT EltTy = VecTy.getVectorElementType();
2419  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2420  DAG.getValueType(EltTy));
2421  }
2422 
2423  return Op;
2424 }
2425 
2426 static bool isConstantOrUndef(const SDValue Op) {
2427  if (Op->isUndef())
2428  return true;
2429  if (isa<ConstantSDNode>(Op))
2430  return true;
2431  if (isa<ConstantFPSDNode>(Op))
2432  return true;
2433  return false;
2434 }
2435 
2437  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2438  if (isConstantOrUndef(Op->getOperand(i)))
2439  return true;
2440  return false;
2441 }
2442 
2443 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2444 // backend.
2445 //
2446 // Lowers according to the following rules:
2447 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2448 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2449 // immediate
2450 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2451 // is a power of 2 less than or equal to 64 and the value does not fit into a
2452 // signed 10-bit immediate
2453 // - Non-constant splats are legal as-is.
2454 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2455 // - All others are illegal and must be expanded.
2456 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2457  SelectionDAG &DAG) const {
2458  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2459  EVT ResTy = Op->getValueType(0);
2460  SDLoc DL(Op);
2461  APInt SplatValue, SplatUndef;
2462  unsigned SplatBitSize;
2463  bool HasAnyUndefs;
2464 
2465  if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2466  return SDValue();
2467 
2468  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2469  HasAnyUndefs, 8,
2470  !Subtarget.isLittle()) && SplatBitSize <= 64) {
2471  // We can only cope with 8, 16, 32, or 64-bit elements
2472  if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2473  SplatBitSize != 64)
2474  return SDValue();
2475 
2476  // If the value isn't an integer type we will have to bitcast
2477  // from an integer type first. Also, if there are any undefs, we must
2478  // lower them to defined values first.
2479  if (ResTy.isInteger() && !HasAnyUndefs)
2480  return Op;
2481 
2482  EVT ViaVecTy;
2483 
2484  switch (SplatBitSize) {
2485  default:
2486  return SDValue();
2487  case 8:
2488  ViaVecTy = MVT::v16i8;
2489  break;
2490  case 16:
2491  ViaVecTy = MVT::v8i16;
2492  break;
2493  case 32:
2494  ViaVecTy = MVT::v4i32;
2495  break;
2496  case 64:
2497  // There's no fill.d to fall back on for 64-bit values
2498  return SDValue();
2499  }
2500 
2501  // SelectionDAG::getConstant will promote SplatValue appropriately.
2502  SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
2503 
2504  // Bitcast to the type we originally wanted
2505  if (ViaVecTy != ResTy)
2506  Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2507 
2508  return Result;
2509  } else if (DAG.isSplatValue(Op, /* AllowUndefs */ false))
2510  return Op;
2511  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2512  // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2513  // The resulting code is the same length as the expansion, but it doesn't
2514  // use memory operations
2515  EVT ResTy = Node->getValueType(0);
2516 
2517  assert(ResTy.isVector());
2518 
2519  unsigned NumElts = ResTy.getVectorNumElements();
2520  SDValue Vector = DAG.getUNDEF(ResTy);
2521  for (unsigned i = 0; i < NumElts; ++i) {
2522  Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2523  Node->getOperand(i),
2524  DAG.getConstant(i, DL, MVT::i32));
2525  }
2526  return Vector;
2527  }
2528 
2529  return SDValue();
2530 }
2531 
2532 // Lower VECTOR_SHUFFLE into SHF (if possible).
2533 //
2534 // SHF splits the vector into blocks of four elements, then shuffles these
2535 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2536 //
2537 // It is therefore possible to lower into SHF when the mask takes the form:
2538 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2539 // When undef's appear they are treated as if they were whatever value is
2540 // necessary in order to fit the above forms.
2541 //
2542 // For example:
2543 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2544 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2545 // i32 7, i32 6, i32 5, i32 4>
2546 // is lowered to:
2547 // (SHF_H $w0, $w1, 27)
2548 // where the 27 comes from:
2549 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2551  SmallVector<int, 16> Indices,
2552  SelectionDAG &DAG) {
2553  int SHFIndices[4] = { -1, -1, -1, -1 };
2554 
2555  if (Indices.size() < 4)
2556  return SDValue();
2557 
2558  for (unsigned i = 0; i < 4; ++i) {
2559  for (unsigned j = i; j < Indices.size(); j += 4) {
2560  int Idx = Indices[j];
2561 
2562  // Convert from vector index to 4-element subvector index
2563  // If an index refers to an element outside of the subvector then give up
2564  if (Idx != -1) {
2565  Idx -= 4 * (j / 4);
2566  if (Idx < 0 || Idx >= 4)
2567  return SDValue();
2568  }
2569 
2570  // If the mask has an undef, replace it with the current index.
2571  // Note that it might still be undef if the current index is also undef
2572  if (SHFIndices[i] == -1)
2573  SHFIndices[i] = Idx;
2574 
2575  // Check that non-undef values are the same as in the mask. If they
2576  // aren't then give up
2577  if (!(Idx == -1 || Idx == SHFIndices[i]))
2578  return SDValue();
2579  }
2580  }
2581 
2582  // Calculate the immediate. Replace any remaining undefs with zero
2583  APInt Imm(32, 0);
2584  for (int i = 3; i >= 0; --i) {
2585  int Idx = SHFIndices[i];
2586 
2587  if (Idx == -1)
2588  Idx = 0;
2589 
2590  Imm <<= 2;
2591  Imm |= Idx & 0x3;
2592  }
2593 
2594  SDLoc DL(Op);
2595  return DAG.getNode(MipsISD::SHF, DL, ResTy,
2596  DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
2597 }
2598 
2599 /// Determine whether a range fits a regular pattern of values.
2600 /// This function accounts for the possibility of jumping over the End iterator.
2601 template <typename ValType>
2602 static bool
2604  unsigned CheckStride,
2606  ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2607  auto &I = Begin;
2608 
2609  while (I != End) {
2610  if (*I != -1 && *I != ExpectedIndex)
2611  return false;
2612  ExpectedIndex += ExpectedIndexStride;
2613 
2614  // Incrementing past End is undefined behaviour so we must increment one
2615  // step at a time and check for End at each step.
2616  for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2617  ; // Empty loop body.
2618  }
2619  return true;
2620 }
2621 
2622 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2623 //
2624 // It is a SPLATI when the mask is:
2625 // <x, x, x, ...>
2626 // where x is any valid index.
2627 //
2628 // When undef's appear in the mask they are treated as if they were whatever
2629 // value is necessary in order to fit the above form.
2630 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2631  SmallVector<int, 16> Indices,
2632  SelectionDAG &DAG) {
2633  assert((Indices.size() % 2) == 0);
2634 
2635  int SplatIndex = -1;
2636  for (const auto &V : Indices) {
2637  if (V != -1) {
2638  SplatIndex = V;
2639  break;
2640  }
2641  }
2642 
2643  return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2644  0);
2645 }
2646 
2647 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2648 //
2649 // ILVEV interleaves the even elements from each vector.
2650 //
2651 // It is possible to lower into ILVEV when the mask consists of two of the
2652 // following forms interleaved:
2653 // <0, 2, 4, ...>
2654 // <n, n+2, n+4, ...>
2655 // where n is the number of elements in the vector.
2656 // For example:
2657 // <0, 0, 2, 2, 4, 4, ...>
2658 // <0, n, 2, n+2, 4, n+4, ...>
2659 //
2660 // When undef's appear in the mask they are treated as if they were whatever
2661 // value is necessary in order to fit the above forms.
2663  SmallVector<int, 16> Indices,
2664  SelectionDAG &DAG) {
2665  assert((Indices.size() % 2) == 0);
2666 
2667  SDValue Wt;
2668  SDValue Ws;
2669  const auto &Begin = Indices.begin();
2670  const auto &End = Indices.end();
2671 
2672  // Check even elements are taken from the even elements of one half or the
2673  // other and pick an operand accordingly.
2674  if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2675  Wt = Op->getOperand(0);
2676  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2677  Wt = Op->getOperand(1);
2678  else
2679  return SDValue();
2680 
2681  // Check odd elements are taken from the even elements of one half or the
2682  // other and pick an operand accordingly.
2683  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2684  Ws = Op->getOperand(0);
2685  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2686  Ws = Op->getOperand(1);
2687  else
2688  return SDValue();
2689 
2690  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2691 }
2692 
2693 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2694 //
2695 // ILVOD interleaves the odd elements from each vector.
2696 //
2697 // It is possible to lower into ILVOD when the mask consists of two of the
2698 // following forms interleaved:
2699 // <1, 3, 5, ...>
2700 // <n+1, n+3, n+5, ...>
2701 // where n is the number of elements in the vector.
2702 // For example:
2703 // <1, 1, 3, 3, 5, 5, ...>
2704 // <1, n+1, 3, n+3, 5, n+5, ...>
2705 //
2706 // When undef's appear in the mask they are treated as if they were whatever
2707 // value is necessary in order to fit the above forms.
2709  SmallVector<int, 16> Indices,
2710  SelectionDAG &DAG) {
2711  assert((Indices.size() % 2) == 0);
2712 
2713  SDValue Wt;
2714  SDValue Ws;
2715  const auto &Begin = Indices.begin();
2716  const auto &End = Indices.end();
2717 
2718  // Check even elements are taken from the odd elements of one half or the
2719  // other and pick an operand accordingly.
2720  if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2721  Wt = Op->getOperand(0);
2722  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2723  Wt = Op->getOperand(1);
2724  else
2725  return SDValue();
2726 
2727  // Check odd elements are taken from the odd elements of one half or the
2728  // other and pick an operand accordingly.
2729  if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2730  Ws = Op->getOperand(0);
2731  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2732  Ws = Op->getOperand(1);
2733  else
2734  return SDValue();
2735 
2736  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2737 }
2738 
2739 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2740 //
2741 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2742 // each vector.
2743 //
2744 // It is possible to lower into ILVR when the mask consists of two of the
2745 // following forms interleaved:
2746 // <0, 1, 2, ...>
2747 // <n, n+1, n+2, ...>
2748 // where n is the number of elements in the vector.
2749 // For example:
2750 // <0, 0, 1, 1, 2, 2, ...>
2751 // <0, n, 1, n+1, 2, n+2, ...>
2752 //
2753 // When undef's appear in the mask they are treated as if they were whatever
2754 // value is necessary in order to fit the above forms.
2756  SmallVector<int, 16> Indices,
2757  SelectionDAG &DAG) {
2758  assert((Indices.size() % 2) == 0);
2759 
2760  SDValue Wt;
2761  SDValue Ws;
2762  const auto &Begin = Indices.begin();
2763  const auto &End = Indices.end();
2764 
2765  // Check even elements are taken from the right (lowest-indexed) elements of
2766  // one half or the other and pick an operand accordingly.
2767  if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2768  Wt = Op->getOperand(0);
2769  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2770  Wt = Op->getOperand(1);
2771  else
2772  return SDValue();
2773 
2774  // Check odd elements are taken from the right (lowest-indexed) elements of
2775  // one half or the other and pick an operand accordingly.
2776  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2777  Ws = Op->getOperand(0);
2778  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2779  Ws = Op->getOperand(1);
2780  else
2781  return SDValue();
2782 
2783  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2784 }
2785 
2786 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2787 //
2788 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2789 // of each vector.
2790 //
2791 // It is possible to lower into ILVL when the mask consists of two of the
2792 // following forms interleaved:
2793 // <x, x+1, x+2, ...>
2794 // <n+x, n+x+1, n+x+2, ...>
2795 // where n is the number of elements in the vector and x is half n.
2796 // For example:
2797 // <x, x, x+1, x+1, x+2, x+2, ...>
2798 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2799 //
2800 // When undef's appear in the mask they are treated as if they were whatever
2801 // value is necessary in order to fit the above forms.
2803  SmallVector<int, 16> Indices,
2804  SelectionDAG &DAG) {
2805  assert((Indices.size() % 2) == 0);
2806 
2807  unsigned HalfSize = Indices.size() / 2;
2808  SDValue Wt;
2809  SDValue Ws;
2810  const auto &Begin = Indices.begin();
2811  const auto &End = Indices.end();
2812 
2813  // Check even elements are taken from the left (highest-indexed) elements of
2814  // one half or the other and pick an operand accordingly.
2815  if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2816  Wt = Op->getOperand(0);
2817  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2818  Wt = Op->getOperand(1);
2819  else
2820  return SDValue();
2821 
2822  // Check odd elements are taken from the left (highest-indexed) elements of
2823  // one half or the other and pick an operand accordingly.
2824  if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2825  Ws = Op->getOperand(0);
2826  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2827  1))
2828  Ws = Op->getOperand(1);
2829  else
2830  return SDValue();
2831 
2832  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2833 }
2834 
2835 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2836 //
2837 // PCKEV copies the even elements of each vector into the result vector.
2838 //
2839 // It is possible to lower into PCKEV when the mask consists of two of the
2840 // following forms concatenated:
2841 // <0, 2, 4, ...>
2842 // <n, n+2, n+4, ...>
2843 // where n is the number of elements in the vector.
2844 // For example:
2845 // <0, 2, 4, ..., 0, 2, 4, ...>
2846 // <0, 2, 4, ..., n, n+2, n+4, ...>
2847 //
2848 // When undef's appear in the mask they are treated as if they were whatever
2849 // value is necessary in order to fit the above forms.
2851  SmallVector<int, 16> Indices,
2852  SelectionDAG &DAG) {
2853  assert((Indices.size() % 2) == 0);
2854 
2855  SDValue Wt;
2856  SDValue Ws;
2857  const auto &Begin = Indices.begin();
2858  const auto &Mid = Indices.begin() + Indices.size() / 2;
2859  const auto &End = Indices.end();
2860 
2861  if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2862  Wt = Op->getOperand(0);
2863  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2864  Wt = Op->getOperand(1);
2865  else
2866  return SDValue();
2867 
2868  if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2869  Ws = Op->getOperand(0);
2870  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2871  Ws = Op->getOperand(1);
2872  else
2873  return SDValue();
2874 
2875  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2876 }
2877 
2878 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2879 //
2880 // PCKOD copies the odd elements of each vector into the result vector.
2881 //
2882 // It is possible to lower into PCKOD when the mask consists of two of the
2883 // following forms concatenated:
2884 // <1, 3, 5, ...>
2885 // <n+1, n+3, n+5, ...>
2886 // where n is the number of elements in the vector.
2887 // For example:
2888 // <1, 3, 5, ..., 1, 3, 5, ...>
2889 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2890 //
2891 // When undef's appear in the mask they are treated as if they were whatever
2892 // value is necessary in order to fit the above forms.
2894  SmallVector<int, 16> Indices,
2895  SelectionDAG &DAG) {
2896  assert((Indices.size() % 2) == 0);
2897 
2898  SDValue Wt;
2899  SDValue Ws;
2900  const auto &Begin = Indices.begin();
2901  const auto &Mid = Indices.begin() + Indices.size() / 2;
2902  const auto &End = Indices.end();
2903 
2904  if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2905  Wt = Op->getOperand(0);
2906  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2907  Wt = Op->getOperand(1);
2908  else
2909  return SDValue();
2910 
2911  if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2912  Ws = Op->getOperand(0);
2913  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2914  Ws = Op->getOperand(1);
2915  else
2916  return SDValue();
2917 
2918  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2919 }
2920 
2921 // Lower VECTOR_SHUFFLE into VSHF.
2922 //
2923 // This mostly consists of converting the shuffle indices in Indices into a
2924 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2925 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2926 // if the type is v8i16 and all the indices are less than 8 then the second
2927 // operand is unused and can be replaced with anything. We choose to replace it
2928 // with the used operand since this reduces the number of instructions overall.
2930  SmallVector<int, 16> Indices,
2931  SelectionDAG &DAG) {
2933  SDValue Op0;
2934  SDValue Op1;
2935  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2936  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2937  bool Using1stVec = false;
2938  bool Using2ndVec = false;
2939  SDLoc DL(Op);
2940  int ResTyNumElts = ResTy.getVectorNumElements();
2941 
2942  for (int i = 0; i < ResTyNumElts; ++i) {
2943  // Idx == -1 means UNDEF
2944  int Idx = Indices[i];
2945 
2946  if (0 <= Idx && Idx < ResTyNumElts)
2947  Using1stVec = true;
2948  if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2949  Using2ndVec = true;
2950  }
2951 
2952  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2953  ++I)
2954  Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
2955 
2956  SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
2957 
2958  if (Using1stVec && Using2ndVec) {
2959  Op0 = Op->getOperand(0);
2960  Op1 = Op->getOperand(1);
2961  } else if (Using1stVec)
2962  Op0 = Op1 = Op->getOperand(0);
2963  else if (Using2ndVec)
2964  Op0 = Op1 = Op->getOperand(1);
2965  else
2966  llvm_unreachable("shuffle vector mask references neither vector operand?");
2967 
2968  // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2969  // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2970  // VSHF concatenates the vectors in a bitwise fashion:
2971  // <0b00, 0b01> + <0b10, 0b11> ->
2972  // 0b0100 + 0b1110 -> 0b01001110
2973  // <0b10, 0b11, 0b00, 0b01>
2974  // We must therefore swap the operands to get the correct result.
2975  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2976 }
2977 
2978 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2979 // indices in the shuffle.
2980 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2981  SelectionDAG &DAG) const {
2982  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2983  EVT ResTy = Op->getValueType(0);
2984 
2985  if (!ResTy.is128BitVector())
2986  return SDValue();
2987 
2988  int ResTyNumElts = ResTy.getVectorNumElements();
2989  SmallVector<int, 16> Indices;
2990 
2991  for (int i = 0; i < ResTyNumElts; ++i)
2992  Indices.push_back(Node->getMaskElt(i));
2993 
2994  // splati.[bhwd] is preferable to the others but is matched from
2995  // MipsISD::VSHF.
2996  if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2997  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2998  SDValue Result;
2999  if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
3000  return Result;
3001  if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
3002  return Result;
3003  if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
3004  return Result;
3005  if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
3006  return Result;
3007  if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
3008  return Result;
3009  if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
3010  return Result;
3011  if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
3012  return Result;
3013  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
3014 }
3015 
3017 MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
3018  MachineBasicBlock *BB) const {
3019  // $bb:
3020  // bposge32_pseudo $vr0
3021  // =>
3022  // $bb:
3023  // bposge32 $tbb
3024  // $fbb:
3025  // li $vr2, 0
3026  // b $sink
3027  // $tbb:
3028  // li $vr1, 1
3029  // $sink:
3030  // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
3031 
3032  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3034  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3035  DebugLoc DL = MI.getDebugLoc();
3036  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3038  MachineFunction *F = BB->getParent();
3039  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3040  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3042  F->insert(It, FBB);
3043  F->insert(It, TBB);
3044  F->insert(It, Sink);
3045 
3046  // Transfer the remainder of BB and its successor edges to Sink.
3047  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3048  BB->end());
3050 
3051  // Add successors.
3052  BB->addSuccessor(FBB);
3053  BB->addSuccessor(TBB);
3054  FBB->addSuccessor(Sink);
3055  TBB->addSuccessor(Sink);
3056 
3057  // Insert the real bposge32 instruction to $BB.
3058  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3059  // Insert the real bposge32c instruction to $BB.
3060  BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3061 
3062  // Fill $FBB.
3063  unsigned VR2 = RegInfo.createVirtualRegister(RC);
3064  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3065  .addReg(Mips::ZERO).addImm(0);
3066  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3067 
3068  // Fill $TBB.
3069  unsigned VR1 = RegInfo.createVirtualRegister(RC);
3070  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3071  .addReg(Mips::ZERO).addImm(1);
3072 
3073  // Insert phi function to $Sink.
3074  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3075  MI.getOperand(0).getReg())
3076  .addReg(VR2)
3077  .addMBB(FBB)
3078  .addReg(VR1)
3079  .addMBB(TBB);
3080 
3081  MI.eraseFromParent(); // The pseudo instruction is gone now.
3082  return Sink;
3083 }
3084 
3085 MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
3086  MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
3087  // $bb:
3088  // vany_nonzero $rd, $ws
3089  // =>
3090  // $bb:
3091  // bnz.b $ws, $tbb
3092  // b $fbb
3093  // $fbb:
3094  // li $rd1, 0
3095  // b $sink
3096  // $tbb:
3097  // li $rd2, 1
3098  // $sink:
3099  // $rd = phi($rd1, $fbb, $rd2, $tbb)
3100 
3101  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3103  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3104  DebugLoc DL = MI.getDebugLoc();
3105  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3107  MachineFunction *F = BB->getParent();
3108  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3109  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3111  F->insert(It, FBB);
3112  F->insert(It, TBB);
3113  F->insert(It, Sink);
3114 
3115  // Transfer the remainder of BB and its successor edges to Sink.
3116  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3117  BB->end());
3119 
3120  // Add successors.
3121  BB->addSuccessor(FBB);
3122  BB->addSuccessor(TBB);
3123  FBB->addSuccessor(Sink);
3124  TBB->addSuccessor(Sink);
3125 
3126  // Insert the real bnz.b instruction to $BB.
3127  BuildMI(BB, DL, TII->get(BranchOp))
3128  .addReg(MI.getOperand(1).getReg())
3129  .addMBB(TBB);
3130 
3131  // Fill $FBB.
3132  unsigned RD1 = RegInfo.createVirtualRegister(RC);
3133  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3134  .addReg(Mips::ZERO).addImm(0);
3135  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3136 
3137  // Fill $TBB.
3138  unsigned RD2 = RegInfo.createVirtualRegister(RC);
3139  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3140  .addReg(Mips::ZERO).addImm(1);
3141 
3142  // Insert phi function to $Sink.
3143  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3144  MI.getOperand(0).getReg())
3145  .addReg(RD1)
3146  .addMBB(FBB)
3147  .addReg(RD2)
3148  .addMBB(TBB);
3149 
3150  MI.eraseFromParent(); // The pseudo instruction is gone now.
3151  return Sink;
3152 }
3153 
3154 // Emit the COPY_FW pseudo instruction.
3155 //
3156 // copy_fw_pseudo $fd, $ws, n
3157 // =>
3158 // copy_u_w $rt, $ws, $n
3159 // mtc1 $rt, $fd
3160 //
3161 // When n is zero, the equivalent operation can be performed with (potentially)
3162 // zero instructions due to register overlaps. This optimization is never valid
3163 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3165 MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3166  MachineBasicBlock *BB) const {
3168  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3169  DebugLoc DL = MI.getDebugLoc();
3170  unsigned Fd = MI.getOperand(0).getReg();
3171  unsigned Ws = MI.getOperand(1).getReg();
3172  unsigned Lane = MI.getOperand(2).getImm();
3173 
3174  if (Lane == 0) {
3175  unsigned Wt = Ws;
3176  if (!Subtarget.useOddSPReg()) {
3177  // We must copy to an even-numbered MSA register so that the
3178  // single-precision sub-register is also guaranteed to be even-numbered.
3179  Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3180 
3181  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3182  }
3183 
3184  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3185  } else {
3186  unsigned Wt = RegInfo.createVirtualRegister(
3187  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3188  &Mips::MSA128WEvensRegClass);
3189 
3190  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3191  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3192  }
3193 
3194  MI.eraseFromParent(); // The pseudo instruction is gone now.
3195  return BB;
3196 }
3197 
3198 // Emit the COPY_FD pseudo instruction.
3199 //
3200 // copy_fd_pseudo $fd, $ws, n
3201 // =>
3202 // splati.d $wt, $ws, $n
3203 // copy $fd, $wt:sub_64
3204 //
3205 // When n is zero, the equivalent operation can be performed with (potentially)
3206 // zero instructions due to register overlaps. This optimization is always
3207 // valid because FR=1 mode which is the only supported mode in MSA.
3209 MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3210  MachineBasicBlock *BB) const {
3212 
3214  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3215  unsigned Fd = MI.getOperand(0).getReg();
3216  unsigned Ws = MI.getOperand(1).getReg();
3217  unsigned Lane = MI.getOperand(2).getImm() * 2;
3218  DebugLoc DL = MI.getDebugLoc();
3219 
3220  if (Lane == 0)
3221  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3222  else {
3223  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3224 
3225  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3226  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3227  }
3228 
3229  MI.eraseFromParent(); // The pseudo instruction is gone now.
3230  return BB;
3231 }
3232 
3233 // Emit the INSERT_FW pseudo instruction.
3234 //
3235 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3236 // =>
3237 // subreg_to_reg $wt:sub_lo, $fs
3238 // insve_w $wd[$n], $wd_in, $wt[0]
3240 MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
3241  MachineBasicBlock *BB) const {
3243  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3244  DebugLoc DL = MI.getDebugLoc();
3245  unsigned Wd = MI.getOperand(0).getReg();
3246  unsigned Wd_in = MI.getOperand(1).getReg();
3247  unsigned Lane = MI.getOperand(2).getImm();
3248  unsigned Fs = MI.getOperand(3).getReg();
3249  unsigned Wt = RegInfo.createVirtualRegister(
3250  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3251  &Mips::MSA128WEvensRegClass);
3252 
3253  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3254  .addImm(0)
3255  .addReg(Fs)
3256  .addImm(Mips::sub_lo);
3257  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3258  .addReg(Wd_in)
3259  .addImm(Lane)
3260  .addReg(Wt)
3261  .addImm(0);
3262 
3263  MI.eraseFromParent(); // The pseudo instruction is gone now.
3264  return BB;
3265 }
3266 
3267 // Emit the INSERT_FD pseudo instruction.
3268 //
3269 // insert_fd_pseudo $wd, $fs, n
3270 // =>
3271 // subreg_to_reg $wt:sub_64, $fs
3272 // insve_d $wd[$n], $wd_in, $wt[0]
3274 MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
3275  MachineBasicBlock *BB) const {
3277 
3279  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3280  DebugLoc DL = MI.getDebugLoc();
3281  unsigned Wd = MI.getOperand(0).getReg();
3282  unsigned Wd_in = MI.getOperand(1).getReg();
3283  unsigned Lane = MI.getOperand(2).getImm();
3284  unsigned Fs = MI.getOperand(3).getReg();
3285  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3286 
3287  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3288  .addImm(0)
3289  .addReg(Fs)
3290  .addImm(Mips::sub_64);
3291  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3292  .addReg(Wd_in)
3293  .addImm(Lane)
3294  .addReg(Wt)
3295  .addImm(0);
3296 
3297  MI.eraseFromParent(); // The pseudo instruction is gone now.
3298  return BB;
3299 }
3300 
3301 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3302 //
3303 // For integer:
3304 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3305 // =>
3306 // (SLL $lanetmp1, $lane, <log2size)
3307 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3308 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3309 // (NEG $lanetmp2, $lanetmp1)
3310 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3311 //
3312 // For floating point:
3313 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3314 // =>
3315 // (SUBREG_TO_REG $wt, $fs, <subreg>)
3316 // (SLL $lanetmp1, $lane, <log2size)
3317 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3318 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3319 // (NEG $lanetmp2, $lanetmp1)
3320 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3321 MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3322  MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3323  bool IsFP) const {
3325  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3326  DebugLoc DL = MI.getDebugLoc();
3327  unsigned Wd = MI.getOperand(0).getReg();
3328  unsigned SrcVecReg = MI.getOperand(1).getReg();
3329  unsigned LaneReg = MI.getOperand(2).getReg();
3330  unsigned SrcValReg = MI.getOperand(3).getReg();
3331 
3332  const TargetRegisterClass *VecRC = nullptr;
3333  // FIXME: This should be true for N32 too.
3334  const TargetRegisterClass *GPRRC =
3335  Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3336  unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3337  unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
3338  unsigned EltLog2Size;
3339  unsigned InsertOp = 0;
3340  unsigned InsveOp = 0;
3341  switch (EltSizeInBytes) {
3342  default:
3343  llvm_unreachable("Unexpected size");
3344  case 1:
3345  EltLog2Size = 0;
3346  InsertOp = Mips::INSERT_B;
3347  InsveOp = Mips::INSVE_B;
3348  VecRC = &Mips::MSA128BRegClass;
3349  break;
3350  case 2:
3351  EltLog2Size = 1;
3352  InsertOp = Mips::INSERT_H;
3353  InsveOp = Mips::INSVE_H;
3354  VecRC = &Mips::MSA128HRegClass;
3355  break;
3356  case 4:
3357  EltLog2Size = 2;
3358  InsertOp = Mips::INSERT_W;
3359  InsveOp = Mips::INSVE_W;
3360  VecRC = &Mips::MSA128WRegClass;
3361  break;
3362  case 8:
3363  EltLog2Size = 3;
3364  InsertOp = Mips::INSERT_D;
3365  InsveOp = Mips::INSVE_D;
3366  VecRC = &Mips::MSA128DRegClass;
3367  break;
3368  }
3369 
3370  if (IsFP) {
3371  unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3372  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3373  .addImm(0)
3374  .addReg(SrcValReg)
3375  .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3376  SrcValReg = Wt;
3377  }
3378 
3379  // Convert the lane index into a byte index
3380  if (EltSizeInBytes != 1) {
3381  unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3382  BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3383  .addReg(LaneReg)
3384  .addImm(EltLog2Size);
3385  LaneReg = LaneTmp1;
3386  }
3387 
3388  // Rotate bytes around so that the desired lane is element zero
3389  unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3390  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3391  .addReg(SrcVecReg)
3392  .addReg(SrcVecReg)
3393  .addReg(LaneReg, 0, SubRegIdx);
3394 
3395  unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3396  if (IsFP) {
3397  // Use insve.df to insert to element zero
3398  BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3399  .addReg(WdTmp1)
3400  .addImm(0)
3401  .addReg(SrcValReg)
3402  .addImm(0);
3403  } else {
3404  // Use insert.df to insert to element zero
3405  BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3406  .addReg(WdTmp1)
3407  .addReg(SrcValReg)
3408  .addImm(0);
3409  }
3410 
3411  // Rotate elements the rest of the way for a full rotation.
3412  // sld.df inteprets $rt modulo the number of columns so we only need to negate
3413  // the lane index to do this.
3414  unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3415  BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3416  LaneTmp2)
3417  .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3418  .addReg(LaneReg);
3419  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3420  .addReg(WdTmp2)
3421  .addReg(WdTmp2)
3422  .addReg(LaneTmp2, 0, SubRegIdx);
3423 
3424  MI.eraseFromParent(); // The pseudo instruction is gone now.
3425  return BB;
3426 }
3427 
3428 // Emit the FILL_FW pseudo instruction.
3429 //
3430 // fill_fw_pseudo $wd, $fs
3431 // =>
3432 // implicit_def $wt1
3433 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3434 // splati.w $wd, $wt2[0]
3436 MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
3437  MachineBasicBlock *BB) const {
3439  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3440  DebugLoc DL = MI.getDebugLoc();
3441  unsigned Wd = MI.getOperand(0).getReg();
3442  unsigned Fs = MI.getOperand(1).getReg();
3443  unsigned Wt1 = RegInfo.createVirtualRegister(
3444  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3445  : &Mips::MSA128WEvensRegClass);
3446  unsigned Wt2 = RegInfo.createVirtualRegister(
3447  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3448  : &Mips::MSA128WEvensRegClass);
3449 
3450  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3451  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3452  .addReg(Wt1)
3453  .addReg(Fs)
3454  .addImm(Mips::sub_lo);
3455  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3456 
3457  MI.eraseFromParent(); // The pseudo instruction is gone now.
3458  return BB;
3459 }
3460 
3461 // Emit the FILL_FD pseudo instruction.
3462 //
3463 // fill_fd_pseudo $wd, $fs
3464 // =>
3465 // implicit_def $wt1
3466 // insert_subreg $wt2:subreg_64, $wt1, $fs
3467 // splati.d $wd, $wt2[0]
3469 MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
3470  MachineBasicBlock *BB) const {
3472 
3474  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3475  DebugLoc DL = MI.getDebugLoc();
3476  unsigned Wd = MI.getOperand(0).getReg();
3477  unsigned Fs = MI.getOperand(1).getReg();
3478  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3479  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3480 
3481  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3482  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3483  .addReg(Wt1)
3484  .addReg(Fs)
3485  .addImm(Mips::sub_64);
3486  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3487 
3488  MI.eraseFromParent(); // The pseudo instruction is gone now.
3489  return BB;
3490 }
3491 
3492 // Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3493 // register.
3494 //
3495 // STF16 MSA128F16:$wd, mem_simm10:$addr
3496 // =>
3497 // copy_u.h $rtemp,$wd[0]
3498 // sh $rtemp, $addr
3499 //
3500 // Safety: We can't use st.h & co as they would over write the memory after
3501 // the destination. It would require half floats be allocated 16 bytes(!) of
3502 // space.
3504 MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3505  MachineBasicBlock *BB) const {
3506 
3508  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3509  DebugLoc DL = MI.getDebugLoc();
3510  unsigned Ws = MI.getOperand(0).getReg();
3511  unsigned Rt = MI.getOperand(1).getReg();
3512  const MachineMemOperand &MMO = **MI.memoperands_begin();
3513  unsigned Imm = MMO.getOffset();
3514 
3515  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3516  // spill and reload can expand as a GPR64 operand. Examine the
3517  // operand in detail and default to ABI.
3518  const TargetRegisterClass *RC =
3519  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3520  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3521  : &Mips::GPR64RegClass);
3522  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3523  unsigned Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3524 
3525  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3526  if(!UsingMips32) {
3527  unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3528  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3529  .addImm(0)
3530  .addReg(Rs)
3531  .addImm(Mips::sub_32);
3532  Rs = Tmp;
3533  }
3534  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3535  .addReg(Rs)
3536  .addReg(Rt)
3537  .addImm(Imm)
3539  &MMO, MMO.getOffset(), MMO.getSize()));
3540 
3541  MI.eraseFromParent();
3542  return BB;
3543 }
3544 
3545 // Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3546 //
3547 // LD_F16 MSA128F16:$wd, mem_simm10:$addr
3548 // =>
3549 // lh $rtemp, $addr
3550 // fill.h $wd, $rtemp
3551 //
3552 // Safety: We can't use ld.h & co as they over-read from the source.
3553 // Additionally, if the address is not modulo 16, 2 cases can occur:
3554 // a) Segmentation fault as the load instruction reads from a memory page
3555 // memory it's not supposed to.
3556 // b) The load crosses an implementation specific boundary, requiring OS
3557 // intervention.
3559 MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3560  MachineBasicBlock *BB) const {
3561 
3563  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3564  DebugLoc DL = MI.getDebugLoc();
3565  unsigned Wd = MI.getOperand(0).getReg();
3566 
3567  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3568  // spill and reload can expand as a GPR64 operand. Examine the
3569  // operand in detail and default to ABI.
3570  const TargetRegisterClass *RC =
3571  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3572  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3573  : &Mips::GPR64RegClass);
3574 
3575  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3576  unsigned Rt = RegInfo.createVirtualRegister(RC);
3577 
3578  MachineInstrBuilder MIB =
3579  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3580  for (unsigned i = 1; i < MI.getNumOperands(); i++)
3581  MIB.add(MI.getOperand(i));
3582 
3583  if(!UsingMips32) {
3584  unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3585  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3586  Rt = Tmp;
3587  }
3588 
3589  BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3590 
3591  MI.eraseFromParent();
3592  return BB;
3593 }
3594 
3595 // Emit the FPROUND_PSEUDO instruction.
3596 //
3597 // Round an FGR64Opnd, FGR32Opnd to an f16.
3598 //
3599 // Safety: Cycle the operand through the GPRs so the result always ends up
3600 // the correct MSA register.
3601 //
3602 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3603 // / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3604 // (which they can be, as the MSA registers are defined to alias the
3605 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3606 // the correct register class. That requires operands be tie-able across
3607 // register classes which have a sub/super register class relationship.
3608 //
3609 // For FPG32Opnd:
3610 //
3611 // FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3612 // =>
3613 // mfc1 $rtemp, $fs
3614 // fill.w $rtemp, $wtemp
3615 // fexdo.w $wd, $wtemp, $wtemp
3616 //
3617 // For FPG64Opnd on mips32r2+:
3618 //
3619 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3620 // =>
3621 // mfc1 $rtemp, $fs
3622 // fill.w $rtemp, $wtemp
3623 // mfhc1 $rtemp2, $fs
3624 // insert.w $wtemp[1], $rtemp2
3625 // insert.w $wtemp[3], $rtemp2
3626 // fexdo.w $wtemp2, $wtemp, $wtemp
3627 // fexdo.h $wd, $temp2, $temp2
3628 //
3629 // For FGR64Opnd on mips64r2+:
3630 //
3631 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3632 // =>
3633 // dmfc1 $rtemp, $fs
3634 // fill.d $rtemp, $wtemp
3635 // fexdo.w $wtemp2, $wtemp, $wtemp
3636 // fexdo.h $wd, $wtemp2, $wtemp2
3637 //
3638 // Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3639 // undef bits are "just right" and the exception enable bits are
3640 // set. By using fill.w to replicate $fs into all elements over
3641 // insert.w for one element, we avoid that potiential case. If
3642 // fexdo.[hw] causes an exception in, the exception is valid and it
3643 // occurs for all elements.
3645 MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3646  MachineBasicBlock *BB,
3647  bool IsFGR64) const {
3648 
3649  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3650  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3651  // it.
3653 
3654  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3655  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3656 
3658  DebugLoc DL = MI.getDebugLoc();
3659  unsigned Wd = MI.getOperand(0).getReg();
3660  unsigned Fs = MI.getOperand(1).getReg();
3661 
3662  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3663  unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3664  const TargetRegisterClass *GPRRC =
3665  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3666  unsigned MFC1Opc = IsFGR64onMips64
3667  ? Mips::DMFC1
3668  : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3669  unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3670 
3671  // Perform the register class copy as mentioned above.
3672  unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3673  BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3674  BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3675  unsigned WPHI = Wtemp;
3676 
3677  if (IsFGR64onMips32) {
3678  unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3679  BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3680  unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3681  unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3682  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3683  .addReg(Wtemp)
3684  .addReg(Rtemp2)
3685  .addImm(1);
3686  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3687  .addReg(Wtemp2)
3688  .addReg(Rtemp2)
3689  .addImm(3);
3690  WPHI = Wtemp3;
3691  }
3692 
3693  if (IsFGR64) {
3694  unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3695  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3696  .addReg(WPHI)
3697  .addReg(WPHI);
3698  WPHI = Wtemp2;
3699  }
3700 
3701  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3702 
3703  MI.eraseFromParent();
3704  return BB;
3705 }
3706 
3707 // Emit the FPEXTEND_PSEUDO instruction.
3708 //
3709 // Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3710 //
3711 // Safety: Cycle the result through the GPRs so the result always ends up
3712 // the correct floating point register.
3713 //
3714 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3715 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3716 // (which they can be, as the MSA registers are defined to alias the
3717 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3718 // the correct register class. That requires operands be tie-able across
3719 // register classes which have a sub/super register class relationship. I
3720 // haven't checked.
3721 //
3722 // For FGR32Opnd:
3723 //
3724 // FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3725 // =>
3726 // fexupr.w $wtemp, $ws
3727 // copy_s.w $rtemp, $ws[0]
3728 // mtc1 $rtemp, $fd
3729 //
3730 // For FGR64Opnd on Mips64:
3731 //
3732 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3733 // =>
3734 // fexupr.w $wtemp, $ws
3735 // fexupr.d $wtemp2, $wtemp
3736 // copy_s.d $rtemp, $wtemp2s[0]
3737 // dmtc1 $rtemp, $fd
3738 //
3739 // For FGR64Opnd on Mips32:
3740 //
3741 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3742 // =>
3743 // fexupr.w $wtemp, $ws
3744 // fexupr.d $wtemp2, $wtemp
3745 // copy_s.w $rtemp, $wtemp2[0]
3746 // mtc1 $rtemp, $ftemp
3747 // copy_s.w $rtemp2, $wtemp2[1]
3748 // $fd = mthc1 $rtemp2, $ftemp
3750 MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3751  MachineBasicBlock *BB,
3752  bool IsFGR64) const {
3753 
3754  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3755  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3756  // it.
3758 
3759  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3760  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3761 
3763  DebugLoc DL = MI.getDebugLoc();
3764  unsigned Fd = MI.getOperand(0).getReg();
3765  unsigned Ws = MI.getOperand(1).getReg();
3766 
3767  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3768  const TargetRegisterClass *GPRRC =
3769  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3770  unsigned MTC1Opc = IsFGR64onMips64
3771  ? Mips::DMTC1
3772  : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3773  unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3774 
3775  unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3776  unsigned WPHI = Wtemp;
3777 
3778  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3779  if (IsFGR64) {
3780  WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3781  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3782  }
3783 
3784  // Perform the safety regclass copy mentioned above.
3785  unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3786  unsigned FPRPHI = IsFGR64onMips32
3787  ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3788  : Fd;
3789  BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3790  BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3791 
3792  if (IsFGR64onMips32) {
3793  unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3794  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3795  .addReg(WPHI)
3796  .addImm(1);
3797  BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3798  .addReg(FPRPHI)
3799  .addReg(Rtemp2);
3800  }
3801 
3802  MI.eraseFromParent();
3803  return BB;
3804 }
3805 
3806 // Emit the FEXP2_W_1 pseudo instructions.
3807 //
3808 // fexp2_w_1_pseudo $wd, $wt
3809 // =>
3810 // ldi.w $ws, 1
3811 // fexp2.w $wd, $ws, $wt
3813 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
3814  MachineBasicBlock *BB) const {
3816  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3817  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3818  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3819  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3820  DebugLoc DL = MI.getDebugLoc();
3821 
3822  // Splat 1.0 into a vector
3823  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3824  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3825 
3826  // Emit 1.0 * fexp2(Wt)
3827  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3828  .addReg(Ws2)
3829  .addReg(MI.getOperand(1).getReg());
3830 
3831  MI.eraseFromParent(); // The pseudo instruction is gone now.
3832  return BB;
3833 }
3834 
3835 // Emit the FEXP2_D_1 pseudo instructions.
3836 //
3837 // fexp2_d_1_pseudo $wd, $wt
3838 // =>
3839 // ldi.d $ws, 1
3840 // fexp2.d $wd, $ws, $wt
3842 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
3843  MachineBasicBlock *BB) const {
3845  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3846  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3847  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3848  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3849  DebugLoc DL = MI.getDebugLoc();
3850 
3851  // Splat 1.0 into a vector
3852  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3853  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3854 
3855  // Emit 1.0 * fexp2(Wt)
3856  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3857  .addReg(Ws2)
3858  .addReg(MI.getOperand(1).getReg());
3859 
3860  MI.eraseFromParent(); // The pseudo instruction is gone now.
3861  return BB;
3862 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:590
static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
const MachineInstrBuilder & add(const MachineOperand &MO) const
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:908
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:617
EVT getValueType() const
Return the ValueType of the referenced return value.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:952
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MipsSubtarget & Subtarget
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:673
This class represents lattice values for constants.
Definition: AllocatorList.h:23
value_iterator value_end() const
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:628
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:386
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
const SDValue & getBasePtr() const
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
unsigned getReg() const
getReg - Returns the register number.
const SDValue & getValue() const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
SDVTList getVTList() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:647
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
const MipsInstrInfo * getInstrInfo() const override
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
const SDValue & getChain() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isABI_O32() const
unsigned getAlignment() const
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:403
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:807
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:454
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const
Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
const Triple & getTargetTriple() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool hasMips64() const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool hasDSPR2() const
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
Shift and rotation operations.
Definition: ISDOpcodes.h:429
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getScalarValueSizeInBits() const
bool isGP64bit() const
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
bool hasMips32r6() const
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
unsigned Intr
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
This file implements a class to represent arbitrary precision integral constant values and operations...
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:497
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:448
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
static bool isConstantOrUndef(const SDValue Op)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
unsigned getIncomingArgSize() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:867
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:990
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:124
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:581
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:543
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:346
TargetInstrInfo - Interface to description of machine instruction set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:635
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1165
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:363
const SDValue & getBasePtr() const
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:395
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Machine Value Type.
bool isLittleEndian() const
Tests whether the target triple is little endian.
Definition: Triple.cpp:1510
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const SDValue & getOperand(unsigned Num) const
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:351
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
const APInt & getAPIntValue() const
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static mvt_range vector_valuetypes()
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:575
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)
Extended Value Type.
Definition: ValueTypes.h:33
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
bool isSingleFloat() const
unsigned ceilLogBase2() const
Definition: APInt.h:1750
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
bool hasMips64r6() const
This class contains a discriminated union of information about pointers in memory operands...
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isABI_N32() const
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:970
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:406
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG)
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
bool isLittle() const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
const MipsRegisterInfo * getRegisterInfo() const override
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:358
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
double Log2(double Value)
Return the log base 2 of the specified value.
Definition: MathExtras.h:527
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
value_iterator value_begin() const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
Definition: SelectionDAG.h:739
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
bool hasCnMips() const
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:95
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:667
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Represents one node in the SelectionDAG.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
int64_t getImm() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool hasDSP() const
unsigned logBase2() const
Definition: APInt.h:1747
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG)
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:439
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
bool isPowerOf2() const
Check if this APInt&#39;s value is a power of two greater than zero.
Definition: APInt.h:463
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:487
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:331
int getMaskElt(unsigned Idx) const
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:406
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool is128BitVector() const
Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:181
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:637
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the &#39;representative&#39; register class for the specified value type.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:405
Flags getFlags() const
Return the raw flags of the source value,.
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332