LLVM  10.0.0svn
MipsSEISelLowering.cpp
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1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsTargetLowering specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelLowering.h"
14 #include "MipsMachineFunction.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Triple.h"
35 #include "llvm/IR/DebugLoc.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/Casting.h"
39 #include "llvm/Support/Debug.h"
44 #include <algorithm>
45 #include <cassert>
46 #include <cstdint>
47 #include <iterator>
48 #include <utility>
49 
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "mips-isel"
53 
54 static cl::opt<bool>
55 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
56  cl::desc("MIPS: permit tail calls."), cl::init(false));
57 
58 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
59  cl::desc("Expand double precision loads and "
60  "stores to their single precision "
61  "counterparts"));
62 
64  const MipsSubtarget &STI)
65  : MipsTargetLowering(TM, STI) {
66  // Set up the register classes
67  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
68 
69  if (Subtarget.isGP64bit())
70  addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
71 
72  if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
73  // Expand all truncating stores and extending loads.
74  for (MVT VT0 : MVT::vector_valuetypes()) {
75  for (MVT VT1 : MVT::vector_valuetypes()) {
76  setTruncStoreAction(VT0, VT1, Expand);
80  }
81  }
82  }
83 
84  if (Subtarget.hasDSP()) {
86 
87  for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
88  addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
89 
90  // Expand all builtin opcodes.
91  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
92  setOperationAction(Opc, VecTys[i], Expand);
93 
94  setOperationAction(ISD::ADD, VecTys[i], Legal);
95  setOperationAction(ISD::SUB, VecTys[i], Legal);
96  setOperationAction(ISD::LOAD, VecTys[i], Legal);
97  setOperationAction(ISD::STORE, VecTys[i], Legal);
99  }
100 
106 
107  if (Subtarget.hasMips32r2()) {
110  }
111  }
112 
113  if (Subtarget.hasDSPR2())
115 
116  if (Subtarget.hasMSA()) {
117  addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
118  addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
119  addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
120  addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
121  addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
122  addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
123  addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
124 
125  // f16 is a storage-only type, always promote it to f32.
126  addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
162 
168  }
169 
170  if (!Subtarget.useSoftFloat()) {
171  addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
172 
173  // When dealing with single precision only, use libcalls
174  if (!Subtarget.isSingleFloat()) {
175  if (Subtarget.isFP64bit())
176  addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
177  else
178  addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
179  }
180  }
181 
186 
187  if (Subtarget.hasCnMips())
189  else if (Subtarget.isGP64bit())
191 
192  if (Subtarget.isGP64bit()) {
199  }
200 
203 
209 
211 
215 
217  !Subtarget.hasMips64()) {
219  }
220 
221  if (NoDPLoadStore) {
224  }
225 
226  if (Subtarget.hasMips32r6()) {
227  // MIPS32r6 replaces the accumulator-based multiplies with a three register
228  // instruction
234 
235  // MIPS32r6 replaces the accumulator-based division/remainder with separate
236  // three register division and remainder instructions.
243 
244  // MIPS32r6 replaces conditional moves with an equivalent that removes the
245  // need for three GPR read ports.
249 
253 
254  assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
258 
260 
261  // Floating point > and >= are supported via < and <=
266 
271  }
272 
273  if (Subtarget.hasMips64r6()) {
274  // MIPS64r6 replaces the accumulator-based multiplies with a three register
275  // instruction
281 
282  // MIPS32r6 replaces the accumulator-based division/remainder with separate
283  // three register division and remainder instructions.
290 
291  // MIPS64r6 replaces conditional moves with an equivalent that removes the
292  // need for three GPR read ports.
296  }
297 
299 }
300 
301 const MipsTargetLowering *
303  const MipsSubtarget &STI) {
304  return new MipsSETargetLowering(TM, STI);
305 }
306 
307 const TargetRegisterClass *
309  if (VT == MVT::Untyped)
310  return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
311 
313 }
314 
315 // Enable MSA support for the given integer type and Register class.
318  addRegisterClass(Ty, RC);
319 
320  // Expand all builtin opcodes.
321  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
322  setOperationAction(Opc, Ty, Expand);
323 
331 
353 
354  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
359  }
360 
367 }
368 
369 // Enable MSA support for the given floating-point type and Register class.
372  addRegisterClass(Ty, RC);
373 
374  // Expand all builtin opcodes.
375  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
376  setOperationAction(Opc, Ty, Expand);
377 
384 
385  if (Ty != MVT::v8f16) {
397 
405  }
406 }
407 
408 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
409  if(!Subtarget.hasMips32r6())
410  return MipsTargetLowering::LowerOperation(Op, DAG);
411 
412  EVT ResTy = Op->getValueType(0);
413  SDLoc DL(Op);
414 
415  // Although MTC1_D64 takes an i32 and writes an f64, the upper 32 bits of the
416  // floating point register are undefined. Not really an issue as sel.d, which
417  // is produced from an FSELECT node, only looks at bit 0.
418  SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
419  return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
420  Op->getOperand(2));
421 }
422 
424  EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const {
426 
428  // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
429  // implementation defined whether this is handled by hardware, software, or
430  // a hybrid of the two but it's expected that most implementations will
431  // handle the majority of cases in hardware.
432  if (Fast)
433  *Fast = true;
434  return true;
435  }
436 
437  switch (SVT) {
438  case MVT::i64:
439  case MVT::i32:
440  if (Fast)
441  *Fast = true;
442  return true;
443  default:
444  return false;
445  }
446 }
447 
449  SelectionDAG &DAG) const {
450  switch(Op.getOpcode()) {
451  case ISD::LOAD: return lowerLOAD(Op, DAG);
452  case ISD::STORE: return lowerSTORE(Op, DAG);
453  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
454  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
455  case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
456  case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
457  case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
458  case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
459  case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
460  DAG);
461  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
462  case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
463  case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
464  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
465  case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
466  case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
467  case ISD::SELECT: return lowerSELECT(Op, DAG);
468  case ISD::BITCAST: return lowerBITCAST(Op, DAG);
469  }
470 
471  return MipsTargetLowering::LowerOperation(Op, DAG);
472 }
473 
474 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
475 //
476 // Performs the following transformations:
477 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
478 // sign/zero-extension is completely overwritten by the new one performed by
479 // the ISD::AND.
480 // - Removes redundant zero extensions performed by an ISD::AND.
483  const MipsSubtarget &Subtarget) {
484  if (!Subtarget.hasMSA())
485  return SDValue();
486 
487  SDValue Op0 = N->getOperand(0);
488  SDValue Op1 = N->getOperand(1);
489  unsigned Op0Opcode = Op0->getOpcode();
490 
491  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
492  // where $d + 1 == 2^n and n == 32
493  // or $d + 1 == 2^n and n <= 32 and ZExt
494  // -> (MipsVExtractZExt $a, $b, $c)
495  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
496  Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
498 
499  if (!Mask)
500  return SDValue();
501 
502  int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
503 
504  if (Log2IfPositive <= 0)
505  return SDValue(); // Mask+1 is not a power of 2
506 
507  SDValue Op0Op2 = Op0->getOperand(2);
508  EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
509  unsigned ExtendTySize = ExtendTy.getSizeInBits();
510  unsigned Log2 = Log2IfPositive;
511 
512  if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
513  Log2 == ExtendTySize) {
514  SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
515  return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
516  Op0->getVTList(),
517  makeArrayRef(Ops, Op0->getNumOperands()));
518  }
519  }
520 
521  return SDValue();
522 }
523 
524 // Determine if the specified node is a constant vector splat.
525 //
526 // Returns true and sets Imm if:
527 // * N is a ISD::BUILD_VECTOR representing a constant splat
528 //
529 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
530 // differences are that it assumes the MSA has already been checked and the
531 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
532 // must not be in order for binsri.d to be selectable).
533 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
535 
536  if (!Node)
537  return false;
538 
539  APInt SplatValue, SplatUndef;
540  unsigned SplatBitSize;
541  bool HasAnyUndefs;
542 
543  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
544  8, !IsLittleEndian))
545  return false;
546 
547  Imm = SplatValue;
548 
549  return true;
550 }
551 
552 // Test whether the given node is an all-ones build_vector.
553 static bool isVectorAllOnes(SDValue N) {
554  // Look through bitcasts. Endianness doesn't matter because we are looking
555  // for an all-ones value.
556  if (N->getOpcode() == ISD::BITCAST)
557  N = N->getOperand(0);
558 
560 
561  if (!BVN)
562  return false;
563 
564  APInt SplatValue, SplatUndef;
565  unsigned SplatBitSize;
566  bool HasAnyUndefs;
567 
568  // Endianness doesn't matter in this context because we are looking for
569  // an all-ones value.
570  if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
571  return SplatValue.isAllOnesValue();
572 
573  return false;
574 }
575 
576 // Test whether N is the bitwise inverse of OfNode.
577 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
578  if (N->getOpcode() != ISD::XOR)
579  return false;
580 
581  if (isVectorAllOnes(N->getOperand(0)))
582  return N->getOperand(1) == OfNode;
583 
584  if (isVectorAllOnes(N->getOperand(1)))
585  return N->getOperand(0) == OfNode;
586 
587  return false;
588 }
589 
590 // Perform combines where ISD::OR is the root node.
591 //
592 // Performs the following transformations:
593 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
594 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
595 // vector type.
598  const MipsSubtarget &Subtarget) {
599  if (!Subtarget.hasMSA())
600  return SDValue();
601 
602  EVT Ty = N->getValueType(0);
603 
604  if (!Ty.is128BitVector())
605  return SDValue();
606 
607  SDValue Op0 = N->getOperand(0);
608  SDValue Op1 = N->getOperand(1);
609 
610  if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
611  SDValue Op0Op0 = Op0->getOperand(0);
612  SDValue Op0Op1 = Op0->getOperand(1);
613  SDValue Op1Op0 = Op1->getOperand(0);
614  SDValue Op1Op1 = Op1->getOperand(1);
615  bool IsLittleEndian = !Subtarget.isLittle();
616 
617  SDValue IfSet, IfClr, Cond;
618  bool IsConstantMask = false;
619  APInt Mask, InvMask;
620 
621  // If Op0Op0 is an appropriate mask, try to find it's inverse in either
622  // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
623  // looking.
624  // IfClr will be set if we find a valid match.
625  if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
626  Cond = Op0Op0;
627  IfSet = Op0Op1;
628 
629  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
630  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
631  IfClr = Op1Op1;
632  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
633  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
634  IfClr = Op1Op0;
635 
636  IsConstantMask = true;
637  }
638 
639  // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
640  // thing again using this mask.
641  // IfClr will be set if we find a valid match.
642  if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
643  Cond = Op0Op1;
644  IfSet = Op0Op0;
645 
646  if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
647  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
648  IfClr = Op1Op1;
649  else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
650  Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
651  IfClr = Op1Op0;
652 
653  IsConstantMask = true;
654  }
655 
656  // If IfClr is not yet set, try looking for a non-constant match.
657  // IfClr will be set if we find a valid match amongst the eight
658  // possibilities.
659  if (!IfClr.getNode()) {
660  if (isBitwiseInverse(Op0Op0, Op1Op0)) {
661  Cond = Op1Op0;
662  IfSet = Op1Op1;
663  IfClr = Op0Op1;
664  } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
665  Cond = Op1Op0;
666  IfSet = Op1Op1;
667  IfClr = Op0Op0;
668  } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
669  Cond = Op1Op1;
670  IfSet = Op1Op0;
671  IfClr = Op0Op1;
672  } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
673  Cond = Op1Op1;
674  IfSet = Op1Op0;
675  IfClr = Op0Op0;
676  } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
677  Cond = Op0Op0;
678  IfSet = Op0Op1;
679  IfClr = Op1Op1;
680  } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
681  Cond = Op0Op0;
682  IfSet = Op0Op1;
683  IfClr = Op1Op0;
684  } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
685  Cond = Op0Op1;
686  IfSet = Op0Op0;
687  IfClr = Op1Op1;
688  } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
689  Cond = Op0Op1;
690  IfSet = Op0Op0;
691  IfClr = Op1Op0;
692  }
693  }
694 
695  // At this point, IfClr will be set if we have a valid match.
696  if (!IfClr.getNode())
697  return SDValue();
698 
699  assert(Cond.getNode() && IfSet.getNode());
700 
701  // Fold degenerate cases.
702  if (IsConstantMask) {
703  if (Mask.isAllOnesValue())
704  return IfSet;
705  else if (Mask == 0)
706  return IfClr;
707  }
708 
709  // Transform the DAG into an equivalent VSELECT.
710  return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
711  }
712 
713  return SDValue();
714 }
715 
717  SelectionDAG &DAG,
718  const MipsSubtarget &Subtarget) {
719  // Estimate the number of operations the below transform will turn a
720  // constant multiply into. The number is approximately equal to the minimal
721  // number of powers of two that constant can be broken down to by adding
722  // or subtracting them.
723  //
724  // If we have taken more than 12[1] / 8[2] steps to attempt the
725  // optimization for a native sized value, it is more than likely that this
726  // optimization will make things worse.
727  //
728  // [1] MIPS64 requires 6 instructions at most to materialize any constant,
729  // multiplication requires at least 4 cycles, but another cycle (or two)
730  // to retrieve the result from the HI/LO registers.
731  //
732  // [2] For MIPS32, more than 8 steps is expensive as the constant could be
733  // materialized in 2 instructions, multiplication requires at least 4
734  // cycles, but another cycle (or two) to retrieve the result from the
735  // HI/LO registers.
736  //
737  // TODO:
738  // - MaxSteps needs to consider the `VT` of the constant for the current
739  // target.
740  // - Consider to perform this optimization after type legalization.
741  // That allows to remove a workaround for types not supported natively.
742  // - Take in account `-Os, -Oz` flags because this optimization
743  // increases code size.
744  unsigned MaxSteps = Subtarget.isABI_O32() ? 8 : 12;
745 
746  SmallVector<APInt, 16> WorkStack(1, C);
747  unsigned Steps = 0;
748  unsigned BitWidth = C.getBitWidth();
749 
750  while (!WorkStack.empty()) {
751  APInt Val = WorkStack.pop_back_val();
752 
753  if (Val == 0 || Val == 1)
754  continue;
755 
756  if (Steps >= MaxSteps)
757  return false;
758 
759  if (Val.isPowerOf2()) {
760  ++Steps;
761  continue;
762  }
763 
764  APInt Floor = APInt(BitWidth, 1) << Val.logBase2();
765  APInt Ceil = Val.isNegative() ? APInt(BitWidth, 0)
766  : APInt(BitWidth, 1) << C.ceilLogBase2();
767  if ((Val - Floor).ule(Ceil - Val)) {
768  WorkStack.push_back(Floor);
769  WorkStack.push_back(Val - Floor);
770  } else {
771  WorkStack.push_back(Ceil);
772  WorkStack.push_back(Ceil - Val);
773  }
774 
775  ++Steps;
776  }
777 
778  // If the value being multiplied is not supported natively, we have to pay
779  // an additional legalization cost, conservatively assume an increase in the
780  // cost of 3 instructions per step. This values for this heuristic were
781  // determined experimentally.
782  unsigned RegisterSize = DAG.getTargetLoweringInfo()
783  .getRegisterType(*DAG.getContext(), VT)
784  .getSizeInBits();
785  Steps *= (VT.getSizeInBits() != RegisterSize) * 3;
786  if (Steps > 27)
787  return false;
788 
789  return true;
790 }
791 
792 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT,
793  EVT ShiftTy, SelectionDAG &DAG) {
794  // Return 0.
795  if (C == 0)
796  return DAG.getConstant(0, DL, VT);
797 
798  // Return x.
799  if (C == 1)
800  return X;
801 
802  // If c is power of 2, return (shl x, log2(c)).
803  if (C.isPowerOf2())
804  return DAG.getNode(ISD::SHL, DL, VT, X,
805  DAG.getConstant(C.logBase2(), DL, ShiftTy));
806 
807  unsigned BitWidth = C.getBitWidth();
808  APInt Floor = APInt(BitWidth, 1) << C.logBase2();
809  APInt Ceil = C.isNegative() ? APInt(BitWidth, 0) :
810  APInt(BitWidth, 1) << C.ceilLogBase2();
811 
812  // If |c - floor_c| <= |c - ceil_c|,
813  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
814  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
815  if ((C - Floor).ule(Ceil - C)) {
816  SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
817  SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
818  return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
819  }
820 
821  // If |c - floor_c| > |c - ceil_c|,
822  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
823  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
824  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
825  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
826 }
827 
830  const MipsSETargetLowering *TL,
831  const MipsSubtarget &Subtarget) {
832  EVT VT = N->getValueType(0);
833 
834  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
836  C->getAPIntValue(), VT, DAG, Subtarget))
837  return genConstMult(N->getOperand(0), C->getAPIntValue(), SDLoc(N), VT,
838  TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
839  DAG);
840 
841  return SDValue(N, 0);
842 }
843 
844 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
845  SelectionDAG &DAG,
846  const MipsSubtarget &Subtarget) {
847  // See if this is a vector splat immediate node.
848  APInt SplatValue, SplatUndef;
849  unsigned SplatBitSize;
850  bool HasAnyUndefs;
851  unsigned EltSize = Ty.getScalarSizeInBits();
853 
854  if (!Subtarget.hasDSP())
855  return SDValue();
856 
857  if (!BV ||
858  !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
859  EltSize, !Subtarget.isLittle()) ||
860  (SplatBitSize != EltSize) ||
861  (SplatValue.getZExtValue() >= EltSize))
862  return SDValue();
863 
864  SDLoc DL(N);
865  return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
866  DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
867 }
868 
871  const MipsSubtarget &Subtarget) {
872  EVT Ty = N->getValueType(0);
873 
874  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
875  return SDValue();
876 
877  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
878 }
879 
880 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
881 // constant splats into MipsISD::SHRA_DSP for DSPr2.
882 //
883 // Performs the following transformations:
884 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
885 // sign/zero-extension is completely overwritten by the new one performed by
886 // the ISD::SRA and ISD::SHL nodes.
887 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
888 // sequence.
889 //
890 // See performDSPShiftCombine for more information about the transformation
891 // used for DSPr2.
894  const MipsSubtarget &Subtarget) {
895  EVT Ty = N->getValueType(0);
896 
897  if (Subtarget.hasMSA()) {
898  SDValue Op0 = N->getOperand(0);
899  SDValue Op1 = N->getOperand(1);
900 
901  // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
902  // where $d + sizeof($c) == 32
903  // or $d + sizeof($c) <= 32 and SExt
904  // -> (MipsVExtractSExt $a, $b, $c)
905  if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
906  SDValue Op0Op0 = Op0->getOperand(0);
907  ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
908 
909  if (!ShAmount)
910  return SDValue();
911 
912  if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
914  return SDValue();
915 
916  EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
917  unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
918 
919  if (TotalBits == 32 ||
920  (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
921  TotalBits <= 32)) {
922  SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
923  Op0Op0->getOperand(2) };
924  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
925  Op0Op0->getVTList(),
926  makeArrayRef(Ops, Op0Op0->getNumOperands()));
927  }
928  }
929  }
930 
931  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
932  return SDValue();
933 
934  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
935 }
936 
937 
940  const MipsSubtarget &Subtarget) {
941  EVT Ty = N->getValueType(0);
942 
943  if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
944  return SDValue();
945 
946  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
947 }
948 
949 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
950  bool IsV216 = (Ty == MVT::v2i16);
951 
952  switch (CC) {
953  case ISD::SETEQ:
954  case ISD::SETNE: return true;
955  case ISD::SETLT:
956  case ISD::SETLE:
957  case ISD::SETGT:
958  case ISD::SETGE: return IsV216;
959  case ISD::SETULT:
960  case ISD::SETULE:
961  case ISD::SETUGT:
962  case ISD::SETUGE: return !IsV216;
963  default: return false;
964  }
965 }
966 
968  EVT Ty = N->getValueType(0);
969 
970  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
971  return SDValue();
972 
973  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
974  return SDValue();
975 
976  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
977  N->getOperand(1), N->getOperand(2));
978 }
979 
981  EVT Ty = N->getValueType(0);
982 
983  if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
984  SDValue SetCC = N->getOperand(0);
985 
986  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
987  return SDValue();
988 
989  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
990  SetCC.getOperand(0), SetCC.getOperand(1),
991  N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
992  }
993 
994  return SDValue();
995 }
996 
998  const MipsSubtarget &Subtarget) {
999  EVT Ty = N->getValueType(0);
1000 
1001  if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
1002  // Try the following combines:
1003  // (xor (or $a, $b), (build_vector allones))
1004  // (xor (or $a, $b), (bitcast (build_vector allones)))
1005  SDValue Op0 = N->getOperand(0);
1006  SDValue Op1 = N->getOperand(1);
1007  SDValue NotOp;
1008 
1010  NotOp = Op1;
1011  else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1012  NotOp = Op0;
1013  else
1014  return SDValue();
1015 
1016  if (NotOp->getOpcode() == ISD::OR)
1017  return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1018  NotOp->getOperand(1));
1019  }
1020 
1021  return SDValue();
1022 }
1023 
1024 SDValue
1026  SelectionDAG &DAG = DCI.DAG;
1027  SDValue Val;
1028 
1029  switch (N->getOpcode()) {
1030  case ISD::AND:
1031  Val = performANDCombine(N, DAG, DCI, Subtarget);
1032  break;
1033  case ISD::OR:
1034  Val = performORCombine(N, DAG, DCI, Subtarget);
1035  break;
1036  case ISD::MUL:
1037  return performMULCombine(N, DAG, DCI, this, Subtarget);
1038  case ISD::SHL:
1039  Val = performSHLCombine(N, DAG, DCI, Subtarget);
1040  break;
1041  case ISD::SRA:
1042  return performSRACombine(N, DAG, DCI, Subtarget);
1043  case ISD::SRL:
1044  return performSRLCombine(N, DAG, DCI, Subtarget);
1045  case ISD::VSELECT:
1046  return performVSELECTCombine(N, DAG);
1047  case ISD::XOR:
1048  Val = performXORCombine(N, DAG, Subtarget);
1049  break;
1050  case ISD::SETCC:
1051  Val = performSETCCCombine(N, DAG);
1052  break;
1053  }
1054 
1055  if (Val.getNode()) {
1056  LLVM_DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1057  N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n";
1058  Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n");
1059  return Val;
1060  }
1061 
1063 }
1064 
1067  MachineBasicBlock *BB) const {
1068  switch (MI.getOpcode()) {
1069  default:
1071  case Mips::BPOSGE32_PSEUDO:
1072  return emitBPOSGE32(MI, BB);
1073  case Mips::SNZ_B_PSEUDO:
1074  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1075  case Mips::SNZ_H_PSEUDO:
1076  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1077  case Mips::SNZ_W_PSEUDO:
1078  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1079  case Mips::SNZ_D_PSEUDO:
1080  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1081  case Mips::SNZ_V_PSEUDO:
1082  return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1083  case Mips::SZ_B_PSEUDO:
1084  return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1085  case Mips::SZ_H_PSEUDO:
1086  return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1087  case Mips::SZ_W_PSEUDO:
1088  return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1089  case Mips::SZ_D_PSEUDO:
1090  return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1091  case Mips::SZ_V_PSEUDO:
1092  return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1093  case Mips::COPY_FW_PSEUDO:
1094  return emitCOPY_FW(MI, BB);
1095  case Mips::COPY_FD_PSEUDO:
1096  return emitCOPY_FD(MI, BB);
1097  case Mips::INSERT_FW_PSEUDO:
1098  return emitINSERT_FW(MI, BB);
1099  case Mips::INSERT_FD_PSEUDO:
1100  return emitINSERT_FD(MI, BB);
1101  case Mips::INSERT_B_VIDX_PSEUDO:
1102  case Mips::INSERT_B_VIDX64_PSEUDO:
1103  return emitINSERT_DF_VIDX(MI, BB, 1, false);
1104  case Mips::INSERT_H_VIDX_PSEUDO:
1105  case Mips::INSERT_H_VIDX64_PSEUDO:
1106  return emitINSERT_DF_VIDX(MI, BB, 2, false);
1107  case Mips::INSERT_W_VIDX_PSEUDO:
1108  case Mips::INSERT_W_VIDX64_PSEUDO:
1109  return emitINSERT_DF_VIDX(MI, BB, 4, false);
1110  case Mips::INSERT_D_VIDX_PSEUDO:
1111  case Mips::INSERT_D_VIDX64_PSEUDO:
1112  return emitINSERT_DF_VIDX(MI, BB, 8, false);
1113  case Mips::INSERT_FW_VIDX_PSEUDO:
1114  case Mips::INSERT_FW_VIDX64_PSEUDO:
1115  return emitINSERT_DF_VIDX(MI, BB, 4, true);
1116  case Mips::INSERT_FD_VIDX_PSEUDO:
1117  case Mips::INSERT_FD_VIDX64_PSEUDO:
1118  return emitINSERT_DF_VIDX(MI, BB, 8, true);
1119  case Mips::FILL_FW_PSEUDO:
1120  return emitFILL_FW(MI, BB);
1121  case Mips::FILL_FD_PSEUDO:
1122  return emitFILL_FD(MI, BB);
1123  case Mips::FEXP2_W_1_PSEUDO:
1124  return emitFEXP2_W_1(MI, BB);
1125  case Mips::FEXP2_D_1_PSEUDO:
1126  return emitFEXP2_D_1(MI, BB);
1127  case Mips::ST_F16:
1128  return emitST_F16_PSEUDO(MI, BB);
1129  case Mips::LD_F16:
1130  return emitLD_F16_PSEUDO(MI, BB);
1131  case Mips::MSA_FP_EXTEND_W_PSEUDO:
1132  return emitFPEXTEND_PSEUDO(MI, BB, false);
1133  case Mips::MSA_FP_ROUND_W_PSEUDO:
1134  return emitFPROUND_PSEUDO(MI, BB, false);
1135  case Mips::MSA_FP_EXTEND_D_PSEUDO:
1136  return emitFPEXTEND_PSEUDO(MI, BB, true);
1137  case Mips::MSA_FP_ROUND_D_PSEUDO:
1138  return emitFPROUND_PSEUDO(MI, BB, true);
1139  }
1140 }
1141 
1142 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1143  const CCState &CCInfo, unsigned NextStackOffset,
1144  const MipsFunctionInfo &FI) const {
1145  if (!UseMipsTailCalls)
1146  return false;
1147 
1148  // Exception has to be cleared with eret.
1149  if (FI.isISR())
1150  return false;
1151 
1152  // Return false if either the callee or caller has a byval argument.
1153  if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1154  return false;
1155 
1156  // Return true if the callee's argument area is no larger than the
1157  // caller's.
1158  return NextStackOffset <= FI.getIncomingArgSize();
1159 }
1160 
1161 void MipsSETargetLowering::
1162 getOpndList(SmallVectorImpl<SDValue> &Ops,
1163  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1164  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1165  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1166  SDValue Chain) const {
1167  Ops.push_back(Callee);
1168  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1169  InternalLinkage, IsCallReloc, CLI, Callee,
1170  Chain);
1171 }
1172 
1173 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1174  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1175 
1176  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1177  return MipsTargetLowering::lowerLOAD(Op, DAG);
1178 
1179  // Replace a double precision load with two i32 loads and a buildpair64.
1180  SDLoc DL(Op);
1181  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1182  EVT PtrVT = Ptr.getValueType();
1183 
1184  // i32 load from lower address.
1185  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1186  Nd.getAlignment(), Nd.getMemOperand()->getFlags());
1187 
1188  // i32 load from higher address.
1189  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1190  SDValue Hi = DAG.getLoad(
1191  MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1192  std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
1193 
1194  if (!Subtarget.isLittle())
1195  std::swap(Lo, Hi);
1196 
1197  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1198  SDValue Ops[2] = {BP, Hi.getValue(1)};
1199  return DAG.getMergeValues(Ops, DL);
1200 }
1201 
1202 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1203  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1204 
1205  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1206  return MipsTargetLowering::lowerSTORE(Op, DAG);
1207 
1208  // Replace a double precision store with two extractelement64s and i32 stores.
1209  SDLoc DL(Op);
1210  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1211  EVT PtrVT = Ptr.getValueType();
1213  Val, DAG.getConstant(0, DL, MVT::i32));
1215  Val, DAG.getConstant(1, DL, MVT::i32));
1216 
1217  if (!Subtarget.isLittle())
1218  std::swap(Lo, Hi);
1219 
1220  // i32 store to lower address.
1221  Chain =
1222  DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1223  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1224 
1225  // i32 store to higher address.
1226  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1227  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1228  std::min(Nd.getAlignment(), 4U),
1229  Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1230 }
1231 
1232 SDValue MipsSETargetLowering::lowerBITCAST(SDValue Op,
1233  SelectionDAG &DAG) const {
1234  SDLoc DL(Op);
1235  MVT Src = Op.getOperand(0).getValueType().getSimpleVT();
1236  MVT Dest = Op.getValueType().getSimpleVT();
1237 
1238  // Bitcast i64 to double.
1239  if (Src == MVT::i64 && Dest == MVT::f64) {
1241  Op.getOperand(0), DAG.getIntPtrConstant(0, DL));
1243  Op.getOperand(0), DAG.getIntPtrConstant(1, DL));
1244  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1245  }
1246 
1247  // Bitcast double to i64.
1248  if (Src == MVT::f64 && Dest == MVT::i64) {
1249  SDValue Lo =
1251  DAG.getConstant(0, DL, MVT::i32));
1252  SDValue Hi =
1254  DAG.getConstant(1, DL, MVT::i32));
1255  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1256  }
1257 
1258  // Skip other cases of bitcast and use default lowering.
1259  return SDValue();
1260 }
1261 
1262 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1263  bool HasLo, bool HasHi,
1264  SelectionDAG &DAG) const {
1265  // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1267 
1268  EVT Ty = Op.getOperand(0).getValueType();
1269  SDLoc DL(Op);
1270  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1271  Op.getOperand(0), Op.getOperand(1));
1272  SDValue Lo, Hi;
1273 
1274  if (HasLo)
1275  Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1276  if (HasHi)
1277  Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1278 
1279  if (!HasLo || !HasHi)
1280  return HasLo ? Lo : Hi;
1281 
1282  SDValue Vals[] = { Lo, Hi };
1283  return DAG.getMergeValues(Vals, DL);
1284 }
1285 
1287  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1288  DAG.getConstant(0, DL, MVT::i32));
1289  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1290  DAG.getConstant(1, DL, MVT::i32));
1291  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1292 }
1293 
1294 static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) {
1295  SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1296  SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1297  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1298 }
1299 
1300 // This function expands mips intrinsic nodes which have 64-bit input operands
1301 // or output values.
1302 //
1303 // out64 = intrinsic-node in64
1304 // =>
1305 // lo = copy (extract-element (in64, 0))
1306 // hi = copy (extract-element (in64, 1))
1307 // mips-specific-node
1308 // v0 = copy lo
1309 // v1 = copy hi
1310 // out64 = merge-values (v0, v1)
1311 //
1312 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1313  SDLoc DL(Op);
1314  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1316  unsigned OpNo = 0;
1317 
1318  // See if Op has a chain input.
1319  if (HasChainIn)
1320  Ops.push_back(Op->getOperand(OpNo++));
1321 
1322  // The next operand is the intrinsic opcode.
1324 
1325  // See if the next operand has type i64.
1326  SDValue Opnd = Op->getOperand(++OpNo), In64;
1327 
1328  if (Opnd.getValueType() == MVT::i64)
1329  In64 = initAccumulator(Opnd, DL, DAG);
1330  else
1331  Ops.push_back(Opnd);
1332 
1333  // Push the remaining operands.
1334  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1335  Ops.push_back(Op->getOperand(OpNo));
1336 
1337  // Add In64 to the end of the list.
1338  if (In64.getNode())
1339  Ops.push_back(In64);
1340 
1341  // Scan output.
1342  SmallVector<EVT, 2> ResTys;
1343 
1344  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1345  I != E; ++I)
1346  ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1347 
1348  // Create node.
1349  SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1350  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1351 
1352  if (!HasChainIn)
1353  return Out;
1354 
1355  assert(Val->getValueType(1) == MVT::Other);
1356  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1357  return DAG.getMergeValues(Vals, DL);
1358 }
1359 
1360 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1361 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1362  SDLoc DL(Op);
1363  SDValue Vec = Op->getOperand(1);
1364  SDValue Idx = Op->getOperand(2);
1365  EVT ResTy = Op->getValueType(0);
1366  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1367 
1368  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1369  DAG.getValueType(EltTy));
1370 
1371  return Result;
1372 }
1373 
1374 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1375  EVT ResVecTy = Op->getValueType(0);
1376  EVT ViaVecTy = ResVecTy;
1377  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1378  SDLoc DL(Op);
1379 
1380  // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1381  // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1382  // lanes.
1383  SDValue LaneA = Op->getOperand(OpNr);
1384  SDValue LaneB;
1385 
1386  if (ResVecTy == MVT::v2i64) {
1387  // In case of the index being passed as an immediate value, set the upper
1388  // lane to 0 so that the splati.d instruction can be matched.
1389  if (isa<ConstantSDNode>(LaneA))
1390  LaneB = DAG.getConstant(0, DL, MVT::i32);
1391  // Having the index passed in a register, set the upper lane to the same
1392  // value as the lower - this results in the BUILD_VECTOR node not being
1393  // expanded through stack. This way we are able to pattern match the set of
1394  // nodes created here to splat.d.
1395  else
1396  LaneB = LaneA;
1397  ViaVecTy = MVT::v4i32;
1398  if(BigEndian)
1399  std::swap(LaneA, LaneB);
1400  } else
1401  LaneB = LaneA;
1402 
1403  SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1404  LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1405 
1406  SDValue Result = DAG.getBuildVector(
1407  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1408 
1409  if (ViaVecTy != ResVecTy) {
1410  SDValue One = DAG.getConstant(1, DL, ViaVecTy);
1411  Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy,
1412  DAG.getNode(ISD::AND, DL, ViaVecTy, Result, One));
1413  }
1414 
1415  return Result;
1416 }
1417 
1418 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG,
1419  bool IsSigned = false) {
1420  auto *CImm = cast<ConstantSDNode>(Op->getOperand(ImmOp));
1421  return DAG.getConstant(
1423  IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),
1424  SDLoc(Op), Op->getValueType(0));
1425 }
1426 
1427 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1428  bool BigEndian, SelectionDAG &DAG) {
1429  EVT ViaVecTy = VecTy;
1430  SDValue SplatValueA = SplatValue;
1431  SDValue SplatValueB = SplatValue;
1432  SDLoc DL(SplatValue);
1433 
1434  if (VecTy == MVT::v2i64) {
1435  // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1436  ViaVecTy = MVT::v4i32;
1437 
1438  SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1439  SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1440  DAG.getConstant(32, DL, MVT::i32));
1441  SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1442  }
1443 
1444  // We currently hold the parts in little endian order. Swap them if
1445  // necessary.
1446  if (BigEndian)
1447  std::swap(SplatValueA, SplatValueB);
1448 
1449  SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1450  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1451  SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1452  SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1453 
1454  SDValue Result = DAG.getBuildVector(
1455  ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1456 
1457  if (VecTy != ViaVecTy)
1458  Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1459 
1460  return Result;
1461 }
1462 
1464  unsigned Opc, SDValue Imm,
1465  bool BigEndian) {
1466  EVT VecTy = Op->getValueType(0);
1467  SDValue Exp2Imm;
1468  SDLoc DL(Op);
1469 
1470  // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1471  // here for now.
1472  if (VecTy == MVT::v2i64) {
1473  if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1474  APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1475 
1476  SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1477  MVT::i32);
1478  SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
1479 
1480  if (BigEndian)
1481  std::swap(BitImmLoOp, BitImmHiOp);
1482 
1483  Exp2Imm = DAG.getNode(
1484  ISD::BITCAST, DL, MVT::v2i64,
1485  DAG.getBuildVector(MVT::v4i32, DL,
1486  {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1487  }
1488  }
1489 
1490  if (!Exp2Imm.getNode()) {
1491  // We couldnt constant fold, do a vector shift instead
1492 
1493  // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1494  // only values 0-63 are valid.
1495  if (VecTy == MVT::v2i64)
1496  Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1497 
1498  Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1499 
1500  Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1501  Exp2Imm);
1502  }
1503 
1504  return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1505 }
1506 
1508  SDLoc DL(Op);
1509  EVT ResTy = Op->getValueType(0);
1510  SDValue Vec = Op->getOperand(2);
1511  bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1512  MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1513  SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
1514  DL, ResEltTy);
1515  SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1516 
1517  return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1518 }
1519 
1521  EVT ResTy = Op->getValueType(0);
1522  SDLoc DL(Op);
1523  SDValue One = DAG.getConstant(1, DL, ResTy);
1524  SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1525 
1526  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1527  DAG.getNOT(DL, Bit, ResTy));
1528 }
1529 
1531  SDLoc DL(Op);
1532  EVT ResTy = Op->getValueType(0);
1533  APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1534  << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1535  SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1536 
1537  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1538 }
1539 
1540 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1541  SelectionDAG &DAG) const {
1542  SDLoc DL(Op);
1543  unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1544  switch (Intrinsic) {
1545  default:
1546  return SDValue();
1547  case Intrinsic::mips_shilo:
1548  return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1549  case Intrinsic::mips_dpau_h_qbl:
1550  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1551  case Intrinsic::mips_dpau_h_qbr:
1552  return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1553  case Intrinsic::mips_dpsu_h_qbl:
1554  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1555  case Intrinsic::mips_dpsu_h_qbr:
1556  return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1557  case Intrinsic::mips_dpa_w_ph:
1558  return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1559  case Intrinsic::mips_dps_w_ph:
1560  return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1561  case Intrinsic::mips_dpax_w_ph:
1562  return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1563  case Intrinsic::mips_dpsx_w_ph:
1564  return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1565  case Intrinsic::mips_mulsa_w_ph:
1566  return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1567  case Intrinsic::mips_mult:
1568  return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1569  case Intrinsic::mips_multu:
1570  return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1571  case Intrinsic::mips_madd:
1572  return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1573  case Intrinsic::mips_maddu:
1574  return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1575  case Intrinsic::mips_msub:
1576  return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1577  case Intrinsic::mips_msubu:
1578  return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1579  case Intrinsic::mips_addv_b:
1580  case Intrinsic::mips_addv_h:
1581  case Intrinsic::mips_addv_w:
1582  case Intrinsic::mips_addv_d:
1583  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1584  Op->getOperand(2));
1585  case Intrinsic::mips_addvi_b:
1586  case Intrinsic::mips_addvi_h:
1587  case Intrinsic::mips_addvi_w:
1588  case Intrinsic::mips_addvi_d:
1589  return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1590  lowerMSASplatImm(Op, 2, DAG));
1591  case Intrinsic::mips_and_v:
1592  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1593  Op->getOperand(2));
1594  case Intrinsic::mips_andi_b:
1595  return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1596  lowerMSASplatImm(Op, 2, DAG));
1597  case Intrinsic::mips_bclr_b:
1598  case Intrinsic::mips_bclr_h:
1599  case Intrinsic::mips_bclr_w:
1600  case Intrinsic::mips_bclr_d:
1601  return lowerMSABitClear(Op, DAG);
1602  case Intrinsic::mips_bclri_b:
1603  case Intrinsic::mips_bclri_h:
1604  case Intrinsic::mips_bclri_w:
1605  case Intrinsic::mips_bclri_d:
1606  return lowerMSABitClearImm(Op, DAG);
1607  case Intrinsic::mips_binsli_b:
1608  case Intrinsic::mips_binsli_h:
1609  case Intrinsic::mips_binsli_w:
1610  case Intrinsic::mips_binsli_d: {
1611  // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1612  EVT VecTy = Op->getValueType(0);
1613  EVT EltTy = VecTy.getVectorElementType();
1614  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1615  report_fatal_error("Immediate out of range");
1617  Op->getConstantOperandVal(3) + 1);
1618  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1619  DAG.getConstant(Mask, DL, VecTy, true),
1620  Op->getOperand(2), Op->getOperand(1));
1621  }
1622  case Intrinsic::mips_binsri_b:
1623  case Intrinsic::mips_binsri_h:
1624  case Intrinsic::mips_binsri_w:
1625  case Intrinsic::mips_binsri_d: {
1626  // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1627  EVT VecTy = Op->getValueType(0);
1628  EVT EltTy = VecTy.getVectorElementType();
1629  if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1630  report_fatal_error("Immediate out of range");
1632  Op->getConstantOperandVal(3) + 1);
1633  return DAG.getNode(ISD::VSELECT, DL, VecTy,
1634  DAG.getConstant(Mask, DL, VecTy, true),
1635  Op->getOperand(2), Op->getOperand(1));
1636  }
1637  case Intrinsic::mips_bmnz_v:
1638  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1639  Op->getOperand(2), Op->getOperand(1));
1640  case Intrinsic::mips_bmnzi_b:
1641  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1642  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1643  Op->getOperand(1));
1644  case Intrinsic::mips_bmz_v:
1645  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1646  Op->getOperand(1), Op->getOperand(2));
1647  case Intrinsic::mips_bmzi_b:
1648  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1649  lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1650  Op->getOperand(2));
1651  case Intrinsic::mips_bneg_b:
1652  case Intrinsic::mips_bneg_h:
1653  case Intrinsic::mips_bneg_w:
1654  case Intrinsic::mips_bneg_d: {
1655  EVT VecTy = Op->getValueType(0);
1656  SDValue One = DAG.getConstant(1, DL, VecTy);
1657 
1658  return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1659  DAG.getNode(ISD::SHL, DL, VecTy, One,
1660  truncateVecElts(Op, DAG)));
1661  }
1662  case Intrinsic::mips_bnegi_b:
1663  case Intrinsic::mips_bnegi_h:
1664  case Intrinsic::mips_bnegi_w:
1665  case Intrinsic::mips_bnegi_d:
1666  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1667  !Subtarget.isLittle());
1668  case Intrinsic::mips_bnz_b:
1669  case Intrinsic::mips_bnz_h:
1670  case Intrinsic::mips_bnz_w:
1671  case Intrinsic::mips_bnz_d:
1672  return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1673  Op->getOperand(1));
1674  case Intrinsic::mips_bnz_v:
1675  return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1676  Op->getOperand(1));
1677  case Intrinsic::mips_bsel_v:
1678  // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1679  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1680  Op->getOperand(1), Op->getOperand(3),
1681  Op->getOperand(2));
1682  case Intrinsic::mips_bseli_b:
1683  // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1684  return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1685  Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1686  Op->getOperand(2));
1687  case Intrinsic::mips_bset_b:
1688  case Intrinsic::mips_bset_h:
1689  case Intrinsic::mips_bset_w:
1690  case Intrinsic::mips_bset_d: {
1691  EVT VecTy = Op->getValueType(0);
1692  SDValue One = DAG.getConstant(1, DL, VecTy);
1693 
1694  return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1695  DAG.getNode(ISD::SHL, DL, VecTy, One,
1696  truncateVecElts(Op, DAG)));
1697  }
1698  case Intrinsic::mips_bseti_b:
1699  case Intrinsic::mips_bseti_h:
1700  case Intrinsic::mips_bseti_w:
1701  case Intrinsic::mips_bseti_d:
1702  return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1703  !Subtarget.isLittle());
1704  case Intrinsic::mips_bz_b:
1705  case Intrinsic::mips_bz_h:
1706  case Intrinsic::mips_bz_w:
1707  case Intrinsic::mips_bz_d:
1708  return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1709  Op->getOperand(1));
1710  case Intrinsic::mips_bz_v:
1711  return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1712  Op->getOperand(1));
1713  case Intrinsic::mips_ceq_b:
1714  case Intrinsic::mips_ceq_h:
1715  case Intrinsic::mips_ceq_w:
1716  case Intrinsic::mips_ceq_d:
1717  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1718  Op->getOperand(2), ISD::SETEQ);
1719  case Intrinsic::mips_ceqi_b:
1720  case Intrinsic::mips_ceqi_h:
1721  case Intrinsic::mips_ceqi_w:
1722  case Intrinsic::mips_ceqi_d:
1723  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1724  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
1725  case Intrinsic::mips_cle_s_b:
1726  case Intrinsic::mips_cle_s_h:
1727  case Intrinsic::mips_cle_s_w:
1728  case Intrinsic::mips_cle_s_d:
1729  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1730  Op->getOperand(2), ISD::SETLE);
1731  case Intrinsic::mips_clei_s_b:
1732  case Intrinsic::mips_clei_s_h:
1733  case Intrinsic::mips_clei_s_w:
1734  case Intrinsic::mips_clei_s_d:
1735  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1736  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
1737  case Intrinsic::mips_cle_u_b:
1738  case Intrinsic::mips_cle_u_h:
1739  case Intrinsic::mips_cle_u_w:
1740  case Intrinsic::mips_cle_u_d:
1741  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1742  Op->getOperand(2), ISD::SETULE);
1743  case Intrinsic::mips_clei_u_b:
1744  case Intrinsic::mips_clei_u_h:
1745  case Intrinsic::mips_clei_u_w:
1746  case Intrinsic::mips_clei_u_d:
1747  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1748  lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1749  case Intrinsic::mips_clt_s_b:
1750  case Intrinsic::mips_clt_s_h:
1751  case Intrinsic::mips_clt_s_w:
1752  case Intrinsic::mips_clt_s_d:
1753  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1754  Op->getOperand(2), ISD::SETLT);
1755  case Intrinsic::mips_clti_s_b:
1756  case Intrinsic::mips_clti_s_h:
1757  case Intrinsic::mips_clti_s_w:
1758  case Intrinsic::mips_clti_s_d:
1759  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1760  lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
1761  case Intrinsic::mips_clt_u_b:
1762  case Intrinsic::mips_clt_u_h:
1763  case Intrinsic::mips_clt_u_w:
1764  case Intrinsic::mips_clt_u_d:
1765  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1766  Op->getOperand(2), ISD::SETULT);
1767  case Intrinsic::mips_clti_u_b:
1768  case Intrinsic::mips_clti_u_h:
1769  case Intrinsic::mips_clti_u_w:
1770  case Intrinsic::mips_clti_u_d:
1771  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1772  lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1773  case Intrinsic::mips_copy_s_b:
1774  case Intrinsic::mips_copy_s_h:
1775  case Intrinsic::mips_copy_s_w:
1777  case Intrinsic::mips_copy_s_d:
1778  if (Subtarget.hasMips64())
1779  // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1781  else {
1782  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1783  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1784  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1785  Op->getValueType(0), Op->getOperand(1),
1786  Op->getOperand(2));
1787  }
1788  case Intrinsic::mips_copy_u_b:
1789  case Intrinsic::mips_copy_u_h:
1790  case Intrinsic::mips_copy_u_w:
1792  case Intrinsic::mips_copy_u_d:
1793  if (Subtarget.hasMips64())
1794  // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1796  else {
1797  // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1798  // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1799  // Note: When i64 is illegal, this results in copy_s.w instructions
1800  // instead of copy_u.w instructions. This makes no difference to the
1801  // behaviour since i64 is only illegal when the register file is 32-bit.
1802  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1803  Op->getValueType(0), Op->getOperand(1),
1804  Op->getOperand(2));
1805  }
1806  case Intrinsic::mips_div_s_b:
1807  case Intrinsic::mips_div_s_h:
1808  case Intrinsic::mips_div_s_w:
1809  case Intrinsic::mips_div_s_d:
1810  return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1811  Op->getOperand(2));
1812  case Intrinsic::mips_div_u_b:
1813  case Intrinsic::mips_div_u_h:
1814  case Intrinsic::mips_div_u_w:
1815  case Intrinsic::mips_div_u_d:
1816  return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1817  Op->getOperand(2));
1818  case Intrinsic::mips_fadd_w:
1819  case Intrinsic::mips_fadd_d:
1820  // TODO: If intrinsics have fast-math-flags, propagate them.
1821  return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1822  Op->getOperand(2));
1823  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1824  case Intrinsic::mips_fceq_w:
1825  case Intrinsic::mips_fceq_d:
1826  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1827  Op->getOperand(2), ISD::SETOEQ);
1828  case Intrinsic::mips_fcle_w:
1829  case Intrinsic::mips_fcle_d:
1830  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1831  Op->getOperand(2), ISD::SETOLE);
1832  case Intrinsic::mips_fclt_w:
1833  case Intrinsic::mips_fclt_d:
1834  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1835  Op->getOperand(2), ISD::SETOLT);
1836  case Intrinsic::mips_fcne_w:
1837  case Intrinsic::mips_fcne_d:
1838  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1839  Op->getOperand(2), ISD::SETONE);
1840  case Intrinsic::mips_fcor_w:
1841  case Intrinsic::mips_fcor_d:
1842  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1843  Op->getOperand(2), ISD::SETO);
1844  case Intrinsic::mips_fcueq_w:
1845  case Intrinsic::mips_fcueq_d:
1846  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1847  Op->getOperand(2), ISD::SETUEQ);
1848  case Intrinsic::mips_fcule_w:
1849  case Intrinsic::mips_fcule_d:
1850  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1851  Op->getOperand(2), ISD::SETULE);
1852  case Intrinsic::mips_fcult_w:
1853  case Intrinsic::mips_fcult_d:
1854  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1855  Op->getOperand(2), ISD::SETULT);
1856  case Intrinsic::mips_fcun_w:
1857  case Intrinsic::mips_fcun_d:
1858  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1859  Op->getOperand(2), ISD::SETUO);
1860  case Intrinsic::mips_fcune_w:
1861  case Intrinsic::mips_fcune_d:
1862  return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1863  Op->getOperand(2), ISD::SETUNE);
1864  case Intrinsic::mips_fdiv_w:
1865  case Intrinsic::mips_fdiv_d:
1866  // TODO: If intrinsics have fast-math-flags, propagate them.
1867  return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1868  Op->getOperand(2));
1869  case Intrinsic::mips_ffint_u_w:
1870  case Intrinsic::mips_ffint_u_d:
1871  return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1872  Op->getOperand(1));
1873  case Intrinsic::mips_ffint_s_w:
1874  case Intrinsic::mips_ffint_s_d:
1875  return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1876  Op->getOperand(1));
1877  case Intrinsic::mips_fill_b:
1878  case Intrinsic::mips_fill_h:
1879  case Intrinsic::mips_fill_w:
1880  case Intrinsic::mips_fill_d: {
1881  EVT ResTy = Op->getValueType(0);
1883  Op->getOperand(1));
1884 
1885  // If ResTy is v2i64 then the type legalizer will break this node down into
1886  // an equivalent v4i32.
1887  return DAG.getBuildVector(ResTy, DL, Ops);
1888  }
1889  case Intrinsic::mips_fexp2_w:
1890  case Intrinsic::mips_fexp2_d: {
1891  // TODO: If intrinsics have fast-math-flags, propagate them.
1892  EVT ResTy = Op->getValueType(0);
1893  return DAG.getNode(
1894  ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1895  DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1896  }
1897  case Intrinsic::mips_flog2_w:
1898  case Intrinsic::mips_flog2_d:
1899  return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1900  case Intrinsic::mips_fmadd_w:
1901  case Intrinsic::mips_fmadd_d:
1902  return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1903  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1904  case Intrinsic::mips_fmul_w:
1905  case Intrinsic::mips_fmul_d:
1906  // TODO: If intrinsics have fast-math-flags, propagate them.
1907  return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1908  Op->getOperand(2));
1909  case Intrinsic::mips_fmsub_w:
1910  case Intrinsic::mips_fmsub_d: {
1911  // TODO: If intrinsics have fast-math-flags, propagate them.
1912  return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0),
1913  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1914  }
1915  case Intrinsic::mips_frint_w:
1916  case Intrinsic::mips_frint_d:
1917  return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1918  case Intrinsic::mips_fsqrt_w:
1919  case Intrinsic::mips_fsqrt_d:
1920  return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1921  case Intrinsic::mips_fsub_w:
1922  case Intrinsic::mips_fsub_d:
1923  // TODO: If intrinsics have fast-math-flags, propagate them.
1924  return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1925  Op->getOperand(2));
1926  case Intrinsic::mips_ftrunc_u_w:
1927  case Intrinsic::mips_ftrunc_u_d:
1928  return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1929  Op->getOperand(1));
1930  case Intrinsic::mips_ftrunc_s_w:
1931  case Intrinsic::mips_ftrunc_s_d:
1932  return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1933  Op->getOperand(1));
1934  case Intrinsic::mips_ilvev_b:
1935  case Intrinsic::mips_ilvev_h:
1936  case Intrinsic::mips_ilvev_w:
1937  case Intrinsic::mips_ilvev_d:
1938  return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1939  Op->getOperand(1), Op->getOperand(2));
1940  case Intrinsic::mips_ilvl_b:
1941  case Intrinsic::mips_ilvl_h:
1942  case Intrinsic::mips_ilvl_w:
1943  case Intrinsic::mips_ilvl_d:
1944  return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1945  Op->getOperand(1), Op->getOperand(2));
1946  case Intrinsic::mips_ilvod_b:
1947  case Intrinsic::mips_ilvod_h:
1948  case Intrinsic::mips_ilvod_w:
1949  case Intrinsic::mips_ilvod_d:
1950  return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1951  Op->getOperand(1), Op->getOperand(2));
1952  case Intrinsic::mips_ilvr_b:
1953  case Intrinsic::mips_ilvr_h:
1954  case Intrinsic::mips_ilvr_w:
1955  case Intrinsic::mips_ilvr_d:
1956  return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1957  Op->getOperand(1), Op->getOperand(2));
1958  case Intrinsic::mips_insert_b:
1959  case Intrinsic::mips_insert_h:
1960  case Intrinsic::mips_insert_w:
1961  case Intrinsic::mips_insert_d:
1962  return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1963  Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1964  case Intrinsic::mips_insve_b:
1965  case Intrinsic::mips_insve_h:
1966  case Intrinsic::mips_insve_w:
1967  case Intrinsic::mips_insve_d: {
1968  // Report an error for out of range values.
1969  int64_t Max;
1970  switch (Intrinsic) {
1971  case Intrinsic::mips_insve_b: Max = 15; break;
1972  case Intrinsic::mips_insve_h: Max = 7; break;
1973  case Intrinsic::mips_insve_w: Max = 3; break;
1974  case Intrinsic::mips_insve_d: Max = 1; break;
1975  default: llvm_unreachable("Unmatched intrinsic");
1976  }
1977  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
1978  if (Value < 0 || Value > Max)
1979  report_fatal_error("Immediate out of range");
1980  return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1981  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1982  DAG.getConstant(0, DL, MVT::i32));
1983  }
1984  case Intrinsic::mips_ldi_b:
1985  case Intrinsic::mips_ldi_h:
1986  case Intrinsic::mips_ldi_w:
1987  case Intrinsic::mips_ldi_d:
1988  return lowerMSASplatImm(Op, 1, DAG, true);
1989  case Intrinsic::mips_lsa:
1990  case Intrinsic::mips_dlsa: {
1991  EVT ResTy = Op->getValueType(0);
1992  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1993  DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1994  Op->getOperand(2), Op->getOperand(3)));
1995  }
1996  case Intrinsic::mips_maddv_b:
1997  case Intrinsic::mips_maddv_h:
1998  case Intrinsic::mips_maddv_w:
1999  case Intrinsic::mips_maddv_d: {
2000  EVT ResTy = Op->getValueType(0);
2001  return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2002  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2003  Op->getOperand(2), Op->getOperand(3)));
2004  }
2005  case Intrinsic::mips_max_s_b:
2006  case Intrinsic::mips_max_s_h:
2007  case Intrinsic::mips_max_s_w:
2008  case Intrinsic::mips_max_s_d:
2009  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2010  Op->getOperand(1), Op->getOperand(2));
2011  case Intrinsic::mips_max_u_b:
2012  case Intrinsic::mips_max_u_h:
2013  case Intrinsic::mips_max_u_w:
2014  case Intrinsic::mips_max_u_d:
2015  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2016  Op->getOperand(1), Op->getOperand(2));
2017  case Intrinsic::mips_maxi_s_b:
2018  case Intrinsic::mips_maxi_s_h:
2019  case Intrinsic::mips_maxi_s_w:
2020  case Intrinsic::mips_maxi_s_d:
2021  return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2022  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2023  case Intrinsic::mips_maxi_u_b:
2024  case Intrinsic::mips_maxi_u_h:
2025  case Intrinsic::mips_maxi_u_w:
2026  case Intrinsic::mips_maxi_u_d:
2027  return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2028  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2029  case Intrinsic::mips_min_s_b:
2030  case Intrinsic::mips_min_s_h:
2031  case Intrinsic::mips_min_s_w:
2032  case Intrinsic::mips_min_s_d:
2033  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2034  Op->getOperand(1), Op->getOperand(2));
2035  case Intrinsic::mips_min_u_b:
2036  case Intrinsic::mips_min_u_h:
2037  case Intrinsic::mips_min_u_w:
2038  case Intrinsic::mips_min_u_d:
2039  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2040  Op->getOperand(1), Op->getOperand(2));
2041  case Intrinsic::mips_mini_s_b:
2042  case Intrinsic::mips_mini_s_h:
2043  case Intrinsic::mips_mini_s_w:
2044  case Intrinsic::mips_mini_s_d:
2045  return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2046  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2047  case Intrinsic::mips_mini_u_b:
2048  case Intrinsic::mips_mini_u_h:
2049  case Intrinsic::mips_mini_u_w:
2050  case Intrinsic::mips_mini_u_d:
2051  return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2052  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2053  case Intrinsic::mips_mod_s_b:
2054  case Intrinsic::mips_mod_s_h:
2055  case Intrinsic::mips_mod_s_w:
2056  case Intrinsic::mips_mod_s_d:
2057  return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2058  Op->getOperand(2));
2059  case Intrinsic::mips_mod_u_b:
2060  case Intrinsic::mips_mod_u_h:
2061  case Intrinsic::mips_mod_u_w:
2062  case Intrinsic::mips_mod_u_d:
2063  return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2064  Op->getOperand(2));
2065  case Intrinsic::mips_mulv_b:
2066  case Intrinsic::mips_mulv_h:
2067  case Intrinsic::mips_mulv_w:
2068  case Intrinsic::mips_mulv_d:
2069  return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2070  Op->getOperand(2));
2071  case Intrinsic::mips_msubv_b:
2072  case Intrinsic::mips_msubv_h:
2073  case Intrinsic::mips_msubv_w:
2074  case Intrinsic::mips_msubv_d: {
2075  EVT ResTy = Op->getValueType(0);
2076  return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2077  DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2078  Op->getOperand(2), Op->getOperand(3)));
2079  }
2080  case Intrinsic::mips_nlzc_b:
2081  case Intrinsic::mips_nlzc_h:
2082  case Intrinsic::mips_nlzc_w:
2083  case Intrinsic::mips_nlzc_d:
2084  return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2085  case Intrinsic::mips_nor_v: {
2086  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2087  Op->getOperand(1), Op->getOperand(2));
2088  return DAG.getNOT(DL, Res, Res->getValueType(0));
2089  }
2090  case Intrinsic::mips_nori_b: {
2091  SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2092  Op->getOperand(1),
2093  lowerMSASplatImm(Op, 2, DAG));
2094  return DAG.getNOT(DL, Res, Res->getValueType(0));
2095  }
2096  case Intrinsic::mips_or_v:
2097  return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2098  Op->getOperand(2));
2099  case Intrinsic::mips_ori_b:
2100  return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2101  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2102  case Intrinsic::mips_pckev_b:
2103  case Intrinsic::mips_pckev_h:
2104  case Intrinsic::mips_pckev_w:
2105  case Intrinsic::mips_pckev_d:
2106  return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2107  Op->getOperand(1), Op->getOperand(2));
2108  case Intrinsic::mips_pckod_b:
2109  case Intrinsic::mips_pckod_h:
2110  case Intrinsic::mips_pckod_w:
2111  case Intrinsic::mips_pckod_d:
2112  return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2113  Op->getOperand(1), Op->getOperand(2));
2114  case Intrinsic::mips_pcnt_b:
2115  case Intrinsic::mips_pcnt_h:
2116  case Intrinsic::mips_pcnt_w:
2117  case Intrinsic::mips_pcnt_d:
2118  return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2119  case Intrinsic::mips_sat_s_b:
2120  case Intrinsic::mips_sat_s_h:
2121  case Intrinsic::mips_sat_s_w:
2122  case Intrinsic::mips_sat_s_d:
2123  case Intrinsic::mips_sat_u_b:
2124  case Intrinsic::mips_sat_u_h:
2125  case Intrinsic::mips_sat_u_w:
2126  case Intrinsic::mips_sat_u_d: {
2127  // Report an error for out of range values.
2128  int64_t Max;
2129  switch (Intrinsic) {
2130  case Intrinsic::mips_sat_s_b:
2131  case Intrinsic::mips_sat_u_b: Max = 7; break;
2132  case Intrinsic::mips_sat_s_h:
2133  case Intrinsic::mips_sat_u_h: Max = 15; break;
2134  case Intrinsic::mips_sat_s_w:
2135  case Intrinsic::mips_sat_u_w: Max = 31; break;
2136  case Intrinsic::mips_sat_s_d:
2137  case Intrinsic::mips_sat_u_d: Max = 63; break;
2138  default: llvm_unreachable("Unmatched intrinsic");
2139  }
2140  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2141  if (Value < 0 || Value > Max)
2142  report_fatal_error("Immediate out of range");
2143  return SDValue();
2144  }
2145  case Intrinsic::mips_shf_b:
2146  case Intrinsic::mips_shf_h:
2147  case Intrinsic::mips_shf_w: {
2148  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2149  if (Value < 0 || Value > 255)
2150  report_fatal_error("Immediate out of range");
2151  return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2152  Op->getOperand(2), Op->getOperand(1));
2153  }
2154  case Intrinsic::mips_sldi_b:
2155  case Intrinsic::mips_sldi_h:
2156  case Intrinsic::mips_sldi_w:
2157  case Intrinsic::mips_sldi_d: {
2158  // Report an error for out of range values.
2159  int64_t Max;
2160  switch (Intrinsic) {
2161  case Intrinsic::mips_sldi_b: Max = 15; break;
2162  case Intrinsic::mips_sldi_h: Max = 7; break;
2163  case Intrinsic::mips_sldi_w: Max = 3; break;
2164  case Intrinsic::mips_sldi_d: Max = 1; break;
2165  default: llvm_unreachable("Unmatched intrinsic");
2166  }
2167  int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2168  if (Value < 0 || Value > Max)
2169  report_fatal_error("Immediate out of range");
2170  return SDValue();
2171  }
2172  case Intrinsic::mips_sll_b:
2173  case Intrinsic::mips_sll_h:
2174  case Intrinsic::mips_sll_w:
2175  case Intrinsic::mips_sll_d:
2176  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2177  truncateVecElts(Op, DAG));
2178  case Intrinsic::mips_slli_b:
2179  case Intrinsic::mips_slli_h:
2180  case Intrinsic::mips_slli_w:
2181  case Intrinsic::mips_slli_d:
2182  return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2183  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2184  case Intrinsic::mips_splat_b:
2185  case Intrinsic::mips_splat_h:
2186  case Intrinsic::mips_splat_w:
2187  case Intrinsic::mips_splat_d:
2188  // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2189  // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2190  // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2191  // Instead we lower to MipsISD::VSHF and match from there.
2192  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2193  lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2194  Op->getOperand(1));
2195  case Intrinsic::mips_splati_b:
2196  case Intrinsic::mips_splati_h:
2197  case Intrinsic::mips_splati_w:
2198  case Intrinsic::mips_splati_d:
2199  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2200  lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2201  Op->getOperand(1));
2202  case Intrinsic::mips_sra_b:
2203  case Intrinsic::mips_sra_h:
2204  case Intrinsic::mips_sra_w:
2205  case Intrinsic::mips_sra_d:
2206  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2207  truncateVecElts(Op, DAG));
2208  case Intrinsic::mips_srai_b:
2209  case Intrinsic::mips_srai_h:
2210  case Intrinsic::mips_srai_w:
2211  case Intrinsic::mips_srai_d:
2212  return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2213  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2214  case Intrinsic::mips_srari_b:
2215  case Intrinsic::mips_srari_h:
2216  case Intrinsic::mips_srari_w:
2217  case Intrinsic::mips_srari_d: {
2218  // Report an error for out of range values.
2219  int64_t Max;
2220  switch (Intrinsic) {
2221  case Intrinsic::mips_srari_b: Max = 7; break;
2222  case Intrinsic::mips_srari_h: Max = 15; break;
2223  case Intrinsic::mips_srari_w: Max = 31; break;
2224  case Intrinsic::mips_srari_d: Max = 63; break;
2225  default: llvm_unreachable("Unmatched intrinsic");
2226  }
2227  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2228  if (Value < 0 || Value > Max)
2229  report_fatal_error("Immediate out of range");
2230  return SDValue();
2231  }
2232  case Intrinsic::mips_srl_b:
2233  case Intrinsic::mips_srl_h:
2234  case Intrinsic::mips_srl_w:
2235  case Intrinsic::mips_srl_d:
2236  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2237  truncateVecElts(Op, DAG));
2238  case Intrinsic::mips_srli_b:
2239  case Intrinsic::mips_srli_h:
2240  case Intrinsic::mips_srli_w:
2241  case Intrinsic::mips_srli_d:
2242  return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2243  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2244  case Intrinsic::mips_srlri_b:
2245  case Intrinsic::mips_srlri_h:
2246  case Intrinsic::mips_srlri_w:
2247  case Intrinsic::mips_srlri_d: {
2248  // Report an error for out of range values.
2249  int64_t Max;
2250  switch (Intrinsic) {
2251  case Intrinsic::mips_srlri_b: Max = 7; break;
2252  case Intrinsic::mips_srlri_h: Max = 15; break;
2253  case Intrinsic::mips_srlri_w: Max = 31; break;
2254  case Intrinsic::mips_srlri_d: Max = 63; break;
2255  default: llvm_unreachable("Unmatched intrinsic");
2256  }
2257  int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2258  if (Value < 0 || Value > Max)
2259  report_fatal_error("Immediate out of range");
2260  return SDValue();
2261  }
2262  case Intrinsic::mips_subv_b:
2263  case Intrinsic::mips_subv_h:
2264  case Intrinsic::mips_subv_w:
2265  case Intrinsic::mips_subv_d:
2266  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2267  Op->getOperand(2));
2268  case Intrinsic::mips_subvi_b:
2269  case Intrinsic::mips_subvi_h:
2270  case Intrinsic::mips_subvi_w:
2271  case Intrinsic::mips_subvi_d:
2272  return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2273  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2274  case Intrinsic::mips_vshf_b:
2275  case Intrinsic::mips_vshf_h:
2276  case Intrinsic::mips_vshf_w:
2277  case Intrinsic::mips_vshf_d:
2278  return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2279  Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2280  case Intrinsic::mips_xor_v:
2281  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2282  Op->getOperand(2));
2283  case Intrinsic::mips_xori_b:
2284  return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2285  Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2286  case Intrinsic::thread_pointer: {
2287  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2288  return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2289  }
2290  }
2291 }
2292 
2294  const MipsSubtarget &Subtarget) {
2295  SDLoc DL(Op);
2296  SDValue ChainIn = Op->getOperand(0);
2297  SDValue Address = Op->getOperand(2);
2298  SDValue Offset = Op->getOperand(3);
2299  EVT ResTy = Op->getValueType(0);
2300  EVT PtrTy = Address->getValueType(0);
2301 
2302  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2303  // however takes an i32 signed constant offset. The actual type of the
2304  // intrinsic is a scaled signed i10.
2305  if (Subtarget.isABI_N64())
2306  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2307 
2308  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2309  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2310  /* Alignment = */ 16);
2311 }
2312 
2313 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2314  SelectionDAG &DAG) const {
2315  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2316  switch (Intr) {
2317  default:
2318  return SDValue();
2319  case Intrinsic::mips_extp:
2320  return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2321  case Intrinsic::mips_extpdp:
2322  return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2323  case Intrinsic::mips_extr_w:
2324  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2325  case Intrinsic::mips_extr_r_w:
2326  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2327  case Intrinsic::mips_extr_rs_w:
2328  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2329  case Intrinsic::mips_extr_s_h:
2330  return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2331  case Intrinsic::mips_mthlip:
2332  return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2333  case Intrinsic::mips_mulsaq_s_w_ph:
2334  return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2335  case Intrinsic::mips_maq_s_w_phl:
2336  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2337  case Intrinsic::mips_maq_s_w_phr:
2338  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2339  case Intrinsic::mips_maq_sa_w_phl:
2340  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2341  case Intrinsic::mips_maq_sa_w_phr:
2342  return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2343  case Intrinsic::mips_dpaq_s_w_ph:
2344  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2345  case Intrinsic::mips_dpsq_s_w_ph:
2346  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2347  case Intrinsic::mips_dpaq_sa_l_w:
2348  return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2349  case Intrinsic::mips_dpsq_sa_l_w:
2350  return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2351  case Intrinsic::mips_dpaqx_s_w_ph:
2352  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2353  case Intrinsic::mips_dpaqx_sa_w_ph:
2354  return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2355  case Intrinsic::mips_dpsqx_s_w_ph:
2356  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2357  case Intrinsic::mips_dpsqx_sa_w_ph:
2358  return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2359  case Intrinsic::mips_ld_b:
2360  case Intrinsic::mips_ld_h:
2361  case Intrinsic::mips_ld_w:
2362  case Intrinsic::mips_ld_d:
2363  return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
2364  }
2365 }
2366 
2368  const MipsSubtarget &Subtarget) {
2369  SDLoc DL(Op);
2370  SDValue ChainIn = Op->getOperand(0);
2371  SDValue Value = Op->getOperand(2);
2372  SDValue Address = Op->getOperand(3);
2373  SDValue Offset = Op->getOperand(4);
2374  EVT PtrTy = Address->getValueType(0);
2375 
2376  // For N64 addresses have the underlying type MVT::i64. This intrinsic
2377  // however takes an i32 signed constant offset. The actual type of the
2378  // intrinsic is a scaled signed i10.
2379  if (Subtarget.isABI_N64())
2380  Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2381 
2382  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2383 
2384  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2385  /* Alignment = */ 16);
2386 }
2387 
2388 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2389  SelectionDAG &DAG) const {
2390  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2391  switch (Intr) {
2392  default:
2393  return SDValue();
2394  case Intrinsic::mips_st_b:
2395  case Intrinsic::mips_st_h:
2396  case Intrinsic::mips_st_w:
2397  case Intrinsic::mips_st_d:
2398  return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
2399  }
2400 }
2401 
2402 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2403 //
2404 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2405 // choose to sign-extend but we could have equally chosen zero-extend. The
2406 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2407 // result into this node later (possibly changing it to a zero-extend in the
2408 // process).
2409 SDValue MipsSETargetLowering::
2410 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2411  SDLoc DL(Op);
2412  EVT ResTy = Op->getValueType(0);
2413  SDValue Op0 = Op->getOperand(0);
2414  EVT VecTy = Op0->getValueType(0);
2415 
2416  if (!VecTy.is128BitVector())
2417  return SDValue();
2418 
2419  if (ResTy.isInteger()) {
2420  SDValue Op1 = Op->getOperand(1);
2421  EVT EltTy = VecTy.getVectorElementType();
2422  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2423  DAG.getValueType(EltTy));
2424  }
2425 
2426  return Op;
2427 }
2428 
2429 static bool isConstantOrUndef(const SDValue Op) {
2430  if (Op->isUndef())
2431  return true;
2432  if (isa<ConstantSDNode>(Op))
2433  return true;
2434  if (isa<ConstantFPSDNode>(Op))
2435  return true;
2436  return false;
2437 }
2438 
2440  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2441  if (isConstantOrUndef(Op->getOperand(i)))
2442  return true;
2443  return false;
2444 }
2445 
2446 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2447 // backend.
2448 //
2449 // Lowers according to the following rules:
2450 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2451 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2452 // immediate
2453 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2454 // is a power of 2 less than or equal to 64 and the value does not fit into a
2455 // signed 10-bit immediate
2456 // - Non-constant splats are legal as-is.
2457 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2458 // - All others are illegal and must be expanded.
2459 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2460  SelectionDAG &DAG) const {
2461  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2462  EVT ResTy = Op->getValueType(0);
2463  SDLoc DL(Op);
2464  APInt SplatValue, SplatUndef;
2465  unsigned SplatBitSize;
2466  bool HasAnyUndefs;
2467 
2468  if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2469  return SDValue();
2470 
2471  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2472  HasAnyUndefs, 8,
2473  !Subtarget.isLittle()) && SplatBitSize <= 64) {
2474  // We can only cope with 8, 16, 32, or 64-bit elements
2475  if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2476  SplatBitSize != 64)
2477  return SDValue();
2478 
2479  // If the value isn't an integer type we will have to bitcast
2480  // from an integer type first. Also, if there are any undefs, we must
2481  // lower them to defined values first.
2482  if (ResTy.isInteger() && !HasAnyUndefs)
2483  return Op;
2484 
2485  EVT ViaVecTy;
2486 
2487  switch (SplatBitSize) {
2488  default:
2489  return SDValue();
2490  case 8:
2491  ViaVecTy = MVT::v16i8;
2492  break;
2493  case 16:
2494  ViaVecTy = MVT::v8i16;
2495  break;
2496  case 32:
2497  ViaVecTy = MVT::v4i32;
2498  break;
2499  case 64:
2500  // There's no fill.d to fall back on for 64-bit values
2501  return SDValue();
2502  }
2503 
2504  // SelectionDAG::getConstant will promote SplatValue appropriately.
2505  SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
2506 
2507  // Bitcast to the type we originally wanted
2508  if (ViaVecTy != ResTy)
2509  Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2510 
2511  return Result;
2512  } else if (DAG.isSplatValue(Op, /* AllowUndefs */ false))
2513  return Op;
2514  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2515  // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2516  // The resulting code is the same length as the expansion, but it doesn't
2517  // use memory operations
2518  EVT ResTy = Node->getValueType(0);
2519 
2520  assert(ResTy.isVector());
2521 
2522  unsigned NumElts = ResTy.getVectorNumElements();
2523  SDValue Vector = DAG.getUNDEF(ResTy);
2524  for (unsigned i = 0; i < NumElts; ++i) {
2525  Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2526  Node->getOperand(i),
2527  DAG.getConstant(i, DL, MVT::i32));
2528  }
2529  return Vector;
2530  }
2531 
2532  return SDValue();
2533 }
2534 
2535 // Lower VECTOR_SHUFFLE into SHF (if possible).
2536 //
2537 // SHF splits the vector into blocks of four elements, then shuffles these
2538 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2539 //
2540 // It is therefore possible to lower into SHF when the mask takes the form:
2541 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2542 // When undef's appear they are treated as if they were whatever value is
2543 // necessary in order to fit the above forms.
2544 //
2545 // For example:
2546 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2547 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2548 // i32 7, i32 6, i32 5, i32 4>
2549 // is lowered to:
2550 // (SHF_H $w0, $w1, 27)
2551 // where the 27 comes from:
2552 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2554  SmallVector<int, 16> Indices,
2555  SelectionDAG &DAG) {
2556  int SHFIndices[4] = { -1, -1, -1, -1 };
2557 
2558  if (Indices.size() < 4)
2559  return SDValue();
2560 
2561  for (unsigned i = 0; i < 4; ++i) {
2562  for (unsigned j = i; j < Indices.size(); j += 4) {
2563  int Idx = Indices[j];
2564 
2565  // Convert from vector index to 4-element subvector index
2566  // If an index refers to an element outside of the subvector then give up
2567  if (Idx != -1) {
2568  Idx -= 4 * (j / 4);
2569  if (Idx < 0 || Idx >= 4)
2570  return SDValue();
2571  }
2572 
2573  // If the mask has an undef, replace it with the current index.
2574  // Note that it might still be undef if the current index is also undef
2575  if (SHFIndices[i] == -1)
2576  SHFIndices[i] = Idx;
2577 
2578  // Check that non-undef values are the same as in the mask. If they
2579  // aren't then give up
2580  if (!(Idx == -1 || Idx == SHFIndices[i]))
2581  return SDValue();
2582  }
2583  }
2584 
2585  // Calculate the immediate. Replace any remaining undefs with zero
2586  APInt Imm(32, 0);
2587  for (int i = 3; i >= 0; --i) {
2588  int Idx = SHFIndices[i];
2589 
2590  if (Idx == -1)
2591  Idx = 0;
2592 
2593  Imm <<= 2;
2594  Imm |= Idx & 0x3;
2595  }
2596 
2597  SDLoc DL(Op);
2598  return DAG.getNode(MipsISD::SHF, DL, ResTy,
2599  DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
2600 }
2601 
2602 /// Determine whether a range fits a regular pattern of values.
2603 /// This function accounts for the possibility of jumping over the End iterator.
2604 template <typename ValType>
2605 static bool
2607  unsigned CheckStride,
2609  ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2610  auto &I = Begin;
2611 
2612  while (I != End) {
2613  if (*I != -1 && *I != ExpectedIndex)
2614  return false;
2615  ExpectedIndex += ExpectedIndexStride;
2616 
2617  // Incrementing past End is undefined behaviour so we must increment one
2618  // step at a time and check for End at each step.
2619  for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2620  ; // Empty loop body.
2621  }
2622  return true;
2623 }
2624 
2625 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2626 //
2627 // It is a SPLATI when the mask is:
2628 // <x, x, x, ...>
2629 // where x is any valid index.
2630 //
2631 // When undef's appear in the mask they are treated as if they were whatever
2632 // value is necessary in order to fit the above form.
2633 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2634  SmallVector<int, 16> Indices,
2635  SelectionDAG &DAG) {
2636  assert((Indices.size() % 2) == 0);
2637 
2638  int SplatIndex = -1;
2639  for (const auto &V : Indices) {
2640  if (V != -1) {
2641  SplatIndex = V;
2642  break;
2643  }
2644  }
2645 
2646  return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2647  0);
2648 }
2649 
2650 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2651 //
2652 // ILVEV interleaves the even elements from each vector.
2653 //
2654 // It is possible to lower into ILVEV when the mask consists of two of the
2655 // following forms interleaved:
2656 // <0, 2, 4, ...>
2657 // <n, n+2, n+4, ...>
2658 // where n is the number of elements in the vector.
2659 // For example:
2660 // <0, 0, 2, 2, 4, 4, ...>
2661 // <0, n, 2, n+2, 4, n+4, ...>
2662 //
2663 // When undef's appear in the mask they are treated as if they were whatever
2664 // value is necessary in order to fit the above forms.
2666  SmallVector<int, 16> Indices,
2667  SelectionDAG &DAG) {
2668  assert((Indices.size() % 2) == 0);
2669 
2670  SDValue Wt;
2671  SDValue Ws;
2672  const auto &Begin = Indices.begin();
2673  const auto &End = Indices.end();
2674 
2675  // Check even elements are taken from the even elements of one half or the
2676  // other and pick an operand accordingly.
2677  if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2678  Wt = Op->getOperand(0);
2679  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2680  Wt = Op->getOperand(1);
2681  else
2682  return SDValue();
2683 
2684  // Check odd elements are taken from the even elements of one half or the
2685  // other and pick an operand accordingly.
2686  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2687  Ws = Op->getOperand(0);
2688  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2689  Ws = Op->getOperand(1);
2690  else
2691  return SDValue();
2692 
2693  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2694 }
2695 
2696 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2697 //
2698 // ILVOD interleaves the odd elements from each vector.
2699 //
2700 // It is possible to lower into ILVOD when the mask consists of two of the
2701 // following forms interleaved:
2702 // <1, 3, 5, ...>
2703 // <n+1, n+3, n+5, ...>
2704 // where n is the number of elements in the vector.
2705 // For example:
2706 // <1, 1, 3, 3, 5, 5, ...>
2707 // <1, n+1, 3, n+3, 5, n+5, ...>
2708 //
2709 // When undef's appear in the mask they are treated as if they were whatever
2710 // value is necessary in order to fit the above forms.
2712  SmallVector<int, 16> Indices,
2713  SelectionDAG &DAG) {
2714  assert((Indices.size() % 2) == 0);
2715 
2716  SDValue Wt;
2717  SDValue Ws;
2718  const auto &Begin = Indices.begin();
2719  const auto &End = Indices.end();
2720 
2721  // Check even elements are taken from the odd elements of one half or the
2722  // other and pick an operand accordingly.
2723  if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2724  Wt = Op->getOperand(0);
2725  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2726  Wt = Op->getOperand(1);
2727  else
2728  return SDValue();
2729 
2730  // Check odd elements are taken from the odd elements of one half or the
2731  // other and pick an operand accordingly.
2732  if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2733  Ws = Op->getOperand(0);
2734  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2735  Ws = Op->getOperand(1);
2736  else
2737  return SDValue();
2738 
2739  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2740 }
2741 
2742 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2743 //
2744 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2745 // each vector.
2746 //
2747 // It is possible to lower into ILVR when the mask consists of two of the
2748 // following forms interleaved:
2749 // <0, 1, 2, ...>
2750 // <n, n+1, n+2, ...>
2751 // where n is the number of elements in the vector.
2752 // For example:
2753 // <0, 0, 1, 1, 2, 2, ...>
2754 // <0, n, 1, n+1, 2, n+2, ...>
2755 //
2756 // When undef's appear in the mask they are treated as if they were whatever
2757 // value is necessary in order to fit the above forms.
2759  SmallVector<int, 16> Indices,
2760  SelectionDAG &DAG) {
2761  assert((Indices.size() % 2) == 0);
2762 
2763  SDValue Wt;
2764  SDValue Ws;
2765  const auto &Begin = Indices.begin();
2766  const auto &End = Indices.end();
2767 
2768  // Check even elements are taken from the right (lowest-indexed) elements of
2769  // one half or the other and pick an operand accordingly.
2770  if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2771  Wt = Op->getOperand(0);
2772  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2773  Wt = Op->getOperand(1);
2774  else
2775  return SDValue();
2776 
2777  // Check odd elements are taken from the right (lowest-indexed) elements of
2778  // one half or the other and pick an operand accordingly.
2779  if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2780  Ws = Op->getOperand(0);
2781  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2782  Ws = Op->getOperand(1);
2783  else
2784  return SDValue();
2785 
2786  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2787 }
2788 
2789 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2790 //
2791 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2792 // of each vector.
2793 //
2794 // It is possible to lower into ILVL when the mask consists of two of the
2795 // following forms interleaved:
2796 // <x, x+1, x+2, ...>
2797 // <n+x, n+x+1, n+x+2, ...>
2798 // where n is the number of elements in the vector and x is half n.
2799 // For example:
2800 // <x, x, x+1, x+1, x+2, x+2, ...>
2801 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2802 //
2803 // When undef's appear in the mask they are treated as if they were whatever
2804 // value is necessary in order to fit the above forms.
2806  SmallVector<int, 16> Indices,
2807  SelectionDAG &DAG) {
2808  assert((Indices.size() % 2) == 0);
2809 
2810  unsigned HalfSize = Indices.size() / 2;
2811  SDValue Wt;
2812  SDValue Ws;
2813  const auto &Begin = Indices.begin();
2814  const auto &End = Indices.end();
2815 
2816  // Check even elements are taken from the left (highest-indexed) elements of
2817  // one half or the other and pick an operand accordingly.
2818  if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2819  Wt = Op->getOperand(0);
2820  else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2821  Wt = Op->getOperand(1);
2822  else
2823  return SDValue();
2824 
2825  // Check odd elements are taken from the left (highest-indexed) elements of
2826  // one half or the other and pick an operand accordingly.
2827  if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2828  Ws = Op->getOperand(0);
2829  else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2830  1))
2831  Ws = Op->getOperand(1);
2832  else
2833  return SDValue();
2834 
2835  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2836 }
2837 
2838 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2839 //
2840 // PCKEV copies the even elements of each vector into the result vector.
2841 //
2842 // It is possible to lower into PCKEV when the mask consists of two of the
2843 // following forms concatenated:
2844 // <0, 2, 4, ...>
2845 // <n, n+2, n+4, ...>
2846 // where n is the number of elements in the vector.
2847 // For example:
2848 // <0, 2, 4, ..., 0, 2, 4, ...>
2849 // <0, 2, 4, ..., n, n+2, n+4, ...>
2850 //
2851 // When undef's appear in the mask they are treated as if they were whatever
2852 // value is necessary in order to fit the above forms.
2854  SmallVector<int, 16> Indices,
2855  SelectionDAG &DAG) {
2856  assert((Indices.size() % 2) == 0);
2857 
2858  SDValue Wt;
2859  SDValue Ws;
2860  const auto &Begin = Indices.begin();
2861  const auto &Mid = Indices.begin() + Indices.size() / 2;
2862  const auto &End = Indices.end();
2863 
2864  if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2865  Wt = Op->getOperand(0);
2866  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2867  Wt = Op->getOperand(1);
2868  else
2869  return SDValue();
2870 
2871  if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2872  Ws = Op->getOperand(0);
2873  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2874  Ws = Op->getOperand(1);
2875  else
2876  return SDValue();
2877 
2878  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2879 }
2880 
2881 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2882 //
2883 // PCKOD copies the odd elements of each vector into the result vector.
2884 //
2885 // It is possible to lower into PCKOD when the mask consists of two of the
2886 // following forms concatenated:
2887 // <1, 3, 5, ...>
2888 // <n+1, n+3, n+5, ...>
2889 // where n is the number of elements in the vector.
2890 // For example:
2891 // <1, 3, 5, ..., 1, 3, 5, ...>
2892 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2893 //
2894 // When undef's appear in the mask they are treated as if they were whatever
2895 // value is necessary in order to fit the above forms.
2897  SmallVector<int, 16> Indices,
2898  SelectionDAG &DAG) {
2899  assert((Indices.size() % 2) == 0);
2900 
2901  SDValue Wt;
2902  SDValue Ws;
2903  const auto &Begin = Indices.begin();
2904  const auto &Mid = Indices.begin() + Indices.size() / 2;
2905  const auto &End = Indices.end();
2906 
2907  if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2908  Wt = Op->getOperand(0);
2909  else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2910  Wt = Op->getOperand(1);
2911  else
2912  return SDValue();
2913 
2914  if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2915  Ws = Op->getOperand(0);
2916  else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2917  Ws = Op->getOperand(1);
2918  else
2919  return SDValue();
2920 
2921  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2922 }
2923 
2924 // Lower VECTOR_SHUFFLE into VSHF.
2925 //
2926 // This mostly consists of converting the shuffle indices in Indices into a
2927 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2928 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2929 // if the type is v8i16 and all the indices are less than 8 then the second
2930 // operand is unused and can be replaced with anything. We choose to replace it
2931 // with the used operand since this reduces the number of instructions overall.
2933  SmallVector<int, 16> Indices,
2934  SelectionDAG &DAG) {
2936  SDValue Op0;
2937  SDValue Op1;
2938  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2939  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2940  bool Using1stVec = false;
2941  bool Using2ndVec = false;
2942  SDLoc DL(Op);
2943  int ResTyNumElts = ResTy.getVectorNumElements();
2944 
2945  for (int i = 0; i < ResTyNumElts; ++i) {
2946  // Idx == -1 means UNDEF
2947  int Idx = Indices[i];
2948 
2949  if (0 <= Idx && Idx < ResTyNumElts)
2950  Using1stVec = true;
2951  if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2952  Using2ndVec = true;
2953  }
2954 
2955  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2956  ++I)
2957  Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
2958 
2959  SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
2960 
2961  if (Using1stVec && Using2ndVec) {
2962  Op0 = Op->getOperand(0);
2963  Op1 = Op->getOperand(1);
2964  } else if (Using1stVec)
2965  Op0 = Op1 = Op->getOperand(0);
2966  else if (Using2ndVec)
2967  Op0 = Op1 = Op->getOperand(1);
2968  else
2969  llvm_unreachable("shuffle vector mask references neither vector operand?");
2970 
2971  // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2972  // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2973  // VSHF concatenates the vectors in a bitwise fashion:
2974  // <0b00, 0b01> + <0b10, 0b11> ->
2975  // 0b0100 + 0b1110 -> 0b01001110
2976  // <0b10, 0b11, 0b00, 0b01>
2977  // We must therefore swap the operands to get the correct result.
2978  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2979 }
2980 
2981 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2982 // indices in the shuffle.
2983 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2984  SelectionDAG &DAG) const {
2985  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2986  EVT ResTy = Op->getValueType(0);
2987 
2988  if (!ResTy.is128BitVector())
2989  return SDValue();
2990 
2991  int ResTyNumElts = ResTy.getVectorNumElements();
2992  SmallVector<int, 16> Indices;
2993 
2994  for (int i = 0; i < ResTyNumElts; ++i)
2995  Indices.push_back(Node->getMaskElt(i));
2996 
2997  // splati.[bhwd] is preferable to the others but is matched from
2998  // MipsISD::VSHF.
2999  if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
3000  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
3001  SDValue Result;
3002  if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
3003  return Result;
3004  if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
3005  return Result;
3006  if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
3007  return Result;
3008  if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
3009  return Result;
3010  if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
3011  return Result;
3012  if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
3013  return Result;
3014  if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
3015  return Result;
3016  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
3017 }
3018 
3020 MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
3021  MachineBasicBlock *BB) const {
3022  // $bb:
3023  // bposge32_pseudo $vr0
3024  // =>
3025  // $bb:
3026  // bposge32 $tbb
3027  // $fbb:
3028  // li $vr2, 0
3029  // b $sink
3030  // $tbb:
3031  // li $vr1, 1
3032  // $sink:
3033  // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
3034 
3035  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3037  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3038  DebugLoc DL = MI.getDebugLoc();
3039  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3041  MachineFunction *F = BB->getParent();
3042  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3043  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3045  F->insert(It, FBB);
3046  F->insert(It, TBB);
3047  F->insert(It, Sink);
3048 
3049  // Transfer the remainder of BB and its successor edges to Sink.
3050  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3051  BB->end());
3053 
3054  // Add successors.
3055  BB->addSuccessor(FBB);
3056  BB->addSuccessor(TBB);
3057  FBB->addSuccessor(Sink);
3058  TBB->addSuccessor(Sink);
3059 
3060  // Insert the real bposge32 instruction to $BB.
3061  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3062  // Insert the real bposge32c instruction to $BB.
3063  BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3064 
3065  // Fill $FBB.
3066  Register VR2 = RegInfo.createVirtualRegister(RC);
3067  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3068  .addReg(Mips::ZERO).addImm(0);
3069  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3070 
3071  // Fill $TBB.
3072  Register VR1 = RegInfo.createVirtualRegister(RC);
3073  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3074  .addReg(Mips::ZERO).addImm(1);
3075 
3076  // Insert phi function to $Sink.
3077  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3078  MI.getOperand(0).getReg())
3079  .addReg(VR2)
3080  .addMBB(FBB)
3081  .addReg(VR1)
3082  .addMBB(TBB);
3083 
3084  MI.eraseFromParent(); // The pseudo instruction is gone now.
3085  return Sink;
3086 }
3087 
3088 MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
3089  MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
3090  // $bb:
3091  // vany_nonzero $rd, $ws
3092  // =>
3093  // $bb:
3094  // bnz.b $ws, $tbb
3095  // b $fbb
3096  // $fbb:
3097  // li $rd1, 0
3098  // b $sink
3099  // $tbb:
3100  // li $rd2, 1
3101  // $sink:
3102  // $rd = phi($rd1, $fbb, $rd2, $tbb)
3103 
3104  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3106  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3107  DebugLoc DL = MI.getDebugLoc();
3108  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3110  MachineFunction *F = BB->getParent();
3111  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3112  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3114  F->insert(It, FBB);
3115  F->insert(It, TBB);
3116  F->insert(It, Sink);
3117 
3118  // Transfer the remainder of BB and its successor edges to Sink.
3119  Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3120  BB->end());
3122 
3123  // Add successors.
3124  BB->addSuccessor(FBB);
3125  BB->addSuccessor(TBB);
3126  FBB->addSuccessor(Sink);
3127  TBB->addSuccessor(Sink);
3128 
3129  // Insert the real bnz.b instruction to $BB.
3130  BuildMI(BB, DL, TII->get(BranchOp))
3131  .addReg(MI.getOperand(1).getReg())
3132  .addMBB(TBB);
3133 
3134  // Fill $FBB.
3135  Register RD1 = RegInfo.createVirtualRegister(RC);
3136  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3137  .addReg(Mips::ZERO).addImm(0);
3138  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3139 
3140  // Fill $TBB.
3141  Register RD2 = RegInfo.createVirtualRegister(RC);
3142  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3143  .addReg(Mips::ZERO).addImm(1);
3144 
3145  // Insert phi function to $Sink.
3146  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3147  MI.getOperand(0).getReg())
3148  .addReg(RD1)
3149  .addMBB(FBB)
3150  .addReg(RD2)
3151  .addMBB(TBB);
3152 
3153  MI.eraseFromParent(); // The pseudo instruction is gone now.
3154  return Sink;
3155 }
3156 
3157 // Emit the COPY_FW pseudo instruction.
3158 //
3159 // copy_fw_pseudo $fd, $ws, n
3160 // =>
3161 // copy_u_w $rt, $ws, $n
3162 // mtc1 $rt, $fd
3163 //
3164 // When n is zero, the equivalent operation can be performed with (potentially)
3165 // zero instructions due to register overlaps. This optimization is never valid
3166 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3168 MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3169  MachineBasicBlock *BB) const {
3171  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3172  DebugLoc DL = MI.getDebugLoc();
3173  Register Fd = MI.getOperand(0).getReg();
3174  Register Ws = MI.getOperand(1).getReg();
3175  unsigned Lane = MI.getOperand(2).getImm();
3176 
3177  if (Lane == 0) {
3178  unsigned Wt = Ws;
3179  if (!Subtarget.useOddSPReg()) {
3180  // We must copy to an even-numbered MSA register so that the
3181  // single-precision sub-register is also guaranteed to be even-numbered.
3182  Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3183 
3184  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3185  }
3186 
3187  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3188  } else {
3189  Register Wt = RegInfo.createVirtualRegister(
3190  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3191  : &Mips::MSA128WEvensRegClass);
3192 
3193  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3194  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3195  }
3196 
3197  MI.eraseFromParent(); // The pseudo instruction is gone now.
3198  return BB;
3199 }
3200 
3201 // Emit the COPY_FD pseudo instruction.
3202 //
3203 // copy_fd_pseudo $fd, $ws, n
3204 // =>
3205 // splati.d $wt, $ws, $n
3206 // copy $fd, $wt:sub_64
3207 //
3208 // When n is zero, the equivalent operation can be performed with (potentially)
3209 // zero instructions due to register overlaps. This optimization is always
3210 // valid because FR=1 mode which is the only supported mode in MSA.
3212 MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3213  MachineBasicBlock *BB) const {
3215 
3217  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3218  Register Fd = MI.getOperand(0).getReg();
3219  Register Ws = MI.getOperand(1).getReg();
3220  unsigned Lane = MI.getOperand(2).getImm() * 2;
3221  DebugLoc DL = MI.getDebugLoc();
3222 
3223  if (Lane == 0)
3224  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3225  else {
3226  Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3227 
3228  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3229  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3230  }
3231 
3232  MI.eraseFromParent(); // The pseudo instruction is gone now.
3233  return BB;
3234 }
3235 
3236 // Emit the INSERT_FW pseudo instruction.
3237 //
3238 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3239 // =>
3240 // subreg_to_reg $wt:sub_lo, $fs
3241 // insve_w $wd[$n], $wd_in, $wt[0]
3243 MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
3244  MachineBasicBlock *BB) const {
3246  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3247  DebugLoc DL = MI.getDebugLoc();
3248  Register Wd = MI.getOperand(0).getReg();
3249  Register Wd_in = MI.getOperand(1).getReg();
3250  unsigned Lane = MI.getOperand(2).getImm();
3251  Register Fs = MI.getOperand(3).getReg();
3252  Register Wt = RegInfo.createVirtualRegister(
3253  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3254  : &Mips::MSA128WEvensRegClass);
3255 
3256  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3257  .addImm(0)
3258  .addReg(Fs)
3259  .addImm(Mips::sub_lo);
3260  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3261  .addReg(Wd_in)
3262  .addImm(Lane)
3263  .addReg(Wt)
3264  .addImm(0);
3265 
3266  MI.eraseFromParent(); // The pseudo instruction is gone now.
3267  return BB;
3268 }
3269 
3270 // Emit the INSERT_FD pseudo instruction.
3271 //
3272 // insert_fd_pseudo $wd, $fs, n
3273 // =>
3274 // subreg_to_reg $wt:sub_64, $fs
3275 // insve_d $wd[$n], $wd_in, $wt[0]
3277 MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
3278  MachineBasicBlock *BB) const {
3280 
3282  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3283  DebugLoc DL = MI.getDebugLoc();
3284  Register Wd = MI.getOperand(0).getReg();
3285  Register Wd_in = MI.getOperand(1).getReg();
3286  unsigned Lane = MI.getOperand(2).getImm();
3287  Register Fs = MI.getOperand(3).getReg();
3288  Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3289 
3290  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3291  .addImm(0)
3292  .addReg(Fs)
3293  .addImm(Mips::sub_64);
3294  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3295  .addReg(Wd_in)
3296  .addImm(Lane)
3297  .addReg(Wt)
3298  .addImm(0);
3299 
3300  MI.eraseFromParent(); // The pseudo instruction is gone now.
3301  return BB;
3302 }
3303 
3304 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3305 //
3306 // For integer:
3307 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3308 // =>
3309 // (SLL $lanetmp1, $lane, <log2size)
3310 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3311 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3312 // (NEG $lanetmp2, $lanetmp1)
3313 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3314 //
3315 // For floating point:
3316 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3317 // =>
3318 // (SUBREG_TO_REG $wt, $fs, <subreg>)
3319 // (SLL $lanetmp1, $lane, <log2size)
3320 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3321 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3322 // (NEG $lanetmp2, $lanetmp1)
3323 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3324 MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3325  MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3326  bool IsFP) const {
3328  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3329  DebugLoc DL = MI.getDebugLoc();
3330  Register Wd = MI.getOperand(0).getReg();
3331  Register SrcVecReg = MI.getOperand(1).getReg();
3332  Register LaneReg = MI.getOperand(2).getReg();
3333  Register SrcValReg = MI.getOperand(3).getReg();
3334 
3335  const TargetRegisterClass *VecRC = nullptr;
3336  // FIXME: This should be true for N32 too.
3337  const TargetRegisterClass *GPRRC =
3338  Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3339  unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3340  unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
3341  unsigned EltLog2Size;
3342  unsigned InsertOp = 0;
3343  unsigned InsveOp = 0;
3344  switch (EltSizeInBytes) {
3345  default:
3346  llvm_unreachable("Unexpected size");
3347  case 1:
3348  EltLog2Size = 0;
3349  InsertOp = Mips::INSERT_B;
3350  InsveOp = Mips::INSVE_B;
3351  VecRC = &Mips::MSA128BRegClass;
3352  break;
3353  case 2:
3354  EltLog2Size = 1;
3355  InsertOp = Mips::INSERT_H;
3356  InsveOp = Mips::INSVE_H;
3357  VecRC = &Mips::MSA128HRegClass;
3358  break;
3359  case 4:
3360  EltLog2Size = 2;
3361  InsertOp = Mips::INSERT_W;
3362  InsveOp = Mips::INSVE_W;
3363  VecRC = &Mips::MSA128WRegClass;
3364  break;
3365  case 8:
3366  EltLog2Size = 3;
3367  InsertOp = Mips::INSERT_D;
3368  InsveOp = Mips::INSVE_D;
3369  VecRC = &Mips::MSA128DRegClass;
3370  break;
3371  }
3372 
3373  if (IsFP) {
3374  Register Wt = RegInfo.createVirtualRegister(VecRC);
3375  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3376  .addImm(0)
3377  .addReg(SrcValReg)
3378  .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3379  SrcValReg = Wt;
3380  }
3381 
3382  // Convert the lane index into a byte index
3383  if (EltSizeInBytes != 1) {
3384  Register LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3385  BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3386  .addReg(LaneReg)
3387  .addImm(EltLog2Size);
3388  LaneReg = LaneTmp1;
3389  }
3390 
3391  // Rotate bytes around so that the desired lane is element zero
3392  Register WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3393  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3394  .addReg(SrcVecReg)
3395  .addReg(SrcVecReg)
3396  .addReg(LaneReg, 0, SubRegIdx);
3397 
3398  Register WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3399  if (IsFP) {
3400  // Use insve.df to insert to element zero
3401  BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3402  .addReg(WdTmp1)
3403  .addImm(0)
3404  .addReg(SrcValReg)
3405  .addImm(0);
3406  } else {
3407  // Use insert.df to insert to element zero
3408  BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3409  .addReg(WdTmp1)
3410  .addReg(SrcValReg)
3411  .addImm(0);
3412  }
3413 
3414  // Rotate elements the rest of the way for a full rotation.
3415  // sld.df inteprets $rt modulo the number of columns so we only need to negate
3416  // the lane index to do this.
3417  Register LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3418  BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3419  LaneTmp2)
3420  .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3421  .addReg(LaneReg);
3422  BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3423  .addReg(WdTmp2)
3424  .addReg(WdTmp2)
3425  .addReg(LaneTmp2, 0, SubRegIdx);
3426 
3427  MI.eraseFromParent(); // The pseudo instruction is gone now.
3428  return BB;
3429 }
3430 
3431 // Emit the FILL_FW pseudo instruction.
3432 //
3433 // fill_fw_pseudo $wd, $fs
3434 // =>
3435 // implicit_def $wt1
3436 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3437 // splati.w $wd, $wt2[0]
3439 MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
3440  MachineBasicBlock *BB) const {
3442  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3443  DebugLoc DL = MI.getDebugLoc();
3444  Register Wd = MI.getOperand(0).getReg();
3445  Register Fs = MI.getOperand(1).getReg();
3446  Register Wt1 = RegInfo.createVirtualRegister(
3447  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3448  : &Mips::MSA128WEvensRegClass);
3449  Register Wt2 = RegInfo.createVirtualRegister(
3450  Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3451  : &Mips::MSA128WEvensRegClass);
3452 
3453  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3454  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3455  .addReg(Wt1)
3456  .addReg(Fs)
3457  .addImm(Mips::sub_lo);
3458  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3459 
3460  MI.eraseFromParent(); // The pseudo instruction is gone now.
3461  return BB;
3462 }
3463 
3464 // Emit the FILL_FD pseudo instruction.
3465 //
3466 // fill_fd_pseudo $wd, $fs
3467 // =>
3468 // implicit_def $wt1
3469 // insert_subreg $wt2:subreg_64, $wt1, $fs
3470 // splati.d $wd, $wt2[0]
3472 MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
3473  MachineBasicBlock *BB) const {
3475 
3477  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3478  DebugLoc DL = MI.getDebugLoc();
3479  Register Wd = MI.getOperand(0).getReg();
3480  Register Fs = MI.getOperand(1).getReg();
3481  Register Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3482  Register Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3483 
3484  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3485  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3486  .addReg(Wt1)
3487  .addReg(Fs)
3488  .addImm(Mips::sub_64);
3489  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3490 
3491  MI.eraseFromParent(); // The pseudo instruction is gone now.
3492  return BB;
3493 }
3494 
3495 // Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3496 // register.
3497 //
3498 // STF16 MSA128F16:$wd, mem_simm10:$addr
3499 // =>
3500 // copy_u.h $rtemp,$wd[0]
3501 // sh $rtemp, $addr
3502 //
3503 // Safety: We can't use st.h & co as they would over write the memory after
3504 // the destination. It would require half floats be allocated 16 bytes(!) of
3505 // space.
3507 MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3508  MachineBasicBlock *BB) const {
3509 
3511  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3512  DebugLoc DL = MI.getDebugLoc();
3513  Register Ws = MI.getOperand(0).getReg();
3514  Register Rt = MI.getOperand(1).getReg();
3515  const MachineMemOperand &MMO = **MI.memoperands_begin();
3516  unsigned Imm = MMO.getOffset();
3517 
3518  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3519  // spill and reload can expand as a GPR64 operand. Examine the
3520  // operand in detail and default to ABI.
3521  const TargetRegisterClass *RC =
3522  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3523  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3524  : &Mips::GPR64RegClass);
3525  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3526  Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3527 
3528  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3529  if(!UsingMips32) {
3530  Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3531  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3532  .addImm(0)
3533  .addReg(Rs)
3534  .addImm(Mips::sub_32);
3535  Rs = Tmp;
3536  }
3537  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3538  .addReg(Rs)
3539  .addReg(Rt)
3540  .addImm(Imm)
3542  &MMO, MMO.getOffset(), MMO.getSize()));
3543 
3544  MI.eraseFromParent();
3545  return BB;
3546 }
3547 
3548 // Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3549 //
3550 // LD_F16 MSA128F16:$wd, mem_simm10:$addr
3551 // =>
3552 // lh $rtemp, $addr
3553 // fill.h $wd, $rtemp
3554 //
3555 // Safety: We can't use ld.h & co as they over-read from the source.
3556 // Additionally, if the address is not modulo 16, 2 cases can occur:
3557 // a) Segmentation fault as the load instruction reads from a memory page
3558 // memory it's not supposed to.
3559 // b) The load crosses an implementation specific boundary, requiring OS
3560 // intervention.
3562 MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3563  MachineBasicBlock *BB) const {
3564 
3566  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3567  DebugLoc DL = MI.getDebugLoc();
3568  Register Wd = MI.getOperand(0).getReg();
3569 
3570  // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3571  // spill and reload can expand as a GPR64 operand. Examine the
3572  // operand in detail and default to ABI.
3573  const TargetRegisterClass *RC =
3574  MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3575  : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3576  : &Mips::GPR64RegClass);
3577 
3578  const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3579  Register Rt = RegInfo.createVirtualRegister(RC);
3580 
3581  MachineInstrBuilder MIB =
3582  BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3583  for (unsigned i = 1; i < MI.getNumOperands(); i++)
3584  MIB.add(MI.getOperand(i));
3585 
3586  if(!UsingMips32) {
3587  Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3588  BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3589  Rt = Tmp;
3590  }
3591 
3592  BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3593 
3594  MI.eraseFromParent();
3595  return BB;
3596 }
3597 
3598 // Emit the FPROUND_PSEUDO instruction.
3599 //
3600 // Round an FGR64Opnd, FGR32Opnd to an f16.
3601 //
3602 // Safety: Cycle the operand through the GPRs so the result always ends up
3603 // the correct MSA register.
3604 //
3605 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3606 // / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3607 // (which they can be, as the MSA registers are defined to alias the
3608 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3609 // the correct register class. That requires operands be tie-able across
3610 // register classes which have a sub/super register class relationship.
3611 //
3612 // For FPG32Opnd:
3613 //
3614 // FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3615 // =>
3616 // mfc1 $rtemp, $fs
3617 // fill.w $rtemp, $wtemp
3618 // fexdo.w $wd, $wtemp, $wtemp
3619 //
3620 // For FPG64Opnd on mips32r2+:
3621 //
3622 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3623 // =>
3624 // mfc1 $rtemp, $fs
3625 // fill.w $rtemp, $wtemp
3626 // mfhc1 $rtemp2, $fs
3627 // insert.w $wtemp[1], $rtemp2
3628 // insert.w $wtemp[3], $rtemp2
3629 // fexdo.w $wtemp2, $wtemp, $wtemp
3630 // fexdo.h $wd, $temp2, $temp2
3631 //
3632 // For FGR64Opnd on mips64r2+:
3633 //
3634 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3635 // =>
3636 // dmfc1 $rtemp, $fs
3637 // fill.d $rtemp, $wtemp
3638 // fexdo.w $wtemp2, $wtemp, $wtemp
3639 // fexdo.h $wd, $wtemp2, $wtemp2
3640 //
3641 // Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3642 // undef bits are "just right" and the exception enable bits are
3643 // set. By using fill.w to replicate $fs into all elements over
3644 // insert.w for one element, we avoid that potiential case. If
3645 // fexdo.[hw] causes an exception in, the exception is valid and it
3646 // occurs for all elements.
3648 MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3649  MachineBasicBlock *BB,
3650  bool IsFGR64) const {
3651 
3652  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3653  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3654  // it.
3656 
3657  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3658  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3659 
3661  DebugLoc DL = MI.getDebugLoc();
3662  Register Wd = MI.getOperand(0).getReg();
3663  Register Fs = MI.getOperand(1).getReg();
3664 
3665  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3666  Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3667  const TargetRegisterClass *GPRRC =
3668  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3669  unsigned MFC1Opc = IsFGR64onMips64
3670  ? Mips::DMFC1
3671  : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3672  unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3673 
3674  // Perform the register class copy as mentioned above.
3675  Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
3676  BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3677  BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3678  unsigned WPHI = Wtemp;
3679 
3680  if (IsFGR64onMips32) {
3681  Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3682  BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3683  Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3684  Register Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3685  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3686  .addReg(Wtemp)
3687  .addReg(Rtemp2)
3688  .addImm(1);
3689  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3690  .addReg(Wtemp2)
3691  .addReg(Rtemp2)
3692  .addImm(3);
3693  WPHI = Wtemp3;
3694  }
3695 
3696  if (IsFGR64) {
3697  Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3698  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3699  .addReg(WPHI)
3700  .addReg(WPHI);
3701  WPHI = Wtemp2;
3702  }
3703 
3704  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3705 
3706  MI.eraseFromParent();
3707  return BB;
3708 }
3709 
3710 // Emit the FPEXTEND_PSEUDO instruction.
3711 //
3712 // Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3713 //
3714 // Safety: Cycle the result through the GPRs so the result always ends up
3715 // the correct floating point register.
3716 //
3717 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3718 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3719 // (which they can be, as the MSA registers are defined to alias the
3720 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3721 // the correct register class. That requires operands be tie-able across
3722 // register classes which have a sub/super register class relationship. I
3723 // haven't checked.
3724 //
3725 // For FGR32Opnd:
3726 //
3727 // FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3728 // =>
3729 // fexupr.w $wtemp, $ws
3730 // copy_s.w $rtemp, $ws[0]
3731 // mtc1 $rtemp, $fd
3732 //
3733 // For FGR64Opnd on Mips64:
3734 //
3735 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3736 // =>
3737 // fexupr.w $wtemp, $ws
3738 // fexupr.d $wtemp2, $wtemp
3739 // copy_s.d $rtemp, $wtemp2s[0]
3740 // dmtc1 $rtemp, $fd
3741 //
3742 // For FGR64Opnd on Mips32:
3743 //
3744 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3745 // =>
3746 // fexupr.w $wtemp, $ws
3747 // fexupr.d $wtemp2, $wtemp
3748 // copy_s.w $rtemp, $wtemp2[0]
3749 // mtc1 $rtemp, $ftemp
3750 // copy_s.w $rtemp2, $wtemp2[1]
3751 // $fd = mthc1 $rtemp2, $ftemp
3753 MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3754  MachineBasicBlock *BB,
3755  bool IsFGR64) const {
3756 
3757  // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3758  // here. It's technically doable to support MIPS32 here, but the ISA forbids
3759  // it.
3761 
3762  bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3763  bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3764 
3766  DebugLoc DL = MI.getDebugLoc();
3767  Register Fd = MI.getOperand(0).getReg();
3768  Register Ws = MI.getOperand(1).getReg();
3769 
3770  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3771  const TargetRegisterClass *GPRRC =
3772  IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3773  unsigned MTC1Opc = IsFGR64onMips64
3774  ? Mips::DMTC1
3775  : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3776  Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3777 
3778  Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3779  Register WPHI = Wtemp;
3780 
3781  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3782  if (IsFGR64) {
3783  WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3784  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3785  }
3786 
3787  // Perform the safety regclass copy mentioned above.
3788  Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
3789  Register FPRPHI = IsFGR64onMips32
3790  ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3791  : Fd;
3792  BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3793  BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3794 
3795  if (IsFGR64onMips32) {
3796  Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3797  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3798  .addReg(WPHI)
3799  .addImm(1);
3800  BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3801  .addReg(FPRPHI)
3802  .addReg(Rtemp2);
3803  }
3804 
3805  MI.eraseFromParent();
3806  return BB;
3807 }
3808 
3809 // Emit the FEXP2_W_1 pseudo instructions.
3810 //
3811 // fexp2_w_1_pseudo $wd, $wt
3812 // =>
3813 // ldi.w $ws, 1
3814 // fexp2.w $wd, $ws, $wt
3816 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
3817  MachineBasicBlock *BB) const {
3819  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3820  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3821  Register Ws1 = RegInfo.createVirtualRegister(RC);
3822  Register Ws2 = RegInfo.createVirtualRegister(RC);
3823  DebugLoc DL = MI.getDebugLoc();
3824 
3825  // Splat 1.0 into a vector
3826  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3827  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3828 
3829  // Emit 1.0 * fexp2(Wt)
3830  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3831  .addReg(Ws2)
3832  .addReg(MI.getOperand(1).getReg());
3833 
3834  MI.eraseFromParent(); // The pseudo instruction is gone now.
3835  return BB;
3836 }
3837 
3838 // Emit the FEXP2_D_1 pseudo instructions.
3839 //
3840 // fexp2_d_1_pseudo $wd, $wt
3841 // =>
3842 // ldi.d $ws, 1
3843 // fexp2.d $wd, $ws, $wt
3845 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
3846  MachineBasicBlock *BB) const {
3848  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3849  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3850  Register Ws1 = RegInfo.createVirtualRegister(RC);
3851  Register Ws2 = RegInfo.createVirtualRegister(RC);
3852  DebugLoc DL = MI.getDebugLoc();
3853 
3854  // Splat 1.0 into a vector
3855  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3856  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3857 
3858  // Emit 1.0 * fexp2(Wt)
3859  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3860  .addReg(Ws2)
3861  .addReg(MI.getOperand(1).getReg());
3862 
3863  MI.eraseFromParent(); // The pseudo instruction is gone now.
3864  return BB;
3865 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:143
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
const MachineInstrBuilder & add(const MachineOperand &MO) const
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
EVT getValueType() const
Return the ValueType of the referenced return value.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1569
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:959
const MipsSubtarget & Subtarget
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
This class represents lattice values for constants.
Definition: AllocatorList.h:23
value_iterator value_end() const
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:633
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:398
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const SDValue & getBasePtr() const
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
const SDValue & getValue() const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
SDVTList getVTList() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:647
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
const MipsInstrInfo * getInstrInfo() const override
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
const SDValue & getChain() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isABI_O32() const
unsigned getAlignment() const
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:813
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:415
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:812
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:466
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1515
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const
Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
const Triple & getTargetTriple() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool hasMips64() const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool hasDSPR2() const
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
Shift and rotation operations.
Definition: ISDOpcodes.h:441
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getScalarValueSizeInBits() const
bool isGP64bit() const
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
bool hasMips32r6() const
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
unsigned Intr
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:413
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
This file implements a class to represent arbitrary precision integral constant values and operations...
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:509
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:460
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
static bool isConstantOrUndef(const SDValue Op)
unsigned getIncomingArgSize() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:874
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1012
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:124
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:592
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
UNDEF - An undefined node.
Definition: ISDOpcodes.h:177
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:555
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:358
TargetInstrInfo - Interface to description of machine instruction set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:635
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
Definition: Metadata.h:1165
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:363
const SDValue & getBasePtr() const
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:395
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Machine Value Type.
bool isLittleEndian() const
Tests whether the target triple is little endian.
Definition: Triple.cpp:1518
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const SDValue & getOperand(unsigned Num) const
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:363
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
const APInt & getAPIntValue() const
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static mvt_range vector_valuetypes()
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:580
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)
Extended Value Type.
Definition: ValueTypes.h:33
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
bool isSingleFloat() const
unsigned ceilLogBase2() const
Definition: APInt.h:1757
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
bool hasMips64r6() const
This class contains a discriminated union of information about pointers in memory operands...
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:970
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:416
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG)
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
bool isLittle() const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:552
const MipsRegisterInfo * getRegisterInfo() const override
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:370
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
value_iterator value_begin() const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
Definition: SelectionDAG.h:746
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
bool hasCnMips() const
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:95
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:672
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Represents one node in the SelectionDAG.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
int64_t getImm() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool hasDSP() const
unsigned logBase2() const
Definition: APInt.h:1754
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG)
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:451
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
bool isPowerOf2() const
Check if this APInt&#39;s value is a power of two greater than zero.
Definition: APInt.h:463
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:499
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:343
int getMaskElt(unsigned Idx) const
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
Flags
Flags values. These may be or&#39;d together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:418
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool is128BitVector() const
Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:181
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:642
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the &#39;representative&#39; register class for the specified value type.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:415
Definition: