LLVM  8.0.0svn
PPCISelLowering.cpp
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1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCISelLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCISelLowering.h"
16 #include "PPC.h"
17 #include "PPCCCState.h"
18 #include "PPCCallingConv.h"
19 #include "PPCFrameLowering.h"
20 #include "PPCInstrInfo.h"
21 #include "PPCMachineFunctionInfo.h"
22 #include "PPCPerfectShuffle.h"
23 #include "PPCRegisterInfo.h"
24 #include "PPCSubtarget.h"
25 #include "PPCTargetMachine.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/None.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/StringRef.h"
37 #include "llvm/ADT/StringSwitch.h"
57 #include "llvm/IR/CallSite.h"
58 #include "llvm/IR/CallingConv.h"
59 #include "llvm/IR/Constant.h"
60 #include "llvm/IR/Constants.h"
61 #include "llvm/IR/DataLayout.h"
62 #include "llvm/IR/DebugLoc.h"
63 #include "llvm/IR/DerivedTypes.h"
64 #include "llvm/IR/Function.h"
65 #include "llvm/IR/GlobalValue.h"
66 #include "llvm/IR/IRBuilder.h"
67 #include "llvm/IR/Instructions.h"
68 #include "llvm/IR/Intrinsics.h"
69 #include "llvm/IR/Module.h"
70 #include "llvm/IR/Type.h"
71 #include "llvm/IR/Use.h"
72 #include "llvm/IR/Value.h"
73 #include "llvm/MC/MCExpr.h"
74 #include "llvm/MC/MCRegisterInfo.h"
77 #include "llvm/Support/Casting.h"
78 #include "llvm/Support/CodeGen.h"
80 #include "llvm/Support/Compiler.h"
81 #include "llvm/Support/Debug.h"
83 #include "llvm/Support/Format.h"
84 #include "llvm/Support/KnownBits.h"
90 #include <algorithm>
91 #include <cassert>
92 #include <cstdint>
93 #include <iterator>
94 #include <list>
95 #include <utility>
96 #include <vector>
97 
98 using namespace llvm;
99 
100 #define DEBUG_TYPE "ppc-lowering"
101 
102 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
103 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
104 
105 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
106 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
107 
108 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
109 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
110 
111 static cl::opt<bool> DisableSCO("disable-ppc-sco",
112 cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
113 
114 static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
115 cl::desc("enable quad precision float support on ppc"), cl::Hidden);
116 
117 STATISTIC(NumTailCalls, "Number of tail calls");
118 STATISTIC(NumSiblingCalls, "Number of sibling calls");
119 
120 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
121 
122 // FIXME: Remove this once the bug has been fixed!
124 
126  const PPCSubtarget &STI)
127  : TargetLowering(TM), Subtarget(STI) {
128  // Use _setjmp/_longjmp instead of setjmp/longjmp.
131 
132  // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
133  // arguments are at least 4/8 bytes aligned.
134  bool isPPC64 = Subtarget.isPPC64();
135  setMinStackArgumentAlignment(isPPC64 ? 8:4);
136 
137  // Set up the register classes.
138  addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
139  if (!useSoftFloat()) {
140  if (hasSPE()) {
141  addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass);
142  addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
143  } else {
144  addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
145  addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
146  }
147  }
148 
149  // Match BITREVERSE to customized fast code sequence in the td file.
152 
153  // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
155 
156  // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
157  for (MVT VT : MVT::integer_valuetypes()) {
160  }
161 
163 
164  // PowerPC has pre-inc load and store's.
175  if (!Subtarget.hasSPE()) {
180  }
181 
182  // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
183  const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
184  for (MVT VT : ScalarIntVTs) {
189  }
190 
191  if (Subtarget.useCRBits()) {
193 
194  if (isPPC64 || Subtarget.hasFPCVT()) {
197  isPPC64 ? MVT::i64 : MVT::i32);
200  isPPC64 ? MVT::i64 : MVT::i32);
201  } else {
204  }
205 
206  // PowerPC does not support direct load/store of condition registers.
209 
210  // FIXME: Remove this once the ANDI glue bug is fixed:
211  if (ANDIGlueBug)
213 
214  for (MVT VT : MVT::integer_valuetypes()) {
218  }
219 
220  addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
221  }
222 
223  // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
224  // PPC (the libcall is not available).
227 
228  // We do not currently implement these libm ops for PowerPC.
235 
236  // PowerPC has no SREM/UREM instructions unless we are on P9
237  // On P9 we may use a hardware instruction to compute the remainder.
238  // The instructions are not legalized directly because in the cases where the
239  // result of both the remainder and the division is required it is more
240  // efficient to compute the remainder from the result of the division rather
241  // than use the remainder instruction.
242  if (Subtarget.isISA3_0()) {
245  setOperationAction(ISD::SREM, MVT::i64, Custom);
246  setOperationAction(ISD::UREM, MVT::i64, Custom);
247  } else {
250  setOperationAction(ISD::SREM, MVT::i64, Expand);
251  setOperationAction(ISD::UREM, MVT::i64, Expand);
252  }
253 
254  if (Subtarget.hasP9Vector()) {
258  }
259 
260  // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
269 
270  // We don't support sin/cos/sqrt/fmod/pow
281  if (Subtarget.hasSPE()) {
284  } else {
287  }
288 
290 
291  // If we're enabling GP optimizations, use hardware square root
292  if (!Subtarget.hasFSQRT() &&
293  !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
294  Subtarget.hasFRE()))
296 
297  if (!Subtarget.hasFSQRT() &&
298  !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
299  Subtarget.hasFRES()))
301 
302  if (Subtarget.hasFCPSGN()) {
305  } else {
308  }
309 
310  if (Subtarget.hasFPRND()) {
315 
320  }
321 
322  // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
323  // to speed up scalar BSWAP64.
324  // CTPOP or CTTZ were introduced in P8/P9 respectively
326  if (Subtarget.hasP9Vector())
327  setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
328  else
329  setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
330  if (Subtarget.isISA3_0()) {
332  setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
333  } else {
335  setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
336  }
337 
338  if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
340  setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
341  } else {
343  setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
344  }
345 
346  // PowerPC does not have ROTR
348  setOperationAction(ISD::ROTR, MVT::i64 , Expand);
349 
350  if (!Subtarget.useCRBits()) {
351  // PowerPC does not have Select
356  }
357 
358  // PowerPC wants to turn select_cc of FP into fsel when possible.
361 
362  // PowerPC wants to optimize integer setcc a bit
363  if (!Subtarget.useCRBits())
365 
366  // PowerPC does not have BRCOND which requires SetCC
367  if (!Subtarget.useCRBits())
369 
371 
372  if (Subtarget.hasSPE()) {
373  // SPE has built-in conversions
377  } else {
378  // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
380 
381  // PowerPC does not have [U|S]INT_TO_FP
384  }
385 
386  if (Subtarget.hasDirectMove() && isPPC64) {
391  } else {
396  }
397 
398  // We cannot sextinreg(i1). Expand to shifts.
400 
401  // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
402  // SjLj exception handling but a light-weight setjmp/longjmp replacement to
403  // support continuation, user-level threading, and etc.. As a result, no
404  // other SjLj exception interfaces are implemented and please don't build
405  // your own exception handling based on them.
406  // LLVM/Clang supports zero-cost DWARF exception handling.
409 
410  // We want to legalize GlobalAddress and ConstantPool nodes into the
411  // appropriate instructions to materialize the address.
422 
423  // TRAP is legal.
425 
426  // TRAMPOLINE is custom lowered.
429 
430  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
432 
433  if (Subtarget.isSVR4ABI()) {
434  if (isPPC64) {
435  // VAARG always uses double-word chunks, so promote anything smaller.
437  AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
439  AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
445  } else {
446  // VAARG is custom lowered with the 32-bit SVR4 ABI.
449  }
450  } else
452 
453  if (Subtarget.isSVR4ABI() && !isPPC64)
454  // VACOPY is custom lowered with the 32-bit SVR4 ABI.
456  else
458 
459  // Use the default implementation.
469 
470  // We want to custom lower some of our intrinsics.
472 
473  // To handle counter-based loop conditions.
475 
480 
481  // Comparisons that require checking two conditions.
482  if (Subtarget.hasSPE()) {
487  }
500 
501  if (Subtarget.has64BitSupport()) {
502  // They also have instructions for converting between i64 and fp.
507  // This is just the low 32 bits of a (signed) fp->i64 conversion.
508  // We cannot do this with Promote because i64 is not a legal type.
510 
511  if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
513  } else {
514  // PowerPC does not have FP_TO_UINT on 32-bit implementations.
515  if (Subtarget.hasSPE())
517  else
519  }
520 
521  // With the instructions enabled under FPCVT, we can do everything.
522  if (Subtarget.hasFPCVT()) {
523  if (Subtarget.has64BitSupport()) {
528  }
529 
534  }
535 
536  if (Subtarget.use64BitRegs()) {
537  // 64-bit PowerPC implementations can support i64 types directly
538  addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
539  // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
541  // 64-bit PowerPC wants to expand i128 shifts itself.
545  } else {
546  // 32-bit PowerPC wants to expand i64 shifts itself.
550  }
551 
552  if (Subtarget.hasAltivec()) {
553  // First set operation action for all vector types to expand. Then we
554  // will selectively turn on ones that can be effectively codegen'd.
555  for (MVT VT : MVT::vector_valuetypes()) {
556  // add/sub are legal for all supported vector VT's.
559 
560  // Vector instructions introduced in P8
561  if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
564  }
565  else {
568  }
569 
570  // Vector instructions introduced in P9
571  if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
573  else
575 
576  // We promote all shuffles to v16i8.
579 
580  // We promote all non-typed operations to v4i32.
596 
597  // No other operations are legal.
635 
636  for (MVT InnerVT : MVT::vector_valuetypes()) {
637  setTruncStoreAction(VT, InnerVT, Expand);
638  setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
639  setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
640  setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
641  }
642  }
643 
644  // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
645  // with merges, splats, etc.
647 
653  Subtarget.useCRBits() ? Legal : Expand);
663 
664  addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
665  addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
666  addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
667  addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
668 
671 
672  if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
675  }
676 
677  if (Subtarget.hasP8Altivec())
679  else
681 
684 
687 
692 
693  // Altivec does not contain unordered floating-point compare instructions
698 
699  if (Subtarget.hasVSX()) {
702  if (Subtarget.hasP8Vector()) {
705  }
706  if (Subtarget.hasDirectMove() && isPPC64) {
715  }
717 
723 
725 
728 
731 
732  // Share the Altivec comparison restrictions.
737 
740 
742 
743  if (Subtarget.hasP8Vector())
744  addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
745 
746  addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
747 
748  addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
749  addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
750  addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
751 
752  if (Subtarget.hasP8Altivec()) {
756 
757  // 128 bit shifts can be accomplished via 3 instructions for SHL and
758  // SRL, but not for SRA because of the instructions available:
759  // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
760  // doing
764 
766  }
767  else {
771 
773 
774  // VSX v2i64 only supports non-arithmetic operations.
777  }
778 
783 
785 
790 
793 
798 
799  if (Subtarget.hasDirectMove())
802 
803  addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
804  }
805 
806  if (Subtarget.hasP8Altivec()) {
807  addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
808  addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
809  }
810 
811  if (Subtarget.hasP9Vector()) {
814 
815  // 128 bit shifts can be accomplished via 3 instructions for SHL and
816  // SRL, but not for SRA because of the instructions available:
817  // VS{RL} and VS{RL}O.
821 
822  if (EnableQuadPrecision) {
823  addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
829  // No extending loads to f128 on PPC.
830  for (MVT FPT : MVT::fp_valuetypes())
839 
846 
853  // No implementation for these ops for PowerPC.
859  }
860 
861  }
862 
863  if (Subtarget.hasP9Altivec()) {
866  }
867  }
868 
869  if (Subtarget.hasQPX()) {
874 
877 
880 
883 
884  if (!Subtarget.useCRBits())
887 
895 
898 
902 
913 
916 
919 
920  addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
921 
926 
929 
932 
933  if (!Subtarget.useCRBits())
936 
944 
947 
958 
961 
964 
965  addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
966 
970 
971  if (!Subtarget.useCRBits())
974 
977 
985 
988 
989  addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
990 
995 
1000 
1003 
1004  // These need to set FE_INEXACT, and so cannot be vectorized here.
1007 
1008  if (TM.Options.UnsafeFPMath) {
1011 
1014  } else {
1017 
1020  }
1021  }
1022 
1023  if (Subtarget.has64BitSupport())
1025 
1026  setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1027 
1028  if (!isPPC64) {
1031  }
1032 
1034 
1035  if (Subtarget.hasAltivec()) {
1036  // Altivec instructions set fields to all zeros or all ones.
1038  }
1039 
1040  if (!isPPC64) {
1041  // These libcalls are not available in 32-bit.
1042  setLibcallName(RTLIB::SHL_I128, nullptr);
1043  setLibcallName(RTLIB::SRL_I128, nullptr);
1044  setLibcallName(RTLIB::SRA_I128, nullptr);
1045  }
1046 
1047  setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1048 
1049  // We have target-specific dag combine patterns for the following nodes:
1056  if (Subtarget.hasFPCVT())
1061  if (Subtarget.useCRBits())
1067 
1071 
1073 
1074  if (Subtarget.useCRBits()) {
1078  }
1079 
1080  // Use reciprocal estimates.
1081  if (TM.Options.UnsafeFPMath) {
1084  }
1085 
1086  // Darwin long double math library functions have $LDBL128 appended.
1087  if (Subtarget.isDarwin()) {
1088  setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
1089  setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
1090  setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
1091  setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
1092  setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
1093  setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
1094  setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
1095  setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
1096  setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
1097  setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
1098  }
1099 
1100  if (EnableQuadPrecision) {
1101  setLibcallName(RTLIB::LOG_F128, "logf128");
1102  setLibcallName(RTLIB::LOG2_F128, "log2f128");
1103  setLibcallName(RTLIB::LOG10_F128, "log10f128");
1104  setLibcallName(RTLIB::EXP_F128, "expf128");
1105  setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1106  setLibcallName(RTLIB::SIN_F128, "sinf128");
1107  setLibcallName(RTLIB::COS_F128, "cosf128");
1108  setLibcallName(RTLIB::POW_F128, "powf128");
1109  setLibcallName(RTLIB::FMIN_F128, "fminf128");
1110  setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1111  setLibcallName(RTLIB::POWI_F128, "__powikf2");
1112  setLibcallName(RTLIB::REM_F128, "fmodf128");
1113  }
1114 
1115  // With 32 condition bits, we don't need to sink (and duplicate) compares
1116  // aggressively in CodeGenPrep.
1117  if (Subtarget.useCRBits()) {
1120  }
1121 
1123  if (Subtarget.isDarwin())
1125 
1126  switch (Subtarget.getDarwinDirective()) {
1127  default: break;
1128  case PPC::DIR_970:
1129  case PPC::DIR_A2:
1130  case PPC::DIR_E500:
1131  case PPC::DIR_E500mc:
1132  case PPC::DIR_E5500:
1133  case PPC::DIR_PWR4:
1134  case PPC::DIR_PWR5:
1135  case PPC::DIR_PWR5X:
1136  case PPC::DIR_PWR6:
1137  case PPC::DIR_PWR6X:
1138  case PPC::DIR_PWR7:
1139  case PPC::DIR_PWR8:
1140  case PPC::DIR_PWR9:
1143  break;
1144  }
1145 
1146  if (Subtarget.enableMachineScheduler())
1148  else
1150 
1152 
1153  // The Freescale cores do better with aggressive inlining of memcpy and
1154  // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1155  if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
1156  Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
1157  MaxStoresPerMemset = 32;
1159  MaxStoresPerMemcpy = 32;
1161  MaxStoresPerMemmove = 32;
1163  } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
1164  // The A2 also benefits from (very) aggressive inlining of memcpy and
1165  // friends. The overhead of a the function call, even when warm, can be
1166  // over one hundred cycles.
1167  MaxStoresPerMemset = 128;
1168  MaxStoresPerMemcpy = 128;
1169  MaxStoresPerMemmove = 128;
1170  MaxLoadsPerMemcmp = 128;
1171  } else {
1172  MaxLoadsPerMemcmp = 8;
1174  }
1175 }
1176 
1177 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1178 /// the desired ByVal argument alignment.
1179 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
1180  unsigned MaxMaxAlign) {
1181  if (MaxAlign == MaxMaxAlign)
1182  return;
1183  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1184  if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
1185  MaxAlign = 32;
1186  else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
1187  MaxAlign = 16;
1188  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1189  unsigned EltAlign = 0;
1190  getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1191  if (EltAlign > MaxAlign)
1192  MaxAlign = EltAlign;
1193  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1194  for (auto *EltTy : STy->elements()) {
1195  unsigned EltAlign = 0;
1196  getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1197  if (EltAlign > MaxAlign)
1198  MaxAlign = EltAlign;
1199  if (MaxAlign == MaxMaxAlign)
1200  break;
1201  }
1202  }
1203 }
1204 
1205 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1206 /// function arguments in the caller parameter area.
1208  const DataLayout &DL) const {
1209  // Darwin passes everything on 4 byte boundary.
1210  if (Subtarget.isDarwin())
1211  return 4;
1212 
1213  // 16byte and wider vectors are passed on 16byte boundary.
1214  // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1215  unsigned Align = Subtarget.isPPC64() ? 8 : 4;
1216  if (Subtarget.hasAltivec() || Subtarget.hasQPX())
1217  getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
1218  return Align;
1219 }
1220 
1222  CallingConv:: ID CC,
1223  EVT VT) const {
1224  if (Subtarget.hasSPE() && VT == MVT::f64)
1225  return 2;
1226  return PPCTargetLowering::getNumRegisters(Context, VT);
1227 }
1228 
1230  CallingConv:: ID CC,
1231  EVT VT) const {
1232  if (Subtarget.hasSPE() && VT == MVT::f64)
1233  return MVT::i32;
1234  return PPCTargetLowering::getRegisterType(Context, VT);
1235 }
1236 
1238  return Subtarget.useSoftFloat();
1239 }
1240 
1242  return Subtarget.hasSPE();
1243 }
1244 
1245 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1246  switch ((PPCISD::NodeType)Opcode) {
1247  case PPCISD::FIRST_NUMBER: break;
1248  case PPCISD::FSEL: return "PPCISD::FSEL";
1249  case PPCISD::FCFID: return "PPCISD::FCFID";
1250  case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1251  case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1252  case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1253  case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1254  case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1255  case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1256  case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1258  return "PPCISD::FP_TO_UINT_IN_VSR,";
1260  return "PPCISD::FP_TO_SINT_IN_VSR";
1261  case PPCISD::FRE: return "PPCISD::FRE";
1262  case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1263  case PPCISD::STFIWX: return "PPCISD::STFIWX";
1264  case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1265  case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1266  case PPCISD::VPERM: return "PPCISD::VPERM";
1267  case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1268  case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1269  case PPCISD::XXREVERSE: return "PPCISD::XXREVERSE";
1270  case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1271  case PPCISD::VECSHL: return "PPCISD::VECSHL";
1272  case PPCISD::CMPB: return "PPCISD::CMPB";
1273  case PPCISD::Hi: return "PPCISD::Hi";
1274  case PPCISD::Lo: return "PPCISD::Lo";
1275  case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1276  case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1277  case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1278  case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1279  case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1280  case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1281  case PPCISD::SRL: return "PPCISD::SRL";
1282  case PPCISD::SRA: return "PPCISD::SRA";
1283  case PPCISD::SHL: return "PPCISD::SHL";
1284  case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1285  case PPCISD::CALL: return "PPCISD::CALL";
1286  case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1287  case PPCISD::MTCTR: return "PPCISD::MTCTR";
1288  case PPCISD::BCTRL: return "PPCISD::BCTRL";
1289  case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1290  case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1291  case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1292  case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1293  case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1294  case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1295  case PPCISD::MFVSR: return "PPCISD::MFVSR";
1296  case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1297  case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1298  case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1299  case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1300  case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1301  case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1302  case PPCISD::VCMP: return "PPCISD::VCMP";
1303  case PPCISD::VCMPo: return "PPCISD::VCMPo";
1304  case PPCISD::LBRX: return "PPCISD::LBRX";
1305  case PPCISD::STBRX: return "PPCISD::STBRX";
1306  case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1307  case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1308  case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1309  case PPCISD::STXSIX: return "PPCISD::STXSIX";
1310  case PPCISD::VEXTS: return "PPCISD::VEXTS";
1311  case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
1312  case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1313  case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1315  return "PPCISD::ST_VSR_SCAL_INT";
1316  case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1317  case PPCISD::BDNZ: return "PPCISD::BDNZ";
1318  case PPCISD::BDZ: return "PPCISD::BDZ";
1319  case PPCISD::MFFS: return "PPCISD::MFFS";
1320  case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1321  case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1322  case PPCISD::CR6SET: return "PPCISD::CR6SET";
1323  case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1324  case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1325  case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1326  case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1327  case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1328  case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1329  case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1330  case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1331  case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1332  case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1333  case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1334  case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1335  case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1336  case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1337  case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1338  case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1339  case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1340  case PPCISD::SC: return "PPCISD::SC";
1341  case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1342  case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1343  case PPCISD::RFEBB: return "PPCISD::RFEBB";
1344  case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1345  case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1346  case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1347  case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1348  case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1349  case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1350  case PPCISD::QBFLT: return "PPCISD::QBFLT";
1351  case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1352  case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1353  case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1354  }
1355  return nullptr;
1356 }
1357 
1359  EVT VT) const {
1360  if (!VT.isVector())
1361  return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1362 
1363  if (Subtarget.hasQPX())
1365 
1367 }
1368 
1370  assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1371  return true;
1372 }
1373 
1374 //===----------------------------------------------------------------------===//
1375 // Node matching predicates, for use by the tblgen matching code.
1376 //===----------------------------------------------------------------------===//
1377 
1378 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1380  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1381  return CFP->getValueAPF().isZero();
1382  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1383  // Maybe this has already been legalized into the constant pool?
1384  if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1385  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1386  return CFP->getValueAPF().isZero();
1387  }
1388  return false;
1389 }
1390 
1391 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1392 /// true if Op is undef or if it matches the specified value.
1393 static bool isConstantOrUndef(int Op, int Val) {
1394  return Op < 0 || Op == Val;
1395 }
1396 
1397 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1398 /// VPKUHUM instruction.
1399 /// The ShuffleKind distinguishes between big-endian operations with
1400 /// two different inputs (0), either-endian operations with two identical
1401 /// inputs (1), and little-endian operations with two different inputs (2).
1402 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1404  SelectionDAG &DAG) {
1405  bool IsLE = DAG.getDataLayout().isLittleEndian();
1406  if (ShuffleKind == 0) {
1407  if (IsLE)
1408  return false;
1409  for (unsigned i = 0; i != 16; ++i)
1410  if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1411  return false;
1412  } else if (ShuffleKind == 2) {
1413  if (!IsLE)
1414  return false;
1415  for (unsigned i = 0; i != 16; ++i)
1416  if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1417  return false;
1418  } else if (ShuffleKind == 1) {
1419  unsigned j = IsLE ? 0 : 1;
1420  for (unsigned i = 0; i != 8; ++i)
1421  if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1422  !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1423  return false;
1424  }
1425  return true;
1426 }
1427 
1428 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1429 /// VPKUWUM instruction.
1430 /// The ShuffleKind distinguishes between big-endian operations with
1431 /// two different inputs (0), either-endian operations with two identical
1432 /// inputs (1), and little-endian operations with two different inputs (2).
1433 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1435  SelectionDAG &DAG) {
1436  bool IsLE = DAG.getDataLayout().isLittleEndian();
1437  if (ShuffleKind == 0) {
1438  if (IsLE)
1439  return false;
1440  for (unsigned i = 0; i != 16; i += 2)
1441  if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1442  !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1443  return false;
1444  } else if (ShuffleKind == 2) {
1445  if (!IsLE)
1446  return false;
1447  for (unsigned i = 0; i != 16; i += 2)
1448  if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1449  !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1450  return false;
1451  } else if (ShuffleKind == 1) {
1452  unsigned j = IsLE ? 0 : 2;
1453  for (unsigned i = 0; i != 8; i += 2)
1454  if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1455  !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1456  !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1457  !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1458  return false;
1459  }
1460  return true;
1461 }
1462 
1463 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1464 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1465 /// current subtarget.
1466 ///
1467 /// The ShuffleKind distinguishes between big-endian operations with
1468 /// two different inputs (0), either-endian operations with two identical
1469 /// inputs (1), and little-endian operations with two different inputs (2).
1470 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1472  SelectionDAG &DAG) {
1473  const PPCSubtarget& Subtarget =
1474  static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1475  if (!Subtarget.hasP8Vector())
1476  return false;
1477 
1478  bool IsLE = DAG.getDataLayout().isLittleEndian();
1479  if (ShuffleKind == 0) {
1480  if (IsLE)
1481  return false;
1482  for (unsigned i = 0; i != 16; i += 4)
1483  if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1484  !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1485  !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1486  !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1487  return false;
1488  } else if (ShuffleKind == 2) {
1489  if (!IsLE)
1490  return false;
1491  for (unsigned i = 0; i != 16; i += 4)
1492  if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1493  !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1494  !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1495  !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1496  return false;
1497  } else if (ShuffleKind == 1) {
1498  unsigned j = IsLE ? 0 : 4;
1499  for (unsigned i = 0; i != 8; i += 4)
1500  if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1501  !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1502  !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1503  !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1504  !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1505  !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1506  !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1507  !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1508  return false;
1509  }
1510  return true;
1511 }
1512 
1513 /// isVMerge - Common function, used to match vmrg* shuffles.
1514 ///
1515 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1516  unsigned LHSStart, unsigned RHSStart) {
1517  if (N->getValueType(0) != MVT::v16i8)
1518  return false;
1519  assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1520  "Unsupported merge size!");
1521 
1522  for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1523  for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1524  if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1525  LHSStart+j+i*UnitSize) ||
1526  !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1527  RHSStart+j+i*UnitSize))
1528  return false;
1529  }
1530  return true;
1531 }
1532 
1533 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1534 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1535 /// The ShuffleKind distinguishes between big-endian merges with two
1536 /// different inputs (0), either-endian merges with two identical inputs (1),
1537 /// and little-endian merges with two different inputs (2). For the latter,
1538 /// the input operands are swapped (see PPCInstrAltivec.td).
1540  unsigned ShuffleKind, SelectionDAG &DAG) {
1541  if (DAG.getDataLayout().isLittleEndian()) {
1542  if (ShuffleKind == 1) // unary
1543  return isVMerge(N, UnitSize, 0, 0);
1544  else if (ShuffleKind == 2) // swapped
1545  return isVMerge(N, UnitSize, 0, 16);
1546  else
1547  return false;
1548  } else {
1549  if (ShuffleKind == 1) // unary
1550  return isVMerge(N, UnitSize, 8, 8);
1551  else if (ShuffleKind == 0) // normal
1552  return isVMerge(N, UnitSize, 8, 24);
1553  else
1554  return false;
1555  }
1556 }
1557 
1558 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1559 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1560 /// The ShuffleKind distinguishes between big-endian merges with two
1561 /// different inputs (0), either-endian merges with two identical inputs (1),
1562 /// and little-endian merges with two different inputs (2). For the latter,
1563 /// the input operands are swapped (see PPCInstrAltivec.td).
1565  unsigned ShuffleKind, SelectionDAG &DAG) {
1566  if (DAG.getDataLayout().isLittleEndian()) {
1567  if (ShuffleKind == 1) // unary
1568  return isVMerge(N, UnitSize, 8, 8);
1569  else if (ShuffleKind == 2) // swapped
1570  return isVMerge(N, UnitSize, 8, 24);
1571  else
1572  return false;
1573  } else {
1574  if (ShuffleKind == 1) // unary
1575  return isVMerge(N, UnitSize, 0, 0);
1576  else if (ShuffleKind == 0) // normal
1577  return isVMerge(N, UnitSize, 0, 16);
1578  else
1579  return false;
1580  }
1581 }
1582 
1583 /**
1584  * Common function used to match vmrgew and vmrgow shuffles
1585  *
1586  * The indexOffset determines whether to look for even or odd words in
1587  * the shuffle mask. This is based on the of the endianness of the target
1588  * machine.
1589  * - Little Endian:
1590  * - Use offset of 0 to check for odd elements
1591  * - Use offset of 4 to check for even elements
1592  * - Big Endian:
1593  * - Use offset of 0 to check for even elements
1594  * - Use offset of 4 to check for odd elements
1595  * A detailed description of the vector element ordering for little endian and
1596  * big endian can be found at
1597  * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1598  * Targeting your applications - what little endian and big endian IBM XL C/C++
1599  * compiler differences mean to you
1600  *
1601  * The mask to the shuffle vector instruction specifies the indices of the
1602  * elements from the two input vectors to place in the result. The elements are
1603  * numbered in array-access order, starting with the first vector. These vectors
1604  * are always of type v16i8, thus each vector will contain 16 elements of size
1605  * 8. More info on the shuffle vector can be found in the
1606  * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1607  * Language Reference.
1608  *
1609  * The RHSStartValue indicates whether the same input vectors are used (unary)
1610  * or two different input vectors are used, based on the following:
1611  * - If the instruction uses the same vector for both inputs, the range of the
1612  * indices will be 0 to 15. In this case, the RHSStart value passed should
1613  * be 0.
1614  * - If the instruction has two different vectors then the range of the
1615  * indices will be 0 to 31. In this case, the RHSStart value passed should
1616  * be 16 (indices 0-15 specify elements in the first vector while indices 16
1617  * to 31 specify elements in the second vector).
1618  *
1619  * \param[in] N The shuffle vector SD Node to analyze
1620  * \param[in] IndexOffset Specifies whether to look for even or odd elements
1621  * \param[in] RHSStartValue Specifies the starting index for the righthand input
1622  * vector to the shuffle_vector instruction
1623  * \return true iff this shuffle vector represents an even or odd word merge
1624  */
1625 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1626  unsigned RHSStartValue) {
1627  if (N->getValueType(0) != MVT::v16i8)
1628  return false;
1629 
1630  for (unsigned i = 0; i < 2; ++i)
1631  for (unsigned j = 0; j < 4; ++j)
1632  if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1633  i*RHSStartValue+j+IndexOffset) ||
1634  !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1635  i*RHSStartValue+j+IndexOffset+8))
1636  return false;
1637  return true;
1638 }
1639 
1640 /**
1641  * Determine if the specified shuffle mask is suitable for the vmrgew or
1642  * vmrgow instructions.
1643  *
1644  * \param[in] N The shuffle vector SD Node to analyze
1645  * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1646  * \param[in] ShuffleKind Identify the type of merge:
1647  * - 0 = big-endian merge with two different inputs;
1648  * - 1 = either-endian merge with two identical inputs;
1649  * - 2 = little-endian merge with two different inputs (inputs are swapped for
1650  * little-endian merges).
1651  * \param[in] DAG The current SelectionDAG
1652  * \return true iff this shuffle mask
1653  */
1655  unsigned ShuffleKind, SelectionDAG &DAG) {
1656  if (DAG.getDataLayout().isLittleEndian()) {
1657  unsigned indexOffset = CheckEven ? 4 : 0;
1658  if (ShuffleKind == 1) // Unary
1659  return isVMerge(N, indexOffset, 0);
1660  else if (ShuffleKind == 2) // swapped
1661  return isVMerge(N, indexOffset, 16);
1662  else
1663  return false;
1664  }
1665  else {
1666  unsigned indexOffset = CheckEven ? 0 : 4;
1667  if (ShuffleKind == 1) // Unary
1668  return isVMerge(N, indexOffset, 0);
1669  else if (ShuffleKind == 0) // Normal
1670  return isVMerge(N, indexOffset, 16);
1671  else
1672  return false;
1673  }
1674  return false;
1675 }
1676 
1677 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1678 /// amount, otherwise return -1.
1679 /// The ShuffleKind distinguishes between big-endian operations with two
1680 /// different inputs (0), either-endian operations with two identical inputs
1681 /// (1), and little-endian operations with two different inputs (2). For the
1682 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1683 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1684  SelectionDAG &DAG) {
1685  if (N->getValueType(0) != MVT::v16i8)
1686  return -1;
1687 
1688  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1689 
1690  // Find the first non-undef value in the shuffle mask.
1691  unsigned i;
1692  for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1693  /*search*/;
1694 
1695  if (i == 16) return -1; // all undef.
1696 
1697  // Otherwise, check to see if the rest of the elements are consecutively
1698  // numbered from this value.
1699  unsigned ShiftAmt = SVOp->getMaskElt(i);
1700  if (ShiftAmt < i) return -1;
1701 
1702  ShiftAmt -= i;
1703  bool isLE = DAG.getDataLayout().isLittleEndian();
1704 
1705  if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1706  // Check the rest of the elements to see if they are consecutive.
1707  for (++i; i != 16; ++i)
1708  if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1709  return -1;
1710  } else if (ShuffleKind == 1) {
1711  // Check the rest of the elements to see if they are consecutive.
1712  for (++i; i != 16; ++i)
1713  if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1714  return -1;
1715  } else
1716  return -1;
1717 
1718  if (isLE)
1719  ShiftAmt = 16 - ShiftAmt;
1720 
1721  return ShiftAmt;
1722 }
1723 
1724 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1725 /// specifies a splat of a single element that is suitable for input to
1726 /// VSPLTB/VSPLTH/VSPLTW.
1728  assert(N->getValueType(0) == MVT::v16i8 &&
1729  (EltSize == 1 || EltSize == 2 || EltSize == 4));
1730 
1731  // The consecutive indices need to specify an element, not part of two
1732  // different elements. So abandon ship early if this isn't the case.
1733  if (N->getMaskElt(0) % EltSize != 0)
1734  return false;
1735 
1736  // This is a splat operation if each element of the permute is the same, and
1737  // if the value doesn't reference the second vector.
1738  unsigned ElementBase = N->getMaskElt(0);
1739 
1740  // FIXME: Handle UNDEF elements too!
1741  if (ElementBase >= 16)
1742  return false;
1743 
1744  // Check that the indices are consecutive, in the case of a multi-byte element
1745  // splatted with a v16i8 mask.
1746  for (unsigned i = 1; i != EltSize; ++i)
1747  if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1748  return false;
1749 
1750  for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1751  if (N->getMaskElt(i) < 0) continue;
1752  for (unsigned j = 0; j != EltSize; ++j)
1753  if (N->getMaskElt(i+j) != N->getMaskElt(j))
1754  return false;
1755  }
1756  return true;
1757 }
1758 
1759 /// Check that the mask is shuffling N byte elements. Within each N byte
1760 /// element of the mask, the indices could be either in increasing or
1761 /// decreasing order as long as they are consecutive.
1762 /// \param[in] N the shuffle vector SD Node to analyze
1763 /// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1764 /// Word/DoubleWord/QuadWord).
1765 /// \param[in] StepLen the delta indices number among the N byte element, if
1766 /// the mask is in increasing/decreasing order then it is 1/-1.
1767 /// \return true iff the mask is shuffling N byte elements.
1768 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1769  int StepLen) {
1770  assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
1771  "Unexpected element width.");
1772  assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.");
1773 
1774  unsigned NumOfElem = 16 / Width;
1775  unsigned MaskVal[16]; // Width is never greater than 16
1776  for (unsigned i = 0; i < NumOfElem; ++i) {
1777  MaskVal[0] = N->getMaskElt(i * Width);
1778  if ((StepLen == 1) && (MaskVal[0] % Width)) {
1779  return false;
1780  } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
1781  return false;
1782  }
1783 
1784  for (unsigned int j = 1; j < Width; ++j) {
1785  MaskVal[j] = N->getMaskElt(i * Width + j);
1786  if (MaskVal[j] != MaskVal[j-1] + StepLen) {
1787  return false;
1788  }
1789  }
1790  }
1791 
1792  return true;
1793 }
1794 
1795 bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1796  unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1797  if (!isNByteElemShuffleMask(N, 4, 1))
1798  return false;
1799 
1800  // Now we look at mask elements 0,4,8,12
1801  unsigned M0 = N->getMaskElt(0) / 4;
1802  unsigned M1 = N->getMaskElt(4) / 4;
1803  unsigned M2 = N->getMaskElt(8) / 4;
1804  unsigned M3 = N->getMaskElt(12) / 4;
1805  unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1806  unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1807 
1808  // Below, let H and L be arbitrary elements of the shuffle mask
1809  // where H is in the range [4,7] and L is in the range [0,3].
1810  // H, 1, 2, 3 or L, 5, 6, 7
1811  if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
1812  (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
1813  ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
1814  InsertAtByte = IsLE ? 12 : 0;
1815  Swap = M0 < 4;
1816  return true;
1817  }
1818  // 0, H, 2, 3 or 4, L, 6, 7
1819  if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
1820  (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
1821  ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
1822  InsertAtByte = IsLE ? 8 : 4;
1823  Swap = M1 < 4;
1824  return true;
1825  }
1826  // 0, 1, H, 3 or 4, 5, L, 7
1827  if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
1828  (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
1829  ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
1830  InsertAtByte = IsLE ? 4 : 8;
1831  Swap = M2 < 4;
1832  return true;
1833  }
1834  // 0, 1, 2, H or 4, 5, 6, L
1835  if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
1836  (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
1837  ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
1838  InsertAtByte = IsLE ? 0 : 12;
1839  Swap = M3 < 4;
1840  return true;
1841  }
1842 
1843  // If both vector operands for the shuffle are the same vector, the mask will
1844  // contain only elements from the first one and the second one will be undef.
1845  if (N->getOperand(1).isUndef()) {
1846  ShiftElts = 0;
1847  Swap = true;
1848  unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
1849  if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
1850  InsertAtByte = IsLE ? 12 : 0;
1851  return true;
1852  }
1853  if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
1854  InsertAtByte = IsLE ? 8 : 4;
1855  return true;
1856  }
1857  if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
1858  InsertAtByte = IsLE ? 4 : 8;
1859  return true;
1860  }
1861  if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
1862  InsertAtByte = IsLE ? 0 : 12;
1863  return true;
1864  }
1865  }
1866 
1867  return false;
1868 }
1869 
1871  bool &Swap, bool IsLE) {
1872  assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1873  // Ensure each byte index of the word is consecutive.
1874  if (!isNByteElemShuffleMask(N, 4, 1))
1875  return false;
1876 
1877  // Now we look at mask elements 0,4,8,12, which are the beginning of words.
1878  unsigned M0 = N->getMaskElt(0) / 4;
1879  unsigned M1 = N->getMaskElt(4) / 4;
1880  unsigned M2 = N->getMaskElt(8) / 4;
1881  unsigned M3 = N->getMaskElt(12) / 4;
1882 
1883  // If both vector operands for the shuffle are the same vector, the mask will
1884  // contain only elements from the first one and the second one will be undef.
1885  if (N->getOperand(1).isUndef()) {
1886  assert(M0 < 4 && "Indexing into an undef vector?");
1887  if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
1888  return false;
1889 
1890  ShiftElts = IsLE ? (4 - M0) % 4 : M0;
1891  Swap = false;
1892  return true;
1893  }
1894 
1895  // Ensure each word index of the ShuffleVector Mask is consecutive.
1896  if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
1897  return false;
1898 
1899  if (IsLE) {
1900  if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
1901  // Input vectors don't need to be swapped if the leading element
1902  // of the result is one of the 3 left elements of the second vector
1903  // (or if there is no shift to be done at all).
1904  Swap = false;
1905  ShiftElts = (8 - M0) % 8;
1906  } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
1907  // Input vectors need to be swapped if the leading element
1908  // of the result is one of the 3 left elements of the first vector
1909  // (or if we're shifting by 4 - thereby simply swapping the vectors).
1910  Swap = true;
1911  ShiftElts = (4 - M0) % 4;
1912  }
1913 
1914  return true;
1915  } else { // BE
1916  if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
1917  // Input vectors don't need to be swapped if the leading element
1918  // of the result is one of the 4 elements of the first vector.
1919  Swap = false;
1920  ShiftElts = M0;
1921  } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
1922  // Input vectors need to be swapped if the leading element
1923  // of the result is one of the 4 elements of the right vector.
1924  Swap = true;
1925  ShiftElts = M0 - 4;
1926  }
1927 
1928  return true;
1929  }
1930 }
1931 
1933  assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1934 
1935  if (!isNByteElemShuffleMask(N, Width, -1))
1936  return false;
1937 
1938  for (int i = 0; i < 16; i += Width)
1939  if (N->getMaskElt(i) != i + Width - 1)
1940  return false;
1941 
1942  return true;
1943 }
1944 
1946  return isXXBRShuffleMaskHelper(N, 2);
1947 }
1948 
1950  return isXXBRShuffleMaskHelper(N, 4);
1951 }
1952 
1954  return isXXBRShuffleMaskHelper(N, 8);
1955 }
1956 
1958  return isXXBRShuffleMaskHelper(N, 16);
1959 }
1960 
1961 /// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
1962 /// if the inputs to the instruction should be swapped and set \p DM to the
1963 /// value for the immediate.
1964 /// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
1965 /// AND element 0 of the result comes from the first input (LE) or second input
1966 /// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
1967 /// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
1968 /// mask.
1970  bool &Swap, bool IsLE) {
1971  assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1972 
1973  // Ensure each byte index of the double word is consecutive.
1974  if (!isNByteElemShuffleMask(N, 8, 1))
1975  return false;
1976 
1977  unsigned M0 = N->getMaskElt(0) / 8;
1978  unsigned M1 = N->getMaskElt(8) / 8;
1979  assert(((M0 | M1) < 4) && "A mask element out of bounds?");
1980 
1981  // If both vector operands for the shuffle are the same vector, the mask will
1982  // contain only elements from the first one and the second one will be undef.
1983  if (N->getOperand(1).isUndef()) {
1984  if ((M0 | M1) < 2) {
1985  DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
1986  Swap = false;
1987  return true;
1988  } else
1989  return false;
1990  }
1991 
1992  if (IsLE) {
1993  if (M0 > 1 && M1 < 2) {
1994  Swap = false;
1995  } else if (M0 < 2 && M1 > 1) {
1996  M0 = (M0 + 2) % 4;
1997  M1 = (M1 + 2) % 4;
1998  Swap = true;
1999  } else
2000  return false;
2001 
2002  // Note: if control flow comes here that means Swap is already set above
2003  DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2004  return true;
2005  } else { // BE
2006  if (M0 < 2 && M1 > 1) {
2007  Swap = false;
2008  } else if (M0 > 1 && M1 < 2) {
2009  M0 = (M0 + 2) % 4;
2010  M1 = (M1 + 2) % 4;
2011  Swap = true;
2012  } else
2013  return false;
2014 
2015  // Note: if control flow comes here that means Swap is already set above
2016  DM = (M0 << 1) + (M1 & 1);
2017  return true;
2018  }
2019 }
2020 
2021 
2022 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
2023 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
2024 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
2025  SelectionDAG &DAG) {
2026  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2027  assert(isSplatShuffleMask(SVOp, EltSize));
2028  if (DAG.getDataLayout().isLittleEndian())
2029  return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2030  else
2031  return SVOp->getMaskElt(0) / EltSize;
2032 }
2033 
2034 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2035 /// by using a vspltis[bhw] instruction of the specified element size, return
2036 /// the constant being splatted. The ByteSize field indicates the number of
2037 /// bytes of each element [124] -> [bhw].
2038 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2039  SDValue OpVal(nullptr, 0);
2040 
2041  // If ByteSize of the splat is bigger than the element size of the
2042  // build_vector, then we have a case where we are checking for a splat where
2043  // multiple elements of the buildvector are folded together into a single
2044  // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2045  unsigned EltSize = 16/N->getNumOperands();
2046  if (EltSize < ByteSize) {
2047  unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2048  SDValue UniquedVals[4];
2049  assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
2050 
2051  // See if all of the elements in the buildvector agree across.
2052  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2053  if (N->getOperand(i).isUndef()) continue;
2054  // If the element isn't a constant, bail fully out.
2055  if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2056 
2057  if (!UniquedVals[i&(Multiple-1)].getNode())
2058  UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2059  else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2060  return SDValue(); // no match.
2061  }
2062 
2063  // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2064  // either constant or undef values that are identical for each chunk. See
2065  // if these chunks can form into a larger vspltis*.
2066 
2067  // Check to see if all of the leading entries are either 0 or -1. If
2068  // neither, then this won't fit into the immediate field.
2069  bool LeadingZero = true;
2070  bool LeadingOnes = true;
2071  for (unsigned i = 0; i != Multiple-1; ++i) {
2072  if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2073 
2074  LeadingZero &= isNullConstant(UniquedVals[i]);
2075  LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2076  }
2077  // Finally, check the least significant entry.
2078  if (LeadingZero) {
2079  if (!UniquedVals[Multiple-1].getNode())
2080  return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2081  int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2082  if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2083  return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2084  }
2085  if (LeadingOnes) {
2086  if (!UniquedVals[Multiple-1].getNode())
2087  return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2088  int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2089  if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2090  return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2091  }
2092 
2093  return SDValue();
2094  }
2095 
2096  // Check to see if this buildvec has a single non-undef value in its elements.
2097  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2098  if (N->getOperand(i).isUndef()) continue;
2099  if (!OpVal.getNode())
2100  OpVal = N->getOperand(i);
2101  else if (OpVal != N->getOperand(i))
2102  return SDValue();
2103  }
2104 
2105  if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2106 
2107  unsigned ValSizeInBytes = EltSize;
2108  uint64_t Value = 0;
2109  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2110  Value = CN->getZExtValue();
2111  } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2112  assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
2113  Value = FloatToBits(CN->getValueAPF().convertToFloat());
2114  }
2115 
2116  // If the splat value is larger than the element value, then we can never do
2117  // this splat. The only case that we could fit the replicated bits into our
2118  // immediate field for would be zero, and we prefer to use vxor for it.
2119  if (ValSizeInBytes < ByteSize) return SDValue();
2120 
2121  // If the element value is larger than the splat value, check if it consists
2122  // of a repeated bit pattern of size ByteSize.
2123  if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2124  return SDValue();
2125 
2126  // Properly sign extend the value.
2127  int MaskVal = SignExtend32(Value, ByteSize * 8);
2128 
2129  // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2130  if (MaskVal == 0) return SDValue();
2131 
2132  // Finally, if this value fits in a 5 bit sext field, return it
2133  if (SignExtend32<5>(MaskVal) == MaskVal)
2134  return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2135  return SDValue();
2136 }
2137 
2138 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2139 /// amount, otherwise return -1.
2141  EVT VT = N->getValueType(0);
2142  if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2143  return -1;
2144 
2145  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2146 
2147  // Find the first non-undef value in the shuffle mask.
2148  unsigned i;
2149  for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2150  /*search*/;
2151 
2152  if (i == 4) return -1; // all undef.
2153 
2154  // Otherwise, check to see if the rest of the elements are consecutively
2155  // numbered from this value.
2156  unsigned ShiftAmt = SVOp->getMaskElt(i);
2157  if (ShiftAmt < i) return -1;
2158  ShiftAmt -= i;
2159 
2160  // Check the rest of the elements to see if they are consecutive.
2161  for (++i; i != 4; ++i)
2162  if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2163  return -1;
2164 
2165  return ShiftAmt;
2166 }
2167 
2168 //===----------------------------------------------------------------------===//
2169 // Addressing Mode Selection
2170 //===----------------------------------------------------------------------===//
2171 
2172 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2173 /// or 64-bit immediate, and if the value can be accurately represented as a
2174 /// sign extension from a 16-bit value. If so, this returns true and the
2175 /// immediate.
2176 bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2177  if (!isa<ConstantSDNode>(N))
2178  return false;
2179 
2180  Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2181  if (N->getValueType(0) == MVT::i32)
2182  return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2183  else
2184  return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2185 }
2186 bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2187  return isIntS16Immediate(Op.getNode(), Imm);
2188 }
2189 
2190 /// SelectAddressRegReg - Given the specified addressed, check to see if it
2191 /// can be represented as an indexed [r+r] operation. Returns false if it
2192 /// can be more efficiently represented with [r+imm].
2194  SDValue &Index,
2195  SelectionDAG &DAG) const {
2196  int16_t imm = 0;
2197  if (N.getOpcode() == ISD::ADD) {
2198  if (isIntS16Immediate(N.getOperand(1), imm))
2199  return false; // r+i
2200  if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2201  return false; // r+i
2202 
2203  Base = N.getOperand(0);
2204  Index = N.getOperand(1);
2205  return true;
2206  } else if (N.getOpcode() == ISD::OR) {
2207  if (isIntS16Immediate(N.getOperand(1), imm))
2208  return false; // r+i can fold it if we can.
2209 
2210  // If this is an or of disjoint bitfields, we can codegen this as an add
2211  // (for better address arithmetic) if the LHS and RHS of the OR are provably
2212  // disjoint.
2213  KnownBits LHSKnown, RHSKnown;
2214  DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2215 
2216  if (LHSKnown.Zero.getBoolValue()) {
2217  DAG.computeKnownBits(N.getOperand(1), RHSKnown);
2218  // If all of the bits are known zero on the LHS or RHS, the add won't
2219  // carry.
2220  if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2221  Base = N.getOperand(0);
2222  Index = N.getOperand(1);
2223  return true;
2224  }
2225  }
2226  }
2227 
2228  return false;
2229 }
2230 
2231 // If we happen to be doing an i64 load or store into a stack slot that has
2232 // less than a 4-byte alignment, then the frame-index elimination may need to
2233 // use an indexed load or store instruction (because the offset may not be a
2234 // multiple of 4). The extra register needed to hold the offset comes from the
2235 // register scavenger, and it is possible that the scavenger will need to use
2236 // an emergency spill slot. As a result, we need to make sure that a spill slot
2237 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2238 // stack slot.
2239 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2240  // FIXME: This does not handle the LWA case.
2241  if (VT != MVT::i64)
2242  return;
2243 
2244  // NOTE: We'll exclude negative FIs here, which come from argument
2245  // lowering, because there are no known test cases triggering this problem
2246  // using packed structures (or similar). We can remove this exclusion if
2247  // we find such a test case. The reason why this is so test-case driven is
2248  // because this entire 'fixup' is only to prevent crashes (from the
2249  // register scavenger) on not-really-valid inputs. For example, if we have:
2250  // %a = alloca i1
2251  // %b = bitcast i1* %a to i64*
2252  // store i64* a, i64 b
2253  // then the store should really be marked as 'align 1', but is not. If it
2254  // were marked as 'align 1' then the indexed form would have been
2255  // instruction-selected initially, and the problem this 'fixup' is preventing
2256  // won't happen regardless.
2257  if (FrameIdx < 0)
2258  return;
2259 
2260  MachineFunction &MF = DAG.getMachineFunction();
2261  MachineFrameInfo &MFI = MF.getFrameInfo();
2262 
2263  unsigned Align = MFI.getObjectAlignment(FrameIdx);
2264  if (Align >= 4)
2265  return;
2266 
2267  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2268  FuncInfo->setHasNonRISpills();
2269 }
2270 
2271 /// Returns true if the address N can be represented by a base register plus
2272 /// a signed 16-bit displacement [r+imm], and if it is not better
2273 /// represented as reg+reg. If \p Alignment is non-zero, only accept
2274 /// displacements that are multiples of that value.
2276  SDValue &Base,
2277  SelectionDAG &DAG,
2278  unsigned Alignment) const {
2279  // FIXME dl should come from parent load or store, not from address
2280  SDLoc dl(N);
2281  // If this can be more profitably realized as r+r, fail.
2282  if (SelectAddressRegReg(N, Disp, Base, DAG))
2283  return false;
2284 
2285  if (N.getOpcode() == ISD::ADD) {
2286  int16_t imm = 0;
2287  if (isIntS16Immediate(N.getOperand(1), imm) &&
2288  (!Alignment || (imm % Alignment) == 0)) {
2289  Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2290  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2291  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2292  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2293  } else {
2294  Base = N.getOperand(0);
2295  }
2296  return true; // [r+i]
2297  } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2298  // Match LOAD (ADD (X, Lo(G))).
2299  assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
2300  && "Cannot handle constant offsets yet!");
2301  Disp = N.getOperand(1).getOperand(0); // The global address.
2302  assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
2303  Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
2304  Disp.getOpcode() == ISD::TargetConstantPool ||
2305  Disp.getOpcode() == ISD::TargetJumpTable);
2306  Base = N.getOperand(0);
2307  return true; // [&g+r]
2308  }
2309  } else if (N.getOpcode() == ISD::OR) {
2310  int16_t imm = 0;
2311  if (isIntS16Immediate(N.getOperand(1), imm) &&
2312  (!Alignment || (imm % Alignment) == 0)) {
2313  // If this is an or of disjoint bitfields, we can codegen this as an add
2314  // (for better address arithmetic) if the LHS and RHS of the OR are
2315  // provably disjoint.
2316  KnownBits LHSKnown;
2317  DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2318 
2319  if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2320  // If all of the bits are known zero on the LHS or RHS, the add won't
2321  // carry.
2322  if (FrameIndexSDNode *FI =
2323  dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2324  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2325  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2326  } else {
2327  Base = N.getOperand(0);
2328  }
2329  Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2330  return true;
2331  }
2332  }
2333  } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2334  // Loading from a constant address.
2335 
2336  // If this address fits entirely in a 16-bit sext immediate field, codegen
2337  // this as "d, 0"
2338  int16_t Imm;
2339  if (isIntS16Immediate(CN, Imm) && (!Alignment || (Imm % Alignment) == 0)) {
2340  Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2341  Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2342  CN->getValueType(0));
2343  return true;
2344  }
2345 
2346  // Handle 32-bit sext immediates with LIS + addr mode.
2347  if ((CN->getValueType(0) == MVT::i32 ||
2348  (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2349  (!Alignment || (CN->getZExtValue() % Alignment) == 0)) {
2350  int Addr = (int)CN->getZExtValue();
2351 
2352  // Otherwise, break this down into an LIS + disp.
2353  Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2354 
2355  Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2356  MVT::i32);
2357  unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2358  Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2359  return true;
2360  }
2361  }
2362 
2363  Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2364  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2365  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2366  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2367  } else
2368  Base = N;
2369  return true; // [r+0]
2370 }
2371 
2372 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2373 /// represented as an indexed [r+r] operation.
2375  SDValue &Index,
2376  SelectionDAG &DAG) const {
2377  // Check to see if we can easily represent this as an [r+r] address. This
2378  // will fail if it thinks that the address is more profitably represented as
2379  // reg+imm, e.g. where imm = 0.
2380  if (SelectAddressRegReg(N, Base, Index, DAG))
2381  return true;
2382 
2383  // If the address is the result of an add, we will utilize the fact that the
2384  // address calculation includes an implicit add. However, we can reduce
2385  // register pressure if we do not materialize a constant just for use as the
2386  // index register. We only get rid of the add if it is not an add of a
2387  // value and a 16-bit signed constant and both have a single use.
2388  int16_t imm = 0;
2389  if (N.getOpcode() == ISD::ADD &&
2390  (!isIntS16Immediate(N.getOperand(1), imm) ||
2391  !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2392  Base = N.getOperand(0);
2393  Index = N.getOperand(1);
2394  return true;
2395  }
2396 
2397  // Otherwise, do it the hard way, using R0 as the base register.
2398  Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2399  N.getValueType());
2400  Index = N;
2401  return true;
2402 }
2403 
2404 /// Returns true if we should use a direct load into vector instruction
2405 /// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2407  if (!N->hasOneUse())
2408  return false;
2409 
2410  // If there are any other uses other than scalar to vector, then we should
2411  // keep it as a scalar load -> direct move pattern to prevent multiple
2412  // loads. Currently, only check for i64 since we have lxsd/lfd to do this
2413  // efficiently, but no update equivalent.
2414  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2415  EVT MemVT = LD->getMemoryVT();
2416  if (MemVT.isSimple() && MemVT.getSimpleVT().SimpleTy == MVT::i64) {
2417  SDNode *User = *(LD->use_begin());
2418  if (User->getOpcode() == ISD::SCALAR_TO_VECTOR)
2419  return true;
2420  }
2421  }
2422 
2423  return false;
2424 }
2425 
2426 /// getPreIndexedAddressParts - returns true by value, base pointer and
2427 /// offset pointer and addressing mode by reference if the node's address
2428 /// can be legally represented as pre-indexed load / store address.
2430  SDValue &Offset,
2431  ISD::MemIndexedMode &AM,
2432  SelectionDAG &DAG) const {
2433  if (DisablePPCPreinc) return false;
2434 
2435  bool isLoad = true;
2436  SDValue Ptr;
2437  EVT VT;
2438  unsigned Alignment;
2439  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2440  Ptr = LD->getBasePtr();
2441  VT = LD->getMemoryVT();
2442  Alignment = LD->getAlignment();
2443  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2444  Ptr = ST->getBasePtr();
2445  VT = ST->getMemoryVT();
2446  Alignment = ST->getAlignment();
2447  isLoad = false;
2448  } else
2449  return false;
2450 
2451  // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2452  // instructions because we can fold these into a more efficient instruction
2453  // instead, (such as LXSD).
2454  if (isLoad && usePartialVectorLoads(N)) {
2455  return false;
2456  }
2457 
2458  // PowerPC doesn't have preinc load/store instructions for vectors (except
2459  // for QPX, which does have preinc r+r forms).
2460  if (VT.isVector()) {
2461  if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2462  return false;
2463  } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
2464  AM = ISD::PRE_INC;
2465  return true;
2466  }
2467  }
2468 
2469  if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2470  // Common code will reject creating a pre-inc form if the base pointer
2471  // is a frame index, or if N is a store and the base pointer is either
2472  // the same as or a predecessor of the value being stored. Check for
2473  // those situations here, and try with swapped Base/Offset instead.
2474  bool Swap = false;
2475 
2476  if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2477  Swap = true;
2478  else if (!isLoad) {
2479  SDValue Val = cast<StoreSDNode>(N)->getValue();
2480  if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2481  Swap = true;
2482  }
2483 
2484  if (Swap)
2485  std::swap(Base, Offset);
2486 
2487  AM = ISD::PRE_INC;
2488  return true;
2489  }
2490 
2491  // LDU/STU can only handle immediates that are a multiple of 4.
2492  if (VT != MVT::i64) {
2493  if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 0))
2494  return false;
2495  } else {
2496  // LDU/STU need an address with at least 4-byte alignment.
2497  if (Alignment < 4)
2498  return false;
2499 
2500  if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 4))
2501  return false;
2502  }
2503 
2504  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2505  // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2506  // sext i32 to i64 when addr mode is r+i.
2507  if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2508  LD->getExtensionType() == ISD::SEXTLOAD &&
2509  isa<ConstantSDNode>(Offset))
2510  return false;
2511  }
2512 
2513  AM = ISD::PRE_INC;
2514  return true;
2515 }
2516 
2517 //===----------------------------------------------------------------------===//
2518 // LowerOperation implementation
2519 //===----------------------------------------------------------------------===//
2520 
2521 /// Return true if we should reference labels using a PICBase, set the HiOpFlags
2522 /// and LoOpFlags to the target MO flags.
2523 static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2524  unsigned &HiOpFlags, unsigned &LoOpFlags,
2525  const GlobalValue *GV = nullptr) {
2526  HiOpFlags = PPCII::MO_HA;
2527  LoOpFlags = PPCII::MO_LO;
2528 
2529  // Don't use the pic base if not in PIC relocation model.
2530  if (IsPIC) {
2531  HiOpFlags |= PPCII::MO_PIC_FLAG;
2532  LoOpFlags |= PPCII::MO_PIC_FLAG;
2533  }
2534 
2535  // If this is a reference to a global value that requires a non-lazy-ptr, make
2536  // sure that instruction lowering adds it.
2537  if (GV && Subtarget.hasLazyResolverStub(GV)) {
2538  HiOpFlags |= PPCII::MO_NLP_FLAG;
2539  LoOpFlags |= PPCII::MO_NLP_FLAG;
2540 
2541  if (GV->hasHiddenVisibility()) {
2542  HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2543  LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2544  }
2545  }
2546 }
2547 
2548 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2549  SelectionDAG &DAG) {
2550  SDLoc DL(HiPart);
2551  EVT PtrVT = HiPart.getValueType();
2552  SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2553 
2554  SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2555  SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2556 
2557  // With PIC, the first instruction is actually "GR+hi(&G)".
2558  if (isPIC)
2559  Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2560  DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2561 
2562  // Generate non-pic code that has direct accesses to the constant pool.
2563  // The address of the global is just (hi(&g)+lo(&g)).
2564  return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2565 }
2566 
2568  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2569  FuncInfo->setUsesTOCBasePtr();
2570 }
2571 
2572 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2574 }
2575 
2576 static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit,
2577  SDValue GA) {
2578  EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2579  SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2580  DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2581 
2582  SDValue Ops[] = { GA, Reg };
2583  return DAG.getMemIntrinsicNode(
2584  PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2587 }
2588 
2589 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2590  SelectionDAG &DAG) const {
2591  EVT PtrVT = Op.getValueType();
2592  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2593  const Constant *C = CP->getConstVal();
2594 
2595  // 64-bit SVR4 ABI code is always position-independent.
2596  // The actual address of the GlobalValue is stored in the TOC.
2597  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2598  setUsesTOCBasePtr(DAG);
2599  SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2600  return getTOCEntry(DAG, SDLoc(CP), true, GA);
2601  }
2602 
2603  unsigned MOHiFlag, MOLoFlag;
2604  bool IsPIC = isPositionIndependent();
2605  getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2606 
2607  if (IsPIC && Subtarget.isSVR4ABI()) {
2608  SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2610  return getTOCEntry(DAG, SDLoc(CP), false, GA);
2611  }
2612 
2613  SDValue CPIHi =
2614  DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2615  SDValue CPILo =
2616  DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2617  return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2618 }
2619 
2620 // For 64-bit PowerPC, prefer the more compact relative encodings.
2621 // This trades 32 bits per jump table entry for one or two instructions
2622 // on the jump site.
2624  if (isJumpTableRelative())
2626 
2628 }
2629 
2631  if (Subtarget.isPPC64())
2632  return true;
2634 }
2635 
2637  SelectionDAG &DAG) const {
2638  if (!Subtarget.isPPC64())
2639  return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2640 
2641  switch (getTargetMachine().getCodeModel()) {
2642  case CodeModel::Small:
2643  case CodeModel::Medium:
2644  return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2645  default:
2646  return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2647  getPointerTy(DAG.getDataLayout()));
2648  }
2649 }
2650 
2651 const MCExpr *
2653  unsigned JTI,
2654  MCContext &Ctx) const {
2655  if (!Subtarget.isPPC64())
2656  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2657 
2658  switch (getTargetMachine().getCodeModel()) {
2659  case CodeModel::Small:
2660  case CodeModel::Medium:
2661  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2662  default:
2663  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2664  }
2665 }
2666 
2667 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2668  EVT PtrVT = Op.getValueType();
2669  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2670 
2671  // 64-bit SVR4 ABI code is always position-independent.
2672  // The actual address of the GlobalValue is stored in the TOC.
2673  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2674  setUsesTOCBasePtr(DAG);
2675  SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2676  return getTOCEntry(DAG, SDLoc(JT), true, GA);
2677  }
2678 
2679  unsigned MOHiFlag, MOLoFlag;
2680  bool IsPIC = isPositionIndependent();
2681  getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2682 
2683  if (IsPIC && Subtarget.isSVR4ABI()) {
2684  SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2686  return getTOCEntry(DAG, SDLoc(GA), false, GA);
2687  }
2688 
2689  SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2690  SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2691  return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
2692 }
2693 
2694 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2695  SelectionDAG &DAG) const {
2696  EVT PtrVT = Op.getValueType();
2697  BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2698  const BlockAddress *BA = BASDN->getBlockAddress();
2699 
2700  // 64-bit SVR4 ABI code is always position-independent.
2701  // The actual BlockAddress is stored in the TOC.
2702  if (Subtarget.isSVR4ABI() &&
2703  (Subtarget.isPPC64() || isPositionIndependent())) {
2704  if (Subtarget.isPPC64())
2705  setUsesTOCBasePtr(DAG);
2706  SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2707  return getTOCEntry(DAG, SDLoc(BASDN), Subtarget.isPPC64(), GA);
2708  }
2709 
2710  unsigned MOHiFlag, MOLoFlag;
2711  bool IsPIC = isPositionIndependent();
2712  getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2713  SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2714  SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2715  return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
2716 }
2717 
2718 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2719  SelectionDAG &DAG) const {
2720  // FIXME: TLS addresses currently use medium model code sequences,
2721  // which is the most useful form. Eventually support for small and
2722  // large models could be added if users need it, at the cost of
2723  // additional complexity.
2724  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2725  if (DAG.getTarget().useEmulatedTLS())
2726  return LowerToTLSEmulatedModel(GA, DAG);
2727 
2728  SDLoc dl(GA);
2729  const GlobalValue *GV = GA->getGlobal();
2730  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2731  bool is64bit = Subtarget.isPPC64();
2732  const Module *M = DAG.getMachineFunction().getFunction().getParent();
2733  PICLevel::Level picLevel = M->getPICLevel();
2734 
2736 
2737  if (Model == TLSModel::LocalExec) {
2738  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2740  SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2742  SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
2743  : DAG.getRegister(PPC::R2, MVT::i32);
2744 
2745  SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2746  return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2747  }
2748 
2749  if (Model == TLSModel::InitialExec) {
2750  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2751  SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2752  PPCII::MO_TLS);
2753  SDValue GOTPtr;
2754  if (is64bit) {
2755  setUsesTOCBasePtr(DAG);
2756  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2757  GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2758  PtrVT, GOTReg, TGA);
2759  } else
2760  GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2761  SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2762  PtrVT, TGA, GOTPtr);
2763  return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2764  }
2765 
2766  if (Model == TLSModel::GeneralDynamic) {
2767  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2768  SDValue GOTPtr;
2769  if (is64bit) {
2770  setUsesTOCBasePtr(DAG);
2771  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2772  GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2773  GOTReg, TGA);
2774  } else {
2775  if (picLevel == PICLevel::SmallPIC)
2776  GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2777  else
2778  GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2779  }
2780  return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2781  GOTPtr, TGA, TGA);
2782  }
2783 
2784  if (Model == TLSModel::LocalDynamic) {
2785  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2786  SDValue GOTPtr;
2787  if (is64bit) {
2788  setUsesTOCBasePtr(DAG);
2789  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2790  GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2791  GOTReg, TGA);
2792  } else {
2793  if (picLevel == PICLevel::SmallPIC)
2794  GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2795  else
2796  GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2797  }
2798  SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2799  PtrVT, GOTPtr, TGA, TGA);
2800  SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2801  PtrVT, TLSAddr, TGA);
2802  return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2803  }
2804 
2805  llvm_unreachable("Unknown TLS model!");
2806 }
2807 
2808 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2809  SelectionDAG &DAG) const {
2810  EVT PtrVT = Op.getValueType();
2811  GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2812  SDLoc DL(GSDN);
2813  const GlobalValue *GV = GSDN->getGlobal();
2814 
2815  // 64-bit SVR4 ABI code is always position-independent.
2816  // The actual address of the GlobalValue is stored in the TOC.
2817  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2818  setUsesTOCBasePtr(DAG);
2819  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2820  return getTOCEntry(DAG, DL, true, GA);
2821  }
2822 
2823  unsigned MOHiFlag, MOLoFlag;
2824  bool IsPIC = isPositionIndependent();
2825  getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
2826 
2827  if (IsPIC && Subtarget.isSVR4ABI()) {
2828  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2829  GSDN->getOffset(),
2831  return getTOCEntry(DAG, DL, false, GA);
2832  }
2833 
2834  SDValue GAHi =
2835  DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2836  SDValue GALo =
2837  DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2838 
2839  SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
2840 
2841  // If the global reference is actually to a non-lazy-pointer, we have to do an
2842  // extra load to get the address of the global.
2843  if (MOHiFlag & PPCII::MO_NLP_FLAG)
2844  Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2845  return Ptr;
2846 }
2847 
2848 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2849  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2850  SDLoc dl(Op);
2851 
2852  if (Op.getValueType() == MVT::v2i64) {
2853  // When the operands themselves are v2i64 values, we need to do something
2854  // special because VSX has no underlying comparison operations for these.
2855  if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2856  // Equality can be handled by casting to the legal type for Altivec
2857  // comparisons, everything else needs to be expanded.
2858  if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2859  return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2860  DAG.getSetCC(dl, MVT::v4i32,
2861  DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2862  DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2863  CC));
2864  }
2865 
2866  return SDValue();
2867  }
2868 
2869  // We handle most of these in the usual way.
2870  return Op;
2871  }
2872 
2873  // If we're comparing for equality to zero, expose the fact that this is
2874  // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
2875  // fold the new nodes.
2876  if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
2877  return V;
2878 
2879  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2880  // Leave comparisons against 0 and -1 alone for now, since they're usually
2881  // optimized. FIXME: revisit this when we can custom lower all setcc
2882  // optimizations.
2883  if (C->isAllOnesValue() || C->isNullValue())
2884  return SDValue();
2885  }
2886 
2887  // If we have an integer seteq/setne, turn it into a compare against zero
2888  // by xor'ing the rhs with the lhs, which is faster than setting a
2889  // condition register, reading it back out, and masking the correct bit. The
2890  // normal approach here uses sub to do this instead of xor. Using xor exposes
2891  // the result to other bit-twiddling opportunities.
2892  EVT LHSVT = Op.getOperand(0).getValueType();
2893  if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2894  EVT VT = Op.getValueType();
2895  SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2896  Op.getOperand(1));
2897  return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2898  }
2899  return SDValue();
2900 }
2901 
2902 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2903  SDNode *Node = Op.getNode();
2904  EVT VT = Node->getValueType(0);
2905  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2906  SDValue InChain = Node->getOperand(0);
2907  SDValue VAListPtr = Node->getOperand(1);
2908  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2909  SDLoc dl(Node);
2910 
2911  assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2912 
2913  // gpr_index
2914  SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2915  VAListPtr, MachinePointerInfo(SV), MVT::i8);
2916  InChain = GprIndex.getValue(1);
2917 
2918  if (VT == MVT::i64) {
2919  // Check if GprIndex is even
2920  SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2921  DAG.getConstant(1, dl, MVT::i32));
2922  SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2923  DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2924  SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2925  DAG.getConstant(1, dl, MVT::i32));
2926  // Align GprIndex to be even if it isn't
2927  GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2928  GprIndex);
2929  }
2930 
2931  // fpr index is 1 byte after gpr
2932  SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2933  DAG.getConstant(1, dl, MVT::i32));
2934 
2935  // fpr
2936  SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2937  FprPtr, MachinePointerInfo(SV), MVT::i8);
2938  InChain = FprIndex.getValue(1);
2939 
2940  SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2941  DAG.getConstant(8, dl, MVT::i32));
2942 
2943  SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2944  DAG.getConstant(4, dl, MVT::i32));
2945 
2946  // areas
2947  SDValue OverflowArea =
2948  DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
2949  InChain = OverflowArea.getValue(1);
2950 
2951  SDValue RegSaveArea =
2952  DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
2953  InChain = RegSaveArea.getValue(1);
2954 
2955  // select overflow_area if index > 8
2956  SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2957  DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2958 
2959  // adjustment constant gpr_index * 4/8
2960  SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2961  VT.isInteger() ? GprIndex : FprIndex,
2962  DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2963  MVT::i32));
2964 
2965  // OurReg = RegSaveArea + RegConstant
2966  SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2967  RegConstant);
2968 
2969  // Floating types are 32 bytes into RegSaveArea
2970  if (VT.isFloatingPoint())
2971  OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2972  DAG.getConstant(32, dl, MVT::i32));
2973 
2974  // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2975  SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2976  VT.isInteger() ? GprIndex : FprIndex,
2977  DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2978  MVT::i32));
2979 
2980  InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2981  VT.isInteger() ? VAListPtr : FprPtr,
2983 
2984  // determine if we should load from reg_save_area or overflow_area
2985  SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2986 
2987  // increase overflow_area by 4/8 if gpr/fpr > 8
2988  SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2989  DAG.getConstant(VT.isInteger() ? 4 : 8,
2990  dl, MVT::i32));
2991 
2992  OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2993  OverflowAreaPlusN);
2994 
2995  InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
2997 
2998  return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
2999 }
3000 
3001 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3002  assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
3003 
3004  // We have to copy the entire va_list struct:
3005  // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3006  return DAG.getMemcpy(Op.getOperand(0), Op,
3007  Op.getOperand(1), Op.getOperand(2),
3008  DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
3010 }
3011 
3012 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3013  SelectionDAG &DAG) const {
3014  return Op.getOperand(0);
3015 }
3016 
3017 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3018  SelectionDAG &DAG) const {
3019  SDValue Chain = Op.getOperand(0);
3020  SDValue Trmp = Op.getOperand(1); // trampoline
3021  SDValue FPtr = Op.getOperand(2); // nested function
3022  SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3023  SDLoc dl(Op);
3024 
3025  EVT PtrVT = getPointerTy(DAG.getDataLayout());
3026  bool isPPC64 = (PtrVT == MVT::i64);
3027  Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3028 
3031 
3032  Entry.Ty = IntPtrTy;
3033  Entry.Node = Trmp; Args.push_back(Entry);
3034 
3035  // TrampSize == (isPPC64 ? 48 : 40);
3036  Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3037  isPPC64 ? MVT::i64 : MVT::i32);
3038  Args.push_back(Entry);
3039 
3040  Entry.Node = FPtr; Args.push_back(Entry);
3041  Entry.Node = Nest; Args.push_back(Entry);
3042 
3043  // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3045  CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3047  DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3048 
3049  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3050  return CallResult.second;
3051 }
3052 
3053 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3054  MachineFunction &MF = DAG.getMachineFunction();
3055  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3056  EVT PtrVT = getPointerTy(MF.getDataLayout());
3057 
3058  SDLoc dl(Op);
3059 
3060  if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
3061  // vastart just stores the address of the VarArgsFrameIndex slot into the
3062  // memory location argument.
3063  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3064  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3065  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3066  MachinePointerInfo(SV));
3067  }
3068 
3069  // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3070  // We suppose the given va_list is already allocated.
3071  //
3072  // typedef struct {
3073  // char gpr; /* index into the array of 8 GPRs
3074  // * stored in the register save area
3075  // * gpr=0 corresponds to r3,
3076  // * gpr=1 to r4, etc.
3077  // */
3078  // char fpr; /* index into the array of 8 FPRs
3079  // * stored in the register save area
3080  // * fpr=0 corresponds to f1,
3081  // * fpr=1 to f2, etc.
3082  // */
3083  // char *overflow_arg_area;
3084  // /* location on stack that holds
3085  // * the next overflow argument
3086  // */
3087  // char *reg_save_area;
3088  // /* where r3:r10 and f1:f8 (if saved)
3089  // * are stored
3090  // */
3091  // } va_list[1];
3092 
3093  SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3094  SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3095  SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3096  PtrVT);
3097  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3098  PtrVT);
3099 
3100  uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3101  SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3102 
3103  uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3104  SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3105 
3106  uint64_t FPROffset = 1;
3107  SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3108 
3109  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3110 
3111  // Store first byte : number of int regs
3112  SDValue firstStore =
3113  DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3115  uint64_t nextOffset = FPROffset;
3116  SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3117  ConstFPROffset);
3118 
3119  // Store second byte : number of float regs
3120  SDValue secondStore =
3121  DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3122  MachinePointerInfo(SV, nextOffset), MVT::i8);
3123  nextOffset += StackOffset;
3124  nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3125 
3126  // Store second word : arguments given on stack
3127  SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3128  MachinePointerInfo(SV, nextOffset));
3129  nextOffset += FrameOffset;
3130  nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3131 
3132  // Store third word : arguments given in registers
3133  return DAG.getStore(thirdStore, dl, FR, nextPtr,
3134  MachinePointerInfo(SV, nextOffset));
3135 }
3136 
3137 #include "PPCGenCallingConv.inc"
3138 
3139 // Function whose sole purpose is to kill compiler warnings
3140 // stemming from unused functions included from PPCGenCallingConv.inc.
3141 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
3142  return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
3143 }
3144 
3145 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
3146  CCValAssign::LocInfo &LocInfo,
3147  ISD::ArgFlagsTy &ArgFlags,
3148  CCState &State) {
3149  return true;
3150 }
3151 
3152 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
3153  MVT &LocVT,
3154  CCValAssign::LocInfo &LocInfo,
3155  ISD::ArgFlagsTy &ArgFlags,
3156  CCState &State) {
3157  static const MCPhysReg ArgRegs[] = {
3158  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3159  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3160  };
3161  const unsigned NumArgRegs = array_lengthof(ArgRegs);
3162 
3163  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3164 
3165  // Skip one register if the first unallocated register has an even register
3166  // number and there are still argument registers available which have not been
3167  // allocated yet. RegNum is actually an index into ArgRegs, which means we
3168  // need to skip a register if RegNum is odd.
3169  if (RegNum != NumArgRegs && RegNum % 2 == 1) {
3170  State.AllocateReg(ArgRegs[RegNum]);
3171  }
3172 
3173  // Always return false here, as this function only makes sure that the first
3174  // unallocated register has an odd register number and does not actually
3175  // allocate a register for the current argument.
3176  return false;
3177 }
3178 
3179 bool
3181  MVT &LocVT,
3182  CCValAssign::LocInfo &LocInfo,
3183  ISD::ArgFlagsTy &ArgFlags,
3184  CCState &State) {
3185  static const MCPhysReg ArgRegs[] = {
3186  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3187  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3188  };
3189  const unsigned NumArgRegs = array_lengthof(ArgRegs);
3190 
3191  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3192  int RegsLeft = NumArgRegs - RegNum;
3193 
3194  // Skip if there is not enough registers left for long double type (4 gpr regs
3195  // in soft float mode) and put long double argument on the stack.
3196  if (RegNum != NumArgRegs && RegsLeft < 4) {
3197  for (int i = 0; i < RegsLeft; i++) {
3198  State.AllocateReg(ArgRegs[RegNum + i]);
3199  }
3200  }
3201 
3202  return false;
3203 }
3204 
3205 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
3206  MVT &LocVT,
3207  CCValAssign::LocInfo &LocInfo,
3208  ISD::ArgFlagsTy &ArgFlags,
3209  CCState &State) {
3210  static const MCPhysReg ArgRegs[] = {
3211  PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3212  PPC::F8
3213  };
3214 
3215  const unsigned NumArgRegs = array_lengthof(ArgRegs);
3216 
3217  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3218 
3219  // If there is only one Floating-point register left we need to put both f64
3220  // values of a split ppc_fp128 value on the stack.
3221  if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
3222  State.AllocateReg(ArgRegs[RegNum]);
3223  }
3224 
3225  // Always return false here, as this function only makes sure that the two f64
3226  // values a ppc_fp128 value is split into are both passed in registers or both
3227  // passed on the stack and does not actually allocate a register for the
3228  // current argument.
3229  return false;
3230 }
3231 
3232 /// FPR - The set of FP registers that should be allocated for arguments,
3233 /// on Darwin.
3234 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3235  PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3236  PPC::F11, PPC::F12, PPC::F13};
3237 
3238 /// QFPR - The set of QPX registers that should be allocated for arguments.
3239 static const MCPhysReg QFPR[] = {
3240  PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
3241  PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
3242 
3243 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
3244 /// the stack.
3245 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3246  unsigned PtrByteSize) {
3247  unsigned ArgSize = ArgVT.getStoreSize();
3248  if (Flags.isByVal())
3249  ArgSize = Flags.getByValSize();
3250 
3251  // Round up to multiples of the pointer size, except for array members,
3252  // which are always packed.
3253  if (!Flags.isInConsecutiveRegs())
3254  ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3255 
3256  return ArgSize;
3257 }
3258 
3259 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
3260 /// on the stack.
3261 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3262  ISD::ArgFlagsTy Flags,
3263  unsigned PtrByteSize) {
3264  unsigned Align = PtrByteSize;
3265 
3266  // Altivec parameters are padded to a 16 byte boundary.
3267  if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3268  ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3269  ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3270  ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3271  Align = 16;
3272  // QPX vector types stored in double-precision are padded to a 32 byte
3273  // boundary.
3274  else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
3275  Align = 32;
3276 
3277  // ByVal parameters are aligned as requested.
3278  if (Flags.isByVal()) {
3279  unsigned BVAlign = Flags.getByValAlign();
3280  if (BVAlign > PtrByteSize) {
3281  if (BVAlign % PtrByteSize != 0)
3283  "ByVal alignment is not a multiple of the pointer size");
3284 
3285  Align = BVAlign;
3286  }
3287  }
3288 
3289  // Array members are always packed to their original alignment.
3290  if (Flags.isInConsecutiveRegs()) {
3291  // If the array member was split into multiple registers, the first
3292  // needs to be aligned to the size of the full type. (Except for
3293  // ppcf128, which is only aligned as its f64 components.)
3294  if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3295  Align = OrigVT.getStoreSize();
3296  else
3297  Align = ArgVT.getStoreSize();
3298  }
3299 
3300  return Align;
3301 }
3302 
3303 /// CalculateStackSlotUsed - Return whether this argument will use its
3304 /// stack slot (instead of being passed in registers). ArgOffset,
3305 /// AvailableFPRs, and AvailableVRs must hold the current argument
3306 /// position, and will be updated to account for this argument.
3307 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
3308  ISD::ArgFlagsTy Flags,
3309  unsigned PtrByteSize,
3310  unsigned LinkageSize,
3311  unsigned ParamAreaSize,
3312  unsigned &ArgOffset,
3313  unsigned &AvailableFPRs,
3314  unsigned &AvailableVRs, bool HasQPX) {
3315  bool UseMemory = false;
3316 
3317  // Respect alignment of argument on the stack.
3318  unsigned Align =
3319  CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3320  ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3321  // If there's no space left in the argument save area, we must
3322  // use memory (this check also catches zero-sized arguments).
3323  if (ArgOffset >= LinkageSize + ParamAreaSize)
3324  UseMemory = true;
3325 
3326  // Allocate argument on the stack.
3327  ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3328  if (Flags.isInConsecutiveRegsLast())
3329  ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3330  // If we overran the argument save area, we must use memory
3331  // (this check catches arguments passed partially in memory)
3332  if (ArgOffset > LinkageSize + ParamAreaSize)
3333  UseMemory = true;
3334 
3335  // However, if the argument is actually passed in an FPR or a VR,
3336  // we don't use memory after all.
3337  if (!Flags.isByVal()) {
3338  if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
3339  // QPX registers overlap with the scalar FP registers.
3340  (HasQPX && (ArgVT == MVT::v4f32 ||
3341  ArgVT == MVT::v4f64 ||
3342  ArgVT == MVT::v4i1)))
3343  if (AvailableFPRs > 0) {
3344  --AvailableFPRs;
3345  return false;
3346  }
3347  if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3348  ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3349  ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3350  ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3351  if (AvailableVRs > 0) {
3352  --AvailableVRs;
3353  return false;
3354  }
3355  }
3356 
3357  return UseMemory;
3358 }
3359 
3360 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
3361 /// ensure minimum alignment required for target.
3363  unsigned NumBytes) {
3364  unsigned TargetAlign = Lowering->getStackAlignment();
3365  unsigned AlignMask = TargetAlign - 1;
3366  NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3367  return NumBytes;
3368 }
3369 
3370 SDValue PPCTargetLowering::LowerFormalArguments(
3371  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3372  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3373  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3374  if (Subtarget.isSVR4ABI()) {
3375  if (Subtarget.isPPC64())
3376  return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
3377  dl, DAG, InVals);
3378  else
3379  return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
3380  dl, DAG, InVals);
3381  } else {
3382  return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
3383  dl, DAG, InVals);
3384  }
3385 }
3386 
3387 SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3388  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3389  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3390  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3391 
3392  // 32-bit SVR4 ABI Stack Frame Layout:
3393  // +-----------------------------------+
3394  // +--> | Back chain |
3395  // | +-----------------------------------+
3396  // | | Floating-point register save area |
3397  // | +-----------------------------------+
3398  // | | General register save area |
3399  // | +-----------------------------------+
3400  // | | CR save word |
3401  // | +-----------------------------------+
3402  // | | VRSAVE save word |
3403  // | +-----------------------------------+
3404  // | | Alignment padding |
3405  // | +-----------------------------------+
3406  // | | Vector register save area |
3407  // | +-----------------------------------+
3408  // | | Local variable space |
3409  // | +-----------------------------------+
3410  // | | Parameter list area |
3411  // | +-----------------------------------+
3412  // | | LR save word |
3413  // | +-----------------------------------+
3414  // SP--> +--- | Back chain |
3415  // +-----------------------------------+
3416  //
3417  // Specifications:
3418  // System V Application Binary Interface PowerPC Processor Supplement
3419  // AltiVec Technology Programming Interface Manual
3420 
3421  MachineFunction &MF = DAG.getMachineFunction();
3422  MachineFrameInfo &MFI = MF.getFrameInfo();
3423  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3424 
3425  EVT PtrVT = getPointerTy(MF.getDataLayout());
3426  // Potential tail calls could cause overwriting of argument stack slots.
3427  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3428  (CallConv == CallingConv::Fast));
3429  unsigned PtrByteSize = 4;
3430 
3431  // Assign locations to all of the incoming arguments.
3433  PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3434  *DAG.getContext());
3435 
3436  // Reserve space for the linkage area on the stack.
3437  unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3438  CCInfo.AllocateStack(LinkageSize, PtrByteSize);
3439  if (useSoftFloat() || hasSPE())
3440  CCInfo.PreAnalyzeFormalArguments(Ins);
3441 
3442  CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3443  CCInfo.clearWasPPCF128();
3444 
3445  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3446  CCValAssign &VA = ArgLocs[i];
3447 
3448  // Arguments stored in registers.
3449  if (VA.isRegLoc()) {
3450  const TargetRegisterClass *RC;
3451  EVT ValVT = VA.getValVT();
3452 
3453  switch (ValVT.getSimpleVT().SimpleTy) {
3454  default:
3455  llvm_unreachable("ValVT not supported by formal arguments Lowering");
3456  case MVT::i1:
3457  case MVT::i32:
3458  RC = &PPC::GPRCRegClass;
3459  break;
3460  case MVT::f32:
3461  if (Subtarget.hasP8Vector())
3462  RC = &PPC::VSSRCRegClass;
3463  else if (Subtarget.hasSPE())
3464  RC = &PPC::SPE4RCRegClass;
3465  else
3466  RC = &PPC::F4RCRegClass;
3467  break;
3468  case MVT::f64:
3469  if (Subtarget.hasVSX())
3470  RC = &PPC::VSFRCRegClass;
3471  else if (Subtarget.hasSPE())
3472  RC = &PPC::SPERCRegClass;
3473  else
3474  RC = &PPC::F8RCRegClass;
3475  break;
3476  case MVT::v16i8:
3477  case MVT::v8i16:
3478  case MVT::v4i32:
3479  RC = &PPC::VRRCRegClass;
3480  break;
3481  case MVT::v4f32:
3482  RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3483  break;
3484  case MVT::v2f64:
3485  case MVT::v2i64:
3486  RC = &PPC::VRRCRegClass;
3487  break;
3488  case MVT::v4f64:
3489  RC = &PPC::QFRCRegClass;
3490  break;
3491  case MVT::v4i1:
3492  RC = &PPC::QBRCRegClass;
3493  break;
3494  }
3495 
3496  // Transform the arguments stored in physical registers into virtual ones.
3497  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3498  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3499  ValVT == MVT::i1 ? MVT::i32 : ValVT);
3500 
3501  if (ValVT == MVT::i1)
3502  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3503 
3504  InVals.push_back(ArgValue);
3505  } else {
3506  // Argument stored in memory.
3507  assert(VA.isMemLoc());
3508 
3509  // Get the extended size of the argument type in stack
3510  unsigned ArgSize = VA.getLocVT().getStoreSize();
3511  // Get the actual size of the argument type
3512  unsigned ObjSize = VA.getValVT().getStoreSize();
3513  unsigned ArgOffset = VA.getLocMemOffset();
3514  // Stack objects in PPC32 are right justified.
3515  ArgOffset += ArgSize - ObjSize;
3516  int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
3517 
3518  // Create load nodes to retrieve arguments from the stack.
3519  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3520  InVals.push_back(
3521  DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3522  }
3523  }
3524 
3525  // Assign locations to all of the incoming aggregate by value arguments.
3526  // Aggregates passed by value are stored in the local variable space of the
3527  // caller's stack frame, right above the parameter list area.
3528  SmallVector<CCValAssign, 16> ByValArgLocs;
3529  CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3530  ByValArgLocs, *DAG.getContext());
3531 
3532  // Reserve stack space for the allocations in CCInfo.
3533  CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3534 
3535  CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3536 
3537  // Area that is at least reserved in the caller of this function.
3538  unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3539  MinReservedArea = std::max(MinReservedArea, LinkageSize);
3540 
3541  // Set the size that is at least reserved in caller of this function. Tail
3542  // call optimized function's reserved stack space needs to be aligned so that
3543  // taking the difference between two stack areas will result in an aligned
3544  // stack.
3545  MinReservedArea =
3546  EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3547  FuncInfo->setMinReservedArea(MinReservedArea);
3548 
3549  SmallVector<SDValue, 8> MemOps;
3550 
3551  // If the function takes variable number of arguments, make a frame index for
3552  // the start of the first vararg value... for expansion of llvm.va_start.
3553  if (isVarArg) {
3554  static const MCPhysReg GPArgRegs[] = {
3555  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3556  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3557  };
3558  const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3559 
3560  static const MCPhysReg FPArgRegs[] = {
3561  PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3562  PPC::F8
3563  };
3564  unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3565 
3566  if (useSoftFloat() || hasSPE())
3567  NumFPArgRegs = 0;
3568 
3569  FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3570  FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3571 
3572  // Make room for NumGPArgRegs and NumFPArgRegs.
3573  int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3574  NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3575 
3576  FuncInfo->setVarArgsStackOffset(
3577  MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3578  CCInfo.getNextStackOffset(), true));
3579 
3580  FuncInfo->setVarArgsFrameIndex(MFI.CreateStackObject(Depth, 8, false));
3581  SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3582 
3583  // The fixed integer arguments of a variadic function are stored to the
3584  // VarArgsFrameIndex on the stack so that they may be loaded by
3585  // dereferencing the result of va_next.
3586  for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3587  // Get an existing live-in vreg, or add a new one.
3588  unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3589  if (!VReg)
3590  VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3591 
3592  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3593  SDValue Store =
3594  DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3595  MemOps.push_back(Store);
3596  // Increment the address by four for the next argument to store
3597  SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3598  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3599  }
3600 
3601  // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3602  // is set.
3603  // The double arguments are stored to the VarArgsFrameIndex
3604  // on the stack.
3605  for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3606  // Get an existing live-in vreg, or add a new one.
3607  unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3608  if (!VReg)
3609  VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3610 
3611  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3612  SDValue Store =
3613  DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3614  MemOps.push_back(Store);
3615  // Increment the address by eight for the next argument to store
3616  SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3617  PtrVT);
3618  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3619  }
3620  }
3621 
3622  if (!MemOps.empty())
3623  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3624 
3625  return Chain;
3626 }
3627 
3628 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3629 // value to MVT::i64 and then truncate to the correct register size.
3630 SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3631  EVT ObjectVT, SelectionDAG &DAG,
3632  SDValue ArgVal,
3633  const SDLoc &dl) const {
3634  if (Flags.isSExt())
3635  ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3636  DAG.getValueType(ObjectVT));
3637  else if (Flags.isZExt())
3638  ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3639  DAG.getValueType(ObjectVT));
3640 
3641  return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3642 }
3643 
3644 SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3645  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3646  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3647  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3648  // TODO: add description of PPC stack frame format, or at least some docs.
3649  //
3650  bool isELFv2ABI = Subtarget.isELFv2ABI();
3651  bool isLittleEndian = Subtarget.isLittleEndian();
3652  MachineFunction &MF = DAG.getMachineFunction();
3653  MachineFrameInfo &MFI = MF.getFrameInfo();
3654  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3655 
3656  assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3657  "fastcc not supported on varargs functions");
3658 
3659  EVT PtrVT = getPointerTy(MF.getDataLayout());
3660  // Potential tail calls could cause overwriting of argument stack slots.
3661  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3662  (CallConv == CallingConv::Fast));
3663  unsigned PtrByteSize = 8;
3664  unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3665 
3666  static const MCPhysReg GPR[] = {
3667  PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3668  PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3669  };
3670  static const MCPhysReg VR[] = {
3671  PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3672  PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3673  };
3674 
3675  const unsigned Num_GPR_Regs = array_lengthof(GPR);
3676  const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3677  const unsigned Num_VR_Regs = array_lengthof(VR);
3678  const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3679 
3680  // Do a first pass over the arguments to determine whether the ABI
3681  // guarantees that our caller has allocated the parameter save area
3682  // on its stack frame. In the ELFv1 ABI, this is always the case;
3683  // in the ELFv2 ABI, it is true if this is a vararg function or if
3684  // any parameter is located in a stack slot.
3685 
3686  bool HasParameterArea = !isELFv2ABI || isVarArg;
3687  unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3688  unsigned NumBytes = LinkageSize;
3689  unsigned AvailableFPRs = Num_FPR_Regs;
3690  unsigned AvailableVRs = Num_VR_Regs;
3691  for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3692  if (Ins[i].Flags.isNest())
3693  continue;
3694 
3695  if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3696  PtrByteSize, LinkageSize, ParamAreaSize,
3697  NumBytes, AvailableFPRs, AvailableVRs,
3698  Subtarget.hasQPX()))
3699  HasParameterArea = true;
3700  }
3701 
3702  // Add DAG nodes to load the arguments or copy them out of registers. On
3703  // entry to a function on PPC, the arguments start after the linkage area,
3704  // although the first ones are often in registers.
3705 
3706  unsigned ArgOffset = LinkageSize;
3707  unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3708  unsigned &QFPR_idx = FPR_idx;
3709  SmallVector<SDValue, 8> MemOps;
3711  unsigned CurArgIdx = 0;
3712  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3713  SDValue ArgVal;
3714  bool needsLoad = false;
3715  EVT ObjectVT = Ins[ArgNo].VT;
3716  EVT OrigVT = Ins[ArgNo].ArgVT;
3717  unsigned ObjSize = ObjectVT.getStoreSize();
3718  unsigned ArgSize = ObjSize;
3719  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3720  if (Ins[ArgNo].isOrigArg()) {
3721  std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3722  CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3723  }
3724  // We re-align the argument offset for each argument, except when using the
3725  // fast calling convention, when we need to make sure we do that only when
3726  // we'll actually use a stack slot.
3727  unsigned CurArgOffset, Align;
3728  auto ComputeArgOffset = [&]() {
3729  /* Respect alignment of argument on the stack. */
3730  Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3731  ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3732  CurArgOffset = ArgOffset;
3733  };
3734 
3735  if (CallConv != CallingConv::Fast) {
3736  ComputeArgOffset();
3737 
3738  /* Compute GPR index associated with argument offset. */
3739  GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3740  GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3741  }
3742 
3743  // FIXME the codegen can be much improved in some cases.
3744  // We do not have to keep everything in memory.
3745  if (Flags.isByVal()) {
3746  assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3747 
3748  if (CallConv == CallingConv::Fast)
3749  ComputeArgOffset();
3750 
3751  // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3752  ObjSize = Flags.getByValSize();
3753  ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3754  // Empty aggregate parameters do not take up registers. Examples:
3755  // struct { } a;
3756  // union { } b;
3757  // int c[0];
3758  // etc. However, we have to provide a place-holder in InVals, so
3759  // pretend we have an 8-byte item at the current address for that
3760  // purpose.
3761  if (!ObjSize) {
3762  int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3763  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3764  InVals.push_back(FIN);
3765  continue;
3766  }
3767 
3768  // Create a stack object covering all stack doublewords occupied
3769  // by the argument. If the argument is (fully or partially) on
3770  // the stack, or if the argument is fully in registers but the
3771  // caller has allocated the parameter save anyway, we can refer
3772  // directly to the caller's stack frame. Otherwise, create a
3773  // local copy in our own frame.
3774  int FI;
3775  if (HasParameterArea ||
3776  ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3777  FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
3778  else
3779  FI = MFI.CreateStackObject(ArgSize, Align, false);
3780  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3781 
3782  // Handle aggregates smaller than 8 bytes.
3783  if (ObjSize < PtrByteSize) {
3784  // The value of the object is its address, which differs from the
3785  // address of the enclosing doubleword on big-endian systems.
3786  SDValue Arg = FIN;
3787  if (!isLittleEndian) {
3788  SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3789  Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3790  }
3791  InVals.push_back(Arg);
3792 
3793  if (GPR_idx != Num_GPR_Regs) {
3794  unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3795  FuncInfo->addLiveInAttr(VReg, Flags);
3796  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3797  SDValue Store;
3798 
3799  if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3800  EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3801  (ObjSize == 2 ? MVT::i16 : MVT::i32));
3802  Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3803  MachinePointerInfo(&*FuncArg), ObjType);
3804  } else {
3805  // For sizes that don't fit a truncating store (3, 5, 6, 7),
3806  // store the whole register as-is to the parameter save area
3807  // slot.
3808  Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3809  MachinePointerInfo(&*FuncArg));
3810  }
3811 
3812  MemOps.push_back(Store);
3813  }
3814  // Whether we copied from a register or not, advance the offset
3815  // into the parameter save area by a full doubleword.
3816  ArgOffset += PtrByteSize;
3817  continue;
3818  }
3819 
3820  // The value of the object is its address, which is the address of
3821  // its first stack doubleword.
3822  InVals.push_back(FIN);
3823 
3824  // Store whatever pieces of the object are in registers to memory.
3825  for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3826  if (GPR_idx == Num_GPR_Regs)
3827  break;
3828 
3829  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3830  FuncInfo->addLiveInAttr(VReg, Flags);
3831  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3832  SDValue Addr = FIN;
3833  if (j) {
3834  SDValue Off = DAG.getConstant(j, dl, PtrVT);
3835  Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3836  }
3837  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3838  MachinePointerInfo(&*FuncArg, j));
3839  MemOps.push_back(Store);
3840  ++GPR_idx;
3841  }
3842  ArgOffset += ArgSize;
3843  continue;
3844  }
3845 
3846  switch (ObjectVT.getSimpleVT().SimpleTy) {
3847  default: llvm_unreachable("Unhandled argument type!");
3848  case MVT::i1:
3849  case MVT::i32:
3850  case MVT::i64:
3851  if (Flags.isNest()) {
3852  // The 'nest' parameter, if any, is passed in R11.
3853  unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3854  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3855 
3856  if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3857  ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3858 
3859  break;
3860  }
3861 
3862  // These can be scalar arguments or elements of an integer array type
3863  // passed directly. Clang may use those instead of "byval" aggregate
3864  // types to avoid forcing arguments to memory unnecessarily.
3865  if (GPR_idx != Num_GPR_Regs) {
3866  unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3867  FuncInfo->addLiveInAttr(VReg, Flags);
3868  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3869 
3870  if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3871  // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3872  // value to MVT::i64 and then truncate to the correct register size.
3873  ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3874  } else {
3875  if (CallConv == CallingConv::Fast)
3876  ComputeArgOffset();
3877 
3878  needsLoad = true;
3879  ArgSize = PtrByteSize;
3880  }
3881  if (CallConv != CallingConv::Fast || needsLoad)
3882  ArgOffset += 8;
3883  break;
3884 
3885  case MVT::f32:
3886  case MVT::f64:
3887  // These can be scalar arguments or elements of a float array type
3888  // passed directly. The latter are used to implement ELFv2 homogenous
3889  // float aggregates.
3890  if (FPR_idx != Num_FPR_Regs) {
3891  unsigned VReg;
3892 
3893  if (ObjectVT == MVT::f32)
3894  VReg = MF.addLiveIn(FPR[FPR_idx],
3895  Subtarget.hasP8Vector()
3896  ? &PPC::VSSRCRegClass
3897  : &PPC::F4RCRegClass);
3898  else
3899  VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3900  ? &PPC::VSFRCRegClass
3901  : &PPC::F8RCRegClass);
3902 
3903  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3904  ++FPR_idx;
3905  } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3906  // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3907  // once we support fp <-> gpr moves.
3908 
3909  // This can only ever happen in the presence of f32 array types,
3910  // since otherwise we never run out of FPRs before running out
3911  // of GPRs.
3912  unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3913  FuncInfo->addLiveInAttr(VReg, Flags);
3914  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3915 
3916  if (ObjectVT == MVT::f32) {
3917  if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3918  ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3919  DAG.getConstant(32, dl, MVT::i32));
3920  ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3921  }
3922 
3923  ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3924  } else {
3925  if (CallConv == CallingConv::Fast)
3926  ComputeArgOffset();
3927 
3928  needsLoad = true;
3929  }
3930 
3931  // When passing an array of floats, the array occupies consecutive
3932  // space in the argument area; only round up to the next doubleword
3933  // at the end of the array. Otherwise, each float takes 8 bytes.
3934  if (CallConv != CallingConv::Fast || needsLoad) {
3935  ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3936  ArgOffset += ArgSize;
3937  if (Flags.isInConsecutiveRegsLast())
3938  ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3939  }
3940  break;
3941  case MVT::v4f32:
3942  case MVT::v4i32:
3943  case MVT::v8i16:
3944  case MVT::v16i8:
3945  case MVT::v2f64:
3946  case MVT::v2i64:
3947  case MVT::v1i128:
3948  case MVT::f128:
3949  if (!Subtarget.hasQPX()) {
3950  // These can be scalar arguments or elements of a vector array type
3951  // passed directly. The latter are used to implement ELFv2 homogenous
3952  // vector aggregates.
3953  if (VR_idx != Num_VR_Regs) {
3954  unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3955  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3956  ++VR_idx;
3957  } else {
3958  if (CallConv == CallingConv::Fast)
3959  ComputeArgOffset();
3960  needsLoad = true;
3961  }
3962  if (CallConv != CallingConv::Fast || needsLoad)
3963  ArgOffset += 16;
3964  break;
3965  } // not QPX
3966 
3967  assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3968  "Invalid QPX parameter type");
3970 
3971  case MVT::v4f64:
3972  case MVT::v4i1:
3973  // QPX vectors are treated like their scalar floating-point subregisters
3974  // (except that they're larger).
3975  unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3976  if (QFPR_idx != Num_QFPR_Regs) {
3977  const TargetRegisterClass *RC;
3978  switch (ObjectVT.getSimpleVT().SimpleTy) {
3979  case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3980  case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3981  default: RC = &PPC::QBRCRegClass; break;
3982  }
3983 
3984  unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3985  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3986  ++QFPR_idx;
3987  } else {
3988  if (CallConv == CallingConv::Fast)
3989  ComputeArgOffset();
3990  needsLoad = true;
3991  }
3992  if (CallConv != CallingConv::Fast || needsLoad)
3993  ArgOffset += Sz;
3994  break;
3995  }
3996 
3997  // We need to load the argument to a virtual register if we determined
3998  // above that we ran out of physical registers of the appropriate type.
3999  if (needsLoad) {
4000  if (ObjSize < ArgSize && !isLittleEndian)
4001  CurArgOffset += ArgSize - ObjSize;
4002  int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4003  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4004  ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4005  }
4006 
4007  InVals.push_back(ArgVal);
4008  }
4009 
4010  // Area that is at least reserved in the caller of this function.
4011  unsigned MinReservedArea;
4012  if (HasParameterArea)
4013  MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4014  else
4015  MinReservedArea = LinkageSize;
4016 
4017  // Set the size that is at least reserved in caller of this function. Tail
4018  // call optimized functions' reserved stack space needs to be aligned so that
4019  // taking the difference between two stack areas will result in an aligned
4020  // stack.
4021  MinReservedArea =
4022  EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4023  FuncInfo->setMinReservedArea(MinReservedArea);
4024 
4025  // If the function takes variable number of arguments, make a frame index for
4026  // the start of the first vararg value... for expansion of llvm.va_start.
4027  if (isVarArg) {
4028  int Depth = ArgOffset;
4029 
4030  FuncInfo->setVarArgsFrameIndex(
4031  MFI.CreateFixedObject(PtrByteSize, Depth, true));
4032  SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4033 
4034  // If this function is vararg, store any remaining integer argument regs
4035  // to their spots on the stack so that they may be loaded by dereferencing
4036  // the result of va_next.
4037  for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4038  GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4039  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4040  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4041  SDValue Store =
4042  DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4043  MemOps.push_back(Store);
4044  // Increment the address by four for the next argument to store
4045  SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4046  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4047  }
4048  }
4049 
4050  if (!MemOps.empty())
4051  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4052 
4053  return Chain;
4054 }
4055 
4056 SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
4057  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4058  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4059  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4060  // TODO: add description of PPC stack frame format, or at least some docs.
4061  //
4062  MachineFunction &MF = DAG.getMachineFunction();
4063  MachineFrameInfo &MFI = MF.getFrameInfo();
4064  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4065 
4066  EVT PtrVT = getPointerTy(MF.getDataLayout());
4067  bool isPPC64 = PtrVT == MVT::i64;
4068  // Potential tail calls could cause overwriting of argument stack slots.
4069  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4070  (CallConv == CallingConv::Fast));
4071  unsigned PtrByteSize = isPPC64 ? 8 : 4;
4072  unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4073  unsigned ArgOffset = LinkageSize;
4074  // Area that is at least reserved in caller of this function.
4075  unsigned MinReservedArea = ArgOffset;
4076 
4077  static const MCPhysReg GPR_32[] = { // 32-bit registers.
4078  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4079  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4080  };
4081  static const MCPhysReg GPR_64[] = { // 64-bit registers.
4082  PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4083  PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4084  };
4085  static const MCPhysReg VR[] = {
4086  PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4087  PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4088  };
4089 
4090  const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
4091  const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4092  const unsigned Num_VR_Regs = array_lengthof( VR);
4093 
4094  unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4095 
4096  const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4097 
4098  // In 32-bit non-varargs functions, the stack space for vectors is after the
4099  // stack space for non-vectors. We do not use this space unless we have
4100  // too many vectors to fit in registers, something that only occurs in
4101  // constructed examples:), but we have to walk the arglist to figure
4102  // that out...for the pathological case, compute VecArgOffset as the
4103  // start of the vector parameter area. Computing VecArgOffset is the
4104  // entire point of the following loop.
4105  unsigned VecArgOffset = ArgOffset;
4106  if (!isVarArg && !isPPC64) {
4107  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
4108  ++ArgNo) {
4109  EVT ObjectVT = Ins[ArgNo].VT;
4110  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4111 
4112  if (Flags.isByVal()) {
4113  // ObjSize is the true size, ArgSize rounded up to multiple of regs.
4114  unsigned ObjSize = Flags.getByValSize();
4115  unsigned ArgSize =
4116  ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4117  VecArgOffset += ArgSize;
4118  continue;
4119  }
4120 
4121  switch(ObjectVT.getSimpleVT().SimpleTy) {
4122  default: llvm_unreachable("Unhandled argument type!");
4123  case MVT::i1:
4124  case MVT::i32:
4125  case MVT::f32:
4126  VecArgOffset += 4;
4127  break;
4128  case MVT::i64: // PPC64
4129  case MVT::f64:
4130  // FIXME: We are guaranteed to be !isPPC64 at this point.
4131  // Does MVT::i64 apply?
4132  VecArgOffset += 8;
4133  break;
4134  case MVT::v4f32:
4135  case MVT::v4i32:
4136  case MVT::v8i16:
4137  case MVT::v16i8:
4138  // Nothing to do, we're only looking at Nonvector args here.
4139  break;
4140  }
4141  }
4142  }
4143  // We've found where the vector parameter area in memory is. Skip the
4144  // first 12 parameters; these don't use that memory.
4145  VecArgOffset = ((VecArgOffset+15)/16)*16;
4146  VecArgOffset += 12*16;
4147 
4148  // Add DAG nodes to load the arguments or copy them out of registers. On
4149  // entry to a function on PPC, the arguments start after the linkage area,
4150  // although the first ones are often in registers.
4151 
4152  SmallVector<SDValue, 8> MemOps;
4153  unsigned nAltivecParamsAtEnd = 0;
4155  unsigned CurArgIdx = 0;
4156  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4157  SDValue ArgVal;
4158  bool needsLoad = false;
4159  EVT ObjectVT = Ins[ArgNo].VT;
4160  unsigned ObjSize = ObjectVT.getSizeInBits()/8;
4161  unsigned ArgSize = ObjSize;
4162  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4163  if (Ins[ArgNo].isOrigArg()) {
4164  std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4165  CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4166  }
4167  unsigned CurArgOffset = ArgOffset;
4168 
4169  // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4170  if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4171  ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4172  if (isVarArg || isPPC64) {
4173  MinReservedArea = ((MinReservedArea+15)/16)*16;
4174  MinReservedArea += CalculateStackSlotSize(ObjectVT,
4175  Flags,
4176  PtrByteSize);
4177  } else nAltivecPar