LLVM  10.0.0svn
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "ppc-instr-info"
43 
44 #define GET_INSTRMAP_INFO
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "PPCGenInstrInfo.inc"
47 
48 STATISTIC(NumStoreSPILLVSRRCAsVec,
49  "Number of spillvsrrc spilled to stack as vec");
50 STATISTIC(NumStoreSPILLVSRRCAsGpr,
51  "Number of spillvsrrc spilled to stack as gpr");
52 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
53 STATISTIC(CmpIselsConverted,
54  "Number of ISELs that depend on comparison of constants converted");
55 STATISTIC(MissedConvertibleImmediateInstrs,
56  "Number of compare-immediate instructions fed by constants");
57 STATISTIC(NumRcRotatesConvertedToRcAnd,
58  "Number of record-form rotates converted to record-form andi");
59 
60 static cl::
61 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
62  cl::desc("Disable analysis for CTR loops"));
63 
64 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
65 cl::desc("Disable compare instruction optimization"), cl::Hidden);
66 
67 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
68 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
69 cl::Hidden);
70 
71 static cl::opt<bool>
72 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
73  cl::desc("Use the old (incorrect) instruction latency calculation"));
74 
75 // Index into the OpcodesForSpill array.
93  SOK_LastOpcodeSpill // This must be last on the enum.
94 };
95 
96 // Pin the vtable to this file.
97 void PPCInstrInfo::anchor() {}
98 
100  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
101  /* CatchRetOpcode */ -1,
102  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
103  Subtarget(STI), RI(STI.getTargetMachine()) {}
104 
105 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
106 /// this target when scheduling the DAG.
109  const ScheduleDAG *DAG) const {
110  unsigned Directive =
111  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
112  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
113  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
114  const InstrItineraryData *II =
115  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
116  return new ScoreboardHazardRecognizer(II, DAG);
117  }
118 
120 }
121 
122 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
123 /// to use for this target when scheduling the DAG.
126  const ScheduleDAG *DAG) const {
127  unsigned Directive =
128  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
129 
130  // FIXME: Leaving this as-is until we have POWER9 scheduling info
131  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
132  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
133 
134  // Most subtargets use a PPC970 recognizer.
135  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
136  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
137  assert(DAG->TII && "No InstrInfo?");
138 
139  return new PPCHazardRecognizer970(*DAG);
140  }
141 
142  return new ScoreboardHazardRecognizer(II, DAG);
143 }
144 
146  const MachineInstr &MI,
147  unsigned *PredCost) const {
148  if (!ItinData || UseOldLatencyCalc)
149  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
150 
151  // The default implementation of getInstrLatency calls getStageLatency, but
152  // getStageLatency does not do the right thing for us. While we have
153  // itinerary, most cores are fully pipelined, and so the itineraries only
154  // express the first part of the pipeline, not every stage. Instead, we need
155  // to use the listed output operand cycle number (using operand 0 here, which
156  // is an output).
157 
158  unsigned Latency = 1;
159  unsigned DefClass = MI.getDesc().getSchedClass();
160  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
161  const MachineOperand &MO = MI.getOperand(i);
162  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
163  continue;
164 
165  int Cycle = ItinData->getOperandCycle(DefClass, i);
166  if (Cycle < 0)
167  continue;
168 
169  Latency = std::max(Latency, (unsigned) Cycle);
170  }
171 
172  return Latency;
173 }
174 
176  const MachineInstr &DefMI, unsigned DefIdx,
177  const MachineInstr &UseMI,
178  unsigned UseIdx) const {
179  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
180  UseMI, UseIdx);
181 
182  if (!DefMI.getParent())
183  return Latency;
184 
185  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
186  Register Reg = DefMO.getReg();
187 
188  bool IsRegCR;
189  if (Register::isVirtualRegister(Reg)) {
190  const MachineRegisterInfo *MRI =
191  &DefMI.getParent()->getParent()->getRegInfo();
192  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
193  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
194  } else {
195  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
196  PPC::CRBITRCRegClass.contains(Reg);
197  }
198 
199  if (UseMI.isBranch() && IsRegCR) {
200  if (Latency < 0)
201  Latency = getInstrLatency(ItinData, DefMI);
202 
203  // On some cores, there is an additional delay between writing to a condition
204  // register, and using it from a branch.
205  unsigned Directive = Subtarget.getDarwinDirective();
206  switch (Directive) {
207  default: break;
208  case PPC::DIR_7400:
209  case PPC::DIR_750:
210  case PPC::DIR_970:
211  case PPC::DIR_E5500:
212  case PPC::DIR_PWR4:
213  case PPC::DIR_PWR5:
214  case PPC::DIR_PWR5X:
215  case PPC::DIR_PWR6:
216  case PPC::DIR_PWR6X:
217  case PPC::DIR_PWR7:
218  case PPC::DIR_PWR8:
219  // FIXME: Is this needed for POWER9?
220  Latency += 2;
221  break;
222  }
223  }
224 
225  return Latency;
226 }
227 
228 // This function does not list all associative and commutative operations, but
229 // only those worth feeding through the machine combiner in an attempt to
230 // reduce the critical path. Mostly, this means floating-point operations,
231 // because they have high latencies (compared to other operations, such and
232 // and/or, which are also associative and commutative, but have low latencies).
234  switch (Inst.getOpcode()) {
235  // FP Add:
236  case PPC::FADD:
237  case PPC::FADDS:
238  // FP Multiply:
239  case PPC::FMUL:
240  case PPC::FMULS:
241  // Altivec Add:
242  case PPC::VADDFP:
243  // VSX Add:
244  case PPC::XSADDDP:
245  case PPC::XVADDDP:
246  case PPC::XVADDSP:
247  case PPC::XSADDSP:
248  // VSX Multiply:
249  case PPC::XSMULDP:
250  case PPC::XVMULDP:
251  case PPC::XVMULSP:
252  case PPC::XSMULSP:
253  // QPX Add:
254  case PPC::QVFADD:
255  case PPC::QVFADDS:
256  case PPC::QVFADDSs:
257  // QPX Multiply:
258  case PPC::QVFMUL:
259  case PPC::QVFMULS:
260  case PPC::QVFMULSs:
261  return true;
262  default:
263  return false;
264  }
265 }
266 
268  MachineInstr &Root,
269  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
270  // Using the machine combiner in this way is potentially expensive, so
271  // restrict to when aggressive optimizations are desired.
273  return false;
274 
275  // FP reassociation is only legal when we don't need strict IEEE semantics.
277  return false;
278 
279  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
280 }
281 
282 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
284  unsigned &SrcReg, unsigned &DstReg,
285  unsigned &SubIdx) const {
286  switch (MI.getOpcode()) {
287  default: return false;
288  case PPC::EXTSW:
289  case PPC::EXTSW_32:
290  case PPC::EXTSW_32_64:
291  SrcReg = MI.getOperand(1).getReg();
292  DstReg = MI.getOperand(0).getReg();
293  SubIdx = PPC::sub_32;
294  return true;
295  }
296 }
297 
299  int &FrameIndex) const {
300  unsigned Opcode = MI.getOpcode();
301  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
302  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
303 
304  if (End != std::find(OpcodesForSpill, End, Opcode)) {
305  // Check for the operands added by addFrameReference (the immediate is the
306  // offset which defaults to 0).
307  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
308  MI.getOperand(2).isFI()) {
309  FrameIndex = MI.getOperand(2).getIndex();
310  return MI.getOperand(0).getReg();
311  }
312  }
313  return 0;
314 }
315 
316 // For opcodes with the ReMaterializable flag set, this function is called to
317 // verify the instruction is really rematable.
319  AliasAnalysis *AA) const {
320  switch (MI.getOpcode()) {
321  default:
322  // This function should only be called for opcodes with the ReMaterializable
323  // flag set.
324  llvm_unreachable("Unknown rematerializable operation!");
325  break;
326  case PPC::LI:
327  case PPC::LI8:
328  case PPC::LIS:
329  case PPC::LIS8:
330  case PPC::QVGPCI:
331  case PPC::ADDIStocHA8:
332  case PPC::ADDItocL:
333  case PPC::LOAD_STACK_GUARD:
334  case PPC::XXLXORz:
335  case PPC::XXLXORspz:
336  case PPC::XXLXORdpz:
337  case PPC::XXLEQVOnes:
338  case PPC::V_SET0B:
339  case PPC::V_SET0H:
340  case PPC::V_SET0:
341  case PPC::V_SETALLONESB:
342  case PPC::V_SETALLONESH:
343  case PPC::V_SETALLONES:
344  case PPC::CRSET:
345  case PPC::CRUNSET:
346  return true;
347  }
348  return false;
349 }
350 
352  int &FrameIndex) const {
353  unsigned Opcode = MI.getOpcode();
354  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
355  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
356 
357  if (End != std::find(OpcodesForSpill, End, Opcode)) {
358  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
359  MI.getOperand(2).isFI()) {
360  FrameIndex = MI.getOperand(2).getIndex();
361  return MI.getOperand(0).getReg();
362  }
363  }
364  return 0;
365 }
366 
368  unsigned OpIdx1,
369  unsigned OpIdx2) const {
370  MachineFunction &MF = *MI.getParent()->getParent();
371 
372  // Normal instructions can be commuted the obvious way.
373  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
374  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
375  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
376  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
377  // changing the relative order of the mask operands might change what happens
378  // to the high-bits of the mask (and, thus, the result).
379 
380  // Cannot commute if it has a non-zero rotate count.
381  if (MI.getOperand(3).getImm() != 0)
382  return nullptr;
383 
384  // If we have a zero rotate count, we have:
385  // M = mask(MB,ME)
386  // Op0 = (Op1 & ~M) | (Op2 & M)
387  // Change this to:
388  // M = mask((ME+1)&31, (MB-1)&31)
389  // Op0 = (Op2 & ~M) | (Op1 & M)
390 
391  // Swap op1/op2
392  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
393  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
394  Register Reg0 = MI.getOperand(0).getReg();
395  Register Reg1 = MI.getOperand(1).getReg();
396  Register Reg2 = MI.getOperand(2).getReg();
397  unsigned SubReg1 = MI.getOperand(1).getSubReg();
398  unsigned SubReg2 = MI.getOperand(2).getSubReg();
399  bool Reg1IsKill = MI.getOperand(1).isKill();
400  bool Reg2IsKill = MI.getOperand(2).isKill();
401  bool ChangeReg0 = false;
402  // If machine instrs are no longer in two-address forms, update
403  // destination register as well.
404  if (Reg0 == Reg1) {
405  // Must be two address instruction!
407  "Expecting a two-address instruction!");
408  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
409  Reg2IsKill = false;
410  ChangeReg0 = true;
411  }
412 
413  // Masks.
414  unsigned MB = MI.getOperand(4).getImm();
415  unsigned ME = MI.getOperand(5).getImm();
416 
417  // We can't commute a trivial mask (there is no way to represent an all-zero
418  // mask).
419  if (MB == 0 && ME == 31)
420  return nullptr;
421 
422  if (NewMI) {
423  // Create a new instruction.
424  Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
425  bool Reg0IsDead = MI.getOperand(0).isDead();
426  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
427  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
428  .addReg(Reg2, getKillRegState(Reg2IsKill))
429  .addReg(Reg1, getKillRegState(Reg1IsKill))
430  .addImm((ME + 1) & 31)
431  .addImm((MB - 1) & 31);
432  }
433 
434  if (ChangeReg0) {
435  MI.getOperand(0).setReg(Reg2);
436  MI.getOperand(0).setSubReg(SubReg2);
437  }
438  MI.getOperand(2).setReg(Reg1);
439  MI.getOperand(1).setReg(Reg2);
440  MI.getOperand(2).setSubReg(SubReg1);
441  MI.getOperand(1).setSubReg(SubReg2);
442  MI.getOperand(2).setIsKill(Reg1IsKill);
443  MI.getOperand(1).setIsKill(Reg2IsKill);
444 
445  // Swap the mask around.
446  MI.getOperand(4).setImm((ME + 1) & 31);
447  MI.getOperand(5).setImm((MB - 1) & 31);
448  return &MI;
449 }
450 
452  unsigned &SrcOpIdx2) const {
453  // For VSX A-Type FMA instructions, it is the first two operands that can be
454  // commuted, however, because the non-encoded tied input operand is listed
455  // first, the operands to swap are actually the second and third.
456 
457  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
458  if (AltOpc == -1)
459  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
460 
461  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
462  // and SrcOpIdx2.
463  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
464 }
465 
468  // This function is used for scheduling, and the nop wanted here is the type
469  // that terminates dispatch groups on the POWER cores.
470  unsigned Directive = Subtarget.getDarwinDirective();
471  unsigned Opcode;
472  switch (Directive) {
473  default: Opcode = PPC::NOP; break;
474  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
475  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
476  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
477  // FIXME: Update when POWER9 scheduling model is ready.
478  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
479  }
480 
481  DebugLoc DL;
482  BuildMI(MBB, MI, DL, get(Opcode));
483 }
484 
485 /// Return the noop instruction to use for a noop.
486 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
487  NopInst.setOpcode(PPC::NOP);
488 }
489 
490 // Branch analysis.
491 // Note: If the condition register is set to CTR or CTR8 then this is a
492 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
494  MachineBasicBlock *&TBB,
495  MachineBasicBlock *&FBB,
497  bool AllowModify) const {
498  bool isPPC64 = Subtarget.isPPC64();
499 
500  // If the block has no terminators, it just falls into the block after it.
502  if (I == MBB.end())
503  return false;
504 
505  if (!isUnpredicatedTerminator(*I))
506  return false;
507 
508  if (AllowModify) {
509  // If the BB ends with an unconditional branch to the fallthrough BB,
510  // we eliminate the branch instruction.
511  if (I->getOpcode() == PPC::B &&
512  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
513  I->eraseFromParent();
514 
515  // We update iterator after deleting the last branch.
516  I = MBB.getLastNonDebugInstr();
517  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
518  return false;
519  }
520  }
521 
522  // Get the last instruction in the block.
523  MachineInstr &LastInst = *I;
524 
525  // If there is only one terminator instruction, process it.
526  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
527  if (LastInst.getOpcode() == PPC::B) {
528  if (!LastInst.getOperand(0).isMBB())
529  return true;
530  TBB = LastInst.getOperand(0).getMBB();
531  return false;
532  } else if (LastInst.getOpcode() == PPC::BCC) {
533  if (!LastInst.getOperand(2).isMBB())
534  return true;
535  // Block ends with fall-through condbranch.
536  TBB = LastInst.getOperand(2).getMBB();
537  Cond.push_back(LastInst.getOperand(0));
538  Cond.push_back(LastInst.getOperand(1));
539  return false;
540  } else if (LastInst.getOpcode() == PPC::BC) {
541  if (!LastInst.getOperand(1).isMBB())
542  return true;
543  // Block ends with fall-through condbranch.
544  TBB = LastInst.getOperand(1).getMBB();
546  Cond.push_back(LastInst.getOperand(0));
547  return false;
548  } else if (LastInst.getOpcode() == PPC::BCn) {
549  if (!LastInst.getOperand(1).isMBB())
550  return true;
551  // Block ends with fall-through condbranch.
552  TBB = LastInst.getOperand(1).getMBB();
554  Cond.push_back(LastInst.getOperand(0));
555  return false;
556  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
557  LastInst.getOpcode() == PPC::BDNZ) {
558  if (!LastInst.getOperand(0).isMBB())
559  return true;
560  if (DisableCTRLoopAnal)
561  return true;
562  TBB = LastInst.getOperand(0).getMBB();
564  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
565  true));
566  return false;
567  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
568  LastInst.getOpcode() == PPC::BDZ) {
569  if (!LastInst.getOperand(0).isMBB())
570  return true;
571  if (DisableCTRLoopAnal)
572  return true;
573  TBB = LastInst.getOperand(0).getMBB();
575  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
576  true));
577  return false;
578  }
579 
580  // Otherwise, don't know what this is.
581  return true;
582  }
583 
584  // Get the instruction before it if it's a terminator.
585  MachineInstr &SecondLastInst = *I;
586 
587  // If there are three terminators, we don't know what sort of block this is.
588  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
589  return true;
590 
591  // If the block ends with PPC::B and PPC:BCC, handle it.
592  if (SecondLastInst.getOpcode() == PPC::BCC &&
593  LastInst.getOpcode() == PPC::B) {
594  if (!SecondLastInst.getOperand(2).isMBB() ||
595  !LastInst.getOperand(0).isMBB())
596  return true;
597  TBB = SecondLastInst.getOperand(2).getMBB();
598  Cond.push_back(SecondLastInst.getOperand(0));
599  Cond.push_back(SecondLastInst.getOperand(1));
600  FBB = LastInst.getOperand(0).getMBB();
601  return false;
602  } else if (SecondLastInst.getOpcode() == PPC::BC &&
603  LastInst.getOpcode() == PPC::B) {
604  if (!SecondLastInst.getOperand(1).isMBB() ||
605  !LastInst.getOperand(0).isMBB())
606  return true;
607  TBB = SecondLastInst.getOperand(1).getMBB();
609  Cond.push_back(SecondLastInst.getOperand(0));
610  FBB = LastInst.getOperand(0).getMBB();
611  return false;
612  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
613  LastInst.getOpcode() == PPC::B) {
614  if (!SecondLastInst.getOperand(1).isMBB() ||
615  !LastInst.getOperand(0).isMBB())
616  return true;
617  TBB = SecondLastInst.getOperand(1).getMBB();
619  Cond.push_back(SecondLastInst.getOperand(0));
620  FBB = LastInst.getOperand(0).getMBB();
621  return false;
622  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
623  SecondLastInst.getOpcode() == PPC::BDNZ) &&
624  LastInst.getOpcode() == PPC::B) {
625  if (!SecondLastInst.getOperand(0).isMBB() ||
626  !LastInst.getOperand(0).isMBB())
627  return true;
628  if (DisableCTRLoopAnal)
629  return true;
630  TBB = SecondLastInst.getOperand(0).getMBB();
632  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
633  true));
634  FBB = LastInst.getOperand(0).getMBB();
635  return false;
636  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
637  SecondLastInst.getOpcode() == PPC::BDZ) &&
638  LastInst.getOpcode() == PPC::B) {
639  if (!SecondLastInst.getOperand(0).isMBB() ||
640  !LastInst.getOperand(0).isMBB())
641  return true;
642  if (DisableCTRLoopAnal)
643  return true;
644  TBB = SecondLastInst.getOperand(0).getMBB();
646  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
647  true));
648  FBB = LastInst.getOperand(0).getMBB();
649  return false;
650  }
651 
652  // If the block ends with two PPC:Bs, handle it. The second one is not
653  // executed, so remove it.
654  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
655  if (!SecondLastInst.getOperand(0).isMBB())
656  return true;
657  TBB = SecondLastInst.getOperand(0).getMBB();
658  I = LastInst;
659  if (AllowModify)
660  I->eraseFromParent();
661  return false;
662  }
663 
664  // Otherwise, can't handle this.
665  return true;
666 }
667 
669  int *BytesRemoved) const {
670  assert(!BytesRemoved && "code size not handled");
671 
673  if (I == MBB.end())
674  return 0;
675 
676  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
677  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
678  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
679  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
680  return 0;
681 
682  // Remove the branch.
683  I->eraseFromParent();
684 
685  I = MBB.end();
686 
687  if (I == MBB.begin()) return 1;
688  --I;
689  if (I->getOpcode() != PPC::BCC &&
690  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
691  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
692  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
693  return 1;
694 
695  // Remove the branch.
696  I->eraseFromParent();
697  return 2;
698 }
699 
701  MachineBasicBlock *TBB,
702  MachineBasicBlock *FBB,
704  const DebugLoc &DL,
705  int *BytesAdded) const {
706  // Shouldn't be a fall through.
707  assert(TBB && "insertBranch must not be told to insert a fallthrough");
708  assert((Cond.size() == 2 || Cond.size() == 0) &&
709  "PPC branch conditions have two components!");
710  assert(!BytesAdded && "code size not handled");
711 
712  bool isPPC64 = Subtarget.isPPC64();
713 
714  // One-way branch.
715  if (!FBB) {
716  if (Cond.empty()) // Unconditional branch
717  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
718  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
719  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
720  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
721  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
722  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
723  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
724  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
725  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
726  else // Conditional branch
727  BuildMI(&MBB, DL, get(PPC::BCC))
728  .addImm(Cond[0].getImm())
729  .add(Cond[1])
730  .addMBB(TBB);
731  return 1;
732  }
733 
734  // Two-way Conditional Branch.
735  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
736  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
737  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
738  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
739  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
740  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
741  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
742  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
743  else
744  BuildMI(&MBB, DL, get(PPC::BCC))
745  .addImm(Cond[0].getImm())
746  .add(Cond[1])
747  .addMBB(TBB);
748  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
749  return 2;
750 }
751 
752 // Select analysis.
755  unsigned TrueReg, unsigned FalseReg,
756  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
757  if (Cond.size() != 2)
758  return false;
759 
760  // If this is really a bdnz-like condition, then it cannot be turned into a
761  // select.
762  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
763  return false;
764 
765  // Check register classes.
766  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
767  const TargetRegisterClass *RC =
768  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
769  if (!RC)
770  return false;
771 
772  // isel is for regular integer GPRs only.
773  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
774  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
775  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
776  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
777  return false;
778 
779  // FIXME: These numbers are for the A2, how well they work for other cores is
780  // an open question. On the A2, the isel instruction has a 2-cycle latency
781  // but single-cycle throughput. These numbers are used in combination with
782  // the MispredictPenalty setting from the active SchedMachineModel.
783  CondCycles = 1;
784  TrueCycles = 1;
785  FalseCycles = 1;
786 
787  return true;
788 }
789 
792  const DebugLoc &dl, unsigned DestReg,
793  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
794  unsigned FalseReg) const {
795  assert(Cond.size() == 2 &&
796  "PPC branch conditions have two components!");
797 
798  // Get the register classes.
800  const TargetRegisterClass *RC =
801  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
802  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
803 
804  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
805  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
806  assert((Is64Bit ||
807  PPC::GPRCRegClass.hasSubClassEq(RC) ||
808  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
809  "isel is for regular integer GPRs only");
810 
811  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
812  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
813 
814  unsigned SubIdx = 0;
815  bool SwapOps = false;
816  switch (SelectPred) {
817  case PPC::PRED_EQ:
818  case PPC::PRED_EQ_MINUS:
819  case PPC::PRED_EQ_PLUS:
820  SubIdx = PPC::sub_eq; SwapOps = false; break;
821  case PPC::PRED_NE:
822  case PPC::PRED_NE_MINUS:
823  case PPC::PRED_NE_PLUS:
824  SubIdx = PPC::sub_eq; SwapOps = true; break;
825  case PPC::PRED_LT:
826  case PPC::PRED_LT_MINUS:
827  case PPC::PRED_LT_PLUS:
828  SubIdx = PPC::sub_lt; SwapOps = false; break;
829  case PPC::PRED_GE:
830  case PPC::PRED_GE_MINUS:
831  case PPC::PRED_GE_PLUS:
832  SubIdx = PPC::sub_lt; SwapOps = true; break;
833  case PPC::PRED_GT:
834  case PPC::PRED_GT_MINUS:
835  case PPC::PRED_GT_PLUS:
836  SubIdx = PPC::sub_gt; SwapOps = false; break;
837  case PPC::PRED_LE:
838  case PPC::PRED_LE_MINUS:
839  case PPC::PRED_LE_PLUS:
840  SubIdx = PPC::sub_gt; SwapOps = true; break;
841  case PPC::PRED_UN:
842  case PPC::PRED_UN_MINUS:
843  case PPC::PRED_UN_PLUS:
844  SubIdx = PPC::sub_un; SwapOps = false; break;
845  case PPC::PRED_NU:
846  case PPC::PRED_NU_MINUS:
847  case PPC::PRED_NU_PLUS:
848  SubIdx = PPC::sub_un; SwapOps = true; break;
849  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
850  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
851  }
852 
853  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
854  SecondReg = SwapOps ? TrueReg : FalseReg;
855 
856  // The first input register of isel cannot be r0. If it is a member
857  // of a register class that can be r0, then copy it first (the
858  // register allocator should eliminate the copy).
859  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
860  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
861  const TargetRegisterClass *FirstRC =
862  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
863  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
864  unsigned OldFirstReg = FirstReg;
865  FirstReg = MRI.createVirtualRegister(FirstRC);
866  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
867  .addReg(OldFirstReg);
868  }
869 
870  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
871  .addReg(FirstReg).addReg(SecondReg)
872  .addReg(Cond[1].getReg(), 0, SubIdx);
873 }
874 
875 static unsigned getCRBitValue(unsigned CRBit) {
876  unsigned Ret = 4;
877  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
878  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
879  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
880  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
881  Ret = 3;
882  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
883  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
884  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
885  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
886  Ret = 2;
887  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
888  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
889  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
890  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
891  Ret = 1;
892  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
893  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
894  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
895  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
896  Ret = 0;
897 
898  assert(Ret != 4 && "Invalid CR bit register");
899  return Ret;
900 }
901 
904  const DebugLoc &DL, unsigned DestReg,
905  unsigned SrcReg, bool KillSrc) const {
906  // We can end up with self copies and similar things as a result of VSX copy
907  // legalization. Promote them here.
909  if (PPC::F8RCRegClass.contains(DestReg) &&
910  PPC::VSRCRegClass.contains(SrcReg)) {
911  unsigned SuperReg =
912  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
913 
914  if (VSXSelfCopyCrash && SrcReg == SuperReg)
915  llvm_unreachable("nop VSX copy");
916 
917  DestReg = SuperReg;
918  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
919  PPC::VSRCRegClass.contains(DestReg)) {
920  unsigned SuperReg =
921  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
922 
923  if (VSXSelfCopyCrash && DestReg == SuperReg)
924  llvm_unreachable("nop VSX copy");
925 
926  SrcReg = SuperReg;
927  }
928 
929  // Different class register copy
930  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
931  PPC::GPRCRegClass.contains(DestReg)) {
932  unsigned CRReg = getCRFromCRBit(SrcReg);
933  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
934  getKillRegState(KillSrc);
935  // Rotate the CR bit in the CR fields to be the least significant bit and
936  // then mask with 0x1 (MB = ME = 31).
937  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
938  .addReg(DestReg, RegState::Kill)
939  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
940  .addImm(31)
941  .addImm(31);
942  return;
943  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
944  PPC::G8RCRegClass.contains(DestReg)) {
945  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
946  getKillRegState(KillSrc);
947  return;
948  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
949  PPC::GPRCRegClass.contains(DestReg)) {
950  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
951  getKillRegState(KillSrc);
952  return;
953  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
954  PPC::VSFRCRegClass.contains(DestReg)) {
955  assert(Subtarget.hasDirectMove() &&
956  "Subtarget doesn't support directmove, don't know how to copy.");
957  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
958  NumGPRtoVSRSpill++;
959  getKillRegState(KillSrc);
960  return;
961  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
962  PPC::G8RCRegClass.contains(DestReg)) {
963  assert(Subtarget.hasDirectMove() &&
964  "Subtarget doesn't support directmove, don't know how to copy.");
965  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
966  getKillRegState(KillSrc);
967  return;
968  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
969  PPC::GPRCRegClass.contains(DestReg)) {
970  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
971  getKillRegState(KillSrc);
972  return;
973  } else if (PPC::GPRCRegClass.contains(SrcReg) &&
974  PPC::SPERCRegClass.contains(DestReg)) {
975  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
976  getKillRegState(KillSrc);
977  return;
978  }
979 
980  unsigned Opc;
981  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
982  Opc = PPC::OR;
983  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
984  Opc = PPC::OR8;
985  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
986  Opc = PPC::FMR;
987  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
988  Opc = PPC::MCRF;
989  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
990  Opc = PPC::VOR;
991  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
992  // There are two different ways this can be done:
993  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
994  // issue in VSU pipeline 0.
995  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
996  // can go to either pipeline.
997  // We'll always use xxlor here, because in practically all cases where
998  // copies are generated, they are close enough to some use that the
999  // lower-latency form is preferable.
1000  Opc = PPC::XXLOR;
1001  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1002  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1003  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1004  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
1005  Opc = PPC::QVFMR;
1006  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
1007  Opc = PPC::QVFMRs;
1008  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
1009  Opc = PPC::QVFMRb;
1010  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1011  Opc = PPC::CROR;
1012  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1013  Opc = PPC::EVOR;
1014  else
1015  llvm_unreachable("Impossible reg-to-reg copy");
1016 
1017  const MCInstrDesc &MCID = get(Opc);
1018  if (MCID.getNumOperands() == 3)
1019  BuildMI(MBB, I, DL, MCID, DestReg)
1020  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1021  else
1022  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1023 }
1024 
1026  const TargetRegisterClass *RC)
1027  const {
1028  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1029  int OpcodeIndex = 0;
1030 
1031  if (RC != nullptr) {
1032  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1033  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1034  OpcodeIndex = SOK_Int4Spill;
1035  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1036  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1037  OpcodeIndex = SOK_Int8Spill;
1038  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1039  OpcodeIndex = SOK_Float8Spill;
1040  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1041  OpcodeIndex = SOK_Float4Spill;
1042  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1043  OpcodeIndex = SOK_SPESpill;
1044  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1045  OpcodeIndex = SOK_CRSpill;
1046  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1047  OpcodeIndex = SOK_CRBitSpill;
1048  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1049  OpcodeIndex = SOK_VRVectorSpill;
1050  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1051  OpcodeIndex = SOK_VSXVectorSpill;
1052  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1053  OpcodeIndex = SOK_VectorFloat8Spill;
1054  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1055  OpcodeIndex = SOK_VectorFloat4Spill;
1056  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1057  OpcodeIndex = SOK_VRSaveSpill;
1058  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1059  OpcodeIndex = SOK_QuadFloat8Spill;
1060  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1061  OpcodeIndex = SOK_QuadFloat4Spill;
1062  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1063  OpcodeIndex = SOK_QuadBitSpill;
1064  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1065  OpcodeIndex = SOK_SpillToVSR;
1066  } else {
1067  llvm_unreachable("Unknown regclass!");
1068  }
1069  } else {
1070  if (PPC::GPRCRegClass.contains(Reg) ||
1071  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1072  OpcodeIndex = SOK_Int4Spill;
1073  } else if (PPC::G8RCRegClass.contains(Reg) ||
1074  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1075  OpcodeIndex = SOK_Int8Spill;
1076  } else if (PPC::F8RCRegClass.contains(Reg)) {
1077  OpcodeIndex = SOK_Float8Spill;
1078  } else if (PPC::F4RCRegClass.contains(Reg)) {
1079  OpcodeIndex = SOK_Float4Spill;
1080  } else if (PPC::SPERCRegClass.contains(Reg)) {
1081  OpcodeIndex = SOK_SPESpill;
1082  } else if (PPC::CRRCRegClass.contains(Reg)) {
1083  OpcodeIndex = SOK_CRSpill;
1084  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1085  OpcodeIndex = SOK_CRBitSpill;
1086  } else if (PPC::VRRCRegClass.contains(Reg)) {
1087  OpcodeIndex = SOK_VRVectorSpill;
1088  } else if (PPC::VSRCRegClass.contains(Reg)) {
1089  OpcodeIndex = SOK_VSXVectorSpill;
1090  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1091  OpcodeIndex = SOK_VectorFloat8Spill;
1092  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1093  OpcodeIndex = SOK_VectorFloat4Spill;
1094  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1095  OpcodeIndex = SOK_VRSaveSpill;
1096  } else if (PPC::QFRCRegClass.contains(Reg)) {
1097  OpcodeIndex = SOK_QuadFloat8Spill;
1098  } else if (PPC::QSRCRegClass.contains(Reg)) {
1099  OpcodeIndex = SOK_QuadFloat4Spill;
1100  } else if (PPC::QBRCRegClass.contains(Reg)) {
1101  OpcodeIndex = SOK_QuadBitSpill;
1102  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1103  OpcodeIndex = SOK_SpillToVSR;
1104  } else {
1105  llvm_unreachable("Unknown regclass!");
1106  }
1107  }
1108  return OpcodesForSpill[OpcodeIndex];
1109 }
1110 
1111 unsigned
1113  const TargetRegisterClass *RC) const {
1114  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1115  int OpcodeIndex = 0;
1116 
1117  if (RC != nullptr) {
1118  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1119  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1120  OpcodeIndex = SOK_Int4Spill;
1121  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1122  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1123  OpcodeIndex = SOK_Int8Spill;
1124  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1125  OpcodeIndex = SOK_Float8Spill;
1126  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1127  OpcodeIndex = SOK_Float4Spill;
1128  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1129  OpcodeIndex = SOK_SPESpill;
1130  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1131  OpcodeIndex = SOK_CRSpill;
1132  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1133  OpcodeIndex = SOK_CRBitSpill;
1134  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1135  OpcodeIndex = SOK_VRVectorSpill;
1136  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1137  OpcodeIndex = SOK_VSXVectorSpill;
1138  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1139  OpcodeIndex = SOK_VectorFloat8Spill;
1140  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1141  OpcodeIndex = SOK_VectorFloat4Spill;
1142  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1143  OpcodeIndex = SOK_VRSaveSpill;
1144  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1145  OpcodeIndex = SOK_QuadFloat8Spill;
1146  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1147  OpcodeIndex = SOK_QuadFloat4Spill;
1148  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1149  OpcodeIndex = SOK_QuadBitSpill;
1150  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1151  OpcodeIndex = SOK_SpillToVSR;
1152  } else {
1153  llvm_unreachable("Unknown regclass!");
1154  }
1155  } else {
1156  if (PPC::GPRCRegClass.contains(Reg) ||
1157  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1158  OpcodeIndex = SOK_Int4Spill;
1159  } else if (PPC::G8RCRegClass.contains(Reg) ||
1160  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1161  OpcodeIndex = SOK_Int8Spill;
1162  } else if (PPC::F8RCRegClass.contains(Reg)) {
1163  OpcodeIndex = SOK_Float8Spill;
1164  } else if (PPC::F4RCRegClass.contains(Reg)) {
1165  OpcodeIndex = SOK_Float4Spill;
1166  } else if (PPC::SPERCRegClass.contains(Reg)) {
1167  OpcodeIndex = SOK_SPESpill;
1168  } else if (PPC::CRRCRegClass.contains(Reg)) {
1169  OpcodeIndex = SOK_CRSpill;
1170  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1171  OpcodeIndex = SOK_CRBitSpill;
1172  } else if (PPC::VRRCRegClass.contains(Reg)) {
1173  OpcodeIndex = SOK_VRVectorSpill;
1174  } else if (PPC::VSRCRegClass.contains(Reg)) {
1175  OpcodeIndex = SOK_VSXVectorSpill;
1176  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1177  OpcodeIndex = SOK_VectorFloat8Spill;
1178  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1179  OpcodeIndex = SOK_VectorFloat4Spill;
1180  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1181  OpcodeIndex = SOK_VRSaveSpill;
1182  } else if (PPC::QFRCRegClass.contains(Reg)) {
1183  OpcodeIndex = SOK_QuadFloat8Spill;
1184  } else if (PPC::QSRCRegClass.contains(Reg)) {
1185  OpcodeIndex = SOK_QuadFloat4Spill;
1186  } else if (PPC::QBRCRegClass.contains(Reg)) {
1187  OpcodeIndex = SOK_QuadBitSpill;
1188  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1189  OpcodeIndex = SOK_SpillToVSR;
1190  } else {
1191  llvm_unreachable("Unknown regclass!");
1192  }
1193  }
1194  return OpcodesForSpill[OpcodeIndex];
1195 }
1196 
1197 void PPCInstrInfo::StoreRegToStackSlot(
1198  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1199  const TargetRegisterClass *RC,
1200  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1201  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1202  DebugLoc DL;
1203 
1204  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1205  FuncInfo->setHasSpills();
1206 
1208  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1209  FrameIdx));
1210 
1211  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1212  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1213  FuncInfo->setSpillsCR();
1214 
1215  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1216  FuncInfo->setSpillsVRSAVE();
1217 
1218  if (isXFormMemOp(Opcode))
1219  FuncInfo->setHasNonRISpills();
1220 }
1221 
1224  unsigned SrcReg, bool isKill,
1225  int FrameIdx,
1226  const TargetRegisterClass *RC,
1227  const TargetRegisterInfo *TRI) const {
1228  MachineFunction &MF = *MBB.getParent();
1230 
1231  // We need to avoid a situation in which the value from a VRRC register is
1232  // spilled using an Altivec instruction and reloaded into a VSRC register
1233  // using a VSX instruction. The issue with this is that the VSX
1234  // load/store instructions swap the doublewords in the vector and the Altivec
1235  // ones don't. The register classes on the spill/reload may be different if
1236  // the register is defined using an Altivec instruction and is then used by a
1237  // VSX instruction.
1238  RC = updatedRC(RC);
1239 
1240  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1241 
1242  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1243  MBB.insert(MI, NewMIs[i]);
1244 
1245  const MachineFrameInfo &MFI = MF.getFrameInfo();
1247  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1249  MFI.getObjectAlignment(FrameIdx));
1250  NewMIs.back()->addMemOperand(MF, MMO);
1251 }
1252 
1253 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1254  unsigned DestReg, int FrameIdx,
1255  const TargetRegisterClass *RC,
1257  const {
1258  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1259  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1260  FrameIdx));
1261  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1262 
1263  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1264  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1265  FuncInfo->setSpillsCR();
1266 
1267  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1268  FuncInfo->setSpillsVRSAVE();
1269 
1270  if (isXFormMemOp(Opcode))
1271  FuncInfo->setHasNonRISpills();
1272 }
1273 
1274 void
1277  unsigned DestReg, int FrameIdx,
1278  const TargetRegisterClass *RC,
1279  const TargetRegisterInfo *TRI) const {
1280  MachineFunction &MF = *MBB.getParent();
1282  DebugLoc DL;
1283  if (MI != MBB.end()) DL = MI->getDebugLoc();
1284 
1285  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1286  FuncInfo->setHasSpills();
1287 
1288  // We need to avoid a situation in which the value from a VRRC register is
1289  // spilled using an Altivec instruction and reloaded into a VSRC register
1290  // using a VSX instruction. The issue with this is that the VSX
1291  // load/store instructions swap the doublewords in the vector and the Altivec
1292  // ones don't. The register classes on the spill/reload may be different if
1293  // the register is defined using an Altivec instruction and is then used by a
1294  // VSX instruction.
1295  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1296  RC = &PPC::VSRCRegClass;
1297 
1298  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1299 
1300  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1301  MBB.insert(MI, NewMIs[i]);
1302 
1303  const MachineFrameInfo &MFI = MF.getFrameInfo();
1305  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1307  MFI.getObjectAlignment(FrameIdx));
1308  NewMIs.back()->addMemOperand(MF, MMO);
1309 }
1310 
1311 bool PPCInstrInfo::
1313  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1314  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1315  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1316  else
1317  // Leave the CR# the same, but invert the condition.
1318  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1319  return false;
1320 }
1321 
1323  unsigned Reg, MachineRegisterInfo *MRI) const {
1324  // For some instructions, it is legal to fold ZERO into the RA register field.
1325  // A zero immediate should always be loaded with a single li.
1326  unsigned DefOpc = DefMI.getOpcode();
1327  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1328  return false;
1329  if (!DefMI.getOperand(1).isImm())
1330  return false;
1331  if (DefMI.getOperand(1).getImm() != 0)
1332  return false;
1333 
1334  // Note that we cannot here invert the arguments of an isel in order to fold
1335  // a ZERO into what is presented as the second argument. All we have here
1336  // is the condition bit, and that might come from a CR-logical bit operation.
1337 
1338  const MCInstrDesc &UseMCID = UseMI.getDesc();
1339 
1340  // Only fold into real machine instructions.
1341  if (UseMCID.isPseudo())
1342  return false;
1343 
1344  unsigned UseIdx;
1345  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1346  if (UseMI.getOperand(UseIdx).isReg() &&
1347  UseMI.getOperand(UseIdx).getReg() == Reg)
1348  break;
1349 
1350  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1351  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1352 
1353  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1354 
1355  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1356  // register (which might also be specified as a pointer class kind).
1357  if (UseInfo->isLookupPtrRegClass()) {
1358  if (UseInfo->RegClass /* Kind */ != 1)
1359  return false;
1360  } else {
1361  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1362  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1363  return false;
1364  }
1365 
1366  // Make sure this is not tied to an output register (or otherwise
1367  // constrained). This is true for ST?UX registers, for example, which
1368  // are tied to their output registers.
1369  if (UseInfo->Constraints != 0)
1370  return false;
1371 
1372  unsigned ZeroReg;
1373  if (UseInfo->isLookupPtrRegClass()) {
1374  bool isPPC64 = Subtarget.isPPC64();
1375  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1376  } else {
1377  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1378  PPC::ZERO8 : PPC::ZERO;
1379  }
1380 
1381  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1382  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1383 
1384  if (DeleteDef)
1385  DefMI.eraseFromParent();
1386 
1387  return true;
1388 }
1389 
1391  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1392  I != IE; ++I)
1393  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1394  return true;
1395  return false;
1396 }
1397 
1398 // We should make sure that, if we're going to predicate both sides of a
1399 // condition (a diamond), that both sides don't define the counter register. We
1400 // can predicate counter-decrement-based branches, but while that predicates
1401 // the branching, it does not predicate the counter decrement. If we tried to
1402 // merge the triangle into one predicated block, we'd decrement the counter
1403 // twice.
1405  unsigned NumT, unsigned ExtraT,
1406  MachineBasicBlock &FMBB,
1407  unsigned NumF, unsigned ExtraF,
1408  BranchProbability Probability) const {
1409  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1410 }
1411 
1412 
1414  // The predicated branches are identified by their type, not really by the
1415  // explicit presence of a predicate. Furthermore, some of them can be
1416  // predicated more than once. Because if conversion won't try to predicate
1417  // any instruction which already claims to be predicated (by returning true
1418  // here), always return false. In doing so, we let isPredicable() be the
1419  // final word on whether not the instruction can be (further) predicated.
1420 
1421  return false;
1422 }
1423 
1425  if (!MI.isTerminator())
1426  return false;
1427 
1428  // Conditional branch is a special case.
1429  if (MI.isBranch() && !MI.isBarrier())
1430  return true;
1431 
1432  return !isPredicated(MI);
1433 }
1434 
1436  ArrayRef<MachineOperand> Pred) const {
1437  unsigned OpC = MI.getOpcode();
1438  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1439  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1440  bool isPPC64 = Subtarget.isPPC64();
1441  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1442  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1443  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1444  MI.setDesc(get(PPC::BCLR));
1445  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1446  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1447  MI.setDesc(get(PPC::BCLRn));
1448  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1449  } else {
1450  MI.setDesc(get(PPC::BCCLR));
1452  .addImm(Pred[0].getImm())
1453  .add(Pred[1]);
1454  }
1455 
1456  return true;
1457  } else if (OpC == PPC::B) {
1458  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1459  bool isPPC64 = Subtarget.isPPC64();
1460  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1461  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1462  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1463  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1464  MI.RemoveOperand(0);
1465 
1466  MI.setDesc(get(PPC::BC));
1468  .add(Pred[1])
1469  .addMBB(MBB);
1470  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1471  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1472  MI.RemoveOperand(0);
1473 
1474  MI.setDesc(get(PPC::BCn));
1476  .add(Pred[1])
1477  .addMBB(MBB);
1478  } else {
1479  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1480  MI.RemoveOperand(0);
1481 
1482  MI.setDesc(get(PPC::BCC));
1484  .addImm(Pred[0].getImm())
1485  .add(Pred[1])
1486  .addMBB(MBB);
1487  }
1488 
1489  return true;
1490  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
1491  OpC == PPC::BCTRL8) {
1492  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1493  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1494 
1495  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1496  bool isPPC64 = Subtarget.isPPC64();
1497 
1498  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1499  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1500  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1501  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1502  return true;
1503  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1504  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1505  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1506  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1507  return true;
1508  }
1509 
1510  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1511  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1513  .addImm(Pred[0].getImm())
1514  .add(Pred[1]);
1515  return true;
1516  }
1517 
1518  return false;
1519 }
1520 
1522  ArrayRef<MachineOperand> Pred2) const {
1523  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1524  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1525 
1526  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1527  return false;
1528  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1529  return false;
1530 
1531  // P1 can only subsume P2 if they test the same condition register.
1532  if (Pred1[1].getReg() != Pred2[1].getReg())
1533  return false;
1534 
1535  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1536  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1537 
1538  if (P1 == P2)
1539  return true;
1540 
1541  // Does P1 subsume P2, e.g. GE subsumes GT.
1542  if (P1 == PPC::PRED_LE &&
1543  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1544  return true;
1545  if (P1 == PPC::PRED_GE &&
1546  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1547  return true;
1548 
1549  return false;
1550 }
1551 
1553  std::vector<MachineOperand> &Pred) const {
1554  // Note: At the present time, the contents of Pred from this function is
1555  // unused by IfConversion. This implementation follows ARM by pushing the
1556  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1557  // predicate, instructions defining CTR or CTR8 are also included as
1558  // predicate-defining instructions.
1559 
1560  const TargetRegisterClass *RCs[] =
1561  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1562  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1563 
1564  bool Found = false;
1565  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1566  const MachineOperand &MO = MI.getOperand(i);
1567  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1568  const TargetRegisterClass *RC = RCs[c];
1569  if (MO.isReg()) {
1570  if (MO.isDef() && RC->contains(MO.getReg())) {
1571  Pred.push_back(MO);
1572  Found = true;
1573  }
1574  } else if (MO.isRegMask()) {
1575  for (TargetRegisterClass::iterator I = RC->begin(),
1576  IE = RC->end(); I != IE; ++I)
1577  if (MO.clobbersPhysReg(*I)) {
1578  Pred.push_back(MO);
1579  Found = true;
1580  }
1581  }
1582  }
1583  }
1584 
1585  return Found;
1586 }
1587 
1589  unsigned OpC = MI.getOpcode();
1590  switch (OpC) {
1591  default:
1592  return false;
1593  case PPC::B:
1594  case PPC::BLR:
1595  case PPC::BLR8:
1596  case PPC::BCTR:
1597  case PPC::BCTR8:
1598  case PPC::BCTRL:
1599  case PPC::BCTRL8:
1600  return true;
1601  }
1602 }
1603 
1604 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1605  unsigned &SrcReg2, int &Mask,
1606  int &Value) const {
1607  unsigned Opc = MI.getOpcode();
1608 
1609  switch (Opc) {
1610  default: return false;
1611  case PPC::CMPWI:
1612  case PPC::CMPLWI:
1613  case PPC::CMPDI:
1614  case PPC::CMPLDI:
1615  SrcReg = MI.getOperand(1).getReg();
1616  SrcReg2 = 0;
1617  Value = MI.getOperand(2).getImm();
1618  Mask = 0xFFFF;
1619  return true;
1620  case PPC::CMPW:
1621  case PPC::CMPLW:
1622  case PPC::CMPD:
1623  case PPC::CMPLD:
1624  case PPC::FCMPUS:
1625  case PPC::FCMPUD:
1626  SrcReg = MI.getOperand(1).getReg();
1627  SrcReg2 = MI.getOperand(2).getReg();
1628  Value = 0;
1629  Mask = 0;
1630  return true;
1631  }
1632 }
1633 
1634 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1635  unsigned SrcReg2, int Mask, int Value,
1636  const MachineRegisterInfo *MRI) const {
1637  if (DisableCmpOpt)
1638  return false;
1639 
1640  int OpC = CmpInstr.getOpcode();
1641  Register CRReg = CmpInstr.getOperand(0).getReg();
1642 
1643  // FP record forms set CR1 based on the exception status bits, not a
1644  // comparison with zero.
1645  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1646  return false;
1647 
1649  // The record forms set the condition register based on a signed comparison
1650  // with zero (so says the ISA manual). This is not as straightforward as it
1651  // seems, however, because this is always a 64-bit comparison on PPC64, even
1652  // for instructions that are 32-bit in nature (like slw for example).
1653  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1654  // for equality checks (as those don't depend on the sign). On PPC64,
1655  // we are restricted to equality for unsigned 64-bit comparisons and for
1656  // signed 32-bit comparisons the applicability is more restricted.
1657  bool isPPC64 = Subtarget.isPPC64();
1658  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1659  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1660  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1661 
1662  // Look through copies unless that gets us to a physical register.
1663  unsigned ActualSrc = TRI->lookThruCopyLike(SrcReg, MRI);
1664  if (Register::isVirtualRegister(ActualSrc))
1665  SrcReg = ActualSrc;
1666 
1667  // Get the unique definition of SrcReg.
1668  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1669  if (!MI) return false;
1670 
1671  bool equalityOnly = false;
1672  bool noSub = false;
1673  if (isPPC64) {
1674  if (is32BitSignedCompare) {
1675  // We can perform this optimization only if MI is sign-extending.
1676  if (isSignExtended(*MI))
1677  noSub = true;
1678  else
1679  return false;
1680  } else if (is32BitUnsignedCompare) {
1681  // We can perform this optimization, equality only, if MI is
1682  // zero-extending.
1683  if (isZeroExtended(*MI)) {
1684  noSub = true;
1685  equalityOnly = true;
1686  } else
1687  return false;
1688  } else
1689  equalityOnly = is64BitUnsignedCompare;
1690  } else
1691  equalityOnly = is32BitUnsignedCompare;
1692 
1693  if (equalityOnly) {
1694  // We need to check the uses of the condition register in order to reject
1695  // non-equality comparisons.
1697  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1698  I != IE; ++I) {
1699  MachineInstr *UseMI = &*I;
1700  if (UseMI->getOpcode() == PPC::BCC) {
1701  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1702  unsigned PredCond = PPC::getPredicateCondition(Pred);
1703  // We ignore hint bits when checking for non-equality comparisons.
1704  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1705  return false;
1706  } else if (UseMI->getOpcode() == PPC::ISEL ||
1707  UseMI->getOpcode() == PPC::ISEL8) {
1708  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1709  if (SubIdx != PPC::sub_eq)
1710  return false;
1711  } else
1712  return false;
1713  }
1714  }
1715 
1716  MachineBasicBlock::iterator I = CmpInstr;
1717 
1718  // Scan forward to find the first use of the compare.
1719  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1720  ++I) {
1721  bool FoundUse = false;
1723  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1724  J != JE; ++J)
1725  if (&*J == &*I) {
1726  FoundUse = true;
1727  break;
1728  }
1729 
1730  if (FoundUse)
1731  break;
1732  }
1733 
1736 
1737  // There are two possible candidates which can be changed to set CR[01].
1738  // One is MI, the other is a SUB instruction.
1739  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1740  MachineInstr *Sub = nullptr;
1741  if (SrcReg2 != 0)
1742  // MI is not a candidate for CMPrr.
1743  MI = nullptr;
1744  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1745  // same BB as the comparison. This is to allow the check below to avoid calls
1746  // (and other explicit clobbers); instead we should really check for these
1747  // more explicitly (in at least a few predecessors).
1748  else if (MI->getParent() != CmpInstr.getParent())
1749  return false;
1750  else if (Value != 0) {
1751  // The record-form instructions set CR bit based on signed comparison
1752  // against 0. We try to convert a compare against 1 or -1 into a compare
1753  // against 0 to exploit record-form instructions. For example, we change
1754  // the condition "greater than -1" into "greater than or equal to 0"
1755  // and "less than 1" into "less than or equal to 0".
1756 
1757  // Since we optimize comparison based on a specific branch condition,
1758  // we don't optimize if condition code is used by more than once.
1759  if (equalityOnly || !MRI->hasOneUse(CRReg))
1760  return false;
1761 
1762  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1763  if (UseMI->getOpcode() != PPC::BCC)
1764  return false;
1765 
1766  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1767  unsigned PredCond = PPC::getPredicateCondition(Pred);
1768  unsigned PredHint = PPC::getPredicateHint(Pred);
1769  int16_t Immed = (int16_t)Value;
1770 
1771  // When modifying the condition in the predicate, we propagate hint bits
1772  // from the original predicate to the new one.
1773  if (Immed == -1 && PredCond == PPC::PRED_GT)
1774  // We convert "greater than -1" into "greater than or equal to 0",
1775  // since we are assuming signed comparison by !equalityOnly
1776  Pred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1777  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1778  // We convert "less than or equal to -1" into "less than 0".
1779  Pred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1780  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1781  // We convert "less than 1" into "less than or equal to 0".
1782  Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1783  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1784  // We convert "greater than or equal to 1" into "greater than 0".
1785  Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1786  else
1787  return false;
1788 
1789  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
1790  }
1791 
1792  // Search for Sub.
1793  --I;
1794 
1795  // Get ready to iterate backward from CmpInstr.
1796  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1797 
1798  for (; I != E && !noSub; --I) {
1799  const MachineInstr &Instr = *I;
1800  unsigned IOpC = Instr.getOpcode();
1801 
1802  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1803  Instr.readsRegister(PPC::CR0, TRI)))
1804  // This instruction modifies or uses the record condition register after
1805  // the one we want to change. While we could do this transformation, it
1806  // would likely not be profitable. This transformation removes one
1807  // instruction, and so even forcing RA to generate one move probably
1808  // makes it unprofitable.
1809  return false;
1810 
1811  // Check whether CmpInstr can be made redundant by the current instruction.
1812  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1813  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1814  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1815  ((Instr.getOperand(1).getReg() == SrcReg &&
1816  Instr.getOperand(2).getReg() == SrcReg2) ||
1817  (Instr.getOperand(1).getReg() == SrcReg2 &&
1818  Instr.getOperand(2).getReg() == SrcReg))) {
1819  Sub = &*I;
1820  break;
1821  }
1822 
1823  if (I == B)
1824  // The 'and' is below the comparison instruction.
1825  return false;
1826  }
1827 
1828  // Return false if no candidates exist.
1829  if (!MI && !Sub)
1830  return false;
1831 
1832  // The single candidate is called MI.
1833  if (!MI) MI = Sub;
1834 
1835  int NewOpC = -1;
1836  int MIOpC = MI->getOpcode();
1837  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1838  MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1839  NewOpC = MIOpC;
1840  else {
1841  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1842  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1843  NewOpC = MIOpC;
1844  }
1845 
1846  // FIXME: On the non-embedded POWER architectures, only some of the record
1847  // forms are fast, and we should use only the fast ones.
1848 
1849  // The defining instruction has a record form (or is already a record
1850  // form). It is possible, however, that we'll need to reverse the condition
1851  // code of the users.
1852  if (NewOpC == -1)
1853  return false;
1854 
1855  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1856  // needs to be updated to be based on SUB. Push the condition code
1857  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1858  // condition code of these operands will be modified.
1859  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1860  // comparison against 0, which may modify predicate.
1861  bool ShouldSwap = false;
1862  if (Sub && Value == 0) {
1863  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1864  Sub->getOperand(2).getReg() == SrcReg;
1865 
1866  // The operands to subf are the opposite of sub, so only in the fixed-point
1867  // case, invert the order.
1868  ShouldSwap = !ShouldSwap;
1869  }
1870 
1871  if (ShouldSwap)
1873  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1874  I != IE; ++I) {
1875  MachineInstr *UseMI = &*I;
1876  if (UseMI->getOpcode() == PPC::BCC) {
1877  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1878  unsigned PredCond = PPC::getPredicateCondition(Pred);
1879  assert((!equalityOnly ||
1880  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1881  "Invalid predicate for equality-only optimization");
1882  (void)PredCond; // To suppress warning in release build.
1883  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1884  PPC::getSwappedPredicate(Pred)));
1885  } else if (UseMI->getOpcode() == PPC::ISEL ||
1886  UseMI->getOpcode() == PPC::ISEL8) {
1887  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1888  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1889  "Invalid CR bit for equality-only optimization");
1890 
1891  if (NewSubReg == PPC::sub_lt)
1892  NewSubReg = PPC::sub_gt;
1893  else if (NewSubReg == PPC::sub_gt)
1894  NewSubReg = PPC::sub_lt;
1895 
1896  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1897  NewSubReg));
1898  } else // We need to abort on a user we don't understand.
1899  return false;
1900  }
1901  assert(!(Value != 0 && ShouldSwap) &&
1902  "Non-zero immediate support and ShouldSwap"
1903  "may conflict in updating predicate");
1904 
1905  // Create a new virtual register to hold the value of the CR set by the
1906  // record-form instruction. If the instruction was not previously in
1907  // record form, then set the kill flag on the CR.
1908  CmpInstr.eraseFromParent();
1909 
1911  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1912  get(TargetOpcode::COPY), CRReg)
1913  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1914 
1915  // Even if CR0 register were dead before, it is alive now since the
1916  // instruction we just built uses it.
1917  MI->clearRegisterDeads(PPC::CR0);
1918 
1919  if (MIOpC != NewOpC) {
1920  // We need to be careful here: we're replacing one instruction with
1921  // another, and we need to make sure that we get all of the right
1922  // implicit uses and defs. On the other hand, the caller may be holding
1923  // an iterator to this instruction, and so we can't delete it (this is
1924  // specifically the case if this is the instruction directly after the
1925  // compare).
1926 
1927  // Rotates are expensive instructions. If we're emitting a record-form
1928  // rotate that can just be an andi/andis, we should just emit that.
1929  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
1930  Register GPRRes = MI->getOperand(0).getReg();
1931  int64_t SH = MI->getOperand(2).getImm();
1932  int64_t MB = MI->getOperand(3).getImm();
1933  int64_t ME = MI->getOperand(4).getImm();
1934  // We can only do this if both the start and end of the mask are in the
1935  // same halfword.
1936  bool MBInLoHWord = MB >= 16;
1937  bool MEInLoHWord = ME >= 16;
1938  uint64_t Mask = ~0LLU;
1939 
1940  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1941  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1942  // The mask value needs to shift right 16 if we're emitting andis.
1943  Mask >>= MBInLoHWord ? 0 : 16;
1944  NewOpC = MIOpC == PPC::RLWINM ?
1945  (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1946  (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1947  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1948  (ME - MB + 1 == SH) && (MB >= 16)) {
1949  // If we are rotating by the exact number of bits as are in the mask
1950  // and the mask is in the least significant bits of the register,
1951  // that's just an andis. (as long as the GPR result has no uses).
1952  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1953  Mask >>= 16;
1954  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1955  }
1956  // If we've set the mask, we can transform.
1957  if (Mask != ~0LLU) {
1958  MI->RemoveOperand(4);
1959  MI->RemoveOperand(3);
1960  MI->getOperand(2).setImm(Mask);
1961  NumRcRotatesConvertedToRcAnd++;
1962  }
1963  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1964  int64_t MB = MI->getOperand(3).getImm();
1965  if (MB >= 48) {
1966  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1967  NewOpC = PPC::ANDIo8;
1968  MI->RemoveOperand(3);
1969  MI->getOperand(2).setImm(Mask);
1970  NumRcRotatesConvertedToRcAnd++;
1971  }
1972  }
1973 
1974  const MCInstrDesc &NewDesc = get(NewOpC);
1975  MI->setDesc(NewDesc);
1976 
1977  if (NewDesc.ImplicitDefs)
1978  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1979  *ImpDefs; ++ImpDefs)
1980  if (!MI->definesRegister(*ImpDefs))
1981  MI->addOperand(*MI->getParent()->getParent(),
1982  MachineOperand::CreateReg(*ImpDefs, true, true));
1983  if (NewDesc.ImplicitUses)
1984  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1985  *ImpUses; ++ImpUses)
1986  if (!MI->readsRegister(*ImpUses))
1987  MI->addOperand(*MI->getParent()->getParent(),
1988  MachineOperand::CreateReg(*ImpUses, false, true));
1989  }
1990  assert(MI->definesRegister(PPC::CR0) &&
1991  "Record-form instruction does not define cr0?");
1992 
1993  // Modify the condition code of operands in OperandsToUpdate.
1994  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1995  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1996  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1997  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1998 
1999  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2000  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2001 
2002  return true;
2003 }
2004 
2005 /// GetInstSize - Return the number of bytes of code the specified
2006 /// instruction may be. This returns the maximum number of bytes.
2007 ///
2009  unsigned Opcode = MI.getOpcode();
2010 
2011  if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2012  const MachineFunction *MF = MI.getParent()->getParent();
2013  const char *AsmStr = MI.getOperand(0).getSymbolName();
2014  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2015  } else if (Opcode == TargetOpcode::STACKMAP) {
2016  StackMapOpers Opers(&MI);
2017  return Opers.getNumPatchBytes();
2018  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2019  PatchPointOpers Opers(&MI);
2020  return Opers.getNumPatchBytes();
2021  } else {
2022  return get(Opcode).getSize();
2023  }
2024 }
2025 
2026 std::pair<unsigned, unsigned>
2028  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2029  return std::make_pair(TF & Mask, TF & ~Mask);
2030 }
2031 
2034  using namespace PPCII;
2035  static const std::pair<unsigned, const char *> TargetFlags[] = {
2036  {MO_LO, "ppc-lo"},
2037  {MO_HA, "ppc-ha"},
2038  {MO_TPREL_LO, "ppc-tprel-lo"},
2039  {MO_TPREL_HA, "ppc-tprel-ha"},
2040  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2041  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2042  {MO_TOC_LO, "ppc-toc-lo"},
2043  {MO_TLS, "ppc-tls"}};
2044  return makeArrayRef(TargetFlags);
2045 }
2046 
2049  using namespace PPCII;
2050  static const std::pair<unsigned, const char *> TargetFlags[] = {
2051  {MO_PLT, "ppc-plt"},
2052  {MO_PIC_FLAG, "ppc-pic"},
2053  {MO_NLP_FLAG, "ppc-nlp"},
2054  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2055  return makeArrayRef(TargetFlags);
2056 }
2057 
2058 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2059 // The VSX versions have the advantage of a full 64-register target whereas
2060 // the FP ones have the advantage of lower latency and higher throughput. So
2061 // what we are after is using the faster instructions in low register pressure
2062 // situations and using the larger register file in high register pressure
2063 // situations.
2065  unsigned UpperOpcode, LowerOpcode;
2066  switch (MI.getOpcode()) {
2067  case PPC::DFLOADf32:
2068  UpperOpcode = PPC::LXSSP;
2069  LowerOpcode = PPC::LFS;
2070  break;
2071  case PPC::DFLOADf64:
2072  UpperOpcode = PPC::LXSD;
2073  LowerOpcode = PPC::LFD;
2074  break;
2075  case PPC::DFSTOREf32:
2076  UpperOpcode = PPC::STXSSP;
2077  LowerOpcode = PPC::STFS;
2078  break;
2079  case PPC::DFSTOREf64:
2080  UpperOpcode = PPC::STXSD;
2081  LowerOpcode = PPC::STFD;
2082  break;
2083  case PPC::XFLOADf32:
2084  UpperOpcode = PPC::LXSSPX;
2085  LowerOpcode = PPC::LFSX;
2086  break;
2087  case PPC::XFLOADf64:
2088  UpperOpcode = PPC::LXSDX;
2089  LowerOpcode = PPC::LFDX;
2090  break;
2091  case PPC::XFSTOREf32:
2092  UpperOpcode = PPC::STXSSPX;
2093  LowerOpcode = PPC::STFSX;
2094  break;
2095  case PPC::XFSTOREf64:
2096  UpperOpcode = PPC::STXSDX;
2097  LowerOpcode = PPC::STFDX;
2098  break;
2099  case PPC::LIWAX:
2100  UpperOpcode = PPC::LXSIWAX;
2101  LowerOpcode = PPC::LFIWAX;
2102  break;
2103  case PPC::LIWZX:
2104  UpperOpcode = PPC::LXSIWZX;
2105  LowerOpcode = PPC::LFIWZX;
2106  break;
2107  case PPC::STIWX:
2108  UpperOpcode = PPC::STXSIWX;
2109  LowerOpcode = PPC::STFIWX;
2110  break;
2111  default:
2112  llvm_unreachable("Unknown Operation!");
2113  }
2114 
2115  Register TargetReg = MI.getOperand(0).getReg();
2116  unsigned Opcode;
2117  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2118  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2119  Opcode = LowerOpcode;
2120  else
2121  Opcode = UpperOpcode;
2122  MI.setDesc(get(Opcode));
2123  return true;
2124 }
2125 
2126 static bool isAnImmediateOperand(const MachineOperand &MO) {
2127  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2128 }
2129 
2131  auto &MBB = *MI.getParent();
2132  auto DL = MI.getDebugLoc();
2133 
2134  switch (MI.getOpcode()) {
2135  case TargetOpcode::LOAD_STACK_GUARD: {
2136  assert(Subtarget.isTargetLinux() &&
2137  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2138  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2139  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2140  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2142  .addImm(Offset)
2143  .addReg(Reg);
2144  return true;
2145  }
2146  case PPC::DFLOADf32:
2147  case PPC::DFLOADf64:
2148  case PPC::DFSTOREf32:
2149  case PPC::DFSTOREf64: {
2150  assert(Subtarget.hasP9Vector() &&
2151  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2152  assert(MI.getOperand(2).isReg() &&
2154  "D-form op must have register and immediate operands");
2155  return expandVSXMemPseudo(MI);
2156  }
2157  case PPC::XFLOADf32:
2158  case PPC::XFSTOREf32:
2159  case PPC::LIWAX:
2160  case PPC::LIWZX:
2161  case PPC::STIWX: {
2162  assert(Subtarget.hasP8Vector() &&
2163  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2164  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2165  "X-form op must have register and register operands");
2166  return expandVSXMemPseudo(MI);
2167  }
2168  case PPC::XFLOADf64:
2169  case PPC::XFSTOREf64: {
2170  assert(Subtarget.hasVSX() &&
2171  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2172  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2173  "X-form op must have register and register operands");
2174  return expandVSXMemPseudo(MI);
2175  }
2176  case PPC::SPILLTOVSR_LD: {
2177  Register TargetReg = MI.getOperand(0).getReg();
2178  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2179  MI.setDesc(get(PPC::DFLOADf64));
2180  return expandPostRAPseudo(MI);
2181  }
2182  else
2183  MI.setDesc(get(PPC::LD));
2184  return true;
2185  }
2186  case PPC::SPILLTOVSR_ST: {
2187  Register SrcReg = MI.getOperand(0).getReg();
2188  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2189  NumStoreSPILLVSRRCAsVec++;
2190  MI.setDesc(get(PPC::DFSTOREf64));
2191  return expandPostRAPseudo(MI);
2192  } else {
2193  NumStoreSPILLVSRRCAsGpr++;
2194  MI.setDesc(get(PPC::STD));
2195  }
2196  return true;
2197  }
2198  case PPC::SPILLTOVSR_LDX: {
2199  Register TargetReg = MI.getOperand(0).getReg();
2200  if (PPC::VSFRCRegClass.contains(TargetReg))
2201  MI.setDesc(get(PPC::LXSDX));
2202  else
2203  MI.setDesc(get(PPC::LDX));
2204  return true;
2205  }
2206  case PPC::SPILLTOVSR_STX: {
2207  Register SrcReg = MI.getOperand(0).getReg();
2208  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2209  NumStoreSPILLVSRRCAsVec++;
2210  MI.setDesc(get(PPC::STXSDX));
2211  } else {
2212  NumStoreSPILLVSRRCAsGpr++;
2213  MI.setDesc(get(PPC::STDX));
2214  }
2215  return true;
2216  }
2217 
2218  case PPC::CFENCE8: {
2219  auto Val = MI.getOperand(0).getReg();
2220  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2221  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2223  .addReg(PPC::CR7)
2224  .addImm(1);
2225  MI.setDesc(get(PPC::ISYNC));
2226  MI.RemoveOperand(0);
2227  return true;
2228  }
2229  }
2230  return false;
2231 }
2232 
2233 // Essentially a compile-time implementation of a compare->isel sequence.
2234 // It takes two constants to compare, along with the true/false registers
2235 // and the comparison type (as a subreg to a CR field) and returns one
2236 // of the true/false registers, depending on the comparison results.
2237 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2238  unsigned TrueReg, unsigned FalseReg,
2239  unsigned CRSubReg) {
2240  // Signed comparisons. The immediates are assumed to be sign-extended.
2241  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2242  switch (CRSubReg) {
2243  default: llvm_unreachable("Unknown integer comparison type.");
2244  case PPC::sub_lt:
2245  return Imm1 < Imm2 ? TrueReg : FalseReg;
2246  case PPC::sub_gt:
2247  return Imm1 > Imm2 ? TrueReg : FalseReg;
2248  case PPC::sub_eq:
2249  return Imm1 == Imm2 ? TrueReg : FalseReg;
2250  }
2251  }
2252  // Unsigned comparisons.
2253  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2254  switch (CRSubReg) {
2255  default: llvm_unreachable("Unknown integer comparison type.");
2256  case PPC::sub_lt:
2257  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2258  case PPC::sub_gt:
2259  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2260  case PPC::sub_eq:
2261  return Imm1 == Imm2 ? TrueReg : FalseReg;
2262  }
2263  }
2264  return PPC::NoRegister;
2265 }
2266 
2268  unsigned OpNo,
2269  int64_t Imm) const {
2270  assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2271  // Replace the REG with the Immediate.
2272  Register InUseReg = MI.getOperand(OpNo).getReg();
2273  MI.getOperand(OpNo).ChangeToImmediate(Imm);
2274 
2275  if (empty(MI.implicit_operands()))
2276  return;
2277 
2278  // We need to make sure that the MI didn't have any implicit use
2279  // of this REG any more.
2281  int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
2282  if (UseOpIdx >= 0) {
2283  MachineOperand &MO = MI.getOperand(UseOpIdx);
2284  if (MO.isImplicit())
2285  // The operands must always be in the following order:
2286  // - explicit reg defs,
2287  // - other explicit operands (reg uses, immediates, etc.),
2288  // - implicit reg defs
2289  // - implicit reg uses
2290  // Therefore, removing the implicit operand won't change the explicit
2291  // operands layout.
2292  MI.RemoveOperand(UseOpIdx);
2293  }
2294 }
2295 
2296 // Replace an instruction with one that materializes a constant (and sets
2297 // CR0 if the original instruction was a record-form instruction).
2299  const LoadImmediateInfo &LII) const {
2300  // Remove existing operands.
2301  int OperandToKeep = LII.SetCR ? 1 : 0;
2302  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2303  MI.RemoveOperand(i);
2304 
2305  // Replace the instruction.
2306  if (LII.SetCR) {
2307  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2308  // Set the immediate.
2310  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2311  return;
2312  }
2313  else
2314  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2315 
2316  // Set the immediate.
2318  .addImm(LII.Imm);
2319 }
2320 
2322  bool &SeenIntermediateUse) const {
2323  assert(!MI.getParent()->getParent()->getRegInfo().isSSA() &&
2324  "Should be called after register allocation.");
2327  It++;
2328  SeenIntermediateUse = false;
2329  for (; It != E; ++It) {
2330  if (It->modifiesRegister(Reg, TRI))
2331  return &*It;
2332  if (It->readsRegister(Reg, TRI))
2333  SeenIntermediateUse = true;
2334  }
2335  return nullptr;
2336 }
2337 
2338 MachineInstr *PPCInstrInfo::getForwardingDefMI(
2339  MachineInstr &MI,
2340  unsigned &OpNoForForwarding,
2341  bool &SeenIntermediateUse) const {
2342  OpNoForForwarding = ~0U;
2343  MachineInstr *DefMI = nullptr;
2346  // If we're in SSA, get the defs through the MRI. Otherwise, only look
2347  // within the basic block to see if the register is defined using an LI/LI8.
2348  if (MRI->isSSA()) {
2349  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2350  if (!MI.getOperand(i).isReg())
2351  continue;
2352  Register Reg = MI.getOperand(i).getReg();
2353  if (!Register::isVirtualRegister(Reg))
2354  continue;
2355  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2356  if (Register::isVirtualRegister(TrueReg)) {
2357  DefMI = MRI->getVRegDef(TrueReg);
2358  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2359  OpNoForForwarding = i;
2360  break;
2361  }
2362  }
2363  }
2364  } else {
2365  // Looking back through the definition for each operand could be expensive,
2366  // so exit early if this isn't an instruction that either has an immediate
2367  // form or is already an immediate form that we can handle.
2368  ImmInstrInfo III;
2369  unsigned Opc = MI.getOpcode();
2370  bool ConvertibleImmForm =
2371  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2372  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2373  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2374  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2375  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2376  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2377  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2378  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2379  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2380  bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
2381  ? isVFRegister(MI.getOperand(0).getReg())
2382  : false;
2383  if (!ConvertibleImmForm && !instrHasImmForm(Opc, IsVFReg, III, true))
2384  return nullptr;
2385 
2386  // Don't convert or %X, %Y, %Y since that's just a register move.
2387  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2388  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2389  return nullptr;
2390  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2391  MachineOperand &MO = MI.getOperand(i);
2392  SeenIntermediateUse = false;
2393  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2394  Register Reg = MI.getOperand(i).getReg();
2395  // If we see another use of this reg between the def and the MI,
2396  // we want to flat it so the def isn't deleted.
2397  MachineInstr *DefMI = getDefMIPostRA(Reg, MI, SeenIntermediateUse);
2398  if (DefMI) {
2399  // Is this register defined by some form of add-immediate (including
2400  // load-immediate) within this basic block?
2401  switch (DefMI->getOpcode()) {
2402  default:
2403  break;
2404  case PPC::LI:
2405  case PPC::LI8:
2406  case PPC::ADDItocL:
2407  case PPC::ADDI:
2408  case PPC::ADDI8:
2409  OpNoForForwarding = i;
2410  return DefMI;
2411  }
2412  }
2413  }
2414  }
2415  }
2416  return OpNoForForwarding == ~0U ? nullptr : DefMI;
2417 }
2418 
2419 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2420  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2421  // Power 8
2422  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2423  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2424  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2425  PPC::SPILLTOVSR_ST, PPC::EVSTDD},
2426  // Power 9
2427  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2428  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2429  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2430  PPC::SPILLTOVSR_ST}};
2431 
2432  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2433 }
2434 
2435 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2436  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2437  // Power 8
2438  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2439  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2440  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2441  PPC::SPILLTOVSR_LD, PPC::EVLDD},
2442  // Power 9
2443  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2444  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2445  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2446  PPC::SPILLTOVSR_LD}};
2447 
2448  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2449 }
2450 
2452  unsigned RegNo) const {
2453  const MachineRegisterInfo &MRI =
2454  StartMI.getParent()->getParent()->getRegInfo();
2455  if (MRI.isSSA())
2456  return;
2457 
2458  // Instructions between [StartMI, EndMI] should be in same basic block.
2459  assert((StartMI.getParent() == EndMI.getParent()) &&
2460  "Instructions are not in same basic block");
2461 
2462  bool IsKillSet = false;
2463 
2464  auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
2465  MachineOperand &MO = MI.getOperand(Index);
2466  if (MO.isReg() && MO.isUse() && MO.isKill() &&
2467  getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
2468  MO.setIsKill(false);
2469  };
2470 
2471  // Set killed flag for EndMI.
2472  // No need to do anything if EndMI defines RegNo.
2473  int UseIndex =
2474  EndMI.findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
2475  if (UseIndex != -1) {
2476  EndMI.getOperand(UseIndex).setIsKill(true);
2477  IsKillSet = true;
2478  // Clear killed flag for other EndMI operands related to RegNo. In some
2479  // upexpected cases, killed may be set multiple times for same register
2480  // operand in same MI.
2481  for (int i = 0, e = EndMI.getNumOperands(); i != e; ++i)
2482  if (i != UseIndex)
2483  clearOperandKillInfo(EndMI, i);
2484  }
2485 
2486  // Walking the inst in reverse order (EndMI -> StartMI].
2489  // EndMI has been handled above, skip it here.
2490  It++;
2491  MachineOperand *MO = nullptr;
2492  for (; It != E; ++It) {
2493  // Skip insturctions which could not be a def/use of RegNo.
2494  if (It->isDebugInstr() || It->isPosition())
2495  continue;
2496 
2497  // Clear killed flag for all It operands related to RegNo. In some
2498  // upexpected cases, killed may be set multiple times for same register
2499  // operand in same MI.
2500  for (int i = 0, e = It->getNumOperands(); i != e; ++i)
2501  clearOperandKillInfo(*It, i);
2502 
2503  // If killed is not set, set killed for its last use or set dead for its def
2504  // if no use found.
2505  if (!IsKillSet) {
2506  if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
2507  // Use found, set it killed.
2508  IsKillSet = true;
2509  MO->setIsKill(true);
2510  continue;
2511  } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
2512  &getRegisterInfo()))) {
2513  // No use found, set dead for its def.
2514  assert(&*It == &StartMI && "No new def between StartMI and EndMI.");
2515  MO->setIsDead(true);
2516  break;
2517  }
2518  }
2519 
2520  if ((&*It) == &StartMI)
2521  break;
2522  }
2523  // Ensure RegMo liveness is killed after EndMI.
2524  assert((IsKillSet || (MO && MO->isDead())) &&
2525  "RegNo should be killed or dead");
2526 }
2527 
2528 // If this instruction has an immediate form and one of its operands is a
2529 // result of a load-immediate or an add-immediate, convert it to
2530 // the immediate form if the constant is in range.
2532  MachineInstr **KilledDef) const {
2533  MachineFunction *MF = MI.getParent()->getParent();
2535  bool PostRA = !MRI->isSSA();
2536  bool SeenIntermediateUse = true;
2537  unsigned ForwardingOperand = ~0U;
2538  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2539  SeenIntermediateUse);
2540  if (!DefMI)
2541  return false;
2542  assert(ForwardingOperand < MI.getNumOperands() &&
2543  "The forwarding operand needs to be valid at this point");
2544  bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
2545  bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
2546  Register ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2547  if (KilledDef && KillFwdDefMI)
2548  *KilledDef = DefMI;
2549 
2550  ImmInstrInfo III;
2551  bool IsVFReg = MI.getOperand(0).isReg()
2552  ? isVFRegister(MI.getOperand(0).getReg())
2553  : false;
2554  bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA);
2555  // If this is a reg+reg instruction that has a reg+imm form,
2556  // and one of the operands is produced by an add-immediate,
2557  // try to convert it.
2558  if (HasImmForm &&
2559  transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
2560  KillFwdDefMI))
2561  return true;
2562 
2563  if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2564  !DefMI->getOperand(1).isImm())
2565  return false;
2566 
2567  int64_t Immediate = DefMI->getOperand(1).getImm();
2568  // Sign-extend to 64-bits.
2569  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2570  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2571 
2572  // If this is a reg+reg instruction that has a reg+imm form,
2573  // and one of the operands is produced by LI, convert it now.
2574  if (HasImmForm)
2575  return transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI, SExtImm);
2576 
2577  bool ReplaceWithLI = false;
2578  bool Is64BitLI = false;
2579  int64_t NewImm = 0;
2580  bool SetCR = false;
2581  unsigned Opc = MI.getOpcode();
2582  switch (Opc) {
2583  default: return false;
2584 
2585  // FIXME: Any branches conditional on such a comparison can be made
2586  // unconditional. At this time, this happens too infrequently to be worth
2587  // the implementation effort, but if that ever changes, we could convert
2588  // such a pattern here.
2589  case PPC::CMPWI:
2590  case PPC::CMPLWI:
2591  case PPC::CMPDI:
2592  case PPC::CMPLDI: {
2593  // Doing this post-RA would require dataflow analysis to reliably find uses
2594  // of the CR register set by the compare.
2595  // No need to fixup killed/dead flag since this transformation is only valid
2596  // before RA.
2597  if (PostRA)
2598  return false;
2599  // If a compare-immediate is fed by an immediate and is itself an input of
2600  // an ISEL (the most common case) into a COPY of the correct register.
2601  bool Changed = false;
2602  Register DefReg = MI.getOperand(0).getReg();
2603  int64_t Comparand = MI.getOperand(2).getImm();
2604  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2605  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2606 
2607  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2608  unsigned UseOpc = CompareUseMI.getOpcode();
2609  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2610  continue;
2611  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2612  Register TrueReg = CompareUseMI.getOperand(1).getReg();
2613  Register FalseReg = CompareUseMI.getOperand(2).getReg();
2614  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2615  FalseReg, CRSubReg);
2616  if (RegToCopy == PPC::NoRegister)
2617  continue;
2618  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2619  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2620  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2621  replaceInstrOperandWithImm(CompareUseMI, 1, 0);
2622  CompareUseMI.RemoveOperand(3);
2623  CompareUseMI.RemoveOperand(2);
2624  continue;
2625  }
2626  LLVM_DEBUG(
2627  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2628  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2629  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2630  // Convert to copy and remove unneeded operands.
2631  CompareUseMI.setDesc(get(PPC::COPY));
2632  CompareUseMI.RemoveOperand(3);
2633  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2634  CmpIselsConverted++;
2635  Changed = true;
2636  LLVM_DEBUG(CompareUseMI.dump());
2637  }
2638  if (Changed)
2639  return true;
2640  // This may end up incremented multiple times since this function is called
2641  // during a fixed-point transformation, but it is only meant to indicate the
2642  // presence of this opportunity.
2643  MissedConvertibleImmediateInstrs++;
2644  return false;
2645  }
2646 
2647  // Immediate forms - may simply be convertable to an LI.
2648  case PPC::ADDI:
2649  case PPC::ADDI8: {
2650  // Does the sum fit in a 16-bit signed field?
2651  int64_t Addend = MI.getOperand(2).getImm();
2652  if (isInt<16>(Addend + SExtImm)) {
2653  ReplaceWithLI = true;
2654  Is64BitLI = Opc == PPC::ADDI8;
2655  NewImm = Addend + SExtImm;
2656  break;
2657  }
2658  return false;
2659  }
2660  case PPC::RLDICL:
2661  case PPC::RLDICLo:
2662  case PPC::RLDICL_32:
2663  case PPC::RLDICL_32_64: {
2664  // Use APInt's rotate function.
2665  int64_t SH = MI.getOperand(2).getImm();
2666  int64_t MB = MI.getOperand(3).getImm();
2667  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2668  64 : 32, SExtImm, true);
2669  InVal = InVal.rotl(SH);
2670  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2671  InVal &= Mask;
2672  // Can't replace negative values with an LI as that will sign-extend
2673  // and not clear the left bits. If we're setting the CR bit, we will use
2674  // ANDIo which won't sign extend, so that's safe.
2675  if (isUInt<15>(InVal.getSExtValue()) ||
2676  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2677  ReplaceWithLI = true;
2678  Is64BitLI = Opc != PPC::RLDICL_32;
2679  NewImm = InVal.getSExtValue();
2680  SetCR = Opc == PPC::RLDICLo;
2681  break;
2682  }
2683  return false;
2684  }
2685  case PPC::RLWINM:
2686  case PPC::RLWINM8:
2687  case PPC::RLWINMo:
2688  case PPC::RLWINM8o: {
2689  int64_t SH = MI.getOperand(2).getImm();
2690  int64_t MB = MI.getOperand(3).getImm();
2691  int64_t ME = MI.getOperand(4).getImm();
2692  APInt InVal(32, SExtImm, true);
2693  InVal = InVal.rotl(SH);
2694  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2695  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2696  InVal &= Mask;
2697  // Can't replace negative values with an LI as that will sign-extend
2698  // and not clear the left bits. If we're setting the CR bit, we will use
2699  // ANDIo which won't sign extend, so that's safe.
2700  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2701  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2702  isUInt<16>(InVal.getSExtValue()));
2703  if (ValueFits) {
2704  ReplaceWithLI = true;
2705  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2706  NewImm = InVal.getSExtValue();
2707  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2708  break;
2709  }
2710  return false;
2711  }
2712  case PPC::ORI:
2713  case PPC::ORI8:
2714  case PPC::XORI:
2715  case PPC::XORI8: {
2716  int64_t LogicalImm = MI.getOperand(2).getImm();
2717  int64_t Result = 0;
2718  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2719  Result = LogicalImm | SExtImm;
2720  else
2721  Result = LogicalImm ^ SExtImm;
2722  if (isInt<16>(Result)) {
2723  ReplaceWithLI = true;
2724  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2725  NewImm = Result;
2726  break;
2727  }
2728  return false;
2729  }
2730  }
2731 
2732  if (ReplaceWithLI) {
2733  // We need to be careful with CR-setting instructions we're replacing.
2734  if (SetCR) {
2735  // We don't know anything about uses when we're out of SSA, so only
2736  // replace if the new immediate will be reproduced.
2737  bool ImmChanged = (SExtImm & NewImm) != NewImm;
2738  if (PostRA && ImmChanged)
2739  return false;
2740 
2741  if (!PostRA) {
2742  // If the defining load-immediate has no other uses, we can just replace
2743  // the immediate with the new immediate.
2744  if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2745  DefMI->getOperand(1).setImm(NewImm);
2746 
2747  // If we're not using the GPR result of the CR-setting instruction, we
2748  // just need to and with zero/non-zero depending on the new immediate.
2749  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2750  if (NewImm) {
2751  assert(Immediate && "Transformation converted zero to non-zero?");
2752  NewImm = Immediate;
2753  }
2754  }
2755  else if (ImmChanged)
2756  return false;
2757  }
2758  }
2759 
2760  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2761  LLVM_DEBUG(MI.dump());
2762  LLVM_DEBUG(dbgs() << "Fed by:\n");
2763  LLVM_DEBUG(DefMI->dump());
2764  LoadImmediateInfo LII;
2765  LII.Imm = NewImm;
2766  LII.Is64Bit = Is64BitLI;
2767  LII.SetCR = SetCR;
2768  // If we're setting the CR, the original load-immediate must be kept (as an
2769  // operand to ANDIo/ANDI8o).
2770  if (KilledDef && SetCR)
2771  *KilledDef = nullptr;
2772  replaceInstrWithLI(MI, LII);
2773 
2774  // Fixup killed/dead flag after transformation.
2775  // Pattern:
2776  // ForwardingOperandReg = LI imm1
2777  // y = op2 imm2, ForwardingOperandReg(killed)
2778  if (IsForwardingOperandKilled)
2779  fixupIsDeadOrKill(*DefMI, MI, ForwardingOperandReg);
2780 
2781  LLVM_DEBUG(dbgs() << "With:\n");
2782  LLVM_DEBUG(MI.dump());
2783  return true;
2784  }
2785  return false;
2786 }
2787 
2788 bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
2789  ImmInstrInfo &III, bool PostRA) const {
2790  // The vast majority of the instructions would need their operand 2 replaced
2791  // with an immediate when switching to the reg+imm form. A marked exception
2792  // are the update form loads/stores for which a constant operand 2 would need
2793  // to turn into a displacement and move operand 1 to the operand 2 position.
2794  III.ImmOpNo = 2;
2795  III.OpNoForForwarding = 2;
2796  III.ImmWidth = 16;
2797  III.ImmMustBeMultipleOf = 1;
2798  III.TruncateImmTo = 0;
2799  III.IsSummingOperands = false;
2800  switch (Opc) {
2801  default: return false;
2802  case PPC::ADD4:
2803  case PPC::ADD8:
2804  III.SignedImm = true;
2805  III.ZeroIsSpecialOrig = 0;
2806  III.ZeroIsSpecialNew = 1;
2807  III.IsCommutative = true;
2808  III.IsSummingOperands = true;
2809  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2810  break;
2811  case PPC::ADDC:
2812  case PPC::ADDC8:
2813  III.SignedImm = true;
2814  III.ZeroIsSpecialOrig = 0;
2815  III.ZeroIsSpecialNew = 0;
2816  III.IsCommutative = true;
2817  III.IsSummingOperands = true;
2818  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2819  break;
2820  case PPC::ADDCo:
2821  III.SignedImm = true;
2822  III.ZeroIsSpecialOrig = 0;
2823  III.ZeroIsSpecialNew = 0;
2824  III.IsCommutative = true;
2825  III.IsSummingOperands = true;
2826  III.ImmOpcode = PPC::ADDICo;
2827  break;
2828  case PPC::SUBFC:
2829  case PPC::SUBFC8:
2830  III.SignedImm = true;
2831  III.ZeroIsSpecialOrig = 0;
2832  III.ZeroIsSpecialNew = 0;
2833  III.IsCommutative = false;
2834  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2835  break;
2836  case PPC::CMPW:
2837  case PPC::CMPD:
2838  III.SignedImm = true;
2839  III.ZeroIsSpecialOrig = 0;
2840  III.ZeroIsSpecialNew = 0;
2841  III.IsCommutative = false;
2842  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2843  break;
2844  case PPC::CMPLW:
2845  case PPC::CMPLD:
2846  III.SignedImm = false;
2847  III.ZeroIsSpecialOrig = 0;
2848  III.ZeroIsSpecialNew = 0;
2849  III.IsCommutative = false;
2850  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2851  break;
2852  case PPC::ANDo:
2853  case PPC::AND8o:
2854  case PPC::OR:
2855  case PPC::OR8:
2856  case PPC::XOR:
2857  case PPC::XOR8:
2858  III.SignedImm = false;
2859  III.ZeroIsSpecialOrig = 0;
2860  III.ZeroIsSpecialNew = 0;
2861  III.IsCommutative = true;
2862  switch(Opc) {
2863  default: llvm_unreachable("Unknown opcode");
2864  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2865  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2866  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2867  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2868  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2869  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2870  }
2871  break;
2872  case PPC::RLWNM:
2873  case PPC::RLWNM8:
2874  case PPC::RLWNMo:
2875  case PPC::RLWNM8o:
2876  case PPC::SLW:
2877  case PPC::SLW8:
2878  case PPC::SLWo:
2879  case PPC::SLW8o:
2880  case PPC::SRW:
2881  case PPC::SRW8:
2882  case PPC::SRWo:
2883  case PPC::SRW8o:
2884  case PPC::SRAW:
2885  case PPC::SRAWo:
2886  III.SignedImm = false;
2887  III.ZeroIsSpecialOrig = 0;
2888  III.ZeroIsSpecialNew = 0;
2889  III.IsCommutative = false;
2890  // This isn't actually true, but the instructions ignore any of the
2891  // upper bits, so any immediate loaded with an LI is acceptable.
2892  // This does not apply to shift right algebraic because a value
2893  // out of range will produce a -1/0.
2894  III.ImmWidth = 16;
2895  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2896  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2897  III.TruncateImmTo = 5;
2898  else
2899  III.TruncateImmTo = 6;
2900  switch(Opc) {
2901  default: llvm_unreachable("Unknown opcode");
2902  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2903  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2904  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2905  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2906  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2907  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2908  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2909  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2910  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2911  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2912  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2913  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2914  case PPC::SRAW:
2915  III.ImmWidth = 5;
2916  III.TruncateImmTo = 0;
2917  III.ImmOpcode = PPC::SRAWI;
2918  break;
2919  case PPC::SRAWo:
2920  III.ImmWidth = 5;
2921  III.TruncateImmTo = 0;
2922  III.ImmOpcode = PPC::SRAWIo;
2923  break;
2924  }
2925  break;
2926  case PPC::RLDCL:
2927  case PPC::RLDCLo:
2928  case PPC::RLDCR:
2929  case PPC::RLDCRo:
2930  case PPC::SLD:
2931  case PPC::SLDo:
2932  case PPC::SRD:
2933  case PPC::SRDo:
2934  case PPC::SRAD:
2935  case PPC::SRADo:
2936  III.SignedImm = false;
2937  III.ZeroIsSpecialOrig = 0;
2938  III.ZeroIsSpecialNew = 0;
2939  III.IsCommutative = false;
2940  // This isn't actually true, but the instructions ignore any of the
2941  // upper bits, so any immediate loaded with an LI is acceptable.
2942  // This does not apply to shift right algebraic because a value
2943  // out of range will produce a -1/0.
2944  III.ImmWidth = 16;
2945  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2946  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2947  III.TruncateImmTo = 6;
2948  else
2949  III.TruncateImmTo = 7;
2950  switch(Opc) {
2951  default: llvm_unreachable("Unknown opcode");
2952  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2953  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2954  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2955  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2956  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2957  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2958  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2959  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2960  case PPC::SRAD:
2961  III.ImmWidth = 6;
2962  III.TruncateImmTo = 0;
2963  III.ImmOpcode = PPC::SRADI;
2964  break;
2965  case PPC::SRADo:
2966  III.ImmWidth = 6;
2967  III.TruncateImmTo = 0;
2968  III.ImmOpcode = PPC::SRADIo;
2969  break;
2970  }
2971  break;
2972  // Loads and stores:
2973  case PPC::LBZX:
2974  case PPC::LBZX8:
2975  case PPC::LHZX:
2976  case PPC::LHZX8:
2977  case PPC::LHAX:
2978  case PPC::LHAX8:
2979  case PPC::LWZX:
2980  case PPC::LWZX8:
2981  case PPC::LWAX:
2982  case PPC::LDX:
2983  case PPC::LFSX:
2984  case PPC::LFDX:
2985  case PPC::STBX:
2986  case PPC::STBX8:
2987  case PPC::STHX:
2988  case PPC::STHX8:
2989  case PPC::STWX:
2990  case PPC::STWX8:
2991  case PPC::STDX:
2992  case PPC::STFSX:
2993  case PPC::STFDX:
2994  III.SignedImm = true;
2995  III.ZeroIsSpecialOrig = 1;
2996  III.ZeroIsSpecialNew = 2;
2997  III.IsCommutative = true;
2998  III.IsSummingOperands = true;
2999  III.ImmOpNo = 1;
3000  III.OpNoForForwarding = 2;
3001  switch(Opc) {
3002  default: llvm_unreachable("Unknown opcode");
3003  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
3004  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
3005  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
3006  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
3007  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
3008  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
3009  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
3010  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
3011  case PPC::LWAX:
3012  III.ImmOpcode = PPC::LWA;
3013  III.ImmMustBeMultipleOf = 4;
3014  break;
3015  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
3016  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
3017  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
3018  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
3019  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
3020  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
3021  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
3022  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
3023  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
3024  case PPC::STDX:
3025  III.ImmOpcode = PPC::STD;
3026  III.ImmMustBeMultipleOf = 4;
3027  break;
3028  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
3029  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
3030  }
3031  break;
3032  case PPC::LBZUX:
3033  case PPC::LBZUX8:
3034  case PPC::LHZUX:
3035  case PPC::LHZUX8:
3036  case PPC::LHAUX:
3037  case PPC::LHAUX8:
3038  case PPC::LWZUX:
3039  case PPC::LWZUX8:
3040  case PPC::LDUX:
3041  case PPC::LFSUX:
3042  case PPC::LFDUX:
3043  case PPC::STBUX:
3044  case PPC::STBUX8:
3045  case PPC::STHUX:
3046  case PPC::STHUX8:
3047  case PPC::STWUX:
3048  case PPC::STWUX8:
3049  case PPC::STDUX:
3050  case PPC::STFSUX:
3051  case PPC::STFDUX:
3052  III.SignedImm = true;
3053  III.ZeroIsSpecialOrig = 2;
3054  III.ZeroIsSpecialNew = 3;
3055  III.IsCommutative = false;
3056  III.IsSummingOperands = true;
3057  III.ImmOpNo = 2;
3058  III.OpNoForForwarding = 3;
3059  switch(Opc) {
3060  default: llvm_unreachable("Unknown opcode");
3061  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
3062  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
3063  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
3064  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
3065  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
3066  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
3067  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
3068  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
3069  case PPC::LDUX:
3070  III.ImmOpcode = PPC::LDU;
3071  III.ImmMustBeMultipleOf = 4;
3072  break;
3073  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
3074  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
3075  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
3076  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
3077  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
3078  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
3079  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
3080  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
3081  case PPC::STDUX:
3082  III.ImmOpcode = PPC::STDU;
3083  III.ImmMustBeMultipleOf = 4;
3084  break;
3085  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
3086  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
3087  }
3088  break;
3089  // Power9 and up only. For some of these, the X-Form version has access to all
3090  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
3091  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
3092  // into or stored from is one of the VR registers.
3093  case PPC::LXVX:
3094  case PPC::LXSSPX:
3095  case PPC::LXSDX:
3096  case PPC::STXVX:
3097  case PPC::STXSSPX:
3098  case PPC::STXSDX:
3099  case PPC::XFLOADf32:
3100  case PPC::XFLOADf64:
3101  case PPC::XFSTOREf32:
3102  case PPC::XFSTOREf64:
3103  if (!Subtarget.hasP9Vector())
3104  return false;
3105  III.SignedImm = true;
3106  III.ZeroIsSpecialOrig = 1;
3107  III.ZeroIsSpecialNew = 2;
3108  III.IsCommutative = true;
3109  III.IsSummingOperands = true;
3110  III.ImmOpNo = 1;
3111  III.OpNoForForwarding = 2;
3112  III.ImmMustBeMultipleOf = 4;
3113  switch(Opc) {
3114  default: llvm_unreachable("Unknown opcode");
3115  case PPC::LXVX:
3116  III.ImmOpcode = PPC::LXV;
3117  III.ImmMustBeMultipleOf = 16;
3118  break;
3119  case PPC::LXSSPX:
3120  if (PostRA) {
3121  if (IsVFReg)
3122  III.ImmOpcode = PPC::LXSSP;
3123  else {
3124  III.ImmOpcode = PPC::LFS;
3125  III.ImmMustBeMultipleOf = 1;
3126  }
3127  break;
3128  }
3130  case PPC::XFLOADf32:
3131  III.ImmOpcode = PPC::DFLOADf32;
3132  break;
3133  case PPC::LXSDX:
3134  if (PostRA) {
3135  if (IsVFReg)
3136  III.ImmOpcode = PPC::LXSD;
3137  else {
3138  III.ImmOpcode = PPC::LFD;
3139  III.ImmMustBeMultipleOf = 1;
3140  }
3141  break;
3142  }
3144  case PPC::XFLOADf64:
3145  III.ImmOpcode = PPC::DFLOADf64;
3146  break;
3147  case PPC::STXVX:
3148  III.ImmOpcode = PPC::STXV;
3149  III.ImmMustBeMultipleOf = 16;
3150  break;
3151  case PPC::STXSSPX:
3152  if (PostRA) {
3153  if (IsVFReg)
3154  III.ImmOpcode = PPC::STXSSP;
3155  else {
3156  III.ImmOpcode = PPC::STFS;
3157  III.ImmMustBeMultipleOf = 1;
3158  }
3159  break;
3160  }
3162  case PPC::XFSTOREf32:
3163  III.ImmOpcode = PPC::DFSTOREf32;
3164  break;
3165  case PPC::STXSDX:
3166  if (PostRA) {
3167  if (IsVFReg)
3168  III.ImmOpcode = PPC::STXSD;
3169  else {
3170  III.ImmOpcode = PPC::STFD;
3171  III.ImmMustBeMultipleOf = 1;
3172  }
3173  break;
3174  }
3176  case PPC::XFSTOREf64:
3177  III.ImmOpcode = PPC::DFSTOREf64;
3178  break;
3179  }
3180  break;
3181  }
3182  return true;
3183 }
3184 
3185 // Utility function for swaping two arbitrary operands of an instruction.
3186 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3187  assert(Op1 != Op2 && "Cannot swap operand with itself.");
3188 
3189  unsigned MaxOp = std::max(Op1, Op2);
3190  unsigned MinOp = std::min(Op1, Op2);
3191  MachineOperand MOp1 = MI.getOperand(MinOp);
3192  MachineOperand MOp2 = MI.getOperand(MaxOp);
3193  MI.RemoveOperand(std::max(Op1, Op2));
3194  MI.RemoveOperand(std::min(Op1, Op2));
3195 
3196  // If the operands we are swapping are the two at the end (the common case)
3197  // we can just remove both and add them in the opposite order.
3198  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3199  MI.addOperand(MOp2);
3200  MI.addOperand(MOp1);
3201  } else {
3202  // Store all operands in a temporary vector, remove them and re-add in the
3203  // right order.
3205  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3206  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3207  MOps.push_back(MI.getOperand(i));
3208  MI.RemoveOperand(i);
3209  }
3210  // MOp2 needs to be added next.
3211  MI.addOperand(MOp2);
3212  // Now add the rest.
3213  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3214  if (i == MaxOp)
3215  MI.addOperand(MOp1);
3216  else {
3217  MI.addOperand(MOps.back());
3218  MOps.pop_back();
3219  }
3220  }
3221  }
3222 }
3223 
3224 // Check if the 'MI' that has the index OpNoForForwarding
3225 // meets the requirement described in the ImmInstrInfo.
3226 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3227  const ImmInstrInfo &III,
3228  unsigned OpNoForForwarding
3229  ) const {
3230  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3231  // would not work pre-RA, we can only do the check post RA.
3233  if (MRI.isSSA())
3234  return false;
3235 
3236  // Cannot do the transform if MI isn't summing the operands.
3237  if (!III.IsSummingOperands)
3238  return false;
3239 
3240  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3241  if (!III.ZeroIsSpecialOrig)
3242  return false;
3243 
3244  // We cannot do the transform if the operand we are trying to replace
3245  // isn't the same as the operand the instruction allows.
3246  if (OpNoForForwarding != III.OpNoForForwarding)
3247  return false;
3248 
3249  // Check if the instruction we are trying to transform really has
3250  // the special zero register as its operand.
3251  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3252  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3253  return false;
3254 
3255  // This machine instruction is convertible if it is,
3256  // 1. summing the operands.
3257  // 2. one of the operands is special zero register.
3258  // 3. the operand we are trying to replace is allowed by the MI.
3259  return true;
3260 }
3261 
3262 // Check if the DefMI is the add inst and set the ImmMO and RegMO
3263 // accordingly.
3264 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3265  const ImmInstrInfo &III,
3266  MachineOperand *&ImmMO,
3267  MachineOperand *&RegMO) const {
3268  unsigned Opc = DefMI.getOpcode();
3269  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3270  return false;
3271 
3272  assert(DefMI.getNumOperands() >= 3 &&
3273  "Add inst must have at least three operands");
3274  RegMO = &DefMI.getOperand(1);
3275  ImmMO = &DefMI.getOperand(2);
3276 
3277  // This DefMI is elgible for forwarding if it is:
3278  // 1. add inst
3279  // 2. one of the operands is Imm/CPI/Global.
3280  return isAnImmediateOperand(*ImmMO);
3281 }
3282 
3283 bool PPCInstrInfo::isRegElgibleForForwarding(
3284  const MachineOperand &RegMO, const MachineInstr &DefMI,
3285  const MachineInstr &MI, bool KillDefMI,
3286  bool &IsFwdFeederRegKilled) const {
3287  // x = addi y, imm
3288  // ...
3289  // z = lfdx 0, x -> z = lfd imm(y)
3290  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3291  // of "y" between the DEF of "x" and "z".
3292  // The query is only valid post RA.
3294  if (MRI.isSSA())
3295  return false;
3296 
3297  Register Reg = RegMO.getReg();
3298 
3299  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3302  It++;
3303  for (; It != E; ++It) {
3304  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3305  return false;
3306  else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3307  IsFwdFeederRegKilled = true;
3308  // Made it to DefMI without encountering a clobber.
3309  if ((&*It) == &DefMI)
3310  break;
3311  }
3312  assert((&*It) == &DefMI && "DefMI is missing");
3313 
3314  // If DefMI also defines the register to be forwarded, we can only forward it
3315  // if DefMI is being erased.
3316  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
3317  return KillDefMI;
3318 
3319  return true;
3320 }
3321 
3322 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3323  const MachineInstr &DefMI,
3324  const ImmInstrInfo &III,
3325  int64_t &Imm) const {
3326  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
3327  if (DefMI.getOpcode() == PPC::ADDItocL) {
3328  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3329  // However, we know that, it is 16-bit width, and has the alignment of 4.
3330  // Check if the instruction met the requirement.
3331  if (III.ImmMustBeMultipleOf > 4 ||
3332  III.TruncateImmTo || III.ImmWidth != 16)
3333  return false;
3334 
3335  // Going from XForm to DForm loads means that the displacement needs to be
3336  // not just an immediate but also a multiple of 4, or 16 depending on the
3337  // load. A DForm load cannot be represented if it is a multiple of say 2.
3338  // XForm loads do not have this restriction.
3339  if (ImmMO.isGlobal() &&
3340  ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3341  return false;
3342 
3343  return true;
3344  }
3345 
3346  if (ImmMO.isImm()) {
3347  // It is Imm, we need to check if the Imm fit the range.
3348  int64_t Immediate = ImmMO.getImm();
3349  // Sign-extend to 64-bits.
3350  Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3351  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3352 
3353  if (Imm % III.ImmMustBeMultipleOf)
3354  return false;
3355  if (III.TruncateImmTo)
3356  Imm &= ((1 << III.TruncateImmTo) - 1);
3357  if (III.SignedImm) {
3358  APInt ActualValue(64, Imm, true);
3359  if (!ActualValue.isSignedIntN(III.ImmWidth))
3360  return false;
3361  } else {
3362  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3363  if ((uint64_t)Imm > UnsignedMax)
3364  return false;
3365  }
3366  }
3367  else
3368  return false;
3369 
3370  // This ImmMO is forwarded if it meets the requriement describle
3371  // in ImmInstrInfo
3372  return true;
3373 }
3374 
3375 // If an X-Form instruction is fed by an add-immediate and one of its operands
3376 // is the literal zero, attempt to forward the source of the add-immediate to
3377 // the corresponding D-Form instruction with the displacement coming from
3378 // the immediate being added.
3379 bool PPCInstrInfo::transformToImmFormFedByAdd(
3380  MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
3381  MachineInstr &DefMI, bool KillDefMI) const {
3382  // RegMO ImmMO
3383  // | |
3384  // x = addi reg, imm <----- DefMI
3385  // y = op 0 , x <----- MI
3386  // |
3387  // OpNoForForwarding
3388  // Check if the MI meet the requirement described in the III.
3389  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3390  return false;
3391 
3392  // Check if the DefMI meet the requirement
3393  // described in the III. If yes, set the ImmMO and RegMO accordingly.
3394  MachineOperand *ImmMO = nullptr;
3395  MachineOperand *RegMO = nullptr;
3396  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3397  return false;
3398  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
3399 
3400  // As we get the Imm operand now, we need to check if the ImmMO meet
3401  // the requirement described in the III. If yes set the Imm.
3402  int64_t Imm = 0;
3403  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3404  return false;
3405 
3406  bool IsFwdFeederRegKilled = false;
3407  // Check if the RegMO can be forwarded to MI.
3408  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
3409  IsFwdFeederRegKilled))
3410  return false;
3411 
3412  // Get killed info in case fixup needed after transformation.
3413  unsigned ForwardKilledOperandReg = ~0U;
3415  bool PostRA = !MRI.isSSA();
3416  if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
3417  ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
3418 
3419  // We know that, the MI and DefMI both meet the pattern, and
3420  // the Imm also meet the requirement with the new Imm-form.
3421  // It is safe to do the transformation now.
3422  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
3423  LLVM_DEBUG(MI.dump());
3424  LLVM_DEBUG(dbgs() << "Fed by:\n");
3425  LLVM_DEBUG(DefMI.dump());
3426 
3427  // Update the base reg first.
3429  false, false,
3430  RegMO->isKill());
3431 
3432  // Then, update the imm.
3433  if (ImmMO->isImm()) {
3434  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3435  // directly.
3437  }
3438  else {
3439  // Otherwise, it is Constant Pool Index(CPI) or Global,
3440  // which is relocation in fact. We need to replace the special zero
3441  // register with ImmMO.
3442  // Before that, we need to fixup the target flags for imm.
3443  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3444  if (DefMI.getOpcode() == PPC::ADDItocL)
3446 
3447  // MI didn't have the interface such as MI.setOperand(i) though
3448  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3449  // ImmMO, we need to remove ZERO operand and all the operands behind it,
3450  // and, add the ImmMO, then, move back all the operands behind ZERO.
3452  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3453  MOps.push_back(MI.getOperand(i));
3454  MI.RemoveOperand(i);
3455  }
3456 
3457  // Remove the last MO in the list, which is ZERO operand in fact.
3458  MOps.pop_back();
3459  // Add the imm operand.
3460  MI.addOperand(*ImmMO);
3461  // Now add the rest back.
3462  for (auto &MO : MOps)
3463  MI.addOperand(MO);
3464  }
3465 
3466  // Update the opcode.
3467  MI.setDesc(get(III.ImmOpcode));
3468 
3469  // Fix up killed/dead flag after transformation.
3470  // Pattern 1:
3471  // x = ADD KilledFwdFeederReg, imm
3472  // n = opn KilledFwdFeederReg(killed), regn
3473  // y = XOP 0, x
3474  // Pattern 2:
3475  // x = ADD reg(killed), imm
3476  // y = XOP 0, x
3477  if (IsFwdFeederRegKilled || RegMO->isKill())
3478  fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
3479  // Pattern 3:
3480  // ForwardKilledOperandReg = ADD reg, imm
3481  // y = XOP 0, ForwardKilledOperandReg(killed)
3482  if (ForwardKilledOperandReg != ~0U)
3483  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3484 
3485  LLVM_DEBUG(dbgs() << "With:\n");
3486  LLVM_DEBUG(MI.dump());
3487 
3488  return true;
3489 }
3490 
3491 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3492  const ImmInstrInfo &III,
3493  unsigned ConstantOpNo,
3494  MachineInstr &DefMI,
3495  int64_t Imm) const {
3497  bool PostRA = !MRI.isSSA();
3498  // Exit early if we can't convert this.
3499  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3500  return false;
3501  if (Imm % III.ImmMustBeMultipleOf)
3502  return false;
3503  if (III.TruncateImmTo)
3504  Imm &= ((1 << III.TruncateImmTo) - 1);
3505  if (III.SignedImm) {
3506  APInt ActualValue(64, Imm, true);
3507  if (!ActualValue.isSignedIntN(III.ImmWidth))
3508  return false;
3509  } else {
3510  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3511  if ((uint64_t)Imm > UnsignedMax)
3512  return false;
3513  }
3514 
3515  // If we're post-RA, the instructions don't agree on whether register zero is
3516  // special, we can transform this as long as the register operand that will
3517  // end up in the location where zero is special isn't R0.
3518  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3519  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3520  III.ZeroIsSpecialNew + 1;
3521  Register OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3522  Register NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3523  // If R0 is in the operand where zero is special for the new instruction,
3524  // it is unsafe to transform if the constant operand isn't that operand.
3525  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3526  ConstantOpNo != III.ZeroIsSpecialNew)
3527  return false;
3528  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3529  ConstantOpNo != PosForOrigZero)
3530  return false;
3531  }
3532 
3533  // Get killed info in case fixup needed after transformation.
3534  unsigned ForwardKilledOperandReg = ~0U;
3535  if (PostRA && MI.getOperand(ConstantOpNo).isKill())
3536  ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
3537 
3538  unsigned Opc = MI.getOpcode();
3539  bool SpecialShift32 =
3540  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3541  bool SpecialShift64 =
3542  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3543  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3544  Opc == PPC::SLDo || Opc == PPC::SRDo;
3545  bool RightShift =
3546  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3547 
3548  MI.setDesc(get(III.ImmOpcode));
3549  if (ConstantOpNo == III.OpNoForForwarding) {
3550  // Converting shifts to immediate form is a bit tricky since they may do
3551  // one of three things:
3552  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3553  // 2. If the shift amount is zero, the result is unchanged (save for maybe
3554  // setting CR0)
3555  // 3. If the shift amount is in [1, OpSize), it's just a shift
3556  if (SpecialShift32 || SpecialShift64) {
3557  LoadImmediateInfo LII;
3558  LII.Imm = 0;
3559  LII.SetCR = SetCR;
3560  LII.Is64Bit = SpecialShift64;
3561  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3562  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3563  replaceInstrWithLI(MI, LII);
3564  // Shifts by zero don't change the value. If we don't need to set CR0,
3565  // just convert this to a COPY. Can't do this post-RA since we've already
3566  // cleaned up the copies.
3567  else if (!SetCR && ShAmt == 0 && !PostRA) {
3568  MI.RemoveOperand(2);
3569  MI.setDesc(get(PPC::COPY));
3570  } else {
3571  // The 32 bit and 64 bit instructions are quite different.
3572  if (SpecialShift32) {
3573  // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3574  uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3575  uint64_t MB = RightShift ? ShAmt : 0;
3576  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3578  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3579  .addImm(ME);
3580  } else {
3581  // Left shifts use (N, 63-N), right shifts use (64-N, N).
3582  uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3583  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3585  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3586  }
3587  }
3588  } else
3589  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3590  }
3591  // Convert commutative instructions (switch the operands and convert the
3592  // desired one to an immediate.
3593  else if (III.IsCommutative) {
3594  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3595  swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3596  } else
3597  llvm_unreachable("Should have exited early!");
3598 
3599  // For instructions for which the constant register replaces a different
3600  // operand than where the immediate goes, we need to swap them.
3601  if (III.OpNoForForwarding != III.ImmOpNo)
3603 
3604  // If the special R0/X0 register index are different for original instruction
3605  // and new instruction, we need to fix up the register class in new
3606  // instruction.
3607  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3608  if (III.ZeroIsSpecialNew) {
3609  // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
3610  // need to fix up register class.
3611  Register RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3612  if (Register::isVirtualRegister(RegToModify)) {
3613  const TargetRegisterClass *NewRC =
3614  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3615  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3616  MRI.setRegClass(RegToModify, NewRC);
3617  }
3618  }
3619  }
3620 
3621  // Fix up killed/dead flag after transformation.
3622  // Pattern:
3623  // ForwardKilledOperandReg = LI imm
3624  // y = XOP reg, ForwardKilledOperandReg(killed)
3625  if (ForwardKilledOperandReg != ~0U)
3626  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3627  return true;
3628 }
3629 
3630 const TargetRegisterClass *
3632  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3633  return &PPC::VSRCRegClass;
3634  return RC;
3635 }
3636 
3638  return PPC::getRecordFormOpcode(Opcode);
3639 }
3640 
3641 // This function returns true if the machine instruction
3642 // always outputs a value by sign-extending a 32 bit value,
3643 // i.e. 0 to 31-th bits are same as 32-th bit.
3644 static bool isSignExtendingOp(const MachineInstr &MI) {
3645  int Opcode = MI.getOpcode();
3646  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3647  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3648  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3649  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3650  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3651  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3652  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3653  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3654  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3655  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3656  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3657  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3658  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3659  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3660  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3661  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3662  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3663  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3664  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3665  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3666  Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
3667  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3668  Opcode == PPC::EXTSB8_32_64)
3669  return true;
3670 
3671  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3672  return true;
3673 
3674  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3675  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3676  MI.getOperand(3).getImm() > 0 &&
3677  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3678  return true;
3679 
3680  return false;
3681 }
3682 
3683 // This function returns true if the machine instruction
3684 // always outputs zeros in higher 32 bits.
3685 static bool isZeroExtendingOp(const MachineInstr &MI) {
3686  int Opcode = MI.getOpcode();
3687  // The 16-bit immediate is sign-extended in li/lis.
3688  // If the most significant bit is zero, all higher bits are zero.
3689  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3690  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3691  int64_t Imm = MI.getOperand(1).getImm();
3692  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3693  return true;
3694  }
3695 
3696  // We have some variations of rotate-and-mask instructions
3697  // that clear higher 32-bits.
3698  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3699  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3700  Opcode == PPC::RLDICL_32_64) &&
3701  MI.getOperand(3).getImm() >= 32)
3702  return true;
3703 
3704  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3705  MI.getOperand(3).getImm() >= 32 &&
3706  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3707  return true;
3708 
3709  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3710  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3711  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3712  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3713  return true;
3714 
3715  // There are other instructions that clear higher 32-bits.
3716  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3717  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3718  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3719  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3720  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3721  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3722  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3723  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3724  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3725  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3726  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3727  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3728  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3729  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3730  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3731  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3732  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3733  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3734  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3735  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3736  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3737  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3738  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3739  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3740  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3741  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3742  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3743  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3744  Opcode == PPC::MFVSRWZ)
3745  return true;
3746 
3747  return false;
3748 }
3749 
3750 // This function returns true if the input MachineInstr is a TOC save
3751 // instruction.
3753  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3754  return false;
3755  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3756  unsigned StackOffset = MI.getOperand(1).getImm();
3757  Register StackReg = MI.getOperand(2).getReg();
3758  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3759  return true;
3760 
3761  return false;
3762 }
3763 
3764 // We limit the max depth to track incoming values of PHIs or binary ops
3765 // (e.g. AND) to avoid excessive cost.
3766 const unsigned MAX_DEPTH = 1;
3767 
3768 bool
3770  const unsigned Depth) const {
3771  const MachineFunction *MF = MI.getParent()->getParent();
3772  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3773 
3774  // If we know this instruction returns sign- or zero-extended result,
3775  // return true.
3776  if (SignExt ? isSignExtendingOp(MI):
3777  isZeroExtendingOp(MI))
3778  return true;
3779 
3780  switch (MI.getOpcode()) {
3781  case PPC::COPY: {
3782  Register SrcReg = MI.getOperand(1).getReg();
3783 
3784  // In both ELFv1 and v2 ABI, method parameters and the return value
3785  // are sign- or zero-extended.
3786  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3787  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3788  // We check the ZExt/SExt flags for a method parameter.
3789  if (MI.getParent()->getBasicBlock() ==
3790  &MF->getFunction().getEntryBlock()) {
3791  Register VReg = MI.getOperand(0).getReg();
3792  if (MF->getRegInfo().isLiveIn(VReg))
3793  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3794  FuncInfo->isLiveInZExt(VReg);
3795  }
3796 
3797  // For a method return value, we check the ZExt/SExt flags in attribute.
3798  // We assume the following code sequence for method call.
3799  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3800  // BL8_NOP @func,...
3801  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3802  // %5 = COPY %x3; G8RC:%5
3803  if (SrcReg == PPC::X3) {
3804  const MachineBasicBlock *MBB = MI.getParent();
3807  if (II != MBB->instr_begin() &&
3808  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3809  const MachineInstr &CallMI = *(--II);
3810  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3811  const Function *CalleeFn =
3812  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3813  if (!CalleeFn)
3814  return false;
3815  const IntegerType *IntTy =
3816  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3817  const AttributeSet &Attrs =
3818  CalleeFn->getAttributes().getRetAttributes();
3819  if (IntTy && IntTy->getBitWidth() <= 32)
3820  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3821  Attribute::ZExt);
3822  }
3823  }
3824  }
3825  }
3826 
3827  // If this is a copy from another register, we recursively check source.
3828  if (!Register::isVirtualRegister(SrcReg))
3829  return false;
3830  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3831  if (SrcMI != NULL)
3832  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3833 
3834  return false;
3835  }
3836 
3837  case PPC::ANDIo:
3838  case PPC::ANDISo:
3839  case PPC::ORI:
3840  case PPC::ORIS:
3841  case PPC::XORI:
3842  case PPC::XORIS:
3843  case PPC::ANDIo8:
3844  case PPC::ANDISo8:
3845  case PPC::ORI8:
3846  case PPC::ORIS8:
3847  case PPC::XORI8:
3848  case PPC::XORIS8: {
3849  // logical operation with 16-bit immediate does not change the upper bits.
3850  // So, we track the operand register as we do for register copy.
3851  Register SrcReg = MI.getOperand(1).getReg();
3852  if (!Register::isVirtualRegister(SrcReg))
3853  return false;
3854  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3855  if (SrcMI != NULL)
3856  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3857 
3858  return false;
3859  }
3860 
3861  // If all incoming values are sign-/zero-extended,
3862  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3863  case PPC::OR:
3864  case PPC::OR8:
3865  case PPC::ISEL:
3866  case PPC::PHI: {
3867  if (Depth >= MAX_DEPTH)
3868  return false;
3869 
3870  // The input registers for PHI are operand 1, 3, ...
3871  // The input registers for others are operand 1 and 2.
3872  unsigned E = 3, D = 1;
3873  if (MI.getOpcode() == PPC::PHI) {
3874  E = MI.getNumOperands();
3875  D = 2;
3876  }
3877 
3878  for (unsigned I = 1; I != E; I += D) {
3879  if (MI.getOperand(I).isReg()) {
3880  Register SrcReg = MI.getOperand(I).getReg();
3881  if (!Register::isVirtualRegister(SrcReg))
3882  return false;
3883  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3884  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3885  return false;
3886  }
3887  else
3888  return false;
3889  }
3890  return true;
3891  }
3892 
3893  // If at least one of the incoming values of an AND is zero extended
3894  // then the output is also zero-extended. If both of the incoming values
3895  // are sign-extended then the output is also sign extended.
3896  case PPC::AND:
3897  case PPC::AND8: {
3898  if (Depth >= MAX_DEPTH)
3899  return false;
3900 
3901  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3902 
3903  Register SrcReg1 = MI.getOperand(1).getReg();
3904  Register SrcReg2 = MI.getOperand(2).getReg();
3905 
3906  if (!Register::isVirtualRegister(SrcReg1) ||
3907  !Register::isVirtualRegister(SrcReg2))
3908  return false;
3909 
3910  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3911  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3912  if (!MISrc1 || !MISrc2)
3913  return false;
3914 
3915  if(SignExt)
3916  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3917  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3918  else
3919  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3920  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3921  }
3922 
3923  default:
3924  break;
3925  }
3926  return false;
3927 }
3928 
3929 bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
3930  return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ));
3931 }
3932 
3934  MachineInstr *&CmpInst) const {
3935  MachineBasicBlock *LoopEnd = L.getBottomBlock();
3937  // We really "analyze" only CTR loops right now.
3938  if (I != LoopEnd->end() && isBDNZ(I->getOpcode())) {
3939  IndVarInst = nullptr;
3940  CmpInst = &*I;
3941  return false;
3942  }
3943  return true;
3944 }
3945 
3946 MachineInstr *
3948 
3949  unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop);
3950 
3951  // The loop set-up instruction should be in preheader
3952  for (auto &I : PreHeader.instrs())
3953  if (I.getOpcode() == LOOPi)
3954  return &I;
3955  return nullptr;
3956 }
3957 
3959  MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar,
3961  SmallVectorImpl<MachineInstr *> &PrevInsts, unsigned Iter,
3962  unsigned MaxIter) const {
3963  // We expect a hardware loop currently. This means that IndVar is set
3964  // to null, and the compare is the ENDLOOP instruction.
3965  assert((!IndVar) && isBDNZ(Cmp.getOpcode()) && "Expecting a CTR loop");
3966  MachineFunction *MF = MBB.getParent();
3967  DebugLoc DL = Cmp.getDebugLoc();
3968  MachineInstr *Loop = findLoopInstr(PreHeader);
3969  if (!Loop)
3970  return 0;
3971  Register LoopCountReg = Loop->getOperand(0).getReg();
3973  MachineInstr *LoopCount = MRI.getUniqueVRegDef(LoopCountReg);
3974 
3975  if (!LoopCount)
3976  return 0;
3977  // If the loop trip count is a compile-time value, then just change the
3978  // value.
3979  if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI) {
3980  int64_t Offset = LoopCount->getOperand(1).getImm();
3981  if (Offset <= 1) {
3982  LoopCount->eraseFromParent();
3983  Loop->eraseFromParent();
3984  return 0;
3985  }
3986  LoopCount->getOperand(1).setImm(Offset - 1);
3987  return Offset - 1;
3988  }
3989 
3990  // The loop trip count is a run-time value.
3991  // We need to subtract one from the trip count,
3992  // and insert branch later to check if we're done with the loop.
3993 
3994  // Since BDZ/BDZ8 that we will insert will also decrease the ctr by 1,
3995  // so we don't need to generate any thing here.
3998  Subtarget.isPPC64() ? PPC::CTR8 : PPC::CTR, true));
3999  return LoopCountReg;
4000 }
4001 
4002 // Return true if get the base operand, byte offset of an instruction and the
4003 // memory width. Width is the size of memory that is being loaded/stored.
4005  const MachineInstr &LdSt,
4006  const MachineOperand *&BaseReg,
4007  int64_t &Offset,
4008  unsigned &Width,
4009  const TargetRegisterInfo *TRI) const {
4010  assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
4011 
4012  // Handle only loads/stores with base register followed by immediate offset.
4013  if (LdSt.getNumExplicitOperands() != 3)
4014  return false;
4015  if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
4016  return false;
4017 
4018  if (!LdSt.hasOneMemOperand())
4019  return false;
4020 
4021  Width = (*LdSt.memoperands_begin())->getSize();
4022  Offset = LdSt.getOperand(1).getImm();
4023  BaseReg = &LdSt.getOperand(2);
4024  return true;
4025 }
4026 
4028  const MachineInstr &MIa, const MachineInstr &MIb,
4029  AliasAnalysis * /*AA*/) const {
4030  assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
4031  assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
4032 
4033  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
4035  return false;
4036 
4037  // Retrieve the base register, offset from the base register and width. Width
4038  // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
4039  // base registers are identical, and the offset of a lower memory access +
4040  // the width doesn't overlap the offset of a higher memory access,
4041  // then the memory accesses are different.
4043  const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
4044  int64_t OffsetA = 0, OffsetB = 0;
4045  unsigned int WidthA = 0, WidthB = 0;
4046  if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
4047  getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
4048  if (BaseOpA->isIdenticalTo(*BaseOpB)) {
4049  int LowOffset = std::min(OffsetA, OffsetB);
4050  int HighOffset = std::max(OffsetA, OffsetB);
4051  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
4052  if (LowOffset + LowWidth <= HighOffset)
4053  return true;
4054  }
4055  }
4056  return false;
4057 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
StackOffset is a wrapper around scalable and non-scalable offsets and is used in several functions su...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:651
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:86
void setTargetFlags(unsigned F)
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:543
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
static int getRecordFormOpcode(unsigned Opcode)
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:252
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:88
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:848
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:98
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
void setIsDead(bool Val=true)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader) const
Find the hardware loop instruction used to set-up the specified loop.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:257
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:90
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:100
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:414
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
return AArch64::GPR64RegClass contains(Reg)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:187
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
Analyze the loop code to find the loop induction variable and compare used to compute the number of i...
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:225
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
bool hasDirectMove() const
Definition: PPCSubtarget.h:281
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:196
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:667
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:83
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1581
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:257
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:104
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:194
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
void setReg(Register Reg)
Change the register this operand corresponds to.
unsigned getAlignment() const
Definition: Globals.cpp:97
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:66
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:675
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:657
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:664
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:596
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:565
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:99
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:188
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:567
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:76
Class to represent integer types.
Definition: DerivedTypes.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1186
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:173
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:107
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:197
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:202
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:50
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:552
static uint64_t add(uint64_t LeftOp, uint64_t RightOp)
Definition: FileCheck.cpp:214
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:997
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:398
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:69
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:491
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
Representation of each machine instruction.
Definition: MachineInstr.h:64
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
Return true if two MIs access different memory addresses and false otherwise.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:418
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:35
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:509
TargetOptions Options
static bool isSignExtendingOp(const MachineInstr &MI)
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:80
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and zero-extended.
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:698
LLVM Value Representation.
Definition: Value.h:73
static use_instr_iterator use_instr_end()
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:265
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:189
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:658
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:320
Register getReg() const
getReg - Returns the register number.
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:91
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:185
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:313
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
Instructions::const_iterator const_instr_iterator
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:95
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
static bool isAnImmediateOperand(const MachineOperand &MO)
bool expandPostRAPseudo(MachineInstr &MI) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:187
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:420
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...