LLVM  10.0.0svn
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "ppc-instr-info"
43 
44 #define GET_INSTRMAP_INFO
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "PPCGenInstrInfo.inc"
47 
48 STATISTIC(NumStoreSPILLVSRRCAsVec,
49  "Number of spillvsrrc spilled to stack as vec");
50 STATISTIC(NumStoreSPILLVSRRCAsGpr,
51  "Number of spillvsrrc spilled to stack as gpr");
52 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
53 STATISTIC(CmpIselsConverted,
54  "Number of ISELs that depend on comparison of constants converted");
55 STATISTIC(MissedConvertibleImmediateInstrs,
56  "Number of compare-immediate instructions fed by constants");
57 STATISTIC(NumRcRotatesConvertedToRcAnd,
58  "Number of record-form rotates converted to record-form andi");
59 
60 static cl::
61 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
62  cl::desc("Disable analysis for CTR loops"));
63 
64 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
65 cl::desc("Disable compare instruction optimization"), cl::Hidden);
66 
67 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
68 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
69 cl::Hidden);
70 
71 static cl::opt<bool>
72 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
73  cl::desc("Use the old (incorrect) instruction latency calculation"));
74 
75 // Index into the OpcodesForSpill array.
94  SOK_LastOpcodeSpill // This must be last on the enum.
95 };
96 
97 // Pin the vtable to this file.
98 void PPCInstrInfo::anchor() {}
99 
101  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
102  /* CatchRetOpcode */ -1,
103  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
104  Subtarget(STI), RI(STI.getTargetMachine()) {}
105 
106 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
107 /// this target when scheduling the DAG.
110  const ScheduleDAG *DAG) const {
111  unsigned Directive =
112  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
113  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
114  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
115  const InstrItineraryData *II =
116  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
117  return new ScoreboardHazardRecognizer(II, DAG);
118  }
119 
121 }
122 
123 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
124 /// to use for this target when scheduling the DAG.
127  const ScheduleDAG *DAG) const {
128  unsigned Directive =
129  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
130 
131  // FIXME: Leaving this as-is until we have POWER9 scheduling info
132  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
133  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
134 
135  // Most subtargets use a PPC970 recognizer.
136  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
137  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
138  assert(DAG->TII && "No InstrInfo?");
139 
140  return new PPCHazardRecognizer970(*DAG);
141  }
142 
143  return new ScoreboardHazardRecognizer(II, DAG);
144 }
145 
147  const MachineInstr &MI,
148  unsigned *PredCost) const {
149  if (!ItinData || UseOldLatencyCalc)
150  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
151 
152  // The default implementation of getInstrLatency calls getStageLatency, but
153  // getStageLatency does not do the right thing for us. While we have
154  // itinerary, most cores are fully pipelined, and so the itineraries only
155  // express the first part of the pipeline, not every stage. Instead, we need
156  // to use the listed output operand cycle number (using operand 0 here, which
157  // is an output).
158 
159  unsigned Latency = 1;
160  unsigned DefClass = MI.getDesc().getSchedClass();
161  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
162  const MachineOperand &MO = MI.getOperand(i);
163  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
164  continue;
165 
166  int Cycle = ItinData->getOperandCycle(DefClass, i);
167  if (Cycle < 0)
168  continue;
169 
170  Latency = std::max(Latency, (unsigned) Cycle);
171  }
172 
173  return Latency;
174 }
175 
177  const MachineInstr &DefMI, unsigned DefIdx,
178  const MachineInstr &UseMI,
179  unsigned UseIdx) const {
180  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
181  UseMI, UseIdx);
182 
183  if (!DefMI.getParent())
184  return Latency;
185 
186  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
187  unsigned Reg = DefMO.getReg();
188 
189  bool IsRegCR;
191  const MachineRegisterInfo *MRI =
192  &DefMI.getParent()->getParent()->getRegInfo();
193  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
194  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
195  } else {
196  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
197  PPC::CRBITRCRegClass.contains(Reg);
198  }
199 
200  if (UseMI.isBranch() && IsRegCR) {
201  if (Latency < 0)
202  Latency = getInstrLatency(ItinData, DefMI);
203 
204  // On some cores, there is an additional delay between writing to a condition
205  // register, and using it from a branch.
206  unsigned Directive = Subtarget.getDarwinDirective();
207  switch (Directive) {
208  default: break;
209  case PPC::DIR_7400:
210  case PPC::DIR_750:
211  case PPC::DIR_970:
212  case PPC::DIR_E5500:
213  case PPC::DIR_PWR4:
214  case PPC::DIR_PWR5:
215  case PPC::DIR_PWR5X:
216  case PPC::DIR_PWR6:
217  case PPC::DIR_PWR6X:
218  case PPC::DIR_PWR7:
219  case PPC::DIR_PWR8:
220  // FIXME: Is this needed for POWER9?
221  Latency += 2;
222  break;
223  }
224  }
225 
226  return Latency;
227 }
228 
229 // This function does not list all associative and commutative operations, but
230 // only those worth feeding through the machine combiner in an attempt to
231 // reduce the critical path. Mostly, this means floating-point operations,
232 // because they have high latencies (compared to other operations, such and
233 // and/or, which are also associative and commutative, but have low latencies).
235  switch (Inst.getOpcode()) {
236  // FP Add:
237  case PPC::FADD:
238  case PPC::FADDS:
239  // FP Multiply:
240  case PPC::FMUL:
241  case PPC::FMULS:
242  // Altivec Add:
243  case PPC::VADDFP:
244  // VSX Add:
245  case PPC::XSADDDP:
246  case PPC::XVADDDP:
247  case PPC::XVADDSP:
248  case PPC::XSADDSP:
249  // VSX Multiply:
250  case PPC::XSMULDP:
251  case PPC::XVMULDP:
252  case PPC::XVMULSP:
253  case PPC::XSMULSP:
254  // QPX Add:
255  case PPC::QVFADD:
256  case PPC::QVFADDS:
257  case PPC::QVFADDSs:
258  // QPX Multiply:
259  case PPC::QVFMUL:
260  case PPC::QVFMULS:
261  case PPC::QVFMULSs:
262  return true;
263  default:
264  return false;
265  }
266 }
267 
269  MachineInstr &Root,
270  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
271  // Using the machine combiner in this way is potentially expensive, so
272  // restrict to when aggressive optimizations are desired.
274  return false;
275 
276  // FP reassociation is only legal when we don't need strict IEEE semantics.
278  return false;
279 
280  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
281 }
282 
283 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
285  unsigned &SrcReg, unsigned &DstReg,
286  unsigned &SubIdx) const {
287  switch (MI.getOpcode()) {
288  default: return false;
289  case PPC::EXTSW:
290  case PPC::EXTSW_32:
291  case PPC::EXTSW_32_64:
292  SrcReg = MI.getOperand(1).getReg();
293  DstReg = MI.getOperand(0).getReg();
294  SubIdx = PPC::sub_32;
295  return true;
296  }
297 }
298 
300  int &FrameIndex) const {
301  unsigned Opcode = MI.getOpcode();
302  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
303  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
304 
305  if (End != std::find(OpcodesForSpill, End, Opcode)) {
306  // Check for the operands added by addFrameReference (the immediate is the
307  // offset which defaults to 0).
308  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
309  MI.getOperand(2).isFI()) {
310  FrameIndex = MI.getOperand(2).getIndex();
311  return MI.getOperand(0).getReg();
312  }
313  }
314  return 0;
315 }
316 
317 // For opcodes with the ReMaterializable flag set, this function is called to
318 // verify the instruction is really rematable.
320  AliasAnalysis *AA) const {
321  switch (MI.getOpcode()) {
322  default:
323  // This function should only be called for opcodes with the ReMaterializable
324  // flag set.
325  llvm_unreachable("Unknown rematerializable operation!");
326  break;
327  case PPC::LI:
328  case PPC::LI8:
329  case PPC::LIS:
330  case PPC::LIS8:
331  case PPC::QVGPCI:
332  case PPC::ADDIStocHA:
333  case PPC::ADDItocL:
334  case PPC::LOAD_STACK_GUARD:
335  case PPC::XXLXORz:
336  case PPC::XXLXORspz:
337  case PPC::XXLXORdpz:
338  case PPC::V_SET0B:
339  case PPC::V_SET0H:
340  case PPC::V_SET0:
341  case PPC::V_SETALLONESB:
342  case PPC::V_SETALLONESH:
343  case PPC::V_SETALLONES:
344  case PPC::CRSET:
345  case PPC::CRUNSET:
346  return true;
347  }
348  return false;
349 }
350 
352  int &FrameIndex) const {
353  unsigned Opcode = MI.getOpcode();
354  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
355  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
356 
357  if (End != std::find(OpcodesForSpill, End, Opcode)) {
358  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
359  MI.getOperand(2).isFI()) {
360  FrameIndex = MI.getOperand(2).getIndex();
361  return MI.getOperand(0).getReg();
362  }
363  }
364  return 0;
365 }
366 
368  unsigned OpIdx1,
369  unsigned OpIdx2) const {
370  MachineFunction &MF = *MI.getParent()->getParent();
371 
372  // Normal instructions can be commuted the obvious way.
373  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
374  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
375  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
376  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
377  // changing the relative order of the mask operands might change what happens
378  // to the high-bits of the mask (and, thus, the result).
379 
380  // Cannot commute if it has a non-zero rotate count.
381  if (MI.getOperand(3).getImm() != 0)
382  return nullptr;
383 
384  // If we have a zero rotate count, we have:
385  // M = mask(MB,ME)
386  // Op0 = (Op1 & ~M) | (Op2 & M)
387  // Change this to:
388  // M = mask((ME+1)&31, (MB-1)&31)
389  // Op0 = (Op2 & ~M) | (Op1 & M)
390 
391  // Swap op1/op2
392  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
393  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
394  Register Reg0 = MI.getOperand(0).getReg();
395  Register Reg1 = MI.getOperand(1).getReg();
396  Register Reg2 = MI.getOperand(2).getReg();
397  unsigned SubReg1 = MI.getOperand(1).getSubReg();
398  unsigned SubReg2 = MI.getOperand(2).getSubReg();
399  bool Reg1IsKill = MI.getOperand(1).isKill();
400  bool Reg2IsKill = MI.getOperand(2).isKill();
401  bool ChangeReg0 = false;
402  // If machine instrs are no longer in two-address forms, update
403  // destination register as well.
404  if (Reg0 == Reg1) {
405  // Must be two address instruction!
407  "Expecting a two-address instruction!");
408  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
409  Reg2IsKill = false;
410  ChangeReg0 = true;
411  }
412 
413  // Masks.
414  unsigned MB = MI.getOperand(4).getImm();
415  unsigned ME = MI.getOperand(5).getImm();
416 
417  // We can't commute a trivial mask (there is no way to represent an all-zero
418  // mask).
419  if (MB == 0 && ME == 31)
420  return nullptr;
421 
422  if (NewMI) {
423  // Create a new instruction.
424  Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
425  bool Reg0IsDead = MI.getOperand(0).isDead();
426  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
427  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
428  .addReg(Reg2, getKillRegState(Reg2IsKill))
429  .addReg(Reg1, getKillRegState(Reg1IsKill))
430  .addImm((ME + 1) & 31)
431  .addImm((MB - 1) & 31);
432  }
433 
434  if (ChangeReg0) {
435  MI.getOperand(0).setReg(Reg2);
436  MI.getOperand(0).setSubReg(SubReg2);
437  }
438  MI.getOperand(2).setReg(Reg1);
439  MI.getOperand(1).setReg(Reg2);
440  MI.getOperand(2).setSubReg(SubReg1);
441  MI.getOperand(1).setSubReg(SubReg2);
442  MI.getOperand(2).setIsKill(Reg1IsKill);
443  MI.getOperand(1).setIsKill(Reg2IsKill);
444 
445  // Swap the mask around.
446  MI.getOperand(4).setImm((ME + 1) & 31);
447  MI.getOperand(5).setImm((MB - 1) & 31);
448  return &MI;
449 }
450 
452  unsigned &SrcOpIdx2) const {
453  // For VSX A-Type FMA instructions, it is the first two operands that can be
454  // commuted, however, because the non-encoded tied input operand is listed
455  // first, the operands to swap are actually the second and third.
456 
457  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
458  if (AltOpc == -1)
459  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
460 
461  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
462  // and SrcOpIdx2.
463  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
464 }
465 
468  // This function is used for scheduling, and the nop wanted here is the type
469  // that terminates dispatch groups on the POWER cores.
470  unsigned Directive = Subtarget.getDarwinDirective();
471  unsigned Opcode;
472  switch (Directive) {
473  default: Opcode = PPC::NOP; break;
474  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
475  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
476  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
477  // FIXME: Update when POWER9 scheduling model is ready.
478  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
479  }
480 
481  DebugLoc DL;
482  BuildMI(MBB, MI, DL, get(Opcode));
483 }
484 
485 /// Return the noop instruction to use for a noop.
486 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
487  NopInst.setOpcode(PPC::NOP);
488 }
489 
490 // Branch analysis.
491 // Note: If the condition register is set to CTR or CTR8 then this is a
492 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
494  MachineBasicBlock *&TBB,
495  MachineBasicBlock *&FBB,
497  bool AllowModify) const {
498  bool isPPC64 = Subtarget.isPPC64();
499 
500  // If the block has no terminators, it just falls into the block after it.
502  if (I == MBB.end())
503  return false;
504 
505  if (!isUnpredicatedTerminator(*I))
506  return false;
507 
508  if (AllowModify) {
509  // If the BB ends with an unconditional branch to the fallthrough BB,
510  // we eliminate the branch instruction.
511  if (I->getOpcode() == PPC::B &&
512  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
513  I->eraseFromParent();
514 
515  // We update iterator after deleting the last branch.
516  I = MBB.getLastNonDebugInstr();
517  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
518  return false;
519  }
520  }
521 
522  // Get the last instruction in the block.
523  MachineInstr &LastInst = *I;
524 
525  // If there is only one terminator instruction, process it.
526  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
527  if (LastInst.getOpcode() == PPC::B) {
528  if (!LastInst.getOperand(0).isMBB())
529  return true;
530  TBB = LastInst.getOperand(0).getMBB();
531  return false;
532  } else if (LastInst.getOpcode() == PPC::BCC) {
533  if (!LastInst.getOperand(2).isMBB())
534  return true;
535  // Block ends with fall-through condbranch.
536  TBB = LastInst.getOperand(2).getMBB();
537  Cond.push_back(LastInst.getOperand(0));
538  Cond.push_back(LastInst.getOperand(1));
539  return false;
540  } else if (LastInst.getOpcode() == PPC::BC) {
541  if (!LastInst.getOperand(1).isMBB())
542  return true;
543  // Block ends with fall-through condbranch.
544  TBB = LastInst.getOperand(1).getMBB();
546  Cond.push_back(LastInst.getOperand(0));
547  return false;
548  } else if (LastInst.getOpcode() == PPC::BCn) {
549  if (!LastInst.getOperand(1).isMBB())
550  return true;
551  // Block ends with fall-through condbranch.
552  TBB = LastInst.getOperand(1).getMBB();
554  Cond.push_back(LastInst.getOperand(0));
555  return false;
556  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
557  LastInst.getOpcode() == PPC::BDNZ) {
558  if (!LastInst.getOperand(0).isMBB())
559  return true;
560  if (DisableCTRLoopAnal)
561  return true;
562  TBB = LastInst.getOperand(0).getMBB();
564  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
565  true));
566  return false;
567  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
568  LastInst.getOpcode() == PPC::BDZ) {
569  if (!LastInst.getOperand(0).isMBB())
570  return true;
571  if (DisableCTRLoopAnal)
572  return true;
573  TBB = LastInst.getOperand(0).getMBB();
575  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
576  true));
577  return false;
578  }
579 
580  // Otherwise, don't know what this is.
581  return true;
582  }
583 
584  // Get the instruction before it if it's a terminator.
585  MachineInstr &SecondLastInst = *I;
586 
587  // If there are three terminators, we don't know what sort of block this is.
588  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
589  return true;
590 
591  // If the block ends with PPC::B and PPC:BCC, handle it.
592  if (SecondLastInst.getOpcode() == PPC::BCC &&
593  LastInst.getOpcode() == PPC::B) {
594  if (!SecondLastInst.getOperand(2).isMBB() ||
595  !LastInst.getOperand(0).isMBB())
596  return true;
597  TBB = SecondLastInst.getOperand(2).getMBB();
598  Cond.push_back(SecondLastInst.getOperand(0));
599  Cond.push_back(SecondLastInst.getOperand(1));
600  FBB = LastInst.getOperand(0).getMBB();
601  return false;
602  } else if (SecondLastInst.getOpcode() == PPC::BC &&
603  LastInst.getOpcode() == PPC::B) {
604  if (!SecondLastInst.getOperand(1).isMBB() ||
605  !LastInst.getOperand(0).isMBB())
606  return true;
607  TBB = SecondLastInst.getOperand(1).getMBB();
609  Cond.push_back(SecondLastInst.getOperand(0));
610  FBB = LastInst.getOperand(0).getMBB();
611  return false;
612  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
613  LastInst.getOpcode() == PPC::B) {
614  if (!SecondLastInst.getOperand(1).isMBB() ||
615  !LastInst.getOperand(0).isMBB())
616  return true;
617  TBB = SecondLastInst.getOperand(1).getMBB();
619  Cond.push_back(SecondLastInst.getOperand(0));
620  FBB = LastInst.getOperand(0).getMBB();
621  return false;
622  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
623  SecondLastInst.getOpcode() == PPC::BDNZ) &&
624  LastInst.getOpcode() == PPC::B) {
625  if (!SecondLastInst.getOperand(0).isMBB() ||
626  !LastInst.getOperand(0).isMBB())
627  return true;
628  if (DisableCTRLoopAnal)
629  return true;
630  TBB = SecondLastInst.getOperand(0).getMBB();
632  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
633  true));
634  FBB = LastInst.getOperand(0).getMBB();
635  return false;
636  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
637  SecondLastInst.getOpcode() == PPC::BDZ) &&
638  LastInst.getOpcode() == PPC::B) {
639  if (!SecondLastInst.getOperand(0).isMBB() ||
640  !LastInst.getOperand(0).isMBB())
641  return true;
642  if (DisableCTRLoopAnal)
643  return true;
644  TBB = SecondLastInst.getOperand(0).getMBB();
646  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
647  true));
648  FBB = LastInst.getOperand(0).getMBB();
649  return false;
650  }
651 
652  // If the block ends with two PPC:Bs, handle it. The second one is not
653  // executed, so remove it.
654  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
655  if (!SecondLastInst.getOperand(0).isMBB())
656  return true;
657  TBB = SecondLastInst.getOperand(0).getMBB();
658  I = LastInst;
659  if (AllowModify)
660  I->eraseFromParent();
661  return false;
662  }
663 
664  // Otherwise, can't handle this.
665  return true;
666 }
667 
669  int *BytesRemoved) const {
670  assert(!BytesRemoved && "code size not handled");
671 
673  if (I == MBB.end())
674  return 0;
675 
676  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
677  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
678  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
679  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
680  return 0;
681 
682  // Remove the branch.
683  I->eraseFromParent();
684 
685  I = MBB.end();
686 
687  if (I == MBB.begin()) return 1;
688  --I;
689  if (I->getOpcode() != PPC::BCC &&
690  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
691  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
692  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
693  return 1;
694 
695  // Remove the branch.
696  I->eraseFromParent();
697  return 2;
698 }
699 
701  MachineBasicBlock *TBB,
702  MachineBasicBlock *FBB,
704  const DebugLoc &DL,
705  int *BytesAdded) const {
706  // Shouldn't be a fall through.
707  assert(TBB && "insertBranch must not be told to insert a fallthrough");
708  assert((Cond.size() == 2 || Cond.size() == 0) &&
709  "PPC branch conditions have two components!");
710  assert(!BytesAdded && "code size not handled");
711 
712  bool isPPC64 = Subtarget.isPPC64();
713 
714  // One-way branch.
715  if (!FBB) {
716  if (Cond.empty()) // Unconditional branch
717  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
718  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
719  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
720  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
721  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
722  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
723  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
724  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
725  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
726  else // Conditional branch
727  BuildMI(&MBB, DL, get(PPC::BCC))
728  .addImm(Cond[0].getImm())
729  .add(Cond[1])
730  .addMBB(TBB);
731  return 1;
732  }
733 
734  // Two-way Conditional Branch.
735  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
736  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
737  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
738  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
739  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
740  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
741  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
742  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
743  else
744  BuildMI(&MBB, DL, get(PPC::BCC))
745  .addImm(Cond[0].getImm())
746  .add(Cond[1])
747  .addMBB(TBB);
748  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
749  return 2;
750 }
751 
752 // Select analysis.
755  unsigned TrueReg, unsigned FalseReg,
756  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
757  if (Cond.size() != 2)
758  return false;
759 
760  // If this is really a bdnz-like condition, then it cannot be turned into a
761  // select.
762  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
763  return false;
764 
765  // Check register classes.
766  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
767  const TargetRegisterClass *RC =
768  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
769  if (!RC)
770  return false;
771 
772  // isel is for regular integer GPRs only.
773  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
774  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
775  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
776  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
777  return false;
778 
779  // FIXME: These numbers are for the A2, how well they work for other cores is
780  // an open question. On the A2, the isel instruction has a 2-cycle latency
781  // but single-cycle throughput. These numbers are used in combination with
782  // the MispredictPenalty setting from the active SchedMachineModel.
783  CondCycles = 1;
784  TrueCycles = 1;
785  FalseCycles = 1;
786 
787  return true;
788 }
789 
792  const DebugLoc &dl, unsigned DestReg,
793  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
794  unsigned FalseReg) const {
795  assert(Cond.size() == 2 &&
796  "PPC branch conditions have two components!");
797 
798  // Get the register classes.
800  const TargetRegisterClass *RC =
801  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
802  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
803 
804  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
805  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
806  assert((Is64Bit ||
807  PPC::GPRCRegClass.hasSubClassEq(RC) ||
808  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
809  "isel is for regular integer GPRs only");
810 
811  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
812  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
813 
814  unsigned SubIdx = 0;
815  bool SwapOps = false;
816  switch (SelectPred) {
817  case PPC::PRED_EQ:
818  case PPC::PRED_EQ_MINUS:
819  case PPC::PRED_EQ_PLUS:
820  SubIdx = PPC::sub_eq; SwapOps = false; break;
821  case PPC::PRED_NE:
822  case PPC::PRED_NE_MINUS:
823  case PPC::PRED_NE_PLUS:
824  SubIdx = PPC::sub_eq; SwapOps = true; break;
825  case PPC::PRED_LT:
826  case PPC::PRED_LT_MINUS:
827  case PPC::PRED_LT_PLUS:
828  SubIdx = PPC::sub_lt; SwapOps = false; break;
829  case PPC::PRED_GE:
830  case PPC::PRED_GE_MINUS:
831  case PPC::PRED_GE_PLUS:
832  SubIdx = PPC::sub_lt; SwapOps = true; break;
833  case PPC::PRED_GT:
834  case PPC::PRED_GT_MINUS:
835  case PPC::PRED_GT_PLUS:
836  SubIdx = PPC::sub_gt; SwapOps = false; break;
837  case PPC::PRED_LE:
838  case PPC::PRED_LE_MINUS:
839  case PPC::PRED_LE_PLUS:
840  SubIdx = PPC::sub_gt; SwapOps = true; break;
841  case PPC::PRED_UN:
842  case PPC::PRED_UN_MINUS:
843  case PPC::PRED_UN_PLUS:
844  SubIdx = PPC::sub_un; SwapOps = false; break;
845  case PPC::PRED_NU:
846  case PPC::PRED_NU_MINUS:
847  case PPC::PRED_NU_PLUS:
848  SubIdx = PPC::sub_un; SwapOps = true; break;
849  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
850  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
851  }
852 
853  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
854  SecondReg = SwapOps ? TrueReg : FalseReg;
855 
856  // The first input register of isel cannot be r0. If it is a member
857  // of a register class that can be r0, then copy it first (the
858  // register allocator should eliminate the copy).
859  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
860  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
861  const TargetRegisterClass *FirstRC =
862  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
863  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
864  unsigned OldFirstReg = FirstReg;
865  FirstReg = MRI.createVirtualRegister(FirstRC);
866  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
867  .addReg(OldFirstReg);
868  }
869 
870  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
871  .addReg(FirstReg).addReg(SecondReg)
872  .addReg(Cond[1].getReg(), 0, SubIdx);
873 }
874 
875 static unsigned getCRBitValue(unsigned CRBit) {
876  unsigned Ret = 4;
877  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
878  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
879  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
880  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
881  Ret = 3;
882  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
883  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
884  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
885  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
886  Ret = 2;
887  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
888  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
889  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
890  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
891  Ret = 1;
892  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
893  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
894  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
895  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
896  Ret = 0;
897 
898  assert(Ret != 4 && "Invalid CR bit register");
899  return Ret;
900 }
901 
904  const DebugLoc &DL, unsigned DestReg,
905  unsigned SrcReg, bool KillSrc) const {
906  // We can end up with self copies and similar things as a result of VSX copy
907  // legalization. Promote them here.
909  if (PPC::F8RCRegClass.contains(DestReg) &&
910  PPC::VSRCRegClass.contains(SrcReg)) {
911  unsigned SuperReg =
912  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
913 
914  if (VSXSelfCopyCrash && SrcReg == SuperReg)
915  llvm_unreachable("nop VSX copy");
916 
917  DestReg = SuperReg;
918  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
919  PPC::VSRCRegClass.contains(DestReg)) {
920  unsigned SuperReg =
921  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
922 
923  if (VSXSelfCopyCrash && DestReg == SuperReg)
924  llvm_unreachable("nop VSX copy");
925 
926  SrcReg = SuperReg;
927  }
928 
929  // Different class register copy
930  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
931  PPC::GPRCRegClass.contains(DestReg)) {
932  unsigned CRReg = getCRFromCRBit(SrcReg);
933  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
934  getKillRegState(KillSrc);
935  // Rotate the CR bit in the CR fields to be the least significant bit and
936  // then mask with 0x1 (MB = ME = 31).
937  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
938  .addReg(DestReg, RegState::Kill)
939  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
940  .addImm(31)
941  .addImm(31);
942  return;
943  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
944  PPC::G8RCRegClass.contains(DestReg)) {
945  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
946  getKillRegState(KillSrc);
947  return;
948  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
949  PPC::GPRCRegClass.contains(DestReg)) {
950  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
951  getKillRegState(KillSrc);
952  return;
953  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
954  PPC::VSFRCRegClass.contains(DestReg)) {
955  assert(Subtarget.hasDirectMove() &&
956  "Subtarget doesn't support directmove, don't know how to copy.");
957  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
958  NumGPRtoVSRSpill++;
959  getKillRegState(KillSrc);
960  return;
961  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
962  PPC::G8RCRegClass.contains(DestReg)) {
963  assert(Subtarget.hasDirectMove() &&
964  "Subtarget doesn't support directmove, don't know how to copy.");
965  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
966  getKillRegState(KillSrc);
967  return;
968  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
969  PPC::SPE4RCRegClass.contains(DestReg)) {
970  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
971  getKillRegState(KillSrc);
972  return;
973  } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
974  PPC::SPERCRegClass.contains(DestReg)) {
975  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
976  getKillRegState(KillSrc);
977  return;
978  }
979 
980  unsigned Opc;
981  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
982  Opc = PPC::OR;
983  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
984  Opc = PPC::OR8;
985  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
986  Opc = PPC::FMR;
987  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
988  Opc = PPC::MCRF;
989  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
990  Opc = PPC::VOR;
991  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
992  // There are two different ways this can be done:
993  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
994  // issue in VSU pipeline 0.
995  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
996  // can go to either pipeline.
997  // We'll always use xxlor here, because in practically all cases where
998  // copies are generated, they are close enough to some use that the
999  // lower-latency form is preferable.
1000  Opc = PPC::XXLOR;
1001  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1002  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1003  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1004  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
1005  Opc = PPC::QVFMR;
1006  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
1007  Opc = PPC::QVFMRs;
1008  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
1009  Opc = PPC::QVFMRb;
1010  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1011  Opc = PPC::CROR;
1012  else if (PPC::SPE4RCRegClass.contains(DestReg, SrcReg))
1013  Opc = PPC::OR;
1014  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1015  Opc = PPC::EVOR;
1016  else
1017  llvm_unreachable("Impossible reg-to-reg copy");
1018 
1019  const MCInstrDesc &MCID = get(Opc);
1020  if (MCID.getNumOperands() == 3)
1021  BuildMI(MBB, I, DL, MCID, DestReg)
1022  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1023  else
1024  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1025 }
1026 
1028  const TargetRegisterClass *RC)
1029  const {
1030  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1031  int OpcodeIndex = 0;
1032 
1033  if (RC != nullptr) {
1034  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1035  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1036  OpcodeIndex = SOK_Int4Spill;
1037  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1038  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1039  OpcodeIndex = SOK_Int8Spill;
1040  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1041  OpcodeIndex = SOK_Float8Spill;
1042  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1043  OpcodeIndex = SOK_Float4Spill;
1044  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1045  OpcodeIndex = SOK_SPESpill;
1046  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1047  OpcodeIndex = SOK_SPE4Spill;
1048  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1049  OpcodeIndex = SOK_CRSpill;
1050  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1051  OpcodeIndex = SOK_CRBitSpill;
1052  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1053  OpcodeIndex = SOK_VRVectorSpill;
1054  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1055  OpcodeIndex = SOK_VSXVectorSpill;
1056  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1057  OpcodeIndex = SOK_VectorFloat8Spill;
1058  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1059  OpcodeIndex = SOK_VectorFloat4Spill;
1060  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1061  OpcodeIndex = SOK_VRSaveSpill;
1062  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1063  OpcodeIndex = SOK_QuadFloat8Spill;
1064  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1065  OpcodeIndex = SOK_QuadFloat4Spill;
1066  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1067  OpcodeIndex = SOK_QuadBitSpill;
1068  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1069  OpcodeIndex = SOK_SpillToVSR;
1070  } else {
1071  llvm_unreachable("Unknown regclass!");
1072  }
1073  } else {
1074  if (PPC::GPRCRegClass.contains(Reg) ||
1075  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1076  OpcodeIndex = SOK_Int4Spill;
1077  } else if (PPC::G8RCRegClass.contains(Reg) ||
1078  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1079  OpcodeIndex = SOK_Int8Spill;
1080  } else if (PPC::F8RCRegClass.contains(Reg)) {
1081  OpcodeIndex = SOK_Float8Spill;
1082  } else if (PPC::F4RCRegClass.contains(Reg)) {
1083  OpcodeIndex = SOK_Float4Spill;
1084  } else if (PPC::SPERCRegClass.contains(Reg)) {
1085  OpcodeIndex = SOK_SPESpill;
1086  } else if (PPC::SPE4RCRegClass.contains(Reg)) {
1087  OpcodeIndex = SOK_SPE4Spill;
1088  } else if (PPC::CRRCRegClass.contains(Reg)) {
1089  OpcodeIndex = SOK_CRSpill;
1090  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1091  OpcodeIndex = SOK_CRBitSpill;
1092  } else if (PPC::VRRCRegClass.contains(Reg)) {
1093  OpcodeIndex = SOK_VRVectorSpill;
1094  } else if (PPC::VSRCRegClass.contains(Reg)) {
1095  OpcodeIndex = SOK_VSXVectorSpill;
1096  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1097  OpcodeIndex = SOK_VectorFloat8Spill;
1098  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1099  OpcodeIndex = SOK_VectorFloat4Spill;
1100  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1101  OpcodeIndex = SOK_VRSaveSpill;
1102  } else if (PPC::QFRCRegClass.contains(Reg)) {
1103  OpcodeIndex = SOK_QuadFloat8Spill;
1104  } else if (PPC::QSRCRegClass.contains(Reg)) {
1105  OpcodeIndex = SOK_QuadFloat4Spill;
1106  } else if (PPC::QBRCRegClass.contains(Reg)) {
1107  OpcodeIndex = SOK_QuadBitSpill;
1108  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1109  OpcodeIndex = SOK_SpillToVSR;
1110  } else {
1111  llvm_unreachable("Unknown regclass!");
1112  }
1113  }
1114  return OpcodesForSpill[OpcodeIndex];
1115 }
1116 
1117 unsigned
1119  const TargetRegisterClass *RC) const {
1120  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1121  int OpcodeIndex = 0;
1122 
1123  if (RC != nullptr) {
1124  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1125  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1126  OpcodeIndex = SOK_Int4Spill;
1127  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1128  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1129  OpcodeIndex = SOK_Int8Spill;
1130  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1131  OpcodeIndex = SOK_Float8Spill;
1132  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1133  OpcodeIndex = SOK_Float4Spill;
1134  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1135  OpcodeIndex = SOK_SPESpill;
1136  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1137  OpcodeIndex = SOK_SPE4Spill;
1138  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1139  OpcodeIndex = SOK_CRSpill;
1140  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1141  OpcodeIndex = SOK_CRBitSpill;
1142  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1143  OpcodeIndex = SOK_VRVectorSpill;
1144  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1145  OpcodeIndex = SOK_VSXVectorSpill;
1146  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1147  OpcodeIndex = SOK_VectorFloat8Spill;
1148  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1149  OpcodeIndex = SOK_VectorFloat4Spill;
1150  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1151  OpcodeIndex = SOK_VRSaveSpill;
1152  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1153  OpcodeIndex = SOK_QuadFloat8Spill;
1154  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1155  OpcodeIndex = SOK_QuadFloat4Spill;
1156  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1157  OpcodeIndex = SOK_QuadBitSpill;
1158  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1159  OpcodeIndex = SOK_SpillToVSR;
1160  } else {
1161  llvm_unreachable("Unknown regclass!");
1162  }
1163  } else {
1164  if (PPC::GPRCRegClass.contains(Reg) ||
1165  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1166  OpcodeIndex = SOK_Int4Spill;
1167  } else if (PPC::G8RCRegClass.contains(Reg) ||
1168  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1169  OpcodeIndex = SOK_Int8Spill;
1170  } else if (PPC::F8RCRegClass.contains(Reg)) {
1171  OpcodeIndex = SOK_Float8Spill;
1172  } else if (PPC::F4RCRegClass.contains(Reg)) {
1173  OpcodeIndex = SOK_Float4Spill;
1174  } else if (PPC::SPERCRegClass.contains(Reg)) {
1175  OpcodeIndex = SOK_SPESpill;
1176  } else if (PPC::SPE4RCRegClass.contains(Reg)) {
1177  OpcodeIndex = SOK_SPE4Spill;
1178  } else if (PPC::CRRCRegClass.contains(Reg)) {
1179  OpcodeIndex = SOK_CRSpill;
1180  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1181  OpcodeIndex = SOK_CRBitSpill;
1182  } else if (PPC::VRRCRegClass.contains(Reg)) {
1183  OpcodeIndex = SOK_VRVectorSpill;
1184  } else if (PPC::VSRCRegClass.contains(Reg)) {
1185  OpcodeIndex = SOK_VSXVectorSpill;
1186  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1187  OpcodeIndex = SOK_VectorFloat8Spill;
1188  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1189  OpcodeIndex = SOK_VectorFloat4Spill;
1190  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1191  OpcodeIndex = SOK_VRSaveSpill;
1192  } else if (PPC::QFRCRegClass.contains(Reg)) {
1193  OpcodeIndex = SOK_QuadFloat8Spill;
1194  } else if (PPC::QSRCRegClass.contains(Reg)) {
1195  OpcodeIndex = SOK_QuadFloat4Spill;
1196  } else if (PPC::QBRCRegClass.contains(Reg)) {
1197  OpcodeIndex = SOK_QuadBitSpill;
1198  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1199  OpcodeIndex = SOK_SpillToVSR;
1200  } else {
1201  llvm_unreachable("Unknown regclass!");
1202  }
1203  }
1204  return OpcodesForSpill[OpcodeIndex];
1205 }
1206 
1207 void PPCInstrInfo::StoreRegToStackSlot(
1208  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1209  const TargetRegisterClass *RC,
1210  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1211  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1212  DebugLoc DL;
1213 
1214  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1215  FuncInfo->setHasSpills();
1216 
1218  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1219  FrameIdx));
1220 
1221  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1222  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1223  FuncInfo->setSpillsCR();
1224 
1225  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1226  FuncInfo->setSpillsVRSAVE();
1227 
1228  if (isXFormMemOp(Opcode))
1229  FuncInfo->setHasNonRISpills();
1230 }
1231 
1234  unsigned SrcReg, bool isKill,
1235  int FrameIdx,
1236  const TargetRegisterClass *RC,
1237  const TargetRegisterInfo *TRI) const {
1238  MachineFunction &MF = *MBB.getParent();
1240 
1241  // We need to avoid a situation in which the value from a VRRC register is
1242  // spilled using an Altivec instruction and reloaded into a VSRC register
1243  // using a VSX instruction. The issue with this is that the VSX
1244  // load/store instructions swap the doublewords in the vector and the Altivec
1245  // ones don't. The register classes on the spill/reload may be different if
1246  // the register is defined using an Altivec instruction and is then used by a
1247  // VSX instruction.
1248  RC = updatedRC(RC);
1249 
1250  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1251 
1252  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1253  MBB.insert(MI, NewMIs[i]);
1254 
1255  const MachineFrameInfo &MFI = MF.getFrameInfo();
1257  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1259  MFI.getObjectAlignment(FrameIdx));
1260  NewMIs.back()->addMemOperand(MF, MMO);
1261 }
1262 
1263 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1264  unsigned DestReg, int FrameIdx,
1265  const TargetRegisterClass *RC,
1267  const {
1268  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1269  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1270  FrameIdx));
1271  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1272 
1273  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1274  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1275  FuncInfo->setSpillsCR();
1276 
1277  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1278  FuncInfo->setSpillsVRSAVE();
1279 
1280  if (isXFormMemOp(Opcode))
1281  FuncInfo->setHasNonRISpills();
1282 }
1283 
1284 void
1287  unsigned DestReg, int FrameIdx,
1288  const TargetRegisterClass *RC,
1289  const TargetRegisterInfo *TRI) const {
1290  MachineFunction &MF = *MBB.getParent();
1292  DebugLoc DL;
1293  if (MI != MBB.end()) DL = MI->getDebugLoc();
1294 
1295  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1296  FuncInfo->setHasSpills();
1297 
1298  // We need to avoid a situation in which the value from a VRRC register is
1299  // spilled using an Altivec instruction and reloaded into a VSRC register
1300  // using a VSX instruction. The issue with this is that the VSX
1301  // load/store instructions swap the doublewords in the vector and the Altivec
1302  // ones don't. The register classes on the spill/reload may be different if
1303  // the register is defined using an Altivec instruction and is then used by a
1304  // VSX instruction.
1305  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1306  RC = &PPC::VSRCRegClass;
1307 
1308  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1309 
1310  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1311  MBB.insert(MI, NewMIs[i]);
1312 
1313  const MachineFrameInfo &MFI = MF.getFrameInfo();
1315  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1317  MFI.getObjectAlignment(FrameIdx));
1318  NewMIs.back()->addMemOperand(MF, MMO);
1319 }
1320 
1321 bool PPCInstrInfo::
1323  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1324  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1325  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1326  else
1327  // Leave the CR# the same, but invert the condition.
1328  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1329  return false;
1330 }
1331 
1333  unsigned Reg, MachineRegisterInfo *MRI) const {
1334  // For some instructions, it is legal to fold ZERO into the RA register field.
1335  // A zero immediate should always be loaded with a single li.
1336  unsigned DefOpc = DefMI.getOpcode();
1337  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1338  return false;
1339  if (!DefMI.getOperand(1).isImm())
1340  return false;
1341  if (DefMI.getOperand(1).getImm() != 0)
1342  return false;
1343 
1344  // Note that we cannot here invert the arguments of an isel in order to fold
1345  // a ZERO into what is presented as the second argument. All we have here
1346  // is the condition bit, and that might come from a CR-logical bit operation.
1347 
1348  const MCInstrDesc &UseMCID = UseMI.getDesc();
1349 
1350  // Only fold into real machine instructions.
1351  if (UseMCID.isPseudo())
1352  return false;
1353 
1354  unsigned UseIdx;
1355  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1356  if (UseMI.getOperand(UseIdx).isReg() &&
1357  UseMI.getOperand(UseIdx).getReg() == Reg)
1358  break;
1359 
1360  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1361  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1362 
1363  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1364 
1365  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1366  // register (which might also be specified as a pointer class kind).
1367  if (UseInfo->isLookupPtrRegClass()) {
1368  if (UseInfo->RegClass /* Kind */ != 1)
1369  return false;
1370  } else {
1371  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1372  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1373  return false;
1374  }
1375 
1376  // Make sure this is not tied to an output register (or otherwise
1377  // constrained). This is true for ST?UX registers, for example, which
1378  // are tied to their output registers.
1379  if (UseInfo->Constraints != 0)
1380  return false;
1381 
1382  unsigned ZeroReg;
1383  if (UseInfo->isLookupPtrRegClass()) {
1384  bool isPPC64 = Subtarget.isPPC64();
1385  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1386  } else {
1387  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1388  PPC::ZERO8 : PPC::ZERO;
1389  }
1390 
1391  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1392  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1393 
1394  if (DeleteDef)
1395  DefMI.eraseFromParent();
1396 
1397  return true;
1398 }
1399 
1401  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1402  I != IE; ++I)
1403  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1404  return true;
1405  return false;
1406 }
1407 
1408 // We should make sure that, if we're going to predicate both sides of a
1409 // condition (a diamond), that both sides don't define the counter register. We
1410 // can predicate counter-decrement-based branches, but while that predicates
1411 // the branching, it does not predicate the counter decrement. If we tried to
1412 // merge the triangle into one predicated block, we'd decrement the counter
1413 // twice.
1415  unsigned NumT, unsigned ExtraT,
1416  MachineBasicBlock &FMBB,
1417  unsigned NumF, unsigned ExtraF,
1418  BranchProbability Probability) const {
1419  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1420 }
1421 
1422 
1424  // The predicated branches are identified by their type, not really by the
1425  // explicit presence of a predicate. Furthermore, some of them can be
1426  // predicated more than once. Because if conversion won't try to predicate
1427  // any instruction which already claims to be predicated (by returning true
1428  // here), always return false. In doing so, we let isPredicable() be the
1429  // final word on whether not the instruction can be (further) predicated.
1430 
1431  return false;
1432 }
1433 
1435  if (!MI.isTerminator())
1436  return false;
1437 
1438  // Conditional branch is a special case.
1439  if (MI.isBranch() && !MI.isBarrier())
1440  return true;
1441 
1442  return !isPredicated(MI);
1443 }
1444 
1446  ArrayRef<MachineOperand> Pred) const {
1447  unsigned OpC = MI.getOpcode();
1448  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1449  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1450  bool isPPC64 = Subtarget.isPPC64();
1451  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1452  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1453  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1454  MI.setDesc(get(PPC::BCLR));
1455  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1456  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1457  MI.setDesc(get(PPC::BCLRn));
1458  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1459  } else {
1460  MI.setDesc(get(PPC::BCCLR));
1462  .addImm(Pred[0].getImm())
1463  .add(Pred[1]);
1464  }
1465 
1466  return true;
1467  } else if (OpC == PPC::B) {
1468  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1469  bool isPPC64 = Subtarget.isPPC64();
1470  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1471  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1472  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1473  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1474  MI.RemoveOperand(0);
1475 
1476  MI.setDesc(get(PPC::BC));
1478  .add(Pred[1])
1479  .addMBB(MBB);
1480  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1481  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1482  MI.RemoveOperand(0);
1483 
1484  MI.setDesc(get(PPC::BCn));
1486  .add(Pred[1])
1487  .addMBB(MBB);
1488  } else {
1489  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1490  MI.RemoveOperand(0);
1491 
1492  MI.setDesc(get(PPC::BCC));
1494  .addImm(Pred[0].getImm())
1495  .add(Pred[1])
1496  .addMBB(MBB);
1497  }
1498 
1499  return true;
1500  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
1501  OpC == PPC::BCTRL8) {
1502  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1503  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1504 
1505  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1506  bool isPPC64 = Subtarget.isPPC64();
1507 
1508  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1509  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1510  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1511  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1512  return true;
1513  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1514  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1515  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1516  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1517  return true;
1518  }
1519 
1520  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1521  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1523  .addImm(Pred[0].getImm())
1524  .add(Pred[1]);
1525  return true;
1526  }
1527 
1528  return false;
1529 }
1530 
1532  ArrayRef<MachineOperand> Pred2) const {
1533  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1534  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1535 
1536  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1537  return false;
1538  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1539  return false;
1540 
1541  // P1 can only subsume P2 if they test the same condition register.
1542  if (Pred1[1].getReg() != Pred2[1].getReg())
1543  return false;
1544 
1545  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1546  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1547 
1548  if (P1 == P2)
1549  return true;
1550 
1551  // Does P1 subsume P2, e.g. GE subsumes GT.
1552  if (P1 == PPC::PRED_LE &&
1553  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1554  return true;
1555  if (P1 == PPC::PRED_GE &&
1556  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1557  return true;
1558 
1559  return false;
1560 }
1561 
1563  std::vector<MachineOperand> &Pred) const {
1564  // Note: At the present time, the contents of Pred from this function is
1565  // unused by IfConversion. This implementation follows ARM by pushing the
1566  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1567  // predicate, instructions defining CTR or CTR8 are also included as
1568  // predicate-defining instructions.
1569 
1570  const TargetRegisterClass *RCs[] =
1571  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1572  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1573 
1574  bool Found = false;
1575  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1576  const MachineOperand &MO = MI.getOperand(i);
1577  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1578  const TargetRegisterClass *RC = RCs[c];
1579  if (MO.isReg()) {
1580  if (MO.isDef() && RC->contains(MO.getReg())) {
1581  Pred.push_back(MO);
1582  Found = true;
1583  }
1584  } else if (MO.isRegMask()) {
1585  for (TargetRegisterClass::iterator I = RC->begin(),
1586  IE = RC->end(); I != IE; ++I)
1587  if (MO.clobbersPhysReg(*I)) {
1588  Pred.push_back(MO);
1589  Found = true;
1590  }
1591  }
1592  }
1593  }
1594 
1595  return Found;
1596 }
1597 
1599  unsigned OpC = MI.getOpcode();
1600  switch (OpC) {
1601  default:
1602  return false;
1603  case PPC::B:
1604  case PPC::BLR:
1605  case PPC::BLR8:
1606  case PPC::BCTR:
1607  case PPC::BCTR8:
1608  case PPC::BCTRL:
1609  case PPC::BCTRL8:
1610  return true;
1611  }
1612 }
1613 
1614 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1615  unsigned &SrcReg2, int &Mask,
1616  int &Value) const {
1617  unsigned Opc = MI.getOpcode();
1618 
1619  switch (Opc) {
1620  default: return false;
1621  case PPC::CMPWI:
1622  case PPC::CMPLWI:
1623  case PPC::CMPDI:
1624  case PPC::CMPLDI:
1625  SrcReg = MI.getOperand(1).getReg();
1626  SrcReg2 = 0;
1627  Value = MI.getOperand(2).getImm();
1628  Mask = 0xFFFF;
1629  return true;
1630  case PPC::CMPW:
1631  case PPC::CMPLW:
1632  case PPC::CMPD:
1633  case PPC::CMPLD:
1634  case PPC::FCMPUS:
1635  case PPC::FCMPUD:
1636  SrcReg = MI.getOperand(1).getReg();
1637  SrcReg2 = MI.getOperand(2).getReg();
1638  Value = 0;
1639  Mask = 0;
1640  return true;
1641  }
1642 }
1643 
1644 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1645  unsigned SrcReg2, int Mask, int Value,
1646  const MachineRegisterInfo *MRI) const {
1647  if (DisableCmpOpt)
1648  return false;
1649 
1650  int OpC = CmpInstr.getOpcode();
1651  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1652 
1653  // FP record forms set CR1 based on the exception status bits, not a
1654  // comparison with zero.
1655  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1656  return false;
1657 
1659  // The record forms set the condition register based on a signed comparison
1660  // with zero (so says the ISA manual). This is not as straightforward as it
1661  // seems, however, because this is always a 64-bit comparison on PPC64, even
1662  // for instructions that are 32-bit in nature (like slw for example).
1663  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1664  // for equality checks (as those don't depend on the sign). On PPC64,
1665  // we are restricted to equality for unsigned 64-bit comparisons and for
1666  // signed 32-bit comparisons the applicability is more restricted.
1667  bool isPPC64 = Subtarget.isPPC64();
1668  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1669  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1670  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1671 
1672  // Look through copies unless that gets us to a physical register.
1673  unsigned ActualSrc = TRI->lookThruCopyLike(SrcReg, MRI);
1675  SrcReg = ActualSrc;
1676 
1677  // Get the unique definition of SrcReg.
1678  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1679  if (!MI) return false;
1680 
1681  bool equalityOnly = false;
1682  bool noSub = false;
1683  if (isPPC64) {
1684  if (is32BitSignedCompare) {
1685  // We can perform this optimization only if MI is sign-extending.
1686  if (isSignExtended(*MI))
1687  noSub = true;
1688  else
1689  return false;
1690  } else if (is32BitUnsignedCompare) {
1691  // We can perform this optimization, equality only, if MI is
1692  // zero-extending.
1693  if (isZeroExtended(*MI)) {
1694  noSub = true;
1695  equalityOnly = true;
1696  } else
1697  return false;
1698  } else
1699  equalityOnly = is64BitUnsignedCompare;
1700  } else
1701  equalityOnly = is32BitUnsignedCompare;
1702 
1703  if (equalityOnly) {
1704  // We need to check the uses of the condition register in order to reject
1705  // non-equality comparisons.
1707  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1708  I != IE; ++I) {
1709  MachineInstr *UseMI = &*I;
1710  if (UseMI->getOpcode() == PPC::BCC) {
1711  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1712  unsigned PredCond = PPC::getPredicateCondition(Pred);
1713  // We ignore hint bits when checking for non-equality comparisons.
1714  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1715  return false;
1716  } else if (UseMI->getOpcode() == PPC::ISEL ||
1717  UseMI->getOpcode() == PPC::ISEL8) {
1718  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1719  if (SubIdx != PPC::sub_eq)
1720  return false;
1721  } else
1722  return false;
1723  }
1724  }
1725 
1726  MachineBasicBlock::iterator I = CmpInstr;
1727 
1728  // Scan forward to find the first use of the compare.
1729  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1730  ++I) {
1731  bool FoundUse = false;
1733  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1734  J != JE; ++J)
1735  if (&*J == &*I) {
1736  FoundUse = true;
1737  break;
1738  }
1739 
1740  if (FoundUse)
1741  break;
1742  }
1743 
1746 
1747  // There are two possible candidates which can be changed to set CR[01].
1748  // One is MI, the other is a SUB instruction.
1749  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1750  MachineInstr *Sub = nullptr;
1751  if (SrcReg2 != 0)
1752  // MI is not a candidate for CMPrr.
1753  MI = nullptr;
1754  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1755  // same BB as the comparison. This is to allow the check below to avoid calls
1756  // (and other explicit clobbers); instead we should really check for these
1757  // more explicitly (in at least a few predecessors).
1758  else if (MI->getParent() != CmpInstr.getParent())
1759  return false;
1760  else if (Value != 0) {
1761  // The record-form instructions set CR bit based on signed comparison
1762  // against 0. We try to convert a compare against 1 or -1 into a compare
1763  // against 0 to exploit record-form instructions. For example, we change
1764  // the condition "greater than -1" into "greater than or equal to 0"
1765  // and "less than 1" into "less than or equal to 0".
1766 
1767  // Since we optimize comparison based on a specific branch condition,
1768  // we don't optimize if condition code is used by more than once.
1769  if (equalityOnly || !MRI->hasOneUse(CRReg))
1770  return false;
1771 
1772  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1773  if (UseMI->getOpcode() != PPC::BCC)
1774  return false;
1775 
1776  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1777  unsigned PredCond = PPC::getPredicateCondition(Pred);
1778  unsigned PredHint = PPC::getPredicateHint(Pred);
1779  int16_t Immed = (int16_t)Value;
1780 
1781  // When modifying the condition in the predicate, we propagate hint bits
1782  // from the original predicate to the new one.
1783  if (Immed == -1 && PredCond == PPC::PRED_GT)
1784  // We convert "greater than -1" into "greater than or equal to 0",
1785  // since we are assuming signed comparison by !equalityOnly
1786  Pred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1787  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1788  // We convert "less than or equal to -1" into "less than 0".
1789  Pred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1790  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1791  // We convert "less than 1" into "less than or equal to 0".
1792  Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1793  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1794  // We convert "greater than or equal to 1" into "greater than 0".
1795  Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1796  else
1797  return false;
1798 
1799  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
1800  }
1801 
1802  // Search for Sub.
1803  --I;
1804 
1805  // Get ready to iterate backward from CmpInstr.
1806  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1807 
1808  for (; I != E && !noSub; --I) {
1809  const MachineInstr &Instr = *I;
1810  unsigned IOpC = Instr.getOpcode();
1811 
1812  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1813  Instr.readsRegister(PPC::CR0, TRI)))
1814  // This instruction modifies or uses the record condition register after
1815  // the one we want to change. While we could do this transformation, it
1816  // would likely not be profitable. This transformation removes one
1817  // instruction, and so even forcing RA to generate one move probably
1818  // makes it unprofitable.
1819  return false;
1820 
1821  // Check whether CmpInstr can be made redundant by the current instruction.
1822  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1823  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1824  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1825  ((Instr.getOperand(1).getReg() == SrcReg &&
1826  Instr.getOperand(2).getReg() == SrcReg2) ||
1827  (Instr.getOperand(1).getReg() == SrcReg2 &&
1828  Instr.getOperand(2).getReg() == SrcReg))) {
1829  Sub = &*I;
1830  break;
1831  }
1832 
1833  if (I == B)
1834  // The 'and' is below the comparison instruction.
1835  return false;
1836  }
1837 
1838  // Return false if no candidates exist.
1839  if (!MI && !Sub)
1840  return false;
1841 
1842  // The single candidate is called MI.
1843  if (!MI) MI = Sub;
1844 
1845  int NewOpC = -1;
1846  int MIOpC = MI->getOpcode();
1847  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1848  MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1849  NewOpC = MIOpC;
1850  else {
1851  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1852  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1853  NewOpC = MIOpC;
1854  }
1855 
1856  // FIXME: On the non-embedded POWER architectures, only some of the record
1857  // forms are fast, and we should use only the fast ones.
1858 
1859  // The defining instruction has a record form (or is already a record
1860  // form). It is possible, however, that we'll need to reverse the condition
1861  // code of the users.
1862  if (NewOpC == -1)
1863  return false;
1864 
1865  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1866  // needs to be updated to be based on SUB. Push the condition code
1867  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1868  // condition code of these operands will be modified.
1869  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1870  // comparison against 0, which may modify predicate.
1871  bool ShouldSwap = false;
1872  if (Sub && Value == 0) {
1873  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1874  Sub->getOperand(2).getReg() == SrcReg;
1875 
1876  // The operands to subf are the opposite of sub, so only in the fixed-point
1877  // case, invert the order.
1878  ShouldSwap = !ShouldSwap;
1879  }
1880 
1881  if (ShouldSwap)
1883  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1884  I != IE; ++I) {
1885  MachineInstr *UseMI = &*I;
1886  if (UseMI->getOpcode() == PPC::BCC) {
1887  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1888  unsigned PredCond = PPC::getPredicateCondition(Pred);
1889  assert((!equalityOnly ||
1890  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1891  "Invalid predicate for equality-only optimization");
1892  (void)PredCond; // To suppress warning in release build.
1893  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1894  PPC::getSwappedPredicate(Pred)));
1895  } else if (UseMI->getOpcode() == PPC::ISEL ||
1896  UseMI->getOpcode() == PPC::ISEL8) {
1897  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1898  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1899  "Invalid CR bit for equality-only optimization");
1900 
1901  if (NewSubReg == PPC::sub_lt)
1902  NewSubReg = PPC::sub_gt;
1903  else if (NewSubReg == PPC::sub_gt)
1904  NewSubReg = PPC::sub_lt;
1905 
1906  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1907  NewSubReg));
1908  } else // We need to abort on a user we don't understand.
1909  return false;
1910  }
1911  assert(!(Value != 0 && ShouldSwap) &&
1912  "Non-zero immediate support and ShouldSwap"
1913  "may conflict in updating predicate");
1914 
1915  // Create a new virtual register to hold the value of the CR set by the
1916  // record-form instruction. If the instruction was not previously in
1917  // record form, then set the kill flag on the CR.
1918  CmpInstr.eraseFromParent();
1919 
1921  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1922  get(TargetOpcode::COPY), CRReg)
1923  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1924 
1925  // Even if CR0 register were dead before, it is alive now since the
1926  // instruction we just built uses it.
1927  MI->clearRegisterDeads(PPC::CR0);
1928 
1929  if (MIOpC != NewOpC) {
1930  // We need to be careful here: we're replacing one instruction with
1931  // another, and we need to make sure that we get all of the right
1932  // implicit uses and defs. On the other hand, the caller may be holding
1933  // an iterator to this instruction, and so we can't delete it (this is
1934  // specifically the case if this is the instruction directly after the
1935  // compare).
1936 
1937  // Rotates are expensive instructions. If we're emitting a record-form
1938  // rotate that can just be an andi/andis, we should just emit that.
1939  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
1940  unsigned GPRRes = MI->getOperand(0).getReg();
1941  int64_t SH = MI->getOperand(2).getImm();
1942  int64_t MB = MI->getOperand(3).getImm();
1943  int64_t ME = MI->getOperand(4).getImm();
1944  // We can only do this if both the start and end of the mask are in the
1945  // same halfword.
1946  bool MBInLoHWord = MB >= 16;
1947  bool MEInLoHWord = ME >= 16;
1948  uint64_t Mask = ~0LLU;
1949 
1950  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1951  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1952  // The mask value needs to shift right 16 if we're emitting andis.
1953  Mask >>= MBInLoHWord ? 0 : 16;
1954  NewOpC = MIOpC == PPC::RLWINM ?
1955  (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1956  (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1957  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1958  (ME - MB + 1 == SH) && (MB >= 16)) {
1959  // If we are rotating by the exact number of bits as are in the mask
1960  // and the mask is in the least significant bits of the register,
1961  // that's just an andis. (as long as the GPR result has no uses).
1962  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1963  Mask >>= 16;
1964  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1965  }
1966  // If we've set the mask, we can transform.
1967  if (Mask != ~0LLU) {
1968  MI->RemoveOperand(4);
1969  MI->RemoveOperand(3);
1970  MI->getOperand(2).setImm(Mask);
1971  NumRcRotatesConvertedToRcAnd++;
1972  }
1973  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1974  int64_t MB = MI->getOperand(3).getImm();
1975  if (MB >= 48) {
1976  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1977  NewOpC = PPC::ANDIo8;
1978  MI->RemoveOperand(3);
1979  MI->getOperand(2).setImm(Mask);
1980  NumRcRotatesConvertedToRcAnd++;
1981  }
1982  }
1983 
1984  const MCInstrDesc &NewDesc = get(NewOpC);
1985  MI->setDesc(NewDesc);
1986 
1987  if (NewDesc.ImplicitDefs)
1988  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1989  *ImpDefs; ++ImpDefs)
1990  if (!MI->definesRegister(*ImpDefs))
1991  MI->addOperand(*MI->getParent()->getParent(),
1992  MachineOperand::CreateReg(*ImpDefs, true, true));
1993  if (NewDesc.ImplicitUses)
1994  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1995  *ImpUses; ++ImpUses)
1996  if (!MI->readsRegister(*ImpUses))
1997  MI->addOperand(*MI->getParent()->getParent(),
1998  MachineOperand::CreateReg(*ImpUses, false, true));
1999  }
2000  assert(MI->definesRegister(PPC::CR0) &&
2001  "Record-form instruction does not define cr0?");
2002 
2003  // Modify the condition code of operands in OperandsToUpdate.
2004  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2005  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2006  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
2007  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2008 
2009  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2010  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2011 
2012  return true;
2013 }
2014 
2015 /// GetInstSize - Return the number of bytes of code the specified
2016 /// instruction may be. This returns the maximum number of bytes.
2017 ///
2019  unsigned Opcode = MI.getOpcode();
2020 
2021  if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2022  const MachineFunction *MF = MI.getParent()->getParent();
2023  const char *AsmStr = MI.getOperand(0).getSymbolName();
2024  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2025  } else if (Opcode == TargetOpcode::STACKMAP) {
2026  StackMapOpers Opers(&MI);
2027  return Opers.getNumPatchBytes();
2028  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2029  PatchPointOpers Opers(&MI);
2030  return Opers.getNumPatchBytes();
2031  } else {
2032  return get(Opcode).getSize();
2033  }
2034 }
2035 
2036 std::pair<unsigned, unsigned>
2038  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2039  return std::make_pair(TF & Mask, TF & ~Mask);
2040 }
2041 
2044  using namespace PPCII;
2045  static const std::pair<unsigned, const char *> TargetFlags[] = {
2046  {MO_LO, "ppc-lo"},
2047  {MO_HA, "ppc-ha"},
2048  {MO_TPREL_LO, "ppc-tprel-lo"},
2049  {MO_TPREL_HA, "ppc-tprel-ha"},
2050  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2051  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2052  {MO_TOC_LO, "ppc-toc-lo"},
2053  {MO_TLS, "ppc-tls"}};
2054  return makeArrayRef(TargetFlags);
2055 }
2056 
2059  using namespace PPCII;
2060  static const std::pair<unsigned, const char *> TargetFlags[] = {
2061  {MO_PLT, "ppc-plt"},
2062  {MO_PIC_FLAG, "ppc-pic"},
2063  {MO_NLP_FLAG, "ppc-nlp"},
2064  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2065  return makeArrayRef(TargetFlags);
2066 }
2067 
2068 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2069 // The VSX versions have the advantage of a full 64-register target whereas
2070 // the FP ones have the advantage of lower latency and higher throughput. So
2071 // what we are after is using the faster instructions in low register pressure
2072 // situations and using the larger register file in high register pressure
2073 // situations.
2075  unsigned UpperOpcode, LowerOpcode;
2076  switch (MI.getOpcode()) {
2077  case PPC::DFLOADf32:
2078  UpperOpcode = PPC::LXSSP;
2079  LowerOpcode = PPC::LFS;
2080  break;
2081  case PPC::DFLOADf64:
2082  UpperOpcode = PPC::LXSD;
2083  LowerOpcode = PPC::LFD;
2084  break;
2085  case PPC::DFSTOREf32:
2086  UpperOpcode = PPC::STXSSP;
2087  LowerOpcode = PPC::STFS;
2088  break;
2089  case PPC::DFSTOREf64:
2090  UpperOpcode = PPC::STXSD;
2091  LowerOpcode = PPC::STFD;
2092  break;
2093  case PPC::XFLOADf32:
2094  UpperOpcode = PPC::LXSSPX;
2095  LowerOpcode = PPC::LFSX;
2096  break;
2097  case PPC::XFLOADf64:
2098  UpperOpcode = PPC::LXSDX;
2099  LowerOpcode = PPC::LFDX;
2100  break;
2101  case PPC::XFSTOREf32:
2102  UpperOpcode = PPC::STXSSPX;
2103  LowerOpcode = PPC::STFSX;
2104  break;
2105  case PPC::XFSTOREf64:
2106  UpperOpcode = PPC::STXSDX;
2107  LowerOpcode = PPC::STFDX;
2108  break;
2109  case PPC::LIWAX:
2110  UpperOpcode = PPC::LXSIWAX;
2111  LowerOpcode = PPC::LFIWAX;
2112  break;
2113  case PPC::LIWZX:
2114  UpperOpcode = PPC::LXSIWZX;
2115  LowerOpcode = PPC::LFIWZX;
2116  break;
2117  case PPC::STIWX:
2118  UpperOpcode = PPC::STXSIWX;
2119  LowerOpcode = PPC::STFIWX;
2120  break;
2121  default:
2122  llvm_unreachable("Unknown Operation!");
2123  }
2124 
2125  unsigned TargetReg = MI.getOperand(0).getReg();
2126  unsigned Opcode;
2127  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2128  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2129  Opcode = LowerOpcode;
2130  else
2131  Opcode = UpperOpcode;
2132  MI.setDesc(get(Opcode));
2133  return true;
2134 }
2135 
2136 static bool isAnImmediateOperand(const MachineOperand &MO) {
2137  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2138 }
2139 
2141  auto &MBB = *MI.getParent();
2142  auto DL = MI.getDebugLoc();
2143 
2144  switch (MI.getOpcode()) {
2145  case TargetOpcode::LOAD_STACK_GUARD: {
2146  assert(Subtarget.isTargetLinux() &&
2147  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2148  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2149  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2150  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2152  .addImm(Offset)
2153  .addReg(Reg);
2154  return true;
2155  }
2156  case PPC::DFLOADf32:
2157  case PPC::DFLOADf64:
2158  case PPC::DFSTOREf32:
2159  case PPC::DFSTOREf64: {
2160  assert(Subtarget.hasP9Vector() &&
2161  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2162  assert(MI.getOperand(2).isReg() &&
2164  "D-form op must have register and immediate operands");
2165  return expandVSXMemPseudo(MI);
2166  }
2167  case PPC::XFLOADf32:
2168  case PPC::XFSTOREf32:
2169  case PPC::LIWAX:
2170  case PPC::LIWZX:
2171  case PPC::STIWX: {
2172  assert(Subtarget.hasP8Vector() &&
2173  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2174  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2175  "X-form op must have register and register operands");
2176  return expandVSXMemPseudo(MI);
2177  }
2178  case PPC::XFLOADf64:
2179  case PPC::XFSTOREf64: {
2180  assert(Subtarget.hasVSX() &&
2181  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2182  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2183  "X-form op must have register and register operands");
2184  return expandVSXMemPseudo(MI);
2185  }
2186  case PPC::SPILLTOVSR_LD: {
2187  unsigned TargetReg = MI.getOperand(0).getReg();
2188  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2189  MI.setDesc(get(PPC::DFLOADf64));
2190  return expandPostRAPseudo(MI);
2191  }
2192  else
2193  MI.setDesc(get(PPC::LD));
2194  return true;
2195  }
2196  case PPC::SPILLTOVSR_ST: {
2197  unsigned SrcReg = MI.getOperand(0).getReg();
2198  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2199  NumStoreSPILLVSRRCAsVec++;
2200  MI.setDesc(get(PPC::DFSTOREf64));
2201  return expandPostRAPseudo(MI);
2202  } else {
2203  NumStoreSPILLVSRRCAsGpr++;
2204  MI.setDesc(get(PPC::STD));
2205  }
2206  return true;
2207  }
2208  case PPC::SPILLTOVSR_LDX: {
2209  unsigned TargetReg = MI.getOperand(0).getReg();
2210  if (PPC::VSFRCRegClass.contains(TargetReg))
2211  MI.setDesc(get(PPC::LXSDX));
2212  else
2213  MI.setDesc(get(PPC::LDX));
2214  return true;
2215  }
2216  case PPC::SPILLTOVSR_STX: {
2217  unsigned SrcReg = MI.getOperand(0).getReg();
2218  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2219  NumStoreSPILLVSRRCAsVec++;
2220  MI.setDesc(get(PPC::STXSDX));
2221  } else {
2222  NumStoreSPILLVSRRCAsGpr++;
2223  MI.setDesc(get(PPC::STDX));
2224  }
2225  return true;
2226  }
2227 
2228  case PPC::CFENCE8: {
2229  auto Val = MI.getOperand(0).getReg();
2230  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2231  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2233  .addReg(PPC::CR7)
2234  .addImm(1);
2235  MI.setDesc(get(PPC::ISYNC));
2236  MI.RemoveOperand(0);
2237  return true;
2238  }
2239  }
2240  return false;
2241 }
2242 
2243 // Essentially a compile-time implementation of a compare->isel sequence.
2244 // It takes two constants to compare, along with the true/false registers
2245 // and the comparison type (as a subreg to a CR field) and returns one
2246 // of the true/false registers, depending on the comparison results.
2247 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2248  unsigned TrueReg, unsigned FalseReg,
2249  unsigned CRSubReg) {
2250  // Signed comparisons. The immediates are assumed to be sign-extended.
2251  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2252  switch (CRSubReg) {
2253  default: llvm_unreachable("Unknown integer comparison type.");
2254  case PPC::sub_lt:
2255  return Imm1 < Imm2 ? TrueReg : FalseReg;
2256  case PPC::sub_gt:
2257  return Imm1 > Imm2 ? TrueReg : FalseReg;
2258  case PPC::sub_eq:
2259  return Imm1 == Imm2 ? TrueReg : FalseReg;
2260  }
2261  }
2262  // Unsigned comparisons.
2263  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2264  switch (CRSubReg) {
2265  default: llvm_unreachable("Unknown integer comparison type.");
2266  case PPC::sub_lt:
2267  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2268  case PPC::sub_gt:
2269  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2270  case PPC::sub_eq:
2271  return Imm1 == Imm2 ? TrueReg : FalseReg;
2272  }
2273  }
2274  return PPC::NoRegister;
2275 }
2276 
2278  unsigned OpNo,
2279  int64_t Imm) const {
2280  assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2281  // Replace the REG with the Immediate.
2282  unsigned InUseReg = MI.getOperand(OpNo).getReg();
2283  MI.getOperand(OpNo).ChangeToImmediate(Imm);
2284 
2285  if (empty(MI.implicit_operands()))
2286  return;
2287 
2288  // We need to make sure that the MI didn't have any implicit use
2289  // of this REG any more.
2291  int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
2292  if (UseOpIdx >= 0) {
2293  MachineOperand &MO = MI.getOperand(UseOpIdx);
2294  if (MO.isImplicit())
2295  // The operands must always be in the following order:
2296  // - explicit reg defs,
2297  // - other explicit operands (reg uses, immediates, etc.),
2298  // - implicit reg defs
2299  // - implicit reg uses
2300  // Therefore, removing the implicit operand won't change the explicit
2301  // operands layout.
2302  MI.RemoveOperand(UseOpIdx);
2303  }
2304 }
2305 
2306 // Replace an instruction with one that materializes a constant (and sets
2307 // CR0 if the original instruction was a record-form instruction).
2309  const LoadImmediateInfo &LII) const {
2310  // Remove existing operands.
2311  int OperandToKeep = LII.SetCR ? 1 : 0;
2312  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2313  MI.RemoveOperand(i);
2314 
2315  // Replace the instruction.
2316  if (LII.SetCR) {
2317  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2318  // Set the immediate.
2320  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2321  return;
2322  }
2323  else
2324  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2325 
2326  // Set the immediate.
2328  .addImm(LII.Imm);
2329 }
2330 
2331 MachineInstr *PPCInstrInfo::getForwardingDefMI(
2332  MachineInstr &MI,
2333  unsigned &OpNoForForwarding,
2334  bool &SeenIntermediateUse) const {
2335  OpNoForForwarding = ~0U;
2336  MachineInstr *DefMI = nullptr;
2339  // If we're in SSA, get the defs through the MRI. Otherwise, only look
2340  // within the basic block to see if the register is defined using an LI/LI8.
2341  if (MRI->isSSA()) {
2342  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2343  if (!MI.getOperand(i).isReg())
2344  continue;
2345  unsigned Reg = MI.getOperand(i).getReg();
2347  continue;
2348  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2350  DefMI = MRI->getVRegDef(TrueReg);
2351  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2352  OpNoForForwarding = i;
2353  break;
2354  }
2355  }
2356  }
2357  } else {
2358  // Looking back through the definition for each operand could be expensive,
2359  // so exit early if this isn't an instruction that either has an immediate
2360  // form or is already an immediate form that we can handle.
2361  ImmInstrInfo III;
2362  unsigned Opc = MI.getOpcode();
2363  bool ConvertibleImmForm =
2364  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2365  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2366  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2367  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2368  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2369  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2370  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2371  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2372  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2373  if (!instrHasImmForm(MI, III, true) && !ConvertibleImmForm)
2374  return nullptr;
2375 
2376  // Don't convert or %X, %Y, %Y since that's just a register move.
2377  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2378  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2379  return nullptr;
2380  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2381  MachineOperand &MO = MI.getOperand(i);
2382  SeenIntermediateUse = false;
2383  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2385  It++;
2386  unsigned Reg = MI.getOperand(i).getReg();
2387 
2388  // Is this register defined by some form of add-immediate (including
2389  // load-immediate) within this basic block?
2390  for ( ; It != E; ++It) {
2391  if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2392  switch (It->getOpcode()) {
2393  default: break;
2394  case PPC::LI:
2395  case PPC::LI8:
2396  case PPC::ADDItocL:
2397  case PPC::ADDI:
2398  case PPC::ADDI8:
2399  OpNoForForwarding = i;
2400  return &*It;
2401  }
2402  break;
2403  } else if (It->readsRegister(Reg, &getRegisterInfo()))
2404  // If we see another use of this reg between the def and the MI,
2405  // we want to flat it so the def isn't deleted.
2406  SeenIntermediateUse = true;
2407  }
2408  }
2409  }
2410  }
2411  return OpNoForForwarding == ~0U ? nullptr : DefMI;
2412 }
2413 
2414 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2415  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2416  // Power 8
2417  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2418  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2419  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2420  PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2421  // Power 9
2422  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2423  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2424  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2425  PPC::SPILLTOVSR_ST}};
2426 
2427  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2428 }
2429 
2430 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2431  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2432  // Power 8
2433  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2434  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2435  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2436  PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2437  // Power 9
2438  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2439  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2440  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2441  PPC::SPILLTOVSR_LD}};
2442 
2443  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2444 }
2445 
2447  unsigned RegNo) const {
2448  const MachineRegisterInfo &MRI =
2449  StartMI.getParent()->getParent()->getRegInfo();
2450  if (MRI.isSSA())
2451  return;
2452 
2453  // Instructions between [StartMI, EndMI] should be in same basic block.
2454  assert((StartMI.getParent() == EndMI.getParent()) &&
2455  "Instructions are not in same basic block");
2456 
2457  bool IsKillSet = false;
2458 
2459  auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
2460  MachineOperand &MO = MI.getOperand(Index);
2461  if (MO.isReg() && MO.isUse() && MO.isKill() &&
2462  getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
2463  MO.setIsKill(false);
2464  };
2465 
2466  // Set killed flag for EndMI.
2467  // No need to do anything if EndMI defines RegNo.
2468  int UseIndex =
2469  EndMI.findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
2470  if (UseIndex != -1) {
2471  EndMI.getOperand(UseIndex).setIsKill(true);
2472  IsKillSet = true;
2473  // Clear killed flag for other EndMI operands related to RegNo. In some
2474  // upexpected cases, killed may be set multiple times for same register
2475  // operand in same MI.
2476  for (int i = 0, e = EndMI.getNumOperands(); i != e; ++i)
2477  if (i != UseIndex)
2478  clearOperandKillInfo(EndMI, i);
2479  }
2480 
2481  // Walking the inst in reverse order (EndMI -> StartMI].
2484  // EndMI has been handled above, skip it here.
2485  It++;
2486  MachineOperand *MO = nullptr;
2487  for (; It != E; ++It) {
2488  // Skip insturctions which could not be a def/use of RegNo.
2489  if (It->isDebugInstr() || It->isPosition())
2490  continue;
2491 
2492  // Clear killed flag for all It operands related to RegNo. In some
2493  // upexpected cases, killed may be set multiple times for same register
2494  // operand in same MI.
2495  for (int i = 0, e = It->getNumOperands(); i != e; ++i)
2496  clearOperandKillInfo(*It, i);
2497 
2498  // If killed is not set, set killed for its last use or set dead for its def
2499  // if no use found.
2500  if (!IsKillSet) {
2501  if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
2502  // Use found, set it killed.
2503  IsKillSet = true;
2504  MO->setIsKill(true);
2505  continue;
2506  } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
2507  &getRegisterInfo()))) {
2508  // No use found, set dead for its def.
2509  assert(&*It == &StartMI && "No new def between StartMI and EndMI.");
2510  MO->setIsDead(true);
2511  break;
2512  }
2513  }
2514 
2515  if ((&*It) == &StartMI)
2516  break;
2517  }
2518  // Ensure RegMo liveness is killed after EndMI.
2519  assert((IsKillSet || (MO && MO->isDead())) &&
2520  "RegNo should be killed or dead");
2521 }
2522 
2523 // If this instruction has an immediate form and one of its operands is a
2524 // result of a load-immediate or an add-immediate, convert it to
2525 // the immediate form if the constant is in range.
2527  MachineInstr **KilledDef) const {
2528  MachineFunction *MF = MI.getParent()->getParent();
2530  bool PostRA = !MRI->isSSA();
2531  bool SeenIntermediateUse = true;
2532  unsigned ForwardingOperand = ~0U;
2533  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2534  SeenIntermediateUse);
2535  if (!DefMI)
2536  return false;
2537  assert(ForwardingOperand < MI.getNumOperands() &&
2538  "The forwarding operand needs to be valid at this point");
2539  bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
2540  bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
2541  unsigned ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2542  if (KilledDef && KillFwdDefMI)
2543  *KilledDef = DefMI;
2544 
2545  ImmInstrInfo III;
2546  bool HasImmForm = instrHasImmForm(MI, III, PostRA);
2547  // If this is a reg+reg instruction that has a reg+imm form,
2548  // and one of the operands is produced by an add-immediate,
2549  // try to convert it.
2550  if (HasImmForm &&
2551  transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
2552  KillFwdDefMI))
2553  return true;
2554 
2555  if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2556  !DefMI->getOperand(1).isImm())
2557  return false;
2558 
2559  int64_t Immediate = DefMI->getOperand(1).getImm();
2560  // Sign-extend to 64-bits.
2561  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2562  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2563 
2564  // If this is a reg+reg instruction that has a reg+imm form,
2565  // and one of the operands is produced by LI, convert it now.
2566  if (HasImmForm)
2567  return transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI, SExtImm);
2568 
2569  bool ReplaceWithLI = false;
2570  bool Is64BitLI = false;
2571  int64_t NewImm = 0;
2572  bool SetCR = false;
2573  unsigned Opc = MI.getOpcode();
2574  switch (Opc) {
2575  default: return false;
2576 
2577  // FIXME: Any branches conditional on such a comparison can be made
2578  // unconditional. At this time, this happens too infrequently to be worth
2579  // the implementation effort, but if that ever changes, we could convert
2580  // such a pattern here.
2581  case PPC::CMPWI:
2582  case PPC::CMPLWI:
2583  case PPC::CMPDI:
2584  case PPC::CMPLDI: {
2585  // Doing this post-RA would require dataflow analysis to reliably find uses
2586  // of the CR register set by the compare.
2587  // No need to fixup killed/dead flag since this transformation is only valid
2588  // before RA.
2589  if (PostRA)
2590  return false;
2591  // If a compare-immediate is fed by an immediate and is itself an input of
2592  // an ISEL (the most common case) into a COPY of the correct register.
2593  bool Changed = false;
2594  unsigned DefReg = MI.getOperand(0).getReg();
2595  int64_t Comparand = MI.getOperand(2).getImm();
2596  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2597  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2598 
2599  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2600  unsigned UseOpc = CompareUseMI.getOpcode();
2601  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2602  continue;
2603  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2604  unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2605  unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2606  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2607  FalseReg, CRSubReg);
2608  if (RegToCopy == PPC::NoRegister)
2609  continue;
2610  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2611  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2612  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2613  replaceInstrOperandWithImm(CompareUseMI, 1, 0);
2614  CompareUseMI.RemoveOperand(3);
2615  CompareUseMI.RemoveOperand(2);
2616  continue;
2617  }
2618  LLVM_DEBUG(
2619  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2620  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2621  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2622  // Convert to copy and remove unneeded operands.
2623  CompareUseMI.setDesc(get(PPC::COPY));
2624  CompareUseMI.RemoveOperand(3);
2625  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2626  CmpIselsConverted++;
2627  Changed = true;
2628  LLVM_DEBUG(CompareUseMI.dump());
2629  }
2630  if (Changed)
2631  return true;
2632  // This may end up incremented multiple times since this function is called
2633  // during a fixed-point transformation, but it is only meant to indicate the
2634  // presence of this opportunity.
2635  MissedConvertibleImmediateInstrs++;
2636  return false;
2637  }
2638 
2639  // Immediate forms - may simply be convertable to an LI.
2640  case PPC::ADDI:
2641  case PPC::ADDI8: {
2642  // Does the sum fit in a 16-bit signed field?
2643  int64_t Addend = MI.getOperand(2).getImm();
2644  if (isInt<16>(Addend + SExtImm)) {
2645  ReplaceWithLI = true;
2646  Is64BitLI = Opc == PPC::ADDI8;
2647  NewImm = Addend + SExtImm;
2648  break;
2649  }
2650  return false;
2651  }
2652  case PPC::RLDICL:
2653  case PPC::RLDICLo:
2654  case PPC::RLDICL_32:
2655  case PPC::RLDICL_32_64: {
2656  // Use APInt's rotate function.
2657  int64_t SH = MI.getOperand(2).getImm();
2658  int64_t MB = MI.getOperand(3).getImm();
2659  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2660  64 : 32, SExtImm, true);
2661  InVal = InVal.rotl(SH);
2662  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2663  InVal &= Mask;
2664  // Can't replace negative values with an LI as that will sign-extend
2665  // and not clear the left bits. If we're setting the CR bit, we will use
2666  // ANDIo which won't sign extend, so that's safe.
2667  if (isUInt<15>(InVal.getSExtValue()) ||
2668  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2669  ReplaceWithLI = true;
2670  Is64BitLI = Opc != PPC::RLDICL_32;
2671  NewImm = InVal.getSExtValue();
2672  SetCR = Opc == PPC::RLDICLo;
2673  break;
2674  }
2675  return false;
2676  }
2677  case PPC::RLWINM:
2678  case PPC::RLWINM8:
2679  case PPC::RLWINMo:
2680  case PPC::RLWINM8o: {
2681  int64_t SH = MI.getOperand(2).getImm();
2682  int64_t MB = MI.getOperand(3).getImm();
2683  int64_t ME = MI.getOperand(4).getImm();
2684  APInt InVal(32, SExtImm, true);
2685  InVal = InVal.rotl(SH);
2686  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2687  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2688  InVal &= Mask;
2689  // Can't replace negative values with an LI as that will sign-extend
2690  // and not clear the left bits. If we're setting the CR bit, we will use
2691  // ANDIo which won't sign extend, so that's safe.
2692  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2693  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2694  isUInt<16>(InVal.getSExtValue()));
2695  if (ValueFits) {
2696  ReplaceWithLI = true;
2697  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2698  NewImm = InVal.getSExtValue();
2699  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2700  break;
2701  }
2702  return false;
2703  }
2704  case PPC::ORI:
2705  case PPC::ORI8:
2706  case PPC::XORI:
2707  case PPC::XORI8: {
2708  int64_t LogicalImm = MI.getOperand(2).getImm();
2709  int64_t Result = 0;
2710  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2711  Result = LogicalImm | SExtImm;
2712  else
2713  Result = LogicalImm ^ SExtImm;
2714  if (isInt<16>(Result)) {
2715  ReplaceWithLI = true;
2716  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2717  NewImm = Result;
2718  break;
2719  }
2720  return false;
2721  }
2722  }
2723 
2724  if (ReplaceWithLI) {
2725  // We need to be careful with CR-setting instructions we're replacing.
2726  if (SetCR) {
2727  // We don't know anything about uses when we're out of SSA, so only
2728  // replace if the new immediate will be reproduced.
2729  bool ImmChanged = (SExtImm & NewImm) != NewImm;
2730  if (PostRA && ImmChanged)
2731  return false;
2732 
2733  if (!PostRA) {
2734  // If the defining load-immediate has no other uses, we can just replace
2735  // the immediate with the new immediate.
2736  if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2737  DefMI->getOperand(1).setImm(NewImm);
2738 
2739  // If we're not using the GPR result of the CR-setting instruction, we
2740  // just need to and with zero/non-zero depending on the new immediate.
2741  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2742  if (NewImm) {
2743  assert(Immediate && "Transformation converted zero to non-zero?");
2744  NewImm = Immediate;
2745  }
2746  }
2747  else if (ImmChanged)
2748  return false;
2749  }
2750  }
2751 
2752  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2753  LLVM_DEBUG(MI.dump());
2754  LLVM_DEBUG(dbgs() << "Fed by:\n");
2755  LLVM_DEBUG(DefMI->dump());
2756  LoadImmediateInfo LII;
2757  LII.Imm = NewImm;
2758  LII.Is64Bit = Is64BitLI;
2759  LII.SetCR = SetCR;
2760  // If we're setting the CR, the original load-immediate must be kept (as an
2761  // operand to ANDIo/ANDI8o).
2762  if (KilledDef && SetCR)
2763  *KilledDef = nullptr;
2764  replaceInstrWithLI(MI, LII);
2765 
2766  // Fixup killed/dead flag after transformation.
2767  // Pattern:
2768  // ForwardingOperandReg = LI imm1
2769  // y = op2 imm2, ForwardingOperandReg(killed)
2770  if (IsForwardingOperandKilled)
2771  fixupIsDeadOrKill(*DefMI, MI, ForwardingOperandReg);
2772 
2773  LLVM_DEBUG(dbgs() << "With:\n");
2774  LLVM_DEBUG(MI.dump());
2775  return true;
2776  }
2777  return false;
2778 }
2779 
2781  ImmInstrInfo &III, bool PostRA) const {
2782  unsigned Opc = MI.getOpcode();
2783  // The vast majority of the instructions would need their operand 2 replaced
2784  // with an immediate when switching to the reg+imm form. A marked exception
2785  // are the update form loads/stores for which a constant operand 2 would need
2786  // to turn into a displacement and move operand 1 to the operand 2 position.
2787  III.ImmOpNo = 2;
2788  III.OpNoForForwarding = 2;
2789  III.ImmWidth = 16;
2790  III.ImmMustBeMultipleOf = 1;
2791  III.TruncateImmTo = 0;
2792  III.IsSummingOperands = false;
2793  switch (Opc) {
2794  default: return false;
2795  case PPC::ADD4:
2796  case PPC::ADD8:
2797  III.SignedImm = true;
2798  III.ZeroIsSpecialOrig = 0;
2799  III.ZeroIsSpecialNew = 1;
2800  III.IsCommutative = true;
2801  III.IsSummingOperands = true;
2802  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2803  break;
2804  case PPC::ADDC:
2805  case PPC::ADDC8:
2806  III.SignedImm = true;
2807  III.ZeroIsSpecialOrig = 0;
2808  III.ZeroIsSpecialNew = 0;
2809  III.IsCommutative = true;
2810  III.IsSummingOperands = true;
2811  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2812  break;
2813  case PPC::ADDCo:
2814  III.SignedImm = true;
2815  III.ZeroIsSpecialOrig = 0;
2816  III.ZeroIsSpecialNew = 0;
2817  III.IsCommutative = true;
2818  III.IsSummingOperands = true;
2819  III.ImmOpcode = PPC::ADDICo;
2820  break;
2821  case PPC::SUBFC:
2822  case PPC::SUBFC8:
2823  III.SignedImm = true;
2824  III.ZeroIsSpecialOrig = 0;
2825  III.ZeroIsSpecialNew = 0;
2826  III.IsCommutative = false;
2827  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2828  break;
2829  case PPC::CMPW:
2830  case PPC::CMPD:
2831  III.SignedImm = true;
2832  III.ZeroIsSpecialOrig = 0;
2833  III.ZeroIsSpecialNew = 0;
2834  III.IsCommutative = false;
2835  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2836  break;
2837  case PPC::CMPLW:
2838  case PPC::CMPLD:
2839  III.SignedImm = false;
2840  III.ZeroIsSpecialOrig = 0;
2841  III.ZeroIsSpecialNew = 0;
2842  III.IsCommutative = false;
2843  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2844  break;
2845  case PPC::ANDo:
2846  case PPC::AND8o:
2847  case PPC::OR:
2848  case PPC::OR8:
2849  case PPC::XOR:
2850  case PPC::XOR8:
2851  III.SignedImm = false;
2852  III.ZeroIsSpecialOrig = 0;
2853  III.ZeroIsSpecialNew = 0;
2854  III.IsCommutative = true;
2855  switch(Opc) {
2856  default: llvm_unreachable("Unknown opcode");
2857  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2858  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2859  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2860  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2861  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2862  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2863  }
2864  break;
2865  case PPC::RLWNM:
2866  case PPC::RLWNM8:
2867  case PPC::RLWNMo:
2868  case PPC::RLWNM8o:
2869  case PPC::SLW:
2870  case PPC::SLW8:
2871  case PPC::SLWo:
2872  case PPC::SLW8o:
2873  case PPC::SRW:
2874  case PPC::SRW8:
2875  case PPC::SRWo:
2876  case PPC::SRW8o:
2877  case PPC::SRAW:
2878  case PPC::SRAWo:
2879  III.SignedImm = false;
2880  III.ZeroIsSpecialOrig = 0;
2881  III.ZeroIsSpecialNew = 0;
2882  III.IsCommutative = false;
2883  // This isn't actually true, but the instructions ignore any of the
2884  // upper bits, so any immediate loaded with an LI is acceptable.
2885  // This does not apply to shift right algebraic because a value
2886  // out of range will produce a -1/0.
2887  III.ImmWidth = 16;
2888  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2889  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2890  III.TruncateImmTo = 5;
2891  else
2892  III.TruncateImmTo = 6;
2893  switch(Opc) {
2894  default: llvm_unreachable("Unknown opcode");
2895  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2896  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2897  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2898  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2899  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2900  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2901  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2902  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2903  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2904  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2905  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2906  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2907  case PPC::SRAW:
2908  III.ImmWidth = 5;
2909  III.TruncateImmTo = 0;
2910  III.ImmOpcode = PPC::SRAWI;
2911  break;
2912  case PPC::SRAWo:
2913  III.ImmWidth = 5;
2914  III.TruncateImmTo = 0;
2915  III.ImmOpcode = PPC::SRAWIo;
2916  break;
2917  }
2918  break;
2919  case PPC::RLDCL:
2920  case PPC::RLDCLo:
2921  case PPC::RLDCR:
2922  case PPC::RLDCRo:
2923  case PPC::SLD:
2924  case PPC::SLDo:
2925  case PPC::SRD:
2926  case PPC::SRDo:
2927  case PPC::SRAD:
2928  case PPC::SRADo:
2929  III.SignedImm = false;
2930  III.ZeroIsSpecialOrig = 0;
2931  III.ZeroIsSpecialNew = 0;
2932  III.IsCommutative = false;
2933  // This isn't actually true, but the instructions ignore any of the
2934  // upper bits, so any immediate loaded with an LI is acceptable.
2935  // This does not apply to shift right algebraic because a value
2936  // out of range will produce a -1/0.
2937  III.ImmWidth = 16;
2938  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2939  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2940  III.TruncateImmTo = 6;
2941  else
2942  III.TruncateImmTo = 7;
2943  switch(Opc) {
2944  default: llvm_unreachable("Unknown opcode");
2945  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2946  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2947  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2948  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2949  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2950  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2951  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2952  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2953  case PPC::SRAD:
2954  III.ImmWidth = 6;
2955  III.TruncateImmTo = 0;
2956  III.ImmOpcode = PPC::SRADI;
2957  break;
2958  case PPC::SRADo:
2959  III.ImmWidth = 6;
2960  III.TruncateImmTo = 0;
2961  III.ImmOpcode = PPC::SRADIo;
2962  break;
2963  }
2964  break;
2965  // Loads and stores:
2966  case PPC::LBZX:
2967  case PPC::LBZX8:
2968  case PPC::LHZX:
2969  case PPC::LHZX8:
2970  case PPC::LHAX:
2971  case PPC::LHAX8:
2972  case PPC::LWZX:
2973  case PPC::LWZX8:
2974  case PPC::LWAX:
2975  case PPC::LDX:
2976  case PPC::LFSX:
2977  case PPC::LFDX:
2978  case PPC::STBX:
2979  case PPC::STBX8:
2980  case PPC::STHX:
2981  case PPC::STHX8:
2982  case PPC::STWX:
2983  case PPC::STWX8:
2984  case PPC::STDX:
2985  case PPC::STFSX:
2986  case PPC::STFDX:
2987  III.SignedImm = true;
2988  III.ZeroIsSpecialOrig = 1;
2989  III.ZeroIsSpecialNew = 2;
2990  III.IsCommutative = true;
2991  III.IsSummingOperands = true;
2992  III.ImmOpNo = 1;
2993  III.OpNoForForwarding = 2;
2994  switch(Opc) {
2995  default: llvm_unreachable("Unknown opcode");
2996  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2997  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2998  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2999  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
3000  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
3001  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
3002  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
3003  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
3004  case PPC::LWAX:
3005  III.ImmOpcode = PPC::LWA;
3006  III.ImmMustBeMultipleOf = 4;
3007  break;
3008  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
3009  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
3010  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
3011  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
3012  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
3013  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
3014  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
3015  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
3016  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
3017  case PPC::STDX:
3018  III.ImmOpcode = PPC::STD;
3019  III.ImmMustBeMultipleOf = 4;
3020  break;
3021  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
3022  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
3023  }
3024  break;
3025  case PPC::LBZUX:
3026  case PPC::LBZUX8:
3027  case PPC::LHZUX:
3028  case PPC::LHZUX8:
3029  case PPC::LHAUX:
3030  case PPC::LHAUX8:
3031  case PPC::LWZUX:
3032  case PPC::LWZUX8:
3033  case PPC::LDUX:
3034  case PPC::LFSUX:
3035  case PPC::LFDUX:
3036  case PPC::STBUX:
3037  case PPC::STBUX8:
3038  case PPC::STHUX:
3039  case PPC::STHUX8:
3040  case PPC::STWUX:
3041  case PPC::STWUX8:
3042  case PPC::STDUX:
3043  case PPC::STFSUX:
3044  case PPC::STFDUX:
3045  III.SignedImm = true;
3046  III.ZeroIsSpecialOrig = 2;
3047  III.ZeroIsSpecialNew = 3;
3048  III.IsCommutative = false;
3049  III.IsSummingOperands = true;
3050  III.ImmOpNo = 2;
3051  III.OpNoForForwarding = 3;
3052  switch(Opc) {
3053  default: llvm_unreachable("Unknown opcode");
3054  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
3055  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
3056  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
3057  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
3058  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
3059  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
3060  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
3061  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
3062  case PPC::LDUX:
3063  III.ImmOpcode = PPC::LDU;
3064  III.ImmMustBeMultipleOf = 4;
3065  break;
3066  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
3067  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
3068  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
3069  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
3070  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
3071  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
3072  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
3073  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
3074  case PPC::STDUX:
3075  III.ImmOpcode = PPC::STDU;
3076  III.ImmMustBeMultipleOf = 4;
3077  break;
3078  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
3079  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
3080  }
3081  break;
3082  // Power9 and up only. For some of these, the X-Form version has access to all
3083  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
3084  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
3085  // into or stored from is one of the VR registers.
3086  case PPC::LXVX:
3087  case PPC::LXSSPX:
3088  case PPC::LXSDX:
3089  case PPC::STXVX:
3090  case PPC::STXSSPX:
3091  case PPC::STXSDX:
3092  case PPC::XFLOADf32:
3093  case PPC::XFLOADf64:
3094  case PPC::XFSTOREf32:
3095  case PPC::XFSTOREf64:
3096  if (!Subtarget.hasP9Vector())
3097  return false;
3098  III.SignedImm = true;
3099  III.ZeroIsSpecialOrig = 1;
3100  III.ZeroIsSpecialNew = 2;
3101  III.IsCommutative = true;
3102  III.IsSummingOperands = true;
3103  III.ImmOpNo = 1;
3104  III.OpNoForForwarding = 2;
3105  III.ImmMustBeMultipleOf = 4;
3106  switch(Opc) {
3107  default: llvm_unreachable("Unknown opcode");
3108  case PPC::LXVX:
3109  III.ImmOpcode = PPC::LXV;
3110  III.ImmMustBeMultipleOf = 16;
3111  break;
3112  case PPC::LXSSPX:
3113  if (PostRA) {
3114  if (isVFRegister(MI.getOperand(0).getReg()))
3115  III.ImmOpcode = PPC::LXSSP;
3116  else {
3117  III.ImmOpcode = PPC::LFS;
3118  III.ImmMustBeMultipleOf = 1;
3119  }
3120  break;
3121  }
3123  case PPC::XFLOADf32:
3124  III.ImmOpcode = PPC::DFLOADf32;
3125  break;
3126  case PPC::LXSDX:
3127  if (PostRA) {
3128  if (isVFRegister(MI.getOperand(0).getReg()))
3129  III.ImmOpcode = PPC::LXSD;
3130  else {
3131  III.ImmOpcode = PPC::LFD;
3132  III.ImmMustBeMultipleOf = 1;
3133  }
3134  break;
3135  }
3137  case PPC::XFLOADf64:
3138  III.ImmOpcode = PPC::DFLOADf64;
3139  break;
3140  case PPC::STXVX:
3141  III.ImmOpcode = PPC::STXV;
3142  III.ImmMustBeMultipleOf = 16;
3143  break;
3144  case PPC::STXSSPX:
3145  if (PostRA) {
3146  if (isVFRegister(MI.getOperand(0).getReg()))
3147  III.ImmOpcode = PPC::STXSSP;
3148  else {
3149  III.ImmOpcode = PPC::STFS;
3150  III.ImmMustBeMultipleOf = 1;
3151  }
3152  break;
3153  }
3155  case PPC::XFSTOREf32:
3156  III.ImmOpcode = PPC::DFSTOREf32;
3157  break;
3158  case PPC::STXSDX:
3159  if (PostRA) {
3160  if (isVFRegister(MI.getOperand(0).getReg()))
3161  III.ImmOpcode = PPC::STXSD;
3162  else {
3163  III.ImmOpcode = PPC::STFD;
3164  III.ImmMustBeMultipleOf = 1;
3165  }
3166  break;
3167  }
3169  case PPC::XFSTOREf64:
3170  III.ImmOpcode = PPC::DFSTOREf64;
3171  break;
3172  }
3173  break;
3174  }
3175  return true;
3176 }
3177 
3178 // Utility function for swaping two arbitrary operands of an instruction.
3179 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3180  assert(Op1 != Op2 && "Cannot swap operand with itself.");
3181 
3182  unsigned MaxOp = std::max(Op1, Op2);
3183  unsigned MinOp = std::min(Op1, Op2);
3184  MachineOperand MOp1 = MI.getOperand(MinOp);
3185  MachineOperand MOp2 = MI.getOperand(MaxOp);
3186  MI.RemoveOperand(std::max(Op1, Op2));
3187  MI.RemoveOperand(std::min(Op1, Op2));
3188 
3189  // If the operands we are swapping are the two at the end (the common case)
3190  // we can just remove both and add them in the opposite order.
3191  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3192  MI.addOperand(MOp2);
3193  MI.addOperand(MOp1);
3194  } else {
3195  // Store all operands in a temporary vector, remove them and re-add in the
3196  // right order.
3198  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3199  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3200  MOps.push_back(MI.getOperand(i));
3201  MI.RemoveOperand(i);
3202  }
3203  // MOp2 needs to be added next.
3204  MI.addOperand(MOp2);
3205  // Now add the rest.
3206  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3207  if (i == MaxOp)
3208  MI.addOperand(MOp1);
3209  else {
3210  MI.addOperand(MOps.back());
3211  MOps.pop_back();
3212  }
3213  }
3214  }
3215 }
3216 
3217 // Check if the 'MI' that has the index OpNoForForwarding
3218 // meets the requirement described in the ImmInstrInfo.
3219 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3220  const ImmInstrInfo &III,
3221  unsigned OpNoForForwarding
3222  ) const {
3223  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3224  // would not work pre-RA, we can only do the check post RA.
3226  if (MRI.isSSA())
3227  return false;
3228 
3229  // Cannot do the transform if MI isn't summing the operands.
3230  if (!III.IsSummingOperands)
3231  return false;
3232 
3233  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3234  if (!III.ZeroIsSpecialOrig)
3235  return false;
3236 
3237  // We cannot do the transform if the operand we are trying to replace
3238  // isn't the same as the operand the instruction allows.
3239  if (OpNoForForwarding != III.OpNoForForwarding)
3240  return false;
3241 
3242  // Check if the instruction we are trying to transform really has
3243  // the special zero register as its operand.
3244  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3245  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3246  return false;
3247 
3248  // This machine instruction is convertible if it is,
3249  // 1. summing the operands.
3250  // 2. one of the operands is special zero register.
3251  // 3. the operand we are trying to replace is allowed by the MI.
3252  return true;
3253 }
3254 
3255 // Check if the DefMI is the add inst and set the ImmMO and RegMO
3256 // accordingly.
3257 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3258  const ImmInstrInfo &III,
3259  MachineOperand *&ImmMO,
3260  MachineOperand *&RegMO) const {
3261  unsigned Opc = DefMI.getOpcode();
3262  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3263  return false;
3264 
3265  assert(DefMI.getNumOperands() >= 3 &&
3266  "Add inst must have at least three operands");
3267  RegMO = &DefMI.getOperand(1);
3268  ImmMO = &DefMI.getOperand(2);
3269 
3270  // This DefMI is elgible for forwarding if it is:
3271  // 1. add inst
3272  // 2. one of the operands is Imm/CPI/Global.
3273  return isAnImmediateOperand(*ImmMO);
3274 }
3275 
3276 bool PPCInstrInfo::isRegElgibleForForwarding(
3277  const MachineOperand &RegMO, const MachineInstr &DefMI,
3278  const MachineInstr &MI, bool KillDefMI,
3279  bool &IsFwdFeederRegKilled) const {
3280  // x = addi y, imm
3281  // ...
3282  // z = lfdx 0, x -> z = lfd imm(y)
3283  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3284  // of "y" between the DEF of "x" and "z".
3285  // The query is only valid post RA.
3287  if (MRI.isSSA())
3288  return false;
3289 
3290  unsigned Reg = RegMO.getReg();
3291 
3292  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3295  It++;
3296  for (; It != E; ++It) {
3297  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3298  return false;
3299  else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3300  IsFwdFeederRegKilled = true;
3301  // Made it to DefMI without encountering a clobber.
3302  if ((&*It) == &DefMI)
3303  break;
3304  }
3305  assert((&*It) == &DefMI && "DefMI is missing");
3306 
3307  // If DefMI also defines the register to be forwarded, we can only forward it
3308  // if DefMI is being erased.
3309  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
3310  return KillDefMI;
3311 
3312  return true;
3313 }
3314 
3315 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3316  const MachineInstr &DefMI,
3317  const ImmInstrInfo &III,
3318  int64_t &Imm) const {
3319  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
3320  if (DefMI.getOpcode() == PPC::ADDItocL) {
3321  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3322  // However, we know that, it is 16-bit width, and has the alignment of 4.
3323  // Check if the instruction met the requirement.
3324  if (III.ImmMustBeMultipleOf > 4 ||
3325  III.TruncateImmTo || III.ImmWidth != 16)
3326  return false;
3327 
3328  // Going from XForm to DForm loads means that the displacement needs to be
3329  // not just an immediate but also a multiple of 4, or 16 depending on the
3330  // load. A DForm load cannot be represented if it is a multiple of say 2.
3331  // XForm loads do not have this restriction.
3332  if (ImmMO.isGlobal() &&
3333  ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3334  return false;
3335 
3336  return true;
3337  }
3338 
3339  if (ImmMO.isImm()) {
3340  // It is Imm, we need to check if the Imm fit the range.
3341  int64_t Immediate = ImmMO.getImm();
3342  // Sign-extend to 64-bits.
3343  Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3344  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3345 
3346  if (Imm % III.ImmMustBeMultipleOf)
3347  return false;
3348  if (III.TruncateImmTo)
3349  Imm &= ((1 << III.TruncateImmTo) - 1);
3350  if (III.SignedImm) {
3351  APInt ActualValue(64, Imm, true);
3352  if (!ActualValue.isSignedIntN(III.ImmWidth))
3353  return false;
3354  } else {
3355  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3356  if ((uint64_t)Imm > UnsignedMax)
3357  return false;
3358  }
3359  }
3360  else
3361  return false;
3362 
3363  // This ImmMO is forwarded if it meets the requriement describle
3364  // in ImmInstrInfo
3365  return true;
3366 }
3367 
3368 // If an X-Form instruction is fed by an add-immediate and one of its operands
3369 // is the literal zero, attempt to forward the source of the add-immediate to
3370 // the corresponding D-Form instruction with the displacement coming from
3371 // the immediate being added.
3372 bool PPCInstrInfo::transformToImmFormFedByAdd(
3373  MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
3374  MachineInstr &DefMI, bool KillDefMI) const {
3375  // RegMO ImmMO
3376  // | |
3377  // x = addi reg, imm <----- DefMI
3378  // y = op 0 , x <----- MI
3379  // |
3380  // OpNoForForwarding
3381  // Check if the MI meet the requirement described in the III.
3382  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3383  return false;
3384 
3385  // Check if the DefMI meet the requirement
3386  // described in the III. If yes, set the ImmMO and RegMO accordingly.
3387  MachineOperand *ImmMO = nullptr;
3388  MachineOperand *RegMO = nullptr;
3389  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3390  return false;
3391  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
3392 
3393  // As we get the Imm operand now, we need to check if the ImmMO meet
3394  // the requirement described in the III. If yes set the Imm.
3395  int64_t Imm = 0;
3396  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3397  return false;
3398 
3399  bool IsFwdFeederRegKilled = false;
3400  // Check if the RegMO can be forwarded to MI.
3401  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
3402  IsFwdFeederRegKilled))
3403  return false;
3404 
3405  // Get killed info in case fixup needed after transformation.
3406  unsigned ForwardKilledOperandReg = ~0U;
3408  bool PostRA = !MRI.isSSA();
3409  if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
3410  ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
3411 
3412  // We know that, the MI and DefMI both meet the pattern, and
3413  // the Imm also meet the requirement with the new Imm-form.
3414  // It is safe to do the transformation now.
3415  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
3416  LLVM_DEBUG(MI.dump());
3417  LLVM_DEBUG(dbgs() << "Fed by:\n");
3418  LLVM_DEBUG(DefMI.dump());
3419 
3420  // Update the base reg first.
3422  false, false,
3423  RegMO->isKill());
3424 
3425  // Then, update the imm.
3426  if (ImmMO->isImm()) {
3427  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3428  // directly.
3430  }
3431  else {
3432  // Otherwise, it is Constant Pool Index(CPI) or Global,
3433  // which is relocation in fact. We need to replace the special zero
3434  // register with ImmMO.
3435  // Before that, we need to fixup the target flags for imm.
3436  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3437  if (DefMI.getOpcode() == PPC::ADDItocL)
3439 
3440  // MI didn't have the interface such as MI.setOperand(i) though
3441  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3442  // ImmMO, we need to remove ZERO operand and all the operands behind it,
3443  // and, add the ImmMO, then, move back all the operands behind ZERO.
3445  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3446  MOps.push_back(MI.getOperand(i));
3447  MI.RemoveOperand(i);
3448  }
3449 
3450  // Remove the last MO in the list, which is ZERO operand in fact.
3451  MOps.pop_back();
3452  // Add the imm operand.
3453  MI.addOperand(*ImmMO);
3454  // Now add the rest back.
3455  for (auto &MO : MOps)
3456  MI.addOperand(MO);
3457  }
3458 
3459  // Update the opcode.
3460  MI.setDesc(get(III.ImmOpcode));
3461 
3462  // Fix up killed/dead flag after transformation.
3463  // Pattern 1:
3464  // x = ADD KilledFwdFeederReg, imm
3465  // n = opn KilledFwdFeederReg(killed), regn
3466  // y = XOP 0, x
3467  // Pattern 2:
3468  // x = ADD reg(killed), imm
3469  // y = XOP 0, x
3470  if (IsFwdFeederRegKilled || RegMO->isKill())
3471  fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
3472  // Pattern 3:
3473  // ForwardKilledOperandReg = ADD reg, imm
3474  // y = XOP 0, ForwardKilledOperandReg(killed)
3475  if (ForwardKilledOperandReg != ~0U)
3476  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3477 
3478  LLVM_DEBUG(dbgs() << "With:\n");
3479  LLVM_DEBUG(MI.dump());
3480 
3481  return true;
3482 }
3483 
3484 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3485  const ImmInstrInfo &III,
3486  unsigned ConstantOpNo,
3487  MachineInstr &DefMI,
3488  int64_t Imm) const {
3490  bool PostRA = !MRI.isSSA();
3491  // Exit early if we can't convert this.
3492  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3493  return false;
3494  if (Imm % III.ImmMustBeMultipleOf)
3495  return false;
3496  if (III.TruncateImmTo)
3497  Imm &= ((1 << III.TruncateImmTo) - 1);
3498  if (III.SignedImm) {
3499  APInt ActualValue(64, Imm, true);
3500  if (!ActualValue.isSignedIntN(III.ImmWidth))
3501  return false;
3502  } else {
3503  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3504  if ((uint64_t)Imm > UnsignedMax)
3505  return false;
3506  }
3507 
3508  // If we're post-RA, the instructions don't agree on whether register zero is
3509  // special, we can transform this as long as the register operand that will
3510  // end up in the location where zero is special isn't R0.
3511  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3512  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3513  III.ZeroIsSpecialNew + 1;
3514  unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3515  unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3516  // If R0 is in the operand where zero is special for the new instruction,
3517  // it is unsafe to transform if the constant operand isn't that operand.
3518  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3519  ConstantOpNo != III.ZeroIsSpecialNew)
3520  return false;
3521  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3522  ConstantOpNo != PosForOrigZero)
3523  return false;
3524  }
3525 
3526  // Get killed info in case fixup needed after transformation.
3527  unsigned ForwardKilledOperandReg = ~0U;
3528  if (PostRA && MI.getOperand(ConstantOpNo).isKill())
3529  ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
3530 
3531  unsigned Opc = MI.getOpcode();
3532  bool SpecialShift32 =
3533  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3534  bool SpecialShift64 =
3535  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3536  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3537  Opc == PPC::SLDo || Opc == PPC::SRDo;
3538  bool RightShift =
3539  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3540 
3541  MI.setDesc(get(III.ImmOpcode));
3542  if (ConstantOpNo == III.OpNoForForwarding) {
3543  // Converting shifts to immediate form is a bit tricky since they may do
3544  // one of three things:
3545  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3546  // 2. If the shift amount is zero, the result is unchanged (save for maybe
3547  // setting CR0)
3548  // 3. If the shift amount is in [1, OpSize), it's just a shift
3549  if (SpecialShift32 || SpecialShift64) {
3550  LoadImmediateInfo LII;
3551  LII.Imm = 0;
3552  LII.SetCR = SetCR;
3553  LII.Is64Bit = SpecialShift64;
3554  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3555  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3556  replaceInstrWithLI(MI, LII);
3557  // Shifts by zero don't change the value. If we don't need to set CR0,
3558  // just convert this to a COPY. Can't do this post-RA since we've already
3559  // cleaned up the copies.
3560  else if (!SetCR && ShAmt == 0 && !PostRA) {
3561  MI.RemoveOperand(2);
3562  MI.setDesc(get(PPC::COPY));
3563  } else {
3564  // The 32 bit and 64 bit instructions are quite different.
3565  if (SpecialShift32) {
3566  // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3567  uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3568  uint64_t MB = RightShift ? ShAmt : 0;
3569  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3571  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3572  .addImm(ME);
3573  } else {
3574  // Left shifts use (N, 63-N), right shifts use (64-N, N).
3575  uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3576  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3578  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3579  }
3580  }
3581  } else
3582  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3583  }
3584  // Convert commutative instructions (switch the operands and convert the
3585  // desired one to an immediate.
3586  else if (III.IsCommutative) {
3587  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3588  swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3589  } else
3590  llvm_unreachable("Should have exited early!");
3591 
3592  // For instructions for which the constant register replaces a different
3593  // operand than where the immediate goes, we need to swap them.
3594  if (III.OpNoForForwarding != III.ImmOpNo)
3596 
3597  // If the special R0/X0 register index are different for original instruction
3598  // and new instruction, we need to fix up the register class in new
3599  // instruction.
3600  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3601  if (III.ZeroIsSpecialNew) {
3602  // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
3603  // need to fix up register class.
3604  unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3605  if (TargetRegisterInfo::isVirtualRegister(RegToModify)) {
3606  const TargetRegisterClass *NewRC =
3607  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3608  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3609  MRI.setRegClass(RegToModify, NewRC);
3610  }
3611  }
3612  }
3613 
3614  // Fix up killed/dead flag after transformation.
3615  // Pattern:
3616  // ForwardKilledOperandReg = LI imm
3617  // y = XOP reg, ForwardKilledOperandReg(killed)
3618  if (ForwardKilledOperandReg != ~0U)
3619  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3620  return true;
3621 }
3622 
3623 const TargetRegisterClass *
3625  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3626  return &PPC::VSRCRegClass;
3627  return RC;
3628 }
3629 
3631  return PPC::getRecordFormOpcode(Opcode);
3632 }
3633 
3634 // This function returns true if the machine instruction
3635 // always outputs a value by sign-extending a 32 bit value,
3636 // i.e. 0 to 31-th bits are same as 32-th bit.
3637 static bool isSignExtendingOp(const MachineInstr &MI) {
3638  int Opcode = MI.getOpcode();
3639  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3640  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3641  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3642  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3643  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3644  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3645  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3646  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3647  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3648  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3649  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3650  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3651  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3652  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3653  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3654  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3655  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3656  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3657  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3658  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3659  Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
3660  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3661  Opcode == PPC::EXTSB8_32_64)
3662  return true;
3663 
3664  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3665  return true;
3666 
3667  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3668  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3669  MI.getOperand(3).getImm() > 0 &&
3670  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3671  return true;
3672 
3673  return false;
3674 }
3675 
3676 // This function returns true if the machine instruction
3677 // always outputs zeros in higher 32 bits.
3678 static bool isZeroExtendingOp(const MachineInstr &MI) {
3679  int Opcode = MI.getOpcode();
3680  // The 16-bit immediate is sign-extended in li/lis.
3681  // If the most significant bit is zero, all higher bits are zero.
3682  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3683  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3684  int64_t Imm = MI.getOperand(1).getImm();
3685  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3686  return true;
3687  }
3688 
3689  // We have some variations of rotate-and-mask instructions
3690  // that clear higher 32-bits.
3691  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3692  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3693  Opcode == PPC::RLDICL_32_64) &&
3694  MI.getOperand(3).getImm() >= 32)
3695  return true;
3696 
3697  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3698  MI.getOperand(3).getImm() >= 32 &&
3699  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3700  return true;
3701 
3702  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3703  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3704  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3705  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3706  return true;
3707 
3708  // There are other instructions that clear higher 32-bits.
3709  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3710  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3711  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3712  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3713  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3714  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3715  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3716  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3717  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3718  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3719  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3720  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3721  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3722  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3723  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3724  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3725  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3726  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3727  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3728  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3729  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3730  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3731  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3732  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3733  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3734  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3735  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3736  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3737  Opcode == PPC::MFVSRWZ)
3738  return true;
3739 
3740  return false;
3741 }
3742 
3743 // This function returns true if the input MachineInstr is a TOC save
3744 // instruction.
3746  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3747  return false;
3748  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3749  unsigned StackOffset = MI.getOperand(1).getImm();
3750  unsigned StackReg = MI.getOperand(2).getReg();
3751  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3752  return true;
3753 
3754  return false;
3755 }
3756 
3757 // We limit the max depth to track incoming values of PHIs or binary ops
3758 // (e.g. AND) to avoid excessive cost.
3759 const unsigned MAX_DEPTH = 1;
3760 
3761 bool
3763  const unsigned Depth) const {
3764  const MachineFunction *MF = MI.getParent()->getParent();
3765  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3766 
3767  // If we know this instruction returns sign- or zero-extended result,
3768  // return true.
3769  if (SignExt ? isSignExtendingOp(MI):
3770  isZeroExtendingOp(MI))
3771  return true;
3772 
3773  switch (MI.getOpcode()) {
3774  case PPC::COPY: {
3775  unsigned SrcReg = MI.getOperand(1).getReg();
3776 
3777  // In both ELFv1 and v2 ABI, method parameters and the return value
3778  // are sign- or zero-extended.
3779  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3780  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3781  // We check the ZExt/SExt flags for a method parameter.
3782  if (MI.getParent()->getBasicBlock() ==
3783  &MF->getFunction().getEntryBlock()) {
3784  unsigned VReg = MI.getOperand(0).getReg();
3785  if (MF->getRegInfo().isLiveIn(VReg))
3786  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3787  FuncInfo->isLiveInZExt(VReg);
3788  }
3789 
3790  // For a method return value, we check the ZExt/SExt flags in attribute.
3791  // We assume the following code sequence for method call.
3792  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3793  // BL8_NOP @func,...
3794  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3795  // %5 = COPY %x3; G8RC:%5
3796  if (SrcReg == PPC::X3) {
3797  const MachineBasicBlock *MBB = MI.getParent();
3800  if (II != MBB->instr_begin() &&
3801  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3802  const MachineInstr &CallMI = *(--II);
3803  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3804  const Function *CalleeFn =
3805  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3806  if (!CalleeFn)
3807  return false;
3808  const IntegerType *IntTy =
3809  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3810  const AttributeSet &Attrs =
3811  CalleeFn->getAttributes().getRetAttributes();
3812  if (IntTy && IntTy->getBitWidth() <= 32)
3813  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3814  Attribute::ZExt);
3815  }
3816  }
3817  }
3818  }
3819 
3820  // If this is a copy from another register, we recursively check source.
3822  return false;
3823  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3824  if (SrcMI != NULL)
3825  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3826 
3827  return false;
3828  }
3829 
3830  case PPC::ANDIo:
3831  case PPC::ANDISo:
3832  case PPC::ORI:
3833  case PPC::ORIS:
3834  case PPC::XORI:
3835  case PPC::XORIS:
3836  case PPC::ANDIo8:
3837  case PPC::ANDISo8:
3838  case PPC::ORI8:
3839  case PPC::ORIS8:
3840  case PPC::XORI8:
3841  case PPC::XORIS8: {
3842  // logical operation with 16-bit immediate does not change the upper bits.
3843  // So, we track the operand register as we do for register copy.
3844  unsigned SrcReg = MI.getOperand(1).getReg();
3846  return false;
3847  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3848  if (SrcMI != NULL)
3849  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3850 
3851  return false;
3852  }
3853 
3854  // If all incoming values are sign-/zero-extended,
3855  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3856  case PPC::OR:
3857  case PPC::OR8:
3858  case PPC::ISEL:
3859  case PPC::PHI: {
3860  if (Depth >= MAX_DEPTH)
3861  return false;
3862 
3863  // The input registers for PHI are operand 1, 3, ...
3864  // The input registers for others are operand 1 and 2.
3865  unsigned E = 3, D = 1;
3866  if (MI.getOpcode() == PPC::PHI) {
3867  E = MI.getNumOperands();
3868  D = 2;
3869  }
3870 
3871  for (unsigned I = 1; I != E; I += D) {
3872  if (MI.getOperand(I).isReg()) {
3873  unsigned SrcReg = MI.getOperand(I).getReg();
3875  return false;
3876  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3877  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3878  return false;
3879  }
3880  else
3881  return false;
3882  }
3883  return true;
3884  }
3885 
3886  // If at least one of the incoming values of an AND is zero extended
3887  // then the output is also zero-extended. If both of the incoming values
3888  // are sign-extended then the output is also sign extended.
3889  case PPC::AND:
3890  case PPC::AND8: {
3891  if (Depth >= MAX_DEPTH)
3892  return false;
3893 
3894  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3895 
3896  unsigned SrcReg1 = MI.getOperand(1).getReg();
3897  unsigned SrcReg2 = MI.getOperand(2).getReg();
3898 
3899  if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3901  return false;
3902 
3903  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3904  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3905  if (!MISrc1 || !MISrc2)
3906  return false;
3907 
3908  if(SignExt)
3909  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3910  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3911  else
3912  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3913  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3914  }
3915 
3916  default:
3917  break;
3918  }
3919  return false;
3920 }
3921 
3922 bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
3923  return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ));
3924 }
3925 
3927  MachineInstr *&CmpInst) const {
3928  MachineBasicBlock *LoopEnd = L.getBottomBlock();
3930  // We really "analyze" only CTR loops right now.
3931  if (I != LoopEnd->end() && isBDNZ(I->getOpcode())) {
3932  IndVarInst = nullptr;
3933  CmpInst = &*I;
3934  return false;
3935  }
3936  return true;
3937 }
3938 
3939 MachineInstr *
3941 
3942  unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop);
3943 
3944  // The loop set-up instruction should be in preheader
3945  for (auto &I : PreHeader.instrs())
3946  if (I.getOpcode() == LOOPi)
3947  return &I;
3948  return nullptr;
3949 }
3950 
3952  MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar,
3954  SmallVectorImpl<MachineInstr *> &PrevInsts, unsigned Iter,
3955  unsigned MaxIter) const {
3956  // We expect a hardware loop currently. This means that IndVar is set
3957  // to null, and the compare is the ENDLOOP instruction.
3958  assert((!IndVar) && isBDNZ(Cmp.getOpcode()) && "Expecting a CTR loop");
3959  MachineFunction *MF = MBB.getParent();
3960  DebugLoc DL = Cmp.getDebugLoc();
3961  MachineInstr *Loop = findLoopInstr(PreHeader);
3962  if (!Loop)
3963  return 0;
3964  unsigned LoopCountReg = Loop->getOperand(0).getReg();
3966  MachineInstr *LoopCount = MRI.getUniqueVRegDef(LoopCountReg);
3967 
3968  if (!LoopCount)
3969  return 0;
3970  // If the loop trip count is a compile-time value, then just change the
3971  // value.
3972  if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI) {
3973  int64_t Offset = LoopCount->getOperand(1).getImm();
3974  if (Offset <= 1) {
3975  LoopCount->eraseFromParent();
3976  Loop->eraseFromParent();
3977  return 0;
3978  }
3979  LoopCount->getOperand(1).setImm(Offset - 1);
3980  return Offset - 1;
3981  }
3982 
3983  // The loop trip count is a run-time value.
3984  // We need to subtract one from the trip count,
3985  // and insert branch later to check if we're done with the loop.
3986 
3987  // Since BDZ/BDZ8 that we will insert will also decrease the ctr by 1,
3988  // so we don't need to generate any thing here.
3991  Subtarget.isPPC64() ? PPC::CTR8 : PPC::CTR, true));
3992  return LoopCountReg;
3993 }
3994 
3995 // Return true if get the base operand, byte offset of an instruction and the
3996 // memory width. Width is the size of memory that is being loaded/stored.
3998  const MachineInstr &LdSt,
3999  const MachineOperand *&BaseReg,
4000  int64_t &Offset,
4001  unsigned &Width,
4002  const TargetRegisterInfo *TRI) const {
4003  assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
4004 
4005  // Handle only loads/stores with base register followed by immediate offset.
4006  if (LdSt.getNumExplicitOperands() != 3)
4007  return false;
4008  if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
4009  return false;
4010 
4011  if (!LdSt.hasOneMemOperand())
4012  return false;
4013 
4014  Width = (*LdSt.memoperands_begin())->getSize();
4015  Offset = LdSt.getOperand(1).getImm();
4016  BaseReg = &LdSt.getOperand(2);
4017  return true;
4018 }
4019 
4021  const MachineInstr &MIa, const MachineInstr &MIb,
4022  AliasAnalysis * /*AA*/) const {
4023  assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
4024  assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
4025 
4026  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
4028  return false;
4029 
4030  // Retrieve the base register, offset from the base register and width. Width
4031  // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
4032  // base registers are identical, and the offset of a lower memory access +
4033  // the width doesn't overlap the offset of a higher memory access,
4034  // then the memory accesses are different.
4036  const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
4037  int64_t OffsetA = 0, OffsetB = 0;
4038  unsigned int WidthA = 0, WidthB = 0;
4039  if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
4040  getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
4041  if (BaseOpA->isIdenticalTo(*BaseOpB)) {
4042  int LowOffset = std::min(OffsetA, OffsetB);
4043  int HighOffset = std::max(OffsetA, OffsetB);
4044  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
4045  if (LowOffset + LowWidth <= HighOffset)
4046  return true;
4047  }
4048  }
4049  return false;
4050 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:635
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:86
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:529
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
static int getRecordFormOpcode(unsigned Opcode)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:248
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:88
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:832
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:98
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
void setIsDead(bool Val=true)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader) const
Find the hardware loop instruction used to set-up the specified loop.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:243
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:90
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:100
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:414
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III, bool PostRA) const
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:187
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
Analyze the loop code to find the loop induction variable and compare used to compute the number of i...
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
bool hasDirectMove() const
Definition: PPCSubtarget.h:277
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:196
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:651
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:83
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:253
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:104
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:194
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
unsigned getAlignment() const
Definition: Globals.cpp:97
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:66
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:659
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:657
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:664
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:582
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:551
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:99
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:174
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:551
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:76
Class to represent integer types.
Definition: DerivedTypes.h:40
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1213
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:173
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:107
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:188
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:50
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:536
static uint64_t add(uint64_t LeftOp, uint64_t RightOp)
Definition: FileCheck.cpp:207
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1050
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:997
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:398
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:69
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:475
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
Representation of each machine instruction.
Definition: MachineInstr.h:64
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
Return true if two MIs access different memory addresses and false otherwise.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:35
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:506
TargetOptions Options
static bool isSignExtendingOp(const MachineInstr &MI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:80
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and zero-extended.
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:698
LLVM Value Representation.
Definition: Value.h:72
static use_instr_iterator use_instr_end()
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:642
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:316
Register getReg() const
getReg - Returns the register number.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:91
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:185
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:313
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
Instructions::const_iterator const_instr_iterator
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:95
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
static bool isAnImmediateOperand(const MachineOperand &MO)
bool expandPostRAPseudo(MachineInstr &MI) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:18
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:173
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:420
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...