LLVM  9.0.0svn
PPCRegisterInfo.h
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1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 
18 #include "llvm/ADT/DenseMap.h"
19 
20 #define GET_REGINFO_HEADER
21 #include "PPCGenRegisterInfo.inc"
22 
23 namespace llvm {
24 class PPCTargetMachine;
25 
26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27  unsigned Reg = 0;
28  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29  SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30  Reg = PPC::CR0;
31  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32  SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33  Reg = PPC::CR1;
34  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35  SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36  Reg = PPC::CR2;
37  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38  SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39  Reg = PPC::CR3;
40  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41  SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42  Reg = PPC::CR4;
43  else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44  SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45  Reg = PPC::CR5;
46  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47  SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48  Reg = PPC::CR6;
49  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50  SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51  Reg = PPC::CR7;
52 
53  assert(Reg != 0 && "Invalid CR bit register");
54  return Reg;
55 }
56 
58  DenseMap<unsigned, unsigned> ImmToIdxMap;
59  const PPCTargetMachine &TM;
60 
61 public:
63 
64  /// getPointerRegClass - Return the register class to use to hold pointers.
65  /// This is used for addressing modes.
66  const TargetRegisterClass *
67  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
68 
69  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
70  MachineFunction &MF) const override;
71 
72  const TargetRegisterClass *
74  const MachineFunction &MF) const override;
75 
76  /// Code Generation virtual methods...
77  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
78  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
80  CallingConv::ID CC) const override;
81  const uint32_t *getNoPreservedMask() const override;
82 
83  void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
84 
85  BitVector getReservedRegs(const MachineFunction &MF) const override;
86  bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
87 
88  /// We require the register scavenger.
89  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
90  return true;
91  }
92 
93  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
94 
95  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
96  return true;
97  }
98 
99  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
100  return true;
101  }
102 
106  unsigned FrameIndex) const;
108  unsigned FrameIndex) const;
110  unsigned FrameIndex) const;
112  unsigned FrameIndex) const;
114  unsigned FrameIndex) const;
116  unsigned FrameIndex) const;
117 
118  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
119  int &FrameIdx) const override;
121  unsigned FIOperandNum,
122  RegScavenger *RS = nullptr) const override;
123 
124  // Support for virtual base registers.
125  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
127  unsigned BaseReg, int FrameIdx,
128  int64_t Offset) const override;
129  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
130  int64_t Offset) const override;
131  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
132  int64_t Offset) const override;
133 
134  // Debug information queries.
135  Register getFrameRegister(const MachineFunction &MF) const override;
136 
137  // Base pointer (stack realignment) support.
138  Register getBaseRegister(const MachineFunction &MF) const;
139  bool hasBasePointer(const MachineFunction &MF) const;
140 
141  /// stripRegisterPrefix - This method strips the character prefix from a
142  /// register name so that only the number is left. Used by for linux asm.
143  static const char *stripRegisterPrefix(const char *RegName) {
144  switch (RegName[0]) {
145  case 'r':
146  case 'f':
147  case 'q': // for QPX
148  case 'v':
149  if (RegName[1] == 's')
150  return RegName + 2;
151  return RegName + 1;
152  case 'c': if (RegName[1] == 'r') return RegName + 2;
153  }
154 
155  return RegName;
156  }
157 };
158 
159 } // end namespace llvm
160 
161 #endif
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction&#39;s frame index reference would be better served by a base register oth...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
unsigned Reg
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
We require the register scavenger.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool hasBasePointer(const MachineFunction &MF) const
static const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Common code between 32-bit and 64-bit PowerPC targets.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
const uint32_t * getNoPreservedMask() const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Register getBaseRegister(const MachineFunction &MF) const
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
Register getFrameRegister(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Representation of each machine instruction.
Definition: MachineInstr.h:64
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
Wrapper class representing virtual and physical registers.
Definition: Register.h:18
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override