31 bool ShouldForce =
false;
54 "could not find corresponding %pcrel_hi");
84 const bool WasForced)
const {
89 if (!Resolved && !WasForced)
92 int64_t
Offset = int64_t(Value);
99 return Offset > 254 || Offset < -256;
103 return Offset > 2046 || Offset < -2048;
166 unsigned MinNopLen = HasStdExtC ? 2 : 4;
168 if ((Count % MinNopLen) != 0)
172 for (; Count >= 4; Count -= 4)
173 OS.
write(
"\x13\0\0\0", 4);
176 if (Count && HasStdExtC)
177 OS.
write(
"\x01\0", 2);
200 return Value & 0xfff;
204 return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
209 return ((Value + 0x800) >> 12) & 0xfffff;
211 if (!isInt<21>(Value))
216 unsigned Sbit = (Value >> 20) & 0x1;
217 unsigned Hi8 = (Value >> 12) & 0xff;
218 unsigned Mid1 = (Value >> 11) & 0x1;
219 unsigned Lo10 = (Value >> 1) & 0x3ff;
224 Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
228 if (!isInt<13>(Value))
234 unsigned Sbit = (Value >> 12) & 0x1;
235 unsigned Hi1 = (Value >> 11) & 0x1;
236 unsigned Mid6 = (Value >> 5) & 0x3f;
237 unsigned Lo4 = (Value >> 1) & 0xf;
242 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
250 uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
251 uint64_t LowerImm = Value & 0xfffULL;
252 return UpperImm | ((LowerImm << 20) << 32);
256 unsigned Bit11 = (Value >> 11) & 0x1;
257 unsigned Bit4 = (Value >> 4) & 0x1;
258 unsigned Bit9_8 = (Value >> 8) & 0x3;
259 unsigned Bit10 = (Value >> 10) & 0x1;
260 unsigned Bit6 = (Value >> 6) & 0x1;
261 unsigned Bit7 = (Value >> 7) & 0x1;
262 unsigned Bit3_1 = (Value >> 1) & 0x7;
263 unsigned Bit5 = (Value >> 5) & 0x1;
264 Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
265 (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
270 unsigned Bit8 = (Value >> 8) & 0x1;
271 unsigned Bit7_6 = (Value >> 6) & 0x3;
272 unsigned Bit5 = (Value >> 5) & 0x1;
273 unsigned Bit4_3 = (Value >> 3) & 0x3;
274 unsigned Bit2_1 = (Value >> 1) & 0x3;
275 Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
301 assert(Offset + NumBytes <= Data.
size() &&
"Invalid fixup offset!");
305 for (
unsigned i = 0; i != NumBytes; ++i) {
306 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
321 unsigned MinNopLen = HasStdExtC ? 2 : 4;
355 uint64_t FixedValue = 0;
364 std::unique_ptr<MCObjectTargetWriter>
std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
This class represents lattice values for constants.
This represents an "assembler immediate".
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
bool isAbsolute() const
Is this an absolute (as opposed to relocatable) value.
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
unsigned TargetOffset
The bit offset to write the relocation into.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
const Triple & getTargetTriple() const
MCContext & getContext() const
static MCOperand createReg(unsigned Reg)
const FeatureBitset & getFeatureBits() const
Encapsulates the layout of an assembly file at a particular point in time.
Base class for the full range of assembler expressions which are needed for parsing.
MCObjectWriter & getWriter() const
bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) override
Hook to check if extra nop bytes must be inserted for alignment directive.
This file implements a class to represent arbitrary precision integral constant values and operations...
Context object for machine code objects.
unsigned getRelaxedOpcode(unsigned Op) const
bool writeNopData(raw_ostream &OS, uint64_t Count) const override
Write an (optimal) nop sequence of Count bytes to the given output.
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Analysis containing CSE Info
Instances of this class represent a single low-level machine instruction.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
unsigned const MachineRegisterInfo * MRI
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx)
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) override
Hook which indicates if the target requires a fixup to be generated when handling an align directive ...
size_t size() const
size - Get the array size.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
void reportError(SMLoc L, const Twine &Msg)
uint32_t getOffset() const
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
raw_ostream & write(unsigned char C)
PowerPC TLS Dynamic Call Fixup
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
virtual void recordRelocation(MCAssembler &Asm, const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target, uint64_t &FixedValue)=0
Record a relocation entry.
unsigned TargetSize
The number of bits written by this fixup.
MCFragment * findAssociatedFragment() const
Find the "associated section" for this expression, which is currently defined as the absolute section...
Target - Wrapper for Target specific information.
unsigned getAlignment() const
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
bool isArch64Bit() const
Test whether the architecture is 64-bit.
static MCValue get(const MCSymbolRefExpr *SymA, const MCSymbolRefExpr *SymB=nullptr, int64_t Val=0, uint32_t RefKind=0)
Generic base class for all target subtargets.
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const override
Relax the instruction in the given fragment to the next wider instruction.
Target independent information on a fixup kind.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Generic interface to target specific assembler backends.
unsigned getTargetKind() const
This class implements an extremely fast bulk output stream that can only output to a stream...
const MCExpr * getValue() const
void addOperand(const MCOperand &Op)
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
Represents a location in source code.
unsigned getOpcode() const
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)
MCFixupKind getKind() const