LLVM  10.0.0svn
RISCVELFObjectWriter.cpp
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1 //===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
13 #include "llvm/MC/MCFixup.h"
14 #include "llvm/MC/MCObjectWriter.h"
16 
17 using namespace llvm;
18 
19 namespace {
20 class RISCVELFObjectWriter : public MCELFObjectTargetWriter {
21 public:
22  RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit);
23 
24  ~RISCVELFObjectWriter() override;
25 
26  // Return true if the given relocation must be with a symbol rather than
27  // section plus offset.
28  bool needsRelocateWithSymbol(const MCSymbol &Sym,
29  unsigned Type) const override {
30  // TODO: this is very conservative, update once RISC-V psABI requirements
31  // are clarified.
32  return true;
33  }
34 
35 protected:
36  unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
37  const MCFixup &Fixup, bool IsPCRel) const override;
38 };
39 }
40 
41 RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
42  : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV,
43  /*HasRelocationAddend*/ true) {}
44 
45 RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
46 
48  const MCValue &Target,
49  const MCFixup &Fixup,
50  bool IsPCRel) const {
51  const MCExpr *Expr = Fixup.getValue();
52  // Determine the type of the relocation
53  unsigned Kind = Fixup.getTargetKind();
54  if (IsPCRel) {
55  switch (Kind) {
56  default:
57  llvm_unreachable("invalid fixup kind!");
58  case FK_Data_4:
59  case FK_PCRel_4:
60  return ELF::R_RISCV_32_PCREL;
62  return ELF::R_RISCV_PCREL_HI20;
64  return ELF::R_RISCV_PCREL_LO12_I;
66  return ELF::R_RISCV_PCREL_LO12_S;
68  return ELF::R_RISCV_GOT_HI20;
70  return ELF::R_RISCV_TLS_GOT_HI20;
72  return ELF::R_RISCV_TLS_GD_HI20;
74  return ELF::R_RISCV_JAL;
76  return ELF::R_RISCV_BRANCH;
78  return ELF::R_RISCV_RVC_JUMP;
80  return ELF::R_RISCV_RVC_BRANCH;
82  return ELF::R_RISCV_CALL;
84  return ELF::R_RISCV_CALL_PLT;
85  }
86  }
87 
88  switch (Kind) {
89  default:
90  llvm_unreachable("invalid fixup kind!");
91  case FK_Data_4:
92  if (Expr->getKind() == MCExpr::Target &&
93  cast<RISCVMCExpr>(Expr)->getKind() == RISCVMCExpr::VK_RISCV_32_PCREL)
94  return ELF::R_RISCV_32_PCREL;
95  return ELF::R_RISCV_32;
96  case FK_Data_8:
97  return ELF::R_RISCV_64;
98  case FK_Data_Add_1:
99  return ELF::R_RISCV_ADD8;
100  case FK_Data_Add_2:
101  return ELF::R_RISCV_ADD16;
102  case FK_Data_Add_4:
103  return ELF::R_RISCV_ADD32;
104  case FK_Data_Add_8:
105  return ELF::R_RISCV_ADD64;
106  case FK_Data_Add_6b:
107  return ELF::R_RISCV_SET6;
108  case FK_Data_Sub_1:
109  return ELF::R_RISCV_SUB8;
110  case FK_Data_Sub_2:
111  return ELF::R_RISCV_SUB16;
112  case FK_Data_Sub_4:
113  return ELF::R_RISCV_SUB32;
114  case FK_Data_Sub_8:
115  return ELF::R_RISCV_SUB64;
116  case FK_Data_Sub_6b:
117  return ELF::R_RISCV_SUB6;
119  return ELF::R_RISCV_HI20;
121  return ELF::R_RISCV_LO12_I;
123  return ELF::R_RISCV_LO12_S;
125  return ELF::R_RISCV_TPREL_HI20;
127  return ELF::R_RISCV_TPREL_LO12_I;
129  return ELF::R_RISCV_TPREL_LO12_S;
131  return ELF::R_RISCV_TPREL_ADD;
133  return ELF::R_RISCV_RELAX;
135  return ELF::R_RISCV_ALIGN;
136  }
137 }
138 
139 std::unique_ptr<MCObjectTargetWriter>
140 llvm::createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) {
141  return std::make_unique<RISCVELFObjectWriter>(OSABI, Is64Bit);
142 }
std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This represents an "assembler immediate".
Definition: MCValue.h:39
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A eight-byte sub fixup.
Definition: MCFixup.h:53
block Block Frequency true
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:77
A eight-byte add fixup.
Definition: MCFixup.h:48
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
static unsigned getRelocType(const MCValue &Target, const MCFixupKind FixupKind, const bool IsPCRel)
Translates generic PPC fixup kind to Mach-O/PPC relocation type enum.
A four-byte fixup.
Definition: MCFixup.h:26
Context object for machine code objects.
Definition: MCContext.h:65
A one-byte add fixup.
Definition: MCFixup.h:45
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A four-byte pc relative fixup.
Definition: MCFixup.h:31
ExprKind getKind() const
Definition: MCExpr.h:68
A four-byte add fixup.
Definition: MCFixup.h:47
Target - Wrapper for Target specific information.
A six-bits sub fixup.
Definition: MCFixup.h:54
A two-byte sub fixup.
Definition: MCFixup.h:51
A eight-byte fixup.
Definition: MCFixup.h:27
A one-byte sub fixup.
Definition: MCFixup.h:50
A four-byte sub fixup.
Definition: MCFixup.h:52
unsigned getTargetKind() const
Definition: MCFixup.h:128
A six-bits add fixup.
Definition: MCFixup.h:49
A two-byte add fixup.
Definition: MCFixup.h:46
const MCExpr * getValue() const
Definition: MCFixup.h:133
Target specific expression.
Definition: MCExpr.h:42