LLVM  11.0.0git
RISCVInstPrinter.cpp
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1 //===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an RISCV MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstPrinter.h"
15 #include "Utils/RISCVBaseInfo.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSymbol.h"
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "asm-printer"
28 
29 // Include the auto-generated portion of the assembly writer.
30 #define PRINT_ALIAS_INSTR
31 #include "RISCVGenAsmWriter.inc"
32 
33 // Include the auto-generated portion of the compress emitter.
34 #define GEN_UNCOMPRESS_INSTR
35 #include "RISCVGenCompressInstEmitter.inc"
36 
37 static cl::opt<bool>
38  NoAliases("riscv-no-aliases",
39  cl::desc("Disable the emission of assembler pseudo instructions"),
40  cl::init(false), cl::Hidden);
41 
42 static cl::opt<bool>
43  ArchRegNames("riscv-arch-reg-names",
44  cl::desc("Print architectural register names rather than the "
45  "ABI names (such as x2 instead of sp)"),
46  cl::init(false), cl::Hidden);
47 
48 // The command-line flags above are used by llvm-mc and llc. They can be used by
49 // `llvm-objdump`, but we override their values here to handle options passed to
50 // `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
51 // be an easier way to allow these options in all these tools, without doing it
52 // this way.
54  if (Opt == "no-aliases") {
55  NoAliases = true;
56  return true;
57  }
58  if (Opt == "numeric") {
59  ArchRegNames = true;
60  return true;
61  }
62 
63  return false;
64 }
65 
67  StringRef Annot, const MCSubtargetInfo &STI,
68  raw_ostream &O) {
69  bool Res = false;
70  const MCInst *NewMI = MI;
71  MCInst UncompressedMI;
72  if (!NoAliases)
73  Res = uncompressInst(UncompressedMI, *MI, MRI, STI);
74  if (Res)
75  NewMI = const_cast<MCInst *>(&UncompressedMI);
76  if (NoAliases || !printAliasInstr(NewMI, Address, STI, O))
77  printInstruction(NewMI, Address, STI, O);
78  printAnnotation(O, Annot);
79 }
80 
81 void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
82  O << getRegisterName(RegNo);
83 }
84 
85 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
86  const MCSubtargetInfo &STI, raw_ostream &O,
87  const char *Modifier) {
88  assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
89  const MCOperand &MO = MI->getOperand(OpNo);
90 
91  if (MO.isReg()) {
92  printRegName(O, MO.getReg());
93  return;
94  }
95 
96  if (MO.isImm()) {
97  O << MO.getImm();
98  return;
99  }
100 
101  assert(MO.isExpr() && "Unknown operand kind in printOperand");
102  MO.getExpr()->print(O, &MAI);
103 }
104 
106  const MCSubtargetInfo &STI,
107  raw_ostream &O) {
108  unsigned Imm = MI->getOperand(OpNo).getImm();
109  auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
110  if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
111  O << SysReg->Name;
112  else
113  O << Imm;
114 }
115 
116 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
117  const MCSubtargetInfo &STI,
118  raw_ostream &O) {
119  unsigned FenceArg = MI->getOperand(OpNo).getImm();
120  assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
121 
122  if ((FenceArg & RISCVFenceField::I) != 0)
123  O << 'i';
124  if ((FenceArg & RISCVFenceField::O) != 0)
125  O << 'o';
126  if ((FenceArg & RISCVFenceField::R) != 0)
127  O << 'r';
128  if ((FenceArg & RISCVFenceField::W) != 0)
129  O << 'w';
130  if (FenceArg == 0)
131  O << "unknown";
132 }
133 
134 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
135  const MCSubtargetInfo &STI, raw_ostream &O) {
136  auto FRMArg =
137  static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
139 }
140 
141 void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
142  const MCSubtargetInfo &STI,
143  raw_ostream &O) {
144  const MCOperand &MO = MI->getOperand(OpNo);
145 
146  assert(MO.isReg() && "printAtomicMemOp can only print register operands");
147  O << "(";
148  printRegName(O, MO.getReg());
149  O << ")";
150  return;
151 }
152 
153 void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
154  const MCSubtargetInfo &STI, raw_ostream &O) {
155  unsigned Imm = MI->getOperand(OpNo).getImm();
156  unsigned Sew = (Imm >> 2) & 0x7;
157  unsigned Lmul = Imm & 0x3;
158 
159  Lmul = 0x1 << Lmul;
160  Sew = 0x1 << (Sew + 3);
161  O << "e" << Sew << ",m" << Lmul;
162 }
163 
164 void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
165  const MCSubtargetInfo &STI,
166  raw_ostream &O) {
167  const MCOperand &MO = MI->getOperand(OpNo);
168 
169  assert(MO.isReg() && "printVMaskReg can only print register operands");
170  if (MO.getReg() == RISCV::NoRegister)
171  return;
172  O << ", ";
173  printRegName(O, MO.getReg());
174  O << ".t";
175 }
176 
177 void RISCVInstPrinter::printSImm5Plus1(const MCInst *MI, unsigned OpNo,
178  const MCSubtargetInfo &STI,
179  raw_ostream &O) {
180  const MCOperand &MO = MI->getOperand(OpNo);
181 
182  assert(MO.isImm() && "printSImm5Plus1 can only print constant operands");
183  O << MO.getImm() + 1;
184 }
185 
186 const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) {
187  return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
188  : RISCV::ABIRegAltName);
189 }
bool isImm() const
Definition: MCInst.h:58
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSImm5Plus1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:57
static const char * getRegisterName(unsigned RegNo)
const FeatureBitset & getFeatureBits() const
void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
const MCExpr * getExpr() const
Definition: MCInst.h:95
void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
int64_t getImm() const
Definition: MCInst.h:75
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:434
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:42
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
bool isExpr() const
Definition: MCInst.h:60
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
void printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
static cl::opt< bool > NoAliases("riscv-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), cl::init(false), cl::Hidden)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printAtomicMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier=nullptr)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:48
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
Generic base class for all target subtargets.
void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static cl::opt< bool > ArchRegNames("riscv-arch-reg-names", cl::desc("Print architectural register names rather than the " "ABI names (such as x2 instead of sp)"), cl::init(false), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static StringRef roundingModeToString(RoundingMode RndMode)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const SysReg * lookupSysRegByEncoding(uint16_t)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
void printRegName(raw_ostream &O, unsigned RegNo) const override
Print the assembler register name.
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:50