LLVM 19.0.0git
RISCVInstrInfo.cpp
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1//===-- RISCVInstrInfo.cpp - RISC-V Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVInstrInfo.h"
15#include "RISCV.h"
17#include "RISCVSubtarget.h"
18#include "RISCVTargetMachine.h"
19#include "llvm/ADT/STLExtras.h"
36
37using namespace llvm;
38
39#define GEN_CHECK_COMPRESS_INSTR
40#include "RISCVGenCompressInstEmitter.inc"
41
42#define GET_INSTRINFO_CTOR_DTOR
43#define GET_INSTRINFO_NAMED_OPS
44#include "RISCVGenInstrInfo.inc"
45
47 "riscv-prefer-whole-register-move", cl::init(false), cl::Hidden,
48 cl::desc("Prefer whole register move for vector registers."));
49
51 "riscv-force-machine-combiner-strategy", cl::Hidden,
52 cl::desc("Force machine combiner to use a specific strategy for machine "
53 "trace metrics evaluation."),
54 cl::init(MachineTraceStrategy::TS_NumStrategies),
55 cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local",
56 "Local strategy."),
57 clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr",
58 "MinInstrCount strategy.")));
59
61
62using namespace RISCV;
63
64#define GET_RISCVVPseudosTable_IMPL
65#include "RISCVGenSearchableTables.inc"
66
67} // namespace llvm::RISCVVPseudosTable
68
70 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
71 STI(STI) {}
72
74 if (STI.hasStdExtCOrZca())
75 return MCInstBuilder(RISCV::C_NOP);
76 return MCInstBuilder(RISCV::ADDI)
77 .addReg(RISCV::X0)
78 .addReg(RISCV::X0)
79 .addImm(0);
80}
81
83 int &FrameIndex) const {
84 unsigned Dummy;
85 return isLoadFromStackSlot(MI, FrameIndex, Dummy);
86}
87
89 int &FrameIndex,
90 unsigned &MemBytes) const {
91 switch (MI.getOpcode()) {
92 default:
93 return 0;
94 case RISCV::LB:
95 case RISCV::LBU:
96 MemBytes = 1;
97 break;
98 case RISCV::LH:
99 case RISCV::LHU:
100 case RISCV::FLH:
101 MemBytes = 2;
102 break;
103 case RISCV::LW:
104 case RISCV::FLW:
105 case RISCV::LWU:
106 MemBytes = 4;
107 break;
108 case RISCV::LD:
109 case RISCV::FLD:
110 MemBytes = 8;
111 break;
112 }
113
114 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
115 MI.getOperand(2).getImm() == 0) {
116 FrameIndex = MI.getOperand(1).getIndex();
117 return MI.getOperand(0).getReg();
118 }
119
120 return 0;
121}
122
124 int &FrameIndex) const {
125 unsigned Dummy;
126 return isStoreToStackSlot(MI, FrameIndex, Dummy);
127}
128
130 int &FrameIndex,
131 unsigned &MemBytes) const {
132 switch (MI.getOpcode()) {
133 default:
134 return 0;
135 case RISCV::SB:
136 MemBytes = 1;
137 break;
138 case RISCV::SH:
139 case RISCV::FSH:
140 MemBytes = 2;
141 break;
142 case RISCV::SW:
143 case RISCV::FSW:
144 MemBytes = 4;
145 break;
146 case RISCV::SD:
147 case RISCV::FSD:
148 MemBytes = 8;
149 break;
150 }
151
152 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
153 MI.getOperand(2).getImm() == 0) {
154 FrameIndex = MI.getOperand(1).getIndex();
155 return MI.getOperand(0).getReg();
156 }
157
158 return 0;
159}
160
161static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,
162 unsigned NumRegs) {
163 return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs;
164}
165
167 const MachineBasicBlock &MBB,
170 RISCVII::VLMUL LMul) {
172 return false;
173
174 assert(MBBI->getOpcode() == TargetOpcode::COPY &&
175 "Unexpected COPY instruction.");
176 Register SrcReg = MBBI->getOperand(1).getReg();
178
179 bool FoundDef = false;
180 bool FirstVSetVLI = false;
181 unsigned FirstSEW = 0;
182 while (MBBI != MBB.begin()) {
183 --MBBI;
184 if (MBBI->isMetaInstruction())
185 continue;
186
187 if (MBBI->getOpcode() == RISCV::PseudoVSETVLI ||
188 MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
189 MBBI->getOpcode() == RISCV::PseudoVSETIVLI) {
190 // There is a vsetvli between COPY and source define instruction.
191 // vy = def_vop ... (producing instruction)
192 // ...
193 // vsetvli
194 // ...
195 // vx = COPY vy
196 if (!FoundDef) {
197 if (!FirstVSetVLI) {
198 FirstVSetVLI = true;
199 unsigned FirstVType = MBBI->getOperand(2).getImm();
200 RISCVII::VLMUL FirstLMul = RISCVVType::getVLMUL(FirstVType);
201 FirstSEW = RISCVVType::getSEW(FirstVType);
202 // The first encountered vsetvli must have the same lmul as the
203 // register class of COPY.
204 if (FirstLMul != LMul)
205 return false;
206 }
207 // Only permit `vsetvli x0, x0, vtype` between COPY and the source
208 // define instruction.
209 if (MBBI->getOperand(0).getReg() != RISCV::X0)
210 return false;
211 if (MBBI->getOperand(1).isImm())
212 return false;
213 if (MBBI->getOperand(1).getReg() != RISCV::X0)
214 return false;
215 continue;
216 }
217
218 // MBBI is the first vsetvli before the producing instruction.
219 unsigned VType = MBBI->getOperand(2).getImm();
220 // If there is a vsetvli between COPY and the producing instruction.
221 if (FirstVSetVLI) {
222 // If SEW is different, return false.
223 if (RISCVVType::getSEW(VType) != FirstSEW)
224 return false;
225 }
226
227 // If the vsetvli is tail undisturbed, keep the whole register move.
228 if (!RISCVVType::isTailAgnostic(VType))
229 return false;
230
231 // The checking is conservative. We only have register classes for
232 // LMUL = 1/2/4/8. We should be able to convert vmv1r.v to vmv.v.v
233 // for fractional LMUL operations. However, we could not use the vsetvli
234 // lmul for widening operations. The result of widening operation is
235 // 2 x LMUL.
236 return LMul == RISCVVType::getVLMUL(VType);
237 } else if (MBBI->isInlineAsm() || MBBI->isCall()) {
238 return false;
239 } else if (MBBI->getNumDefs()) {
240 // Check all the instructions which will change VL.
241 // For example, vleff has implicit def VL.
242 if (MBBI->modifiesRegister(RISCV::VL))
243 return false;
244
245 // Only converting whole register copies to vmv.v.v when the defining
246 // value appears in the explicit operands.
247 for (const MachineOperand &MO : MBBI->explicit_operands()) {
248 if (!MO.isReg() || !MO.isDef())
249 continue;
250 if (!FoundDef && TRI->regsOverlap(MO.getReg(), SrcReg)) {
251 // We only permit the source of COPY has the same LMUL as the defined
252 // operand.
253 // There are cases we need to keep the whole register copy if the LMUL
254 // is different.
255 // For example,
256 // $x0 = PseudoVSETIVLI 4, 73 // vsetivli zero, 4, e16,m2,ta,m
257 // $v28m4 = PseudoVWADD_VV_M2 $v26m2, $v8m2
258 // # The COPY may be created by vlmul_trunc intrinsic.
259 // $v26m2 = COPY renamable $v28m2, implicit killed $v28m4
260 //
261 // After widening, the valid value will be 4 x e32 elements. If we
262 // convert the COPY to vmv.v.v, it will only copy 4 x e16 elements.
263 // FIXME: The COPY of subregister of Zvlsseg register will not be able
264 // to convert to vmv.v.[v|i] under the constraint.
265 if (MO.getReg() != SrcReg)
266 return false;
267
268 // In widening reduction instructions with LMUL_1 input vector case,
269 // only checking the LMUL is insufficient due to reduction result is
270 // always LMUL_1.
271 // For example,
272 // $x11 = PseudoVSETIVLI 1, 64 // vsetivli a1, 1, e8, m1, ta, mu
273 // $v8m1 = PseudoVWREDSUM_VS_M1 $v26, $v27
274 // $v26 = COPY killed renamable $v8
275 // After widening, The valid value will be 1 x e16 elements. If we
276 // convert the COPY to vmv.v.v, it will only copy 1 x e8 elements.
277 uint64_t TSFlags = MBBI->getDesc().TSFlags;
279 return false;
280
281 // If the producing instruction does not depend on vsetvli, do not
282 // convert COPY to vmv.v.v. For example, VL1R_V or PseudoVRELOAD.
283 if (!RISCVII::hasSEWOp(TSFlags) || !RISCVII::hasVLOp(TSFlags))
284 return false;
285
286 // Found the definition.
287 FoundDef = true;
288 DefMBBI = MBBI;
289 break;
290 }
291 }
292 }
293 }
294
295 return false;
296}
297
300 const DebugLoc &DL, MCRegister DstReg,
301 MCRegister SrcReg, bool KillSrc,
302 unsigned Opc, unsigned NF) const {
304
305 RISCVII::VLMUL LMul;
306 unsigned SubRegIdx;
307 unsigned VVOpc, VIOpc;
308 switch (Opc) {
309 default:
310 llvm_unreachable("Impossible LMUL for vector register copy.");
311 case RISCV::VMV1R_V:
312 LMul = RISCVII::LMUL_1;
313 SubRegIdx = RISCV::sub_vrm1_0;
314 VVOpc = RISCV::PseudoVMV_V_V_M1;
315 VIOpc = RISCV::PseudoVMV_V_I_M1;
316 break;
317 case RISCV::VMV2R_V:
318 LMul = RISCVII::LMUL_2;
319 SubRegIdx = RISCV::sub_vrm2_0;
320 VVOpc = RISCV::PseudoVMV_V_V_M2;
321 VIOpc = RISCV::PseudoVMV_V_I_M2;
322 break;
323 case RISCV::VMV4R_V:
324 LMul = RISCVII::LMUL_4;
325 SubRegIdx = RISCV::sub_vrm4_0;
326 VVOpc = RISCV::PseudoVMV_V_V_M4;
327 VIOpc = RISCV::PseudoVMV_V_I_M4;
328 break;
329 case RISCV::VMV8R_V:
330 assert(NF == 1);
331 LMul = RISCVII::LMUL_8;
332 SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
333 VVOpc = RISCV::PseudoVMV_V_V_M8;
334 VIOpc = RISCV::PseudoVMV_V_I_M8;
335 break;
336 }
337
338 bool UseVMV_V_V = false;
339 bool UseVMV_V_I = false;
341 if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
342 UseVMV_V_V = true;
343 Opc = VVOpc;
344
345 if (DefMBBI->getOpcode() == VIOpc) {
346 UseVMV_V_I = true;
347 Opc = VIOpc;
348 }
349 }
350
351 if (NF == 1) {
352 auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
353 if (UseVMV_V_V)
354 MIB.addReg(DstReg, RegState::Undef);
355 if (UseVMV_V_I)
356 MIB = MIB.add(DefMBBI->getOperand(2));
357 else
358 MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
359 if (UseVMV_V_V) {
360 const MCInstrDesc &Desc = DefMBBI->getDesc();
361 MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
362 MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
363 MIB.addImm(0); // tu, mu
364 MIB.addReg(RISCV::VL, RegState::Implicit);
365 MIB.addReg(RISCV::VTYPE, RegState::Implicit);
366 }
367 return;
368 }
369
370 int I = 0, End = NF, Incr = 1;
371 unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
372 unsigned DstEncoding = TRI->getEncodingValue(DstReg);
373 unsigned LMulVal;
374 bool Fractional;
375 std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
376 assert(!Fractional && "It is impossible be fractional lmul here.");
377 if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
378 I = NF - 1;
379 End = -1;
380 Incr = -1;
381 }
382
383 for (; I != End; I += Incr) {
384 auto MIB =
385 BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + I));
386 if (UseVMV_V_V)
387 MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
388 if (UseVMV_V_I)
389 MIB = MIB.add(DefMBBI->getOperand(2));
390 else
391 MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
392 getKillRegState(KillSrc));
393 if (UseVMV_V_V) {
394 const MCInstrDesc &Desc = DefMBBI->getDesc();
395 MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
396 MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
397 MIB.addImm(0); // tu, mu
398 MIB.addReg(RISCV::VL, RegState::Implicit);
399 MIB.addReg(RISCV::VTYPE, RegState::Implicit);
400 }
401 }
402}
403
406 const DebugLoc &DL, MCRegister DstReg,
407 MCRegister SrcReg, bool KillSrc) const {
409
410 if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
411 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
412 .addReg(SrcReg, getKillRegState(KillSrc))
413 .addImm(0);
414 return;
415 }
416
417 if (RISCV::GPRPairRegClass.contains(DstReg, SrcReg)) {
418 // Emit an ADDI for both parts of GPRPair.
419 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
420 TRI->getSubReg(DstReg, RISCV::sub_gpr_even))
421 .addReg(TRI->getSubReg(SrcReg, RISCV::sub_gpr_even),
422 getKillRegState(KillSrc))
423 .addImm(0);
424 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
425 TRI->getSubReg(DstReg, RISCV::sub_gpr_odd))
426 .addReg(TRI->getSubReg(SrcReg, RISCV::sub_gpr_odd),
427 getKillRegState(KillSrc))
428 .addImm(0);
429 return;
430 }
431
432 // Handle copy from csr
433 if (RISCV::VCSRRegClass.contains(SrcReg) &&
434 RISCV::GPRRegClass.contains(DstReg)) {
435 BuildMI(MBB, MBBI, DL, get(RISCV::CSRRS), DstReg)
436 .addImm(RISCVSysReg::lookupSysRegByName(TRI->getName(SrcReg))->Encoding)
437 .addReg(RISCV::X0);
438 return;
439 }
440
441 if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
442 unsigned Opc;
443 if (STI.hasStdExtZfh()) {
444 Opc = RISCV::FSGNJ_H;
445 } else {
446 assert(STI.hasStdExtF() &&
447 (STI.hasStdExtZfhmin() || STI.hasStdExtZfbfmin()) &&
448 "Unexpected extensions");
449 // Zfhmin/Zfbfmin doesn't have FSGNJ_H, replace FSGNJ_H with FSGNJ_S.
450 DstReg = TRI->getMatchingSuperReg(DstReg, RISCV::sub_16,
451 &RISCV::FPR32RegClass);
452 SrcReg = TRI->getMatchingSuperReg(SrcReg, RISCV::sub_16,
453 &RISCV::FPR32RegClass);
454 Opc = RISCV::FSGNJ_S;
455 }
456 BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
457 .addReg(SrcReg, getKillRegState(KillSrc))
458 .addReg(SrcReg, getKillRegState(KillSrc));
459 return;
460 }
461
462 if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
463 BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S), DstReg)
464 .addReg(SrcReg, getKillRegState(KillSrc))
465 .addReg(SrcReg, getKillRegState(KillSrc));
466 return;
467 }
468
469 if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {
470 BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_D), DstReg)
471 .addReg(SrcReg, getKillRegState(KillSrc))
472 .addReg(SrcReg, getKillRegState(KillSrc));
473 return;
474 }
475
476 if (RISCV::FPR32RegClass.contains(DstReg) &&
477 RISCV::GPRRegClass.contains(SrcReg)) {
478 BuildMI(MBB, MBBI, DL, get(RISCV::FMV_W_X), DstReg)
479 .addReg(SrcReg, getKillRegState(KillSrc));
480 return;
481 }
482
483 if (RISCV::GPRRegClass.contains(DstReg) &&
484 RISCV::FPR32RegClass.contains(SrcReg)) {
485 BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_W), DstReg)
486 .addReg(SrcReg, getKillRegState(KillSrc));
487 return;
488 }
489
490 if (RISCV::FPR64RegClass.contains(DstReg) &&
491 RISCV::GPRRegClass.contains(SrcReg)) {
492 assert(STI.getXLen() == 64 && "Unexpected GPR size");
493 BuildMI(MBB, MBBI, DL, get(RISCV::FMV_D_X), DstReg)
494 .addReg(SrcReg, getKillRegState(KillSrc));
495 return;
496 }
497
498 if (RISCV::GPRRegClass.contains(DstReg) &&
499 RISCV::FPR64RegClass.contains(SrcReg)) {
500 assert(STI.getXLen() == 64 && "Unexpected GPR size");
501 BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_D), DstReg)
502 .addReg(SrcReg, getKillRegState(KillSrc));
503 return;
504 }
505
506 // VR->VR copies.
507 if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
508 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V);
509 return;
510 }
511
512 if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
513 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V);
514 return;
515 }
516
517 if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
518 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V);
519 return;
520 }
521
522 if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
523 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV8R_V);
524 return;
525 }
526
527 if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
528 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
529 /*NF=*/2);
530 return;
531 }
532
533 if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
534 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
535 /*NF=*/2);
536 return;
537 }
538
539 if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
540 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V,
541 /*NF=*/2);
542 return;
543 }
544
545 if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
546 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
547 /*NF=*/3);
548 return;
549 }
550
551 if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
552 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
553 /*NF=*/3);
554 return;
555 }
556
557 if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
558 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
559 /*NF=*/4);
560 return;
561 }
562
563 if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
564 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
565 /*NF=*/4);
566 return;
567 }
568
569 if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
570 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
571 /*NF=*/5);
572 return;
573 }
574
575 if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
576 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
577 /*NF=*/6);
578 return;
579 }
580
581 if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
582 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
583 /*NF=*/7);
584 return;
585 }
586
587 if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
588 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
589 /*NF=*/8);
590 return;
591 }
592
593 llvm_unreachable("Impossible reg-to-reg copy");
594}
595
598 Register SrcReg, bool IsKill, int FI,
599 const TargetRegisterClass *RC,
600 const TargetRegisterInfo *TRI,
601 Register VReg) const {
603 MachineFrameInfo &MFI = MF->getFrameInfo();
604
605 unsigned Opcode;
606 bool IsScalableVector = true;
607 if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
608 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
609 RISCV::SW : RISCV::SD;
610 IsScalableVector = false;
611 } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) {
612 Opcode = RISCV::PseudoRV32ZdinxSD;
613 IsScalableVector = false;
614 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
615 Opcode = RISCV::FSH;
616 IsScalableVector = false;
617 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
618 Opcode = RISCV::FSW;
619 IsScalableVector = false;
620 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
621 Opcode = RISCV::FSD;
622 IsScalableVector = false;
623 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
624 Opcode = RISCV::VS1R_V;
625 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
626 Opcode = RISCV::VS2R_V;
627 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
628 Opcode = RISCV::VS4R_V;
629 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
630 Opcode = RISCV::VS8R_V;
631 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
632 Opcode = RISCV::PseudoVSPILL2_M1;
633 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
634 Opcode = RISCV::PseudoVSPILL2_M2;
635 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
636 Opcode = RISCV::PseudoVSPILL2_M4;
637 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
638 Opcode = RISCV::PseudoVSPILL3_M1;
639 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
640 Opcode = RISCV::PseudoVSPILL3_M2;
641 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
642 Opcode = RISCV::PseudoVSPILL4_M1;
643 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
644 Opcode = RISCV::PseudoVSPILL4_M2;
645 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
646 Opcode = RISCV::PseudoVSPILL5_M1;
647 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
648 Opcode = RISCV::PseudoVSPILL6_M1;
649 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
650 Opcode = RISCV::PseudoVSPILL7_M1;
651 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
652 Opcode = RISCV::PseudoVSPILL8_M1;
653 else
654 llvm_unreachable("Can't store this register to stack slot");
655
656 if (IsScalableVector) {
660
662 BuildMI(MBB, I, DebugLoc(), get(Opcode))
663 .addReg(SrcReg, getKillRegState(IsKill))
664 .addFrameIndex(FI)
665 .addMemOperand(MMO);
666 } else {
669 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
670
671 BuildMI(MBB, I, DebugLoc(), get(Opcode))
672 .addReg(SrcReg, getKillRegState(IsKill))
673 .addFrameIndex(FI)
674 .addImm(0)
675 .addMemOperand(MMO);
676 }
677}
678
681 Register DstReg, int FI,
682 const TargetRegisterClass *RC,
683 const TargetRegisterInfo *TRI,
684 Register VReg) const {
686 MachineFrameInfo &MFI = MF->getFrameInfo();
687
688 unsigned Opcode;
689 bool IsScalableVector = true;
690 if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
691 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
692 RISCV::LW : RISCV::LD;
693 IsScalableVector = false;
694 } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) {
695 Opcode = RISCV::PseudoRV32ZdinxLD;
696 IsScalableVector = false;
697 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
698 Opcode = RISCV::FLH;
699 IsScalableVector = false;
700 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
701 Opcode = RISCV::FLW;
702 IsScalableVector = false;
703 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
704 Opcode = RISCV::FLD;
705 IsScalableVector = false;
706 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
707 Opcode = RISCV::VL1RE8_V;
708 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
709 Opcode = RISCV::VL2RE8_V;
710 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
711 Opcode = RISCV::VL4RE8_V;
712 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
713 Opcode = RISCV::VL8RE8_V;
714 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
715 Opcode = RISCV::PseudoVRELOAD2_M1;
716 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
717 Opcode = RISCV::PseudoVRELOAD2_M2;
718 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
719 Opcode = RISCV::PseudoVRELOAD2_M4;
720 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
721 Opcode = RISCV::PseudoVRELOAD3_M1;
722 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
723 Opcode = RISCV::PseudoVRELOAD3_M2;
724 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
725 Opcode = RISCV::PseudoVRELOAD4_M1;
726 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
727 Opcode = RISCV::PseudoVRELOAD4_M2;
728 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
729 Opcode = RISCV::PseudoVRELOAD5_M1;
730 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
731 Opcode = RISCV::PseudoVRELOAD6_M1;
732 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
733 Opcode = RISCV::PseudoVRELOAD7_M1;
734 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
735 Opcode = RISCV::PseudoVRELOAD8_M1;
736 else
737 llvm_unreachable("Can't load this register from stack slot");
738
739 if (IsScalableVector) {
743
745 BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg)
746 .addFrameIndex(FI)
747 .addMemOperand(MMO);
748 } else {
751 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
752
753 BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg)
754 .addFrameIndex(FI)
755 .addImm(0)
756 .addMemOperand(MMO);
757 }
758}
759
762 MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS,
763 VirtRegMap *VRM) const {
764 const MachineFrameInfo &MFI = MF.getFrameInfo();
765
766 // The below optimizations narrow the load so they are only valid for little
767 // endian.
768 // TODO: Support big endian by adding an offset into the frame object?
769 if (MF.getDataLayout().isBigEndian())
770 return nullptr;
771
772 // Fold load from stack followed by sext.b/sext.h/sext.w/zext.b/zext.h/zext.w.
773 if (Ops.size() != 1 || Ops[0] != 1)
774 return nullptr;
775
776 unsigned LoadOpc;
777 switch (MI.getOpcode()) {
778 default:
779 if (RISCV::isSEXT_W(MI)) {
780 LoadOpc = RISCV::LW;
781 break;
782 }
783 if (RISCV::isZEXT_W(MI)) {
784 LoadOpc = RISCV::LWU;
785 break;
786 }
787 if (RISCV::isZEXT_B(MI)) {
788 LoadOpc = RISCV::LBU;
789 break;
790 }
791 return nullptr;
792 case RISCV::SEXT_H:
793 LoadOpc = RISCV::LH;
794 break;
795 case RISCV::SEXT_B:
796 LoadOpc = RISCV::LB;
797 break;
798 case RISCV::ZEXT_H_RV32:
799 case RISCV::ZEXT_H_RV64:
800 LoadOpc = RISCV::LHU;
801 break;
802 }
803
805 MachinePointerInfo::getFixedStack(MF, FrameIndex),
807 MFI.getObjectAlign(FrameIndex));
808
809 Register DstReg = MI.getOperand(0).getReg();
810 return BuildMI(*MI.getParent(), InsertPt, MI.getDebugLoc(), get(LoadOpc),
811 DstReg)
812 .addFrameIndex(FrameIndex)
813 .addImm(0)
814 .addMemOperand(MMO);
815}
816
819 const DebugLoc &DL, Register DstReg, uint64_t Val,
820 MachineInstr::MIFlag Flag, bool DstRenamable,
821 bool DstIsDead) const {
822 Register SrcReg = RISCV::X0;
823
824 if (!STI.is64Bit() && !isInt<32>(Val))
825 report_fatal_error("Should only materialize 32-bit constants for RV32");
826
828 assert(!Seq.empty());
829
830 bool SrcRenamable = false;
831 unsigned Num = 0;
832
833 for (const RISCVMatInt::Inst &Inst : Seq) {
834 bool LastItem = ++Num == Seq.size();
835 unsigned DstRegState = getDeadRegState(DstIsDead && LastItem) |
836 getRenamableRegState(DstRenamable);
837 unsigned SrcRegState = getKillRegState(SrcReg != RISCV::X0) |
838 getRenamableRegState(SrcRenamable);
839 switch (Inst.getOpndKind()) {
840 case RISCVMatInt::Imm:
841 BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
842 .addReg(DstReg, RegState::Define | DstRegState)
843 .addImm(Inst.getImm())
844 .setMIFlag(Flag);
845 break;
847 BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
848 .addReg(DstReg, RegState::Define | DstRegState)
849 .addReg(SrcReg, SrcRegState)
850 .addReg(RISCV::X0)
851 .setMIFlag(Flag);
852 break;
854 BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
855 .addReg(DstReg, RegState::Define | DstRegState)
856 .addReg(SrcReg, SrcRegState)
857 .addReg(SrcReg, SrcRegState)
858 .setMIFlag(Flag);
859 break;
861 BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
862 .addReg(DstReg, RegState::Define | DstRegState)
863 .addReg(SrcReg, SrcRegState)
864 .addImm(Inst.getImm())
865 .setMIFlag(Flag);
866 break;
867 }
868
869 // Only the first instruction has X0 as its source.
870 SrcReg = DstReg;
871 SrcRenamable = DstRenamable;
872 }
873}
874
876 switch (Opc) {
877 default:
879 case RISCV::BEQ:
880 return RISCVCC::COND_EQ;
881 case RISCV::BNE:
882 return RISCVCC::COND_NE;
883 case RISCV::BLT:
884 return RISCVCC::COND_LT;
885 case RISCV::BGE:
886 return RISCVCC::COND_GE;
887 case RISCV::BLTU:
888 return RISCVCC::COND_LTU;
889 case RISCV::BGEU:
890 return RISCVCC::COND_GEU;
891 }
892}
893
894// The contents of values added to Cond are not examined outside of
895// RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
896// push BranchOpcode, Reg1, Reg2.
899 // Block ends with fall-through condbranch.
900 assert(LastInst.getDesc().isConditionalBranch() &&
901 "Unknown conditional branch");
902 Target = LastInst.getOperand(2).getMBB();
903 unsigned CC = getCondFromBranchOpc(LastInst.getOpcode());
905 Cond.push_back(LastInst.getOperand(0));
906 Cond.push_back(LastInst.getOperand(1));
907}
908
910 switch (CC) {
911 default:
912 llvm_unreachable("Unknown condition code!");
913 case RISCVCC::COND_EQ:
914 return RISCV::BEQ;
915 case RISCVCC::COND_NE:
916 return RISCV::BNE;
917 case RISCVCC::COND_LT:
918 return RISCV::BLT;
919 case RISCVCC::COND_GE:
920 return RISCV::BGE;
922 return RISCV::BLTU;
924 return RISCV::BGEU;
925 }
926}
927
929 return get(RISCVCC::getBrCond(CC));
930}
931
933 switch (CC) {
934 default:
935 llvm_unreachable("Unrecognized conditional branch");
936 case RISCVCC::COND_EQ:
937 return RISCVCC::COND_NE;
938 case RISCVCC::COND_NE:
939 return RISCVCC::COND_EQ;
940 case RISCVCC::COND_LT:
941 return RISCVCC::COND_GE;
942 case RISCVCC::COND_GE:
943 return RISCVCC::COND_LT;
945 return RISCVCC::COND_GEU;
947 return RISCVCC::COND_LTU;
948 }
949}
950
953 MachineBasicBlock *&FBB,
955 bool AllowModify) const {
956 TBB = FBB = nullptr;
957 Cond.clear();
958
959 // If the block has no terminators, it just falls into the block after it.
961 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
962 return false;
963
964 // Count the number of terminators and find the first unconditional or
965 // indirect branch.
966 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
967 int NumTerminators = 0;
968 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
969 J++) {
970 NumTerminators++;
971 if (J->getDesc().isUnconditionalBranch() ||
972 J->getDesc().isIndirectBranch()) {
973 FirstUncondOrIndirectBr = J.getReverse();
974 }
975 }
976
977 // If AllowModify is true, we can erase any terminators after
978 // FirstUncondOrIndirectBR.
979 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
980 while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
981 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
982 NumTerminators--;
983 }
984 I = FirstUncondOrIndirectBr;
985 }
986
987 // We can't handle blocks that end in an indirect branch.
988 if (I->getDesc().isIndirectBranch())
989 return true;
990
991 // We can't handle Generic branch opcodes from Global ISel.
992 if (I->isPreISelOpcode())
993 return true;
994
995 // We can't handle blocks with more than 2 terminators.
996 if (NumTerminators > 2)
997 return true;
998
999 // Handle a single unconditional branch.
1000 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
1002 return false;
1003 }
1004
1005 // Handle a single conditional branch.
1006 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
1008 return false;
1009 }
1010
1011 // Handle a conditional branch followed by an unconditional branch.
1012 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
1013 I->getDesc().isUnconditionalBranch()) {
1014 parseCondBranch(*std::prev(I), TBB, Cond);
1015 FBB = getBranchDestBlock(*I);
1016 return false;
1017 }
1018
1019 // Otherwise, we can't handle this.
1020 return true;
1021}
1022
1024 int *BytesRemoved) const {
1025 if (BytesRemoved)
1026 *BytesRemoved = 0;
1028 if (I == MBB.end())
1029 return 0;
1030
1031 if (!I->getDesc().isUnconditionalBranch() &&
1032 !I->getDesc().isConditionalBranch())
1033 return 0;
1034
1035 // Remove the branch.
1036 if (BytesRemoved)
1037 *BytesRemoved += getInstSizeInBytes(*I);
1038 I->eraseFromParent();
1039
1040 I = MBB.end();
1041
1042 if (I == MBB.begin())
1043 return 1;
1044 --I;
1045 if (!I->getDesc().isConditionalBranch())
1046 return 1;
1047
1048 // Remove the branch.
1049 if (BytesRemoved)
1050 *BytesRemoved += getInstSizeInBytes(*I);
1051 I->eraseFromParent();
1052 return 2;
1053}
1054
1055// Inserts a branch into the end of the specific MachineBasicBlock, returning
1056// the number of instructions inserted.
1059 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
1060 if (BytesAdded)
1061 *BytesAdded = 0;
1062
1063 // Shouldn't be a fall through.
1064 assert(TBB && "insertBranch must not be told to insert a fallthrough");
1065 assert((Cond.size() == 3 || Cond.size() == 0) &&
1066 "RISC-V branch conditions have two components!");
1067
1068 // Unconditional branch.
1069 if (Cond.empty()) {
1070 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
1071 if (BytesAdded)
1072 *BytesAdded += getInstSizeInBytes(MI);
1073 return 1;
1074 }
1075
1076 // Either a one or two-way conditional branch.
1077 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
1078 MachineInstr &CondMI =
1079 *BuildMI(&MBB, DL, getBrCond(CC)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
1080 if (BytesAdded)
1081 *BytesAdded += getInstSizeInBytes(CondMI);
1082
1083 // One-way conditional branch.
1084 if (!FBB)
1085 return 1;
1086
1087 // Two-way conditional branch.
1088 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
1089 if (BytesAdded)
1090 *BytesAdded += getInstSizeInBytes(MI);
1091 return 2;
1092}
1093
1095 MachineBasicBlock &DestBB,
1096 MachineBasicBlock &RestoreBB,
1097 const DebugLoc &DL, int64_t BrOffset,
1098 RegScavenger *RS) const {
1099 assert(RS && "RegScavenger required for long branching");
1100 assert(MBB.empty() &&
1101 "new block should be inserted for expanding unconditional branch");
1102 assert(MBB.pred_size() == 1);
1103 assert(RestoreBB.empty() &&
1104 "restore block should be inserted for restoring clobbered registers");
1105
1110
1111 if (!isInt<32>(BrOffset))
1113 "Branch offsets outside of the signed 32-bit range not supported");
1114
1115 // FIXME: A virtual register must be used initially, as the register
1116 // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
1117 // uses the same workaround).
1118 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRJALRRegClass);
1119 auto II = MBB.end();
1120 // We may also update the jump target to RestoreBB later.
1121 MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))
1122 .addReg(ScratchReg, RegState::Define | RegState::Dead)
1123 .addMBB(&DestBB, RISCVII::MO_CALL);
1124
1126 Register TmpGPR =
1127 RS->scavengeRegisterBackwards(RISCV::GPRRegClass, MI.getIterator(),
1128 /*RestoreAfter=*/false, /*SpAdj=*/0,
1129 /*AllowSpill=*/false);
1130 if (TmpGPR != RISCV::NoRegister)
1131 RS->setRegUsed(TmpGPR);
1132 else {
1133 // The case when there is no scavenged register needs special handling.
1134
1135 // Pick s11 because it doesn't make a difference.
1136 TmpGPR = RISCV::X27;
1137
1138 int FrameIndex = RVFI->getBranchRelaxationScratchFrameIndex();
1139 if (FrameIndex == -1)
1140 report_fatal_error("underestimated function size");
1141
1142 storeRegToStackSlot(MBB, MI, TmpGPR, /*IsKill=*/true, FrameIndex,
1143 &RISCV::GPRRegClass, TRI, Register());
1144 TRI->eliminateFrameIndex(std::prev(MI.getIterator()),
1145 /*SpAdj=*/0, /*FIOperandNum=*/1);
1146
1147 MI.getOperand(1).setMBB(&RestoreBB);
1148
1149 loadRegFromStackSlot(RestoreBB, RestoreBB.end(), TmpGPR, FrameIndex,
1150 &RISCV::GPRRegClass, TRI, Register());
1151 TRI->eliminateFrameIndex(RestoreBB.back(),
1152 /*SpAdj=*/0, /*FIOperandNum=*/1);
1153 }
1154
1155 MRI.replaceRegWith(ScratchReg, TmpGPR);
1156 MRI.clearVirtRegs();
1157}
1158
1161 assert((Cond.size() == 3) && "Invalid branch condition!");
1162 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
1164 return false;
1165}
1166
1168 MachineBasicBlock *MBB = MI.getParent();
1170
1171 MachineBasicBlock *TBB, *FBB;
1173 if (analyzeBranch(*MBB, TBB, FBB, Cond, /*AllowModify=*/false))
1174 return false;
1175
1176 RISCVCC::CondCode CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
1178
1180 return false;
1181
1182 // For two constants C0 and C1 from
1183 // ```
1184 // li Y, C0
1185 // li Z, C1
1186 // ```
1187 // 1. if C1 = C0 + 1
1188 // we can turn:
1189 // (a) blt Y, X -> bge X, Z
1190 // (b) bge Y, X -> blt X, Z
1191 //
1192 // 2. if C1 = C0 - 1
1193 // we can turn:
1194 // (a) blt X, Y -> bge Z, X
1195 // (b) bge X, Y -> blt Z, X
1196 //
1197 // To make sure this optimization is really beneficial, we only
1198 // optimize for cases where Y had only one use (i.e. only used by the branch).
1199
1200 // Right now we only care about LI (i.e. ADDI x0, imm)
1201 auto isLoadImm = [](const MachineInstr *MI, int64_t &Imm) -> bool {
1202 if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() &&
1203 MI->getOperand(1).getReg() == RISCV::X0) {
1204 Imm = MI->getOperand(2).getImm();
1205 return true;
1206 }
1207 return false;
1208 };
1209 // Either a load from immediate instruction or X0.
1210 auto isFromLoadImm = [&](const MachineOperand &Op, int64_t &Imm) -> bool {
1211 if (!Op.isReg())
1212 return false;
1213 Register Reg = Op.getReg();
1214 return Reg.isVirtual() && isLoadImm(MRI.getVRegDef(Reg), Imm);
1215 };
1216
1217 MachineOperand &LHS = MI.getOperand(0);
1218 MachineOperand &RHS = MI.getOperand(1);
1219 // Try to find the register for constant Z; return
1220 // invalid register otherwise.
1221 auto searchConst = [&](int64_t C1) -> Register {
1223 auto DefC1 = std::find_if(++II, E, [&](const MachineInstr &I) -> bool {
1224 int64_t Imm;
1225 return isLoadImm(&I, Imm) && Imm == C1 &&
1226 I.getOperand(0).getReg().isVirtual();
1227 });
1228 if (DefC1 != E)
1229 return DefC1->getOperand(0).getReg();
1230
1231 return Register();
1232 };
1233
1234 bool Modify = false;
1235 int64_t C0;
1236 if (isFromLoadImm(LHS, C0) && MRI.hasOneUse(LHS.getReg())) {
1237 // Might be case 1.
1238 // Signed integer overflow is UB. (UINT64_MAX is bigger so we don't need
1239 // to worry about unsigned overflow here)
1240 if (C0 < INT64_MAX)
1241 if (Register RegZ = searchConst(C0 + 1)) {
1243 Cond[1] = MachineOperand::CreateReg(RHS.getReg(), /*isDef=*/false);
1244 Cond[2] = MachineOperand::CreateReg(RegZ, /*isDef=*/false);
1245 // We might extend the live range of Z, clear its kill flag to
1246 // account for this.
1247 MRI.clearKillFlags(RegZ);
1248 Modify = true;
1249 }
1250 } else if (isFromLoadImm(RHS, C0) && MRI.hasOneUse(RHS.getReg())) {
1251 // Might be case 2.
1252 // For unsigned cases, we don't want C1 to wrap back to UINT64_MAX
1253 // when C0 is zero.
1254 if ((CC == RISCVCC::COND_GE || CC == RISCVCC::COND_LT) || C0)
1255 if (Register RegZ = searchConst(C0 - 1)) {
1257 Cond[1] = MachineOperand::CreateReg(RegZ, /*isDef=*/false);
1258 Cond[2] = MachineOperand::CreateReg(LHS.getReg(), /*isDef=*/false);
1259 // We might extend the live range of Z, clear its kill flag to
1260 // account for this.
1261 MRI.clearKillFlags(RegZ);
1262 Modify = true;
1263 }
1264 }
1265
1266 if (!Modify)
1267 return false;
1268
1269 // Build the new branch and remove the old one.
1270 BuildMI(*MBB, MI, MI.getDebugLoc(),
1271 getBrCond(static_cast<RISCVCC::CondCode>(Cond[0].getImm())))
1272 .add(Cond[1])
1273 .add(Cond[2])
1274 .addMBB(TBB);
1275 MI.eraseFromParent();
1276
1277 return true;
1278}
1279
1282 assert(MI.getDesc().isBranch() && "Unexpected opcode!");
1283 // The branch target is always the last operand.
1284 int NumOp = MI.getNumExplicitOperands();
1285 return MI.getOperand(NumOp - 1).getMBB();
1286}
1287
1289 int64_t BrOffset) const {
1290 unsigned XLen = STI.getXLen();
1291 // Ideally we could determine the supported branch offset from the
1292 // RISCVII::FormMask, but this can't be used for Pseudo instructions like
1293 // PseudoBR.
1294 switch (BranchOp) {
1295 default:
1296 llvm_unreachable("Unexpected opcode!");
1297 case RISCV::BEQ:
1298 case RISCV::BNE:
1299 case RISCV::BLT:
1300 case RISCV::BGE:
1301 case RISCV::BLTU:
1302 case RISCV::BGEU:
1303 return isIntN(13, BrOffset);
1304 case RISCV::JAL:
1305 case RISCV::PseudoBR:
1306 return isIntN(21, BrOffset);
1307 case RISCV::PseudoJump:
1308 return isIntN(32, SignExtend64(BrOffset + 0x800, XLen));
1309 }
1310}
1311
1312// If the operation has a predicated pseudo instruction, return the pseudo
1313// instruction opcode. Otherwise, return RISCV::INSTRUCTION_LIST_END.
1314// TODO: Support more operations.
1315unsigned getPredicatedOpcode(unsigned Opcode) {
1316 switch (Opcode) {
1317 case RISCV::ADD: return RISCV::PseudoCCADD; break;
1318 case RISCV::SUB: return RISCV::PseudoCCSUB; break;
1319 case RISCV::SLL: return RISCV::PseudoCCSLL; break;
1320 case RISCV::SRL: return RISCV::PseudoCCSRL; break;
1321 case RISCV::SRA: return RISCV::PseudoCCSRA; break;
1322 case RISCV::AND: return RISCV::PseudoCCAND; break;
1323 case RISCV::OR: return RISCV::PseudoCCOR; break;
1324 case RISCV::XOR: return RISCV::PseudoCCXOR; break;
1325
1326 case RISCV::ADDI: return RISCV::PseudoCCADDI; break;
1327 case RISCV::SLLI: return RISCV::PseudoCCSLLI; break;
1328 case RISCV::SRLI: return RISCV::PseudoCCSRLI; break;
1329 case RISCV::SRAI: return RISCV::PseudoCCSRAI; break;
1330 case RISCV::ANDI: return RISCV::PseudoCCANDI; break;
1331 case RISCV::ORI: return RISCV::PseudoCCORI; break;
1332 case RISCV::XORI: return RISCV::PseudoCCXORI; break;
1333
1334 case RISCV::ADDW: return RISCV::PseudoCCADDW; break;
1335 case RISCV::SUBW: return RISCV::PseudoCCSUBW; break;
1336 case RISCV::SLLW: return RISCV::PseudoCCSLLW; break;
1337 case RISCV::SRLW: return RISCV::PseudoCCSRLW; break;
1338 case RISCV::SRAW: return RISCV::PseudoCCSRAW; break;
1339
1340 case RISCV::ADDIW: return RISCV::PseudoCCADDIW; break;
1341 case RISCV::SLLIW: return RISCV::PseudoCCSLLIW; break;
1342 case RISCV::SRLIW: return RISCV::PseudoCCSRLIW; break;
1343 case RISCV::SRAIW: return RISCV::PseudoCCSRAIW; break;
1344
1345 case RISCV::ANDN: return RISCV::PseudoCCANDN; break;
1346 case RISCV::ORN: return RISCV::PseudoCCORN; break;
1347 case RISCV::XNOR: return RISCV::PseudoCCXNOR; break;
1348 }
1349
1350 return RISCV::INSTRUCTION_LIST_END;
1351}
1352
1353/// Identify instructions that can be folded into a CCMOV instruction, and
1354/// return the defining instruction.
1356 const MachineRegisterInfo &MRI,
1357 const TargetInstrInfo *TII) {
1358 if (!Reg.isVirtual())
1359 return nullptr;
1360 if (!MRI.hasOneNonDBGUse(Reg))
1361 return nullptr;
1362 MachineInstr *MI = MRI.getVRegDef(Reg);
1363 if (!MI)
1364 return nullptr;
1365 // Check if MI can be predicated and folded into the CCMOV.
1366 if (getPredicatedOpcode(MI->getOpcode()) == RISCV::INSTRUCTION_LIST_END)
1367 return nullptr;
1368 // Don't predicate li idiom.
1369 if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() &&
1370 MI->getOperand(1).getReg() == RISCV::X0)
1371 return nullptr;
1372 // Check if MI has any other defs or physreg uses.
1373 for (const MachineOperand &MO : llvm::drop_begin(MI->operands())) {
1374 // Reject frame index operands, PEI can't handle the predicated pseudos.
1375 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1376 return nullptr;
1377 if (!MO.isReg())
1378 continue;
1379 // MI can't have any tied operands, that would conflict with predication.
1380 if (MO.isTied())
1381 return nullptr;
1382 if (MO.isDef())
1383 return nullptr;
1384 // Allow constant physregs.
1385 if (MO.getReg().isPhysical() && !MRI.isConstantPhysReg(MO.getReg()))
1386 return nullptr;
1387 }
1388 bool DontMoveAcrossStores = true;
1389 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
1390 return nullptr;
1391 return MI;
1392}
1393
1396 unsigned &TrueOp, unsigned &FalseOp,
1397 bool &Optimizable) const {
1398 assert(MI.getOpcode() == RISCV::PseudoCCMOVGPR &&
1399 "Unknown select instruction");
1400 // CCMOV operands:
1401 // 0: Def.
1402 // 1: LHS of compare.
1403 // 2: RHS of compare.
1404 // 3: Condition code.
1405 // 4: False use.
1406 // 5: True use.
1407 TrueOp = 5;
1408 FalseOp = 4;
1409 Cond.push_back(MI.getOperand(1));
1410 Cond.push_back(MI.getOperand(2));
1411 Cond.push_back(MI.getOperand(3));
1412 // We can only fold when we support short forward branch opt.
1413 Optimizable = STI.hasShortForwardBranchOpt();
1414 return false;
1415}
1416
1420 bool PreferFalse) const {
1421 assert(MI.getOpcode() == RISCV::PseudoCCMOVGPR &&
1422 "Unknown select instruction");
1423 if (!STI.hasShortForwardBranchOpt())
1424 return nullptr;
1425
1426 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1428 canFoldAsPredicatedOp(MI.getOperand(5).getReg(), MRI, this);
1429 bool Invert = !DefMI;
1430 if (!DefMI)
1431 DefMI = canFoldAsPredicatedOp(MI.getOperand(4).getReg(), MRI, this);
1432 if (!DefMI)
1433 return nullptr;
1434
1435 // Find new register class to use.
1436 MachineOperand FalseReg = MI.getOperand(Invert ? 5 : 4);
1437 Register DestReg = MI.getOperand(0).getReg();
1438 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1439 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1440 return nullptr;
1441
1442 unsigned PredOpc = getPredicatedOpcode(DefMI->getOpcode());
1443 assert(PredOpc != RISCV::INSTRUCTION_LIST_END && "Unexpected opcode!");
1444
1445 // Create a new predicated version of DefMI.
1446 MachineInstrBuilder NewMI =
1447 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(PredOpc), DestReg);
1448
1449 // Copy the condition portion.
1450 NewMI.add(MI.getOperand(1));
1451 NewMI.add(MI.getOperand(2));
1452
1453 // Add condition code, inverting if necessary.
1454 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
1455 if (Invert)
1457 NewMI.addImm(CC);
1458
1459 // Copy the false register.
1460 NewMI.add(FalseReg);
1461
1462 // Copy all the DefMI operands.
1463 const MCInstrDesc &DefDesc = DefMI->getDesc();
1464 for (unsigned i = 1, e = DefDesc.getNumOperands(); i != e; ++i)
1465 NewMI.add(DefMI->getOperand(i));
1466
1467 // Update SeenMIs set: register newly created MI and erase removed DefMI.
1468 SeenMIs.insert(NewMI);
1469 SeenMIs.erase(DefMI);
1470
1471 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1472 // DefMI would be invalid when tranferred inside the loop. Checking for a
1473 // loop is expensive, but at least remove kill flags if they are in different
1474 // BBs.
1475 if (DefMI->getParent() != MI.getParent())
1476 NewMI->clearKillInfo();
1477
1478 // The caller will erase MI, but not DefMI.
1480 return NewMI;
1481}
1482
1484 if (MI.isMetaInstruction())
1485 return 0;
1486
1487 unsigned Opcode = MI.getOpcode();
1488
1489 if (Opcode == TargetOpcode::INLINEASM ||
1490 Opcode == TargetOpcode::INLINEASM_BR) {
1491 const MachineFunction &MF = *MI.getParent()->getParent();
1492 const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
1493 return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
1494 *TM.getMCAsmInfo());
1495 }
1496
1497 if (!MI.memoperands_empty()) {
1498 MachineMemOperand *MMO = *(MI.memoperands_begin());
1499 const MachineFunction &MF = *MI.getParent()->getParent();
1500 const auto &ST = MF.getSubtarget<RISCVSubtarget>();
1501 if (ST.hasStdExtZihintntl() && MMO->isNonTemporal()) {
1502 if (ST.hasStdExtCOrZca() && ST.enableRVCHintInstrs()) {
1503 if (isCompressibleInst(MI, STI))
1504 return 4; // c.ntl.all + c.load/c.store
1505 return 6; // c.ntl.all + load/store
1506 }
1507 return 8; // ntl.all + load/store
1508 }
1509 }
1510
1511 if (Opcode == TargetOpcode::BUNDLE)
1512 return getInstBundleLength(MI);
1513
1514 if (MI.getParent() && MI.getParent()->getParent()) {
1515 if (isCompressibleInst(MI, STI))
1516 return 2;
1517 }
1518
1519 switch (Opcode) {
1520 case TargetOpcode::STACKMAP:
1521 // The upper bound for a stackmap intrinsic is the full length of its shadow
1523 case TargetOpcode::PATCHPOINT:
1524 // The size of the patchpoint intrinsic is the number of bytes requested
1526 case TargetOpcode::STATEPOINT:
1527 // The size of the statepoint intrinsic is the number of bytes requested
1529 default:
1530 return get(Opcode).getSize();
1531 }
1532}
1533
1534unsigned RISCVInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
1535 unsigned Size = 0;
1537 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
1538 while (++I != E && I->isInsideBundle()) {
1539 assert(!I->isBundle() && "No nested bundle!");
1541 }
1542 return Size;
1543}
1544
1546 const unsigned Opcode = MI.getOpcode();
1547 switch (Opcode) {
1548 default:
1549 break;
1550 case RISCV::FSGNJ_D:
1551 case RISCV::FSGNJ_S:
1552 case RISCV::FSGNJ_H:
1553 case RISCV::FSGNJ_D_INX:
1554 case RISCV::FSGNJ_D_IN32X:
1555 case RISCV::FSGNJ_S_INX:
1556 case RISCV::FSGNJ_H_INX:
1557 // The canonical floating-point move is fsgnj rd, rs, rs.
1558 return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
1559 MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
1560 case RISCV::ADDI:
1561 case RISCV::ORI:
1562 case RISCV::XORI:
1563 return (MI.getOperand(1).isReg() &&
1564 MI.getOperand(1).getReg() == RISCV::X0) ||
1565 (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
1566 }
1567 return MI.isAsCheapAsAMove();
1568}
1569
1570std::optional<DestSourcePair>
1572 if (MI.isMoveReg())
1573 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1574 switch (MI.getOpcode()) {
1575 default:
1576 break;
1577 case RISCV::ADDI:
1578 // Operand 1 can be a frameindex but callers expect registers
1579 if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
1580 MI.getOperand(2).getImm() == 0)
1581 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1582 break;
1583 case RISCV::FSGNJ_D:
1584 case RISCV::FSGNJ_S:
1585 case RISCV::FSGNJ_H:
1586 case RISCV::FSGNJ_D_INX:
1587 case RISCV::FSGNJ_D_IN32X:
1588 case RISCV::FSGNJ_S_INX:
1589 case RISCV::FSGNJ_H_INX:
1590 // The canonical floating-point move is fsgnj rd, rs, rs.
1591 if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
1592 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
1593 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1594 break;
1595 }
1596 return std::nullopt;
1597}
1598
1600 if (ForceMachineCombinerStrategy.getNumOccurrences() == 0) {
1601 // The option is unused. Choose Local strategy only for in-order cores. When
1602 // scheduling model is unspecified, use MinInstrCount strategy as more
1603 // generic one.
1604 const auto &SchedModel = STI.getSchedModel();
1605 return (!SchedModel.hasInstrSchedModel() || SchedModel.isOutOfOrder())
1608 }
1609 // The strategy was forced by the option.
1611}
1612
1615 SmallVectorImpl<MachineInstr *> &InsInstrs) const {
1616 int16_t FrmOpIdx =
1617 RISCV::getNamedOperandIdx(Root.getOpcode(), RISCV::OpName::frm);
1618 if (FrmOpIdx < 0) {
1619 assert(all_of(InsInstrs,
1620 [](MachineInstr *MI) {
1621 return RISCV::getNamedOperandIdx(MI->getOpcode(),
1622 RISCV::OpName::frm) < 0;
1623 }) &&
1624 "New instructions require FRM whereas the old one does not have it");
1625 return;
1626 }
1627
1628 const MachineOperand &FRM = Root.getOperand(FrmOpIdx);
1629 MachineFunction &MF = *Root.getMF();
1630
1631 for (auto *NewMI : InsInstrs) {
1632 assert(static_cast<unsigned>(RISCV::getNamedOperandIdx(
1633 NewMI->getOpcode(), RISCV::OpName::frm)) ==
1634 NewMI->getNumOperands() &&
1635 "Instruction has unexpected number of operands");
1636 MachineInstrBuilder MIB(MF, NewMI);
1637 MIB.add(FRM);
1638 if (FRM.getImm() == RISCVFPRndMode::DYN)
1639 MIB.addUse(RISCV::FRM, RegState::Implicit);
1640 }
1641}
1642
1643static bool isFADD(unsigned Opc) {
1644 switch (Opc) {
1645 default:
1646 return false;
1647 case RISCV::FADD_H:
1648 case RISCV::FADD_S:
1649 case RISCV::FADD_D:
1650 return true;
1651 }
1652}
1653
1654static bool isFSUB(unsigned Opc) {
1655 switch (Opc) {
1656 default:
1657 return false;
1658 case RISCV::FSUB_H:
1659 case RISCV::FSUB_S:
1660 case RISCV::FSUB_D:
1661 return true;
1662 }
1663}
1664
1665static bool isFMUL(unsigned Opc) {
1666 switch (Opc) {
1667 default:
1668 return false;
1669 case RISCV::FMUL_H:
1670 case RISCV::FMUL_S:
1671 case RISCV::FMUL_D:
1672 return true;
1673 }
1674}
1675
1677 bool &Commuted) const {
1678 if (!TargetInstrInfo::hasReassociableSibling(Inst, Commuted))
1679 return false;
1680
1681 const MachineRegisterInfo &MRI = Inst.getMF()->getRegInfo();
1682 unsigned OperandIdx = Commuted ? 2 : 1;
1683 const MachineInstr &Sibling =
1684 *MRI.getVRegDef(Inst.getOperand(OperandIdx).getReg());
1685
1686 int16_t InstFrmOpIdx =
1687 RISCV::getNamedOperandIdx(Inst.getOpcode(), RISCV::OpName::frm);
1688 int16_t SiblingFrmOpIdx =
1689 RISCV::getNamedOperandIdx(Sibling.getOpcode(), RISCV::OpName::frm);
1690
1691 return (InstFrmOpIdx < 0 && SiblingFrmOpIdx < 0) ||
1692 RISCV::hasEqualFRM(Inst, Sibling);
1693}
1694
1696 bool Invert) const {
1697 unsigned Opc = Inst.getOpcode();
1698 if (Invert) {
1699 auto InverseOpcode = getInverseOpcode(Opc);
1700 if (!InverseOpcode)
1701 return false;
1702 Opc = *InverseOpcode;
1703 }
1704
1705 if (isFADD(Opc) || isFMUL(Opc))
1708
1709 switch (Opc) {
1710 default:
1711 return false;
1712 case RISCV::ADD:
1713 case RISCV::ADDW:
1714 case RISCV::AND:
1715 case RISCV::OR:
1716 case RISCV::XOR:
1717 // From RISC-V ISA spec, if both the high and low bits of the same product
1718 // are required, then the recommended code sequence is:
1719 //
1720 // MULH[[S]U] rdh, rs1, rs2
1721 // MUL rdl, rs1, rs2
1722 // (source register specifiers must be in same order and rdh cannot be the
1723 // same as rs1 or rs2)
1724 //
1725 // Microarchitectures can then fuse these into a single multiply operation
1726 // instead of performing two separate multiplies.
1727 // MachineCombiner may reassociate MUL operands and lose the fusion
1728 // opportunity.
1729 case RISCV::MUL:
1730 case RISCV::MULW:
1731 case RISCV::MIN:
1732 case RISCV::MINU:
1733 case RISCV::MAX:
1734 case RISCV::MAXU:
1735 case RISCV::FMIN_H:
1736 case RISCV::FMIN_S:
1737 case RISCV::FMIN_D:
1738 case RISCV::FMAX_H:
1739 case RISCV::FMAX_S:
1740 case RISCV::FMAX_D:
1741 return true;
1742 }
1743
1744 return false;
1745}
1746
1747std::optional<unsigned>
1748RISCVInstrInfo::getInverseOpcode(unsigned Opcode) const {
1749 switch (Opcode) {
1750 default:
1751 return std::nullopt;
1752 case RISCV::FADD_H:
1753 return RISCV::FSUB_H;
1754 case RISCV::FADD_S:
1755 return RISCV::FSUB_S;
1756 case RISCV::FADD_D:
1757 return RISCV::FSUB_D;
1758 case RISCV::FSUB_H:
1759 return RISCV::FADD_H;
1760 case RISCV::FSUB_S:
1761 return RISCV::FADD_S;
1762 case RISCV::FSUB_D:
1763 return RISCV::FADD_D;
1764 case RISCV::ADD:
1765 return RISCV::SUB;
1766 case RISCV::SUB:
1767 return RISCV::ADD;
1768 case RISCV::ADDW:
1769 return RISCV::SUBW;
1770 case RISCV::SUBW:
1771 return RISCV::ADDW;
1772 }
1773}
1774
1776 const MachineOperand &MO,
1777 bool DoRegPressureReduce) {
1778 if (!MO.isReg() || !MO.getReg().isVirtual())
1779 return false;
1780 const MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
1781 MachineInstr *MI = MRI.getVRegDef(MO.getReg());
1782 if (!MI || !isFMUL(MI->getOpcode()))
1783 return false;
1784
1787 return false;
1788
1789 // Try combining even if fmul has more than one use as it eliminates
1790 // dependency between fadd(fsub) and fmul. However, it can extend liveranges
1791 // for fmul operands, so reject the transformation in register pressure
1792 // reduction mode.
1793 if (DoRegPressureReduce && !MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
1794 return false;
1795
1796 // Do not combine instructions from different basic blocks.
1797 if (Root.getParent() != MI->getParent())
1798 return false;
1799 return RISCV::hasEqualFRM(Root, *MI);
1800}
1801
1802static bool
1805 bool DoRegPressureReduce) {
1806 unsigned Opc = Root.getOpcode();
1807 bool IsFAdd = isFADD(Opc);
1808 if (!IsFAdd && !isFSUB(Opc))
1809 return false;
1810 bool Added = false;
1811 if (canCombineFPFusedMultiply(Root, Root.getOperand(1),
1812 DoRegPressureReduce)) {
1815 Added = true;
1816 }
1817 if (canCombineFPFusedMultiply(Root, Root.getOperand(2),
1818 DoRegPressureReduce)) {
1821 Added = true;
1822 }
1823 return Added;
1824}
1825
1826static bool getFPPatterns(MachineInstr &Root,
1828 bool DoRegPressureReduce) {
1829 return getFPFusedMultiplyPatterns(Root, Patterns, DoRegPressureReduce);
1830}
1831
1834 bool DoRegPressureReduce) const {
1835
1836 if (getFPPatterns(Root, Patterns, DoRegPressureReduce))
1837 return true;
1838
1839 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
1840 DoRegPressureReduce);
1841}
1842
1843static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc,
1845 switch (RootOpc) {
1846 default:
1847 llvm_unreachable("Unexpected opcode");
1848 case RISCV::FADD_H:
1849 return RISCV::FMADD_H;
1850 case RISCV::FADD_S:
1851 return RISCV::FMADD_S;
1852 case RISCV::FADD_D:
1853 return RISCV::FMADD_D;
1854 case RISCV::FSUB_H:
1855 return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_H
1856 : RISCV::FNMSUB_H;
1857 case RISCV::FSUB_S:
1858 return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_S
1859 : RISCV::FNMSUB_S;
1860 case RISCV::FSUB_D:
1861 return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_D
1862 : RISCV::FNMSUB_D;
1863 }
1864}
1865
1867 switch (Pattern) {
1868 default:
1869 llvm_unreachable("Unexpected pattern");
1872 return 2;
1875 return 1;
1876 }
1877}
1878
1883 MachineFunction *MF = Root.getMF();
1886
1887 MachineOperand &Mul1 = Prev.getOperand(1);
1888 MachineOperand &Mul2 = Prev.getOperand(2);
1889 MachineOperand &Dst = Root.getOperand(0);
1891
1892 Register DstReg = Dst.getReg();
1893 unsigned FusedOpc = getFPFusedMultiplyOpcode(Root.getOpcode(), Pattern);
1894 uint32_t IntersectedFlags = Root.getFlags() & Prev.getFlags();
1895 DebugLoc MergedLoc =
1897
1898 bool Mul1IsKill = Mul1.isKill();
1899 bool Mul2IsKill = Mul2.isKill();
1900 bool AddendIsKill = Addend.isKill();
1901
1902 // We need to clear kill flags since we may be extending the live range past
1903 // a kill. If the mul had kill flags, we can preserve those since we know
1904 // where the previous range stopped.
1905 MRI.clearKillFlags(Mul1.getReg());
1906 MRI.clearKillFlags(Mul2.getReg());
1907
1909 BuildMI(*MF, MergedLoc, TII->get(FusedOpc), DstReg)
1910 .addReg(Mul1.getReg(), getKillRegState(Mul1IsKill))
1911 .addReg(Mul2.getReg(), getKillRegState(Mul2IsKill))
1912 .addReg(Addend.getReg(), getKillRegState(AddendIsKill))
1913 .setMIFlags(IntersectedFlags);
1914
1915 InsInstrs.push_back(MIB);
1916 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg()))
1917 DelInstrs.push_back(&Prev);
1918 DelInstrs.push_back(&Root);
1919}
1920
1925 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
1927 switch (Pattern) {
1928 default:
1930 DelInstrs, InstrIdxForVirtReg);
1931 return;
1934 MachineInstr &Prev = *MRI.getVRegDef(Root.getOperand(1).getReg());
1935 combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs);
1936 return;
1937 }
1940 MachineInstr &Prev = *MRI.getVRegDef(Root.getOperand(2).getReg());
1941 combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs);
1942 return;
1943 }
1944 }
1945}
1946
1948 StringRef &ErrInfo) const {
1949 MCInstrDesc const &Desc = MI.getDesc();
1950
1951 for (const auto &[Index, Operand] : enumerate(Desc.operands())) {
1952 unsigned OpType = Operand.OperandType;
1953 if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
1955 const MachineOperand &MO = MI.getOperand(Index);
1956 if (MO.isImm()) {
1957 int64_t Imm = MO.getImm();
1958 bool Ok;
1959 switch (OpType) {
1960 default:
1961 llvm_unreachable("Unexpected operand type");
1962
1963 // clang-format off
1964#define CASE_OPERAND_UIMM(NUM) \
1965 case RISCVOp::OPERAND_UIMM##NUM: \
1966 Ok = isUInt<NUM>(Imm); \
1967 break;
1978 // clang-format on
1980 Ok = isShiftedUInt<1, 1>(Imm);
1981 break;
1983 Ok = isShiftedUInt<5, 2>(Imm);
1984 break;
1986 Ok = isShiftedUInt<6, 2>(Imm);
1987 break;
1989 Ok = isShiftedUInt<5, 3>(Imm);
1990 break;
1992 Ok = isUInt<8>(Imm) && Imm >= 32;
1993 break;
1995 Ok = isShiftedUInt<6, 3>(Imm);
1996 break;
1998 Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0);
1999 break;
2001 Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0);
2002 break;
2004 Ok = Imm == 0;
2005 break;
2007 Ok = isInt<5>(Imm);
2008 break;
2010 Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
2011 break;
2013 Ok = isInt<6>(Imm);
2014 break;
2016 Ok = Imm != 0 && isInt<6>(Imm);
2017 break;
2019 Ok = isUInt<10>(Imm);
2020 break;
2022 Ok = isUInt<11>(Imm);
2023 break;
2025 Ok = isInt<12>(Imm);
2026 break;
2028 Ok = isShiftedInt<7, 5>(Imm);
2029 break;
2031 Ok = STI.is64Bit() ? isUInt<6>(Imm) : isUInt<5>(Imm);
2032 break;
2034 Ok = STI.is64Bit() ? isUInt<6>(Imm) : isUInt<5>(Imm);
2035 Ok = Ok && Imm != 0;
2036 break;
2038 Ok = (isUInt<5>(Imm) && Imm != 0) ||
2039 (Imm >= 0xfffe0 && Imm <= 0xfffff);
2040 break;
2042 Ok = Imm >= 0 && Imm <= 10;
2043 break;
2045 Ok = Imm >= 0 && Imm <= 7;
2046 break;
2048 Ok = Imm >= 1 && Imm <= 10;
2049 break;
2051 Ok = Imm >= 2 && Imm <= 14;
2052 break;
2053 }
2054 if (!Ok) {
2055 ErrInfo = "Invalid immediate";
2056 return false;
2057 }
2058 }
2059 }
2060 }
2061
2062 const uint64_t TSFlags = Desc.TSFlags;
2063 if (RISCVII::hasVLOp(TSFlags)) {
2064 const MachineOperand &Op = MI.getOperand(RISCVII::getVLOpNum(Desc));
2065 if (!Op.isImm() && !Op.isReg()) {
2066 ErrInfo = "Invalid operand type for VL operand";
2067 return false;
2068 }
2069 if (Op.isReg() && Op.getReg() != RISCV::NoRegister) {
2070 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2071 auto *RC = MRI.getRegClass(Op.getReg());
2072 if (!RISCV::GPRRegClass.hasSubClassEq(RC)) {
2073 ErrInfo = "Invalid register class for VL operand";
2074 return false;
2075 }
2076 }
2077 if (!RISCVII::hasSEWOp(TSFlags)) {
2078 ErrInfo = "VL operand w/o SEW operand?";
2079 return false;
2080 }
2081 }
2082 if (RISCVII::hasSEWOp(TSFlags)) {
2083 unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
2084 if (!MI.getOperand(OpIdx).isImm()) {
2085 ErrInfo = "SEW value expected to be an immediate";
2086 return false;
2087 }
2088 uint64_t Log2SEW = MI.getOperand(OpIdx).getImm();
2089 if (Log2SEW > 31) {
2090 ErrInfo = "Unexpected SEW value";
2091 return false;
2092 }
2093 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
2094 if (!RISCVVType::isValidSEW(SEW)) {
2095 ErrInfo = "Unexpected SEW value";
2096 return false;
2097 }
2098 }
2099 if (RISCVII::hasVecPolicyOp(TSFlags)) {
2100 unsigned OpIdx = RISCVII::getVecPolicyOpNum(Desc);
2101 if (!MI.getOperand(OpIdx).isImm()) {
2102 ErrInfo = "Policy operand expected to be an immediate";
2103 return false;
2104 }
2105 uint64_t Policy = MI.getOperand(OpIdx).getImm();
2107 ErrInfo = "Invalid Policy Value";
2108 return false;
2109 }
2110 if (!RISCVII::hasVLOp(TSFlags)) {
2111 ErrInfo = "policy operand w/o VL operand?";
2112 return false;
2113 }
2114
2115 // VecPolicy operands can only exist on instructions with passthru/merge
2116 // arguments. Note that not all arguments with passthru have vec policy
2117 // operands- some instructions have implicit policies.
2118 unsigned UseOpIdx;
2119 if (!MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
2120 ErrInfo = "policy operand w/o tied operand?";
2121 return false;
2122 }
2123 }
2124
2125 return true;
2126}
2127
2129 const MachineInstr &AddrI,
2130 ExtAddrMode &AM) const {
2131 switch (MemI.getOpcode()) {
2132 default:
2133 return false;
2134 case RISCV::LB:
2135 case RISCV::LBU:
2136 case RISCV::LH:
2137 case RISCV::LHU:
2138 case RISCV::LW:
2139 case RISCV::LWU:
2140 case RISCV::LD:
2141 case RISCV::FLH:
2142 case RISCV::FLW:
2143 case RISCV::FLD:
2144 case RISCV::SB:
2145 case RISCV::SH:
2146 case RISCV::SW:
2147 case RISCV::SD:
2148 case RISCV::FSH:
2149 case RISCV::FSW:
2150 case RISCV::FSD:
2151 break;
2152 }
2153
2154 if (MemI.getOperand(0).getReg() == Reg)
2155 return false;
2156
2157 if (AddrI.getOpcode() != RISCV::ADDI || !AddrI.getOperand(1).isReg() ||
2158 !AddrI.getOperand(2).isImm())
2159 return false;
2160
2161 int64_t OldOffset = MemI.getOperand(2).getImm();
2162 int64_t Disp = AddrI.getOperand(2).getImm();
2163 int64_t NewOffset = OldOffset + Disp;
2164 if (!STI.is64Bit())
2165 NewOffset = SignExtend64<32>(NewOffset);
2166
2167 if (!isInt<12>(NewOffset))
2168 return false;
2169
2170 AM.BaseReg = AddrI.getOperand(1).getReg();
2171 AM.ScaledReg = 0;
2172 AM.Scale = 0;
2173 AM.Displacement = NewOffset;
2175 return true;
2176}
2177
2179 const ExtAddrMode &AM) const {
2180
2181 const DebugLoc &DL = MemI.getDebugLoc();
2182 MachineBasicBlock &MBB = *MemI.getParent();
2183
2184 assert(AM.ScaledReg == 0 && AM.Scale == 0 &&
2185 "Addressing mode not supported for folding");
2186
2187 return BuildMI(MBB, MemI, DL, get(MemI.getOpcode()))
2188 .addReg(MemI.getOperand(0).getReg(),
2189 MemI.mayLoad() ? RegState::Define : 0)
2190 .addReg(AM.BaseReg)
2191 .addImm(AM.Displacement)
2192 .setMemRefs(MemI.memoperands())
2193 .setMIFlags(MemI.getFlags());
2194}
2195
2198 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
2199 const TargetRegisterInfo *TRI) const {
2200 if (!LdSt.mayLoadOrStore())
2201 return false;
2202
2203 // Conservatively, only handle scalar loads/stores for now.
2204 switch (LdSt.getOpcode()) {
2205 case RISCV::LB:
2206 case RISCV::LBU:
2207 case RISCV::SB:
2208 case RISCV::LH:
2209 case RISCV::LHU:
2210 case RISCV::FLH:
2211 case RISCV::SH:
2212 case RISCV::FSH:
2213 case RISCV::LW:
2214 case RISCV::LWU:
2215 case RISCV::FLW:
2216 case RISCV::SW:
2217 case RISCV::FSW:
2218 case RISCV::LD:
2219 case RISCV::FLD:
2220 case RISCV::SD:
2221 case RISCV::FSD:
2222 break;
2223 default:
2224 return false;
2225 }
2226 const MachineOperand *BaseOp;
2227 OffsetIsScalable = false;
2228 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
2229 return false;
2230 BaseOps.push_back(BaseOp);
2231 return true;
2232}
2233
2234// TODO: This was copied from SIInstrInfo. Could it be lifted to a common
2235// helper?
2238 const MachineInstr &MI2,
2240 // Only examine the first "base" operand of each instruction, on the
2241 // assumption that it represents the real base address of the memory access.
2242 // Other operands are typically offsets or indices from this base address.
2243 if (BaseOps1.front()->isIdenticalTo(*BaseOps2.front()))
2244 return true;
2245
2246 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
2247 return false;
2248
2249 auto MO1 = *MI1.memoperands_begin();
2250 auto MO2 = *MI2.memoperands_begin();
2251 if (MO1->getAddrSpace() != MO2->getAddrSpace())
2252 return false;
2253
2254 auto Base1 = MO1->getValue();
2255 auto Base2 = MO2->getValue();
2256 if (!Base1 || !Base2)
2257 return false;
2258 Base1 = getUnderlyingObject(Base1);
2259 Base2 = getUnderlyingObject(Base2);
2260
2261 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2))
2262 return false;
2263
2264 return Base1 == Base2;
2265}
2266
2268 ArrayRef<const MachineOperand *> BaseOps1, int64_t Offset1,
2269 bool OffsetIsScalable1, ArrayRef<const MachineOperand *> BaseOps2,
2270 int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize,
2271 unsigned NumBytes) const {
2272 // If the mem ops (to be clustered) do not have the same base ptr, then they
2273 // should not be clustered
2274 if (!BaseOps1.empty() && !BaseOps2.empty()) {
2275 const MachineInstr &FirstLdSt = *BaseOps1.front()->getParent();
2276 const MachineInstr &SecondLdSt = *BaseOps2.front()->getParent();
2277 if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOps1, SecondLdSt, BaseOps2))
2278 return false;
2279 } else if (!BaseOps1.empty() || !BaseOps2.empty()) {
2280 // If only one base op is empty, they do not have the same base ptr
2281 return false;
2282 }
2283
2284 unsigned CacheLineSize =
2285 BaseOps1.front()->getParent()->getMF()->getSubtarget().getCacheLineSize();
2286 // Assume a cache line size of 64 bytes if no size is set in RISCVSubtarget.
2288 // Cluster if the memory operations are on the same or a neighbouring cache
2289 // line, but limit the maximum ClusterSize to avoid creating too much
2290 // additional register pressure.
2291 return ClusterSize <= 4 && std::abs(Offset1 - Offset2) < CacheLineSize;
2292}
2293
2294// Set BaseReg (the base register operand), Offset (the byte offset being
2295// accessed) and the access Width of the passed instruction that reads/writes
2296// memory. Returns false if the instruction does not read/write memory or the
2297// BaseReg/Offset/Width can't be determined. Is not guaranteed to always
2298// recognise base operands and offsets in all cases.
2299// TODO: Add an IsScalable bool ref argument (like the equivalent AArch64
2300// function) and set it as appropriate.
2302 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
2303 LocationSize &Width, const TargetRegisterInfo *TRI) const {
2304 if (!LdSt.mayLoadOrStore())
2305 return false;
2306
2307 // Here we assume the standard RISC-V ISA, which uses a base+offset
2308 // addressing mode. You'll need to relax these conditions to support custom
2309 // load/store instructions.
2310 if (LdSt.getNumExplicitOperands() != 3)
2311 return false;
2312 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
2313 !LdSt.getOperand(2).isImm())
2314 return false;
2315
2316 if (!LdSt.hasOneMemOperand())
2317 return false;
2318
2319 Width = (*LdSt.memoperands_begin())->getSize();
2320 BaseReg = &LdSt.getOperand(1);
2321 Offset = LdSt.getOperand(2).getImm();
2322 return true;
2323}
2324
2326 const MachineInstr &MIa, const MachineInstr &MIb) const {
2327 assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
2328 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
2329
2332 return false;
2333
2334 // Retrieve the base register, offset from the base register and width. Width
2335 // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
2336 // base registers are identical, and the offset of a lower memory access +
2337 // the width doesn't overlap the offset of a higher memory access,
2338 // then the memory accesses are different.
2340 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
2341 int64_t OffsetA = 0, OffsetB = 0;
2342 LocationSize WidthA = 0, WidthB = 0;
2343 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
2344 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
2345 if (BaseOpA->isIdenticalTo(*BaseOpB)) {
2346 int LowOffset = std::min(OffsetA, OffsetB);
2347 int HighOffset = std::max(OffsetA, OffsetB);
2348 LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2349 if (LowWidth.hasValue() &&
2350 LowOffset + (int)LowWidth.getValue() <= HighOffset)
2351 return true;
2352 }
2353 }
2354 return false;
2355}
2356
2357std::pair<unsigned, unsigned>
2359 const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
2360 return std::make_pair(TF & Mask, TF & ~Mask);
2361}
2362
2365 using namespace RISCVII;
2366 static const std::pair<unsigned, const char *> TargetFlags[] = {
2367 {MO_CALL, "riscv-call"},
2368 {MO_LO, "riscv-lo"},
2369 {MO_HI, "riscv-hi"},
2370 {MO_PCREL_LO, "riscv-pcrel-lo"},
2371 {MO_PCREL_HI, "riscv-pcrel-hi"},
2372 {MO_GOT_HI, "riscv-got-hi"},
2373 {MO_TPREL_LO, "riscv-tprel-lo"},
2374 {MO_TPREL_HI, "riscv-tprel-hi"},
2375 {MO_TPREL_ADD, "riscv-tprel-add"},
2376 {MO_TLS_GOT_HI, "riscv-tls-got-hi"},
2377 {MO_TLS_GD_HI, "riscv-tls-gd-hi"},
2378 {MO_TLSDESC_HI, "riscv-tlsdesc-hi"},
2379 {MO_TLSDESC_LOAD_LO, "riscv-tlsdesc-load-lo"},
2380 {MO_TLSDESC_ADD_LO, "riscv-tlsdesc-add-lo"},
2381 {MO_TLSDESC_CALL, "riscv-tlsdesc-call"}};
2382 return ArrayRef(TargetFlags);
2383}
2385 MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
2386 const Function &F = MF.getFunction();
2387
2388 // Can F be deduplicated by the linker? If it can, don't outline from it.
2389 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
2390 return false;
2391
2392 // Don't outline from functions with section markings; the program could
2393 // expect that all the code is in the named section.
2394 if (F.hasSection())
2395 return false;
2396
2397 // It's safe to outline from MF.
2398 return true;
2399}
2400
2402 unsigned &Flags) const {
2403 // More accurate safety checking is done in getOutliningCandidateInfo.
2405}
2406
2407// Enum values indicating how an outlined call should be constructed.
2411
2413 MachineFunction &MF) const {
2414 return MF.getFunction().hasMinSize();
2415}
2416
2417std::optional<outliner::OutlinedFunction>
2419 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
2420
2421 // First we need to filter out candidates where the X5 register (IE t0) can't
2422 // be used to setup the function call.
2423 auto CannotInsertCall = [](outliner::Candidate &C) {
2424 const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
2425 return !C.isAvailableAcrossAndOutOfSeq(RISCV::X5, *TRI);
2426 };
2427
2428 llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall);
2429
2430 // If the sequence doesn't have enough candidates left, then we're done.
2431 if (RepeatedSequenceLocs.size() < 2)
2432 return std::nullopt;
2433
2434 unsigned SequenceSize = 0;
2435
2436 for (auto &MI : RepeatedSequenceLocs[0])
2437 SequenceSize += getInstSizeInBytes(MI);
2438
2439 // call t0, function = 8 bytes.
2440 unsigned CallOverhead = 8;
2441 for (auto &C : RepeatedSequenceLocs)
2442 C.setCallInfo(MachineOutlinerDefault, CallOverhead);
2443
2444 // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
2445 unsigned FrameOverhead = 4;
2446 if (RepeatedSequenceLocs[0]
2447 .getMF()
2448 ->getSubtarget<RISCVSubtarget>()
2449 .hasStdExtCOrZca())
2450 FrameOverhead = 2;
2451
2452 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
2453 FrameOverhead, MachineOutlinerDefault);
2454}
2455
2458 unsigned Flags) const {
2459 MachineInstr &MI = *MBBI;
2460 MachineBasicBlock *MBB = MI.getParent();
2461 const TargetRegisterInfo *TRI =
2463 const auto &F = MI.getMF()->getFunction();
2464
2465 // We can manually strip out CFI instructions later.
2466 if (MI.isCFIInstruction())
2467 // If current function has exception handling code, we can't outline &
2468 // strip these CFI instructions since it may break .eh_frame section
2469 // needed in unwinding.
2470 return F.needsUnwindTableEntry() ? outliner::InstrType::Illegal
2472
2473 // We need support for tail calls to outlined functions before return
2474 // statements can be allowed.
2475 if (MI.isReturn())
2477
2478 // Don't allow modifying the X5 register which we use for return addresses for
2479 // these outlined functions.
2480 if (MI.modifiesRegister(RISCV::X5, TRI) ||
2481 MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
2483
2484 // Make sure the operands don't reference something unsafe.
2485 for (const auto &MO : MI.operands()) {
2486
2487 // pcrel-hi and pcrel-lo can't put in separate sections, filter that out
2488 // if any possible.
2489 if (MO.getTargetFlags() == RISCVII::MO_PCREL_LO &&
2490 (MI.getMF()->getTarget().getFunctionSections() || F.hasComdat() ||
2491 F.hasSection()))
2493 }
2494
2496}
2497
2500 const outliner::OutlinedFunction &OF) const {
2501
2502 // Strip out any CFI instructions
2503 bool Changed = true;
2504 while (Changed) {
2505 Changed = false;
2506 auto I = MBB.begin();
2507 auto E = MBB.end();
2508 for (; I != E; ++I) {
2509 if (I->isCFIInstruction()) {
2510 I->removeFromParent();
2511 Changed = true;
2512 break;
2513 }
2514 }
2515 }
2516
2517 MBB.addLiveIn(RISCV::X5);
2518
2519 // Add in a return instruction to the end of the outlined frame.
2520 MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
2521 .addReg(RISCV::X0, RegState::Define)
2522 .addReg(RISCV::X5)
2523 .addImm(0));
2524}
2525
2529
2530 // Add in a call instruction to the outlined function at the given location.
2531 It = MBB.insert(It,
2532 BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)
2533 .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
2535 return It;
2536}
2537
2538std::optional<RegImmPair> RISCVInstrInfo::isAddImmediate(const MachineInstr &MI,
2539 Register Reg) const {
2540 // TODO: Handle cases where Reg is a super- or sub-register of the
2541 // destination register.
2542 const MachineOperand &Op0 = MI.getOperand(0);
2543 if (!Op0.isReg() || Reg != Op0.getReg())
2544 return std::nullopt;
2545
2546 // Don't consider ADDIW as a candidate because the caller may not be aware
2547 // of its sign extension behaviour.
2548 if (MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&
2549 MI.getOperand(2).isImm())
2550 return RegImmPair{MI.getOperand(1).getReg(), MI.getOperand(2).getImm()};
2551
2552 return std::nullopt;
2553}
2554
2555// MIR printer helper function to annotate Operands with a comment.
2557 const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
2558 const TargetRegisterInfo *TRI) const {
2559 // Print a generic comment for this operand if there is one.
2560 std::string GenericComment =
2562 if (!GenericComment.empty())
2563 return GenericComment;
2564
2565 // If not, we must have an immediate operand.
2566 if (!Op.isImm())
2567 return std::string();
2568
2569 std::string Comment;
2570 raw_string_ostream OS(Comment);
2571
2572 uint64_t TSFlags = MI.getDesc().TSFlags;
2573
2574 // Print the full VType operand of vsetvli/vsetivli instructions, and the SEW
2575 // operand of vector codegen pseudos.
2576 if ((MI.getOpcode() == RISCV::VSETVLI || MI.getOpcode() == RISCV::VSETIVLI ||
2577 MI.getOpcode() == RISCV::PseudoVSETVLI ||
2578 MI.getOpcode() == RISCV::PseudoVSETIVLI ||
2579 MI.getOpcode() == RISCV::PseudoVSETVLIX0) &&
2580 OpIdx == 2) {
2581 unsigned Imm = MI.getOperand(OpIdx).getImm();
2583 } else if (RISCVII::hasSEWOp(TSFlags) &&
2584 OpIdx == RISCVII::getSEWOpNum(MI.getDesc())) {
2585 unsigned Log2SEW = MI.getOperand(OpIdx).getImm();
2586 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
2587 assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
2588 OS << "e" << SEW;
2589 } else if (RISCVII::hasVecPolicyOp(TSFlags) &&
2590 OpIdx == RISCVII::getVecPolicyOpNum(MI.getDesc())) {
2591 unsigned Policy = MI.getOperand(OpIdx).getImm();
2593 "Invalid Policy Value");
2594 OS << (Policy & RISCVII::TAIL_AGNOSTIC ? "ta" : "tu") << ", "
2595 << (Policy & RISCVII::MASK_AGNOSTIC ? "ma" : "mu");
2596 }
2597
2598 OS.flush();
2599 return Comment;
2600}
2601
2602// clang-format off
2603#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL) \
2604 RISCV::PseudoV##OP##_##TYPE##_##LMUL
2605
2606#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE) \
2607 CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1): \
2608 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2): \
2609 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4): \
2610 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)
2611
2612#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE) \
2613 CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2): \
2614 case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)
2615
2616#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE) \
2617 CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4): \
2618 case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)
2619
2620#define CASE_VFMA_OPCODE_LMULS(OP, TYPE) \
2621 CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8): \
2622 case CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
2623
2624#define CASE_VFMA_SPLATS(OP) \
2625 CASE_VFMA_OPCODE_LMULS_MF4(OP, VFPR16): \
2626 case CASE_VFMA_OPCODE_LMULS_MF2(OP, VFPR32): \
2627 case CASE_VFMA_OPCODE_LMULS_M1(OP, VFPR64)
2628// clang-format on
2629
2631 unsigned &SrcOpIdx1,
2632 unsigned &SrcOpIdx2) const {
2633 const MCInstrDesc &Desc = MI.getDesc();
2634 if (!Desc.isCommutable())
2635 return false;
2636
2637 switch (MI.getOpcode()) {
2638 case RISCV::TH_MVEQZ:
2639 case RISCV::TH_MVNEZ:
2640 // We can't commute operands if operand 2 (i.e., rs1 in
2641 // mveqz/mvnez rd,rs1,rs2) is the zero-register (as it is
2642 // not valid as the in/out-operand 1).
2643 if (MI.getOperand(2).getReg() == RISCV::X0)
2644 return false;
2645 // Operands 1 and 2 are commutable, if we switch the opcode.
2646 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
2647 case RISCV::TH_MULA:
2648 case RISCV::TH_MULAW:
2649 case RISCV::TH_MULAH:
2650 case RISCV::TH_MULS:
2651 case RISCV::TH_MULSW:
2652 case RISCV::TH_MULSH:
2653 // Operands 2 and 3 are commutable.
2654 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
2655 case RISCV::PseudoCCMOVGPRNoX0:
2656 case RISCV::PseudoCCMOVGPR:
2657 // Operands 4 and 5 are commutable.
2658 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 4, 5);
2659 case CASE_VFMA_SPLATS(FMADD):
2660 case CASE_VFMA_SPLATS(FMSUB):
2661 case CASE_VFMA_SPLATS(FMACC):
2662 case CASE_VFMA_SPLATS(FMSAC):
2665 case CASE_VFMA_SPLATS(FNMACC):
2666 case CASE_VFMA_SPLATS(FNMSAC):
2667 case CASE_VFMA_OPCODE_LMULS_MF4(FMACC, VV):
2668 case CASE_VFMA_OPCODE_LMULS_MF4(FMSAC, VV):
2669 case CASE_VFMA_OPCODE_LMULS_MF4(FNMACC, VV):
2670 case CASE_VFMA_OPCODE_LMULS_MF4(FNMSAC, VV):
2671 case CASE_VFMA_OPCODE_LMULS(MADD, VX):
2672 case CASE_VFMA_OPCODE_LMULS(NMSUB, VX):
2673 case CASE_VFMA_OPCODE_LMULS(MACC, VX):
2674 case CASE_VFMA_OPCODE_LMULS(NMSAC, VX):
2675 case CASE_VFMA_OPCODE_LMULS(MACC, VV):
2676 case CASE_VFMA_OPCODE_LMULS(NMSAC, VV): {
2677 // If the tail policy is undisturbed we can't commute.
2678 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));
2679 if ((MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 1) == 0)
2680 return false;
2681
2682 // For these instructions we can only swap operand 1 and operand 3 by
2683 // changing the opcode.
2684 unsigned CommutableOpIdx1 = 1;
2685 unsigned CommutableOpIdx2 = 3;
2686 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
2687 CommutableOpIdx2))
2688 return false;
2689 return true;
2690 }
2691 case CASE_VFMA_OPCODE_LMULS_MF4(FMADD, VV):
2695 case CASE_VFMA_OPCODE_LMULS(MADD, VV):
2696 case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): {
2697 // If the tail policy is undisturbed we can't commute.
2698 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));
2699 if ((MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 1) == 0)
2700 return false;
2701
2702 // For these instructions we have more freedom. We can commute with the
2703 // other multiplicand or with the addend/subtrahend/minuend.
2704
2705 // Any fixed operand must be from source 1, 2 or 3.
2706 if (SrcOpIdx1 != CommuteAnyOperandIndex && SrcOpIdx1 > 3)
2707 return false;
2708 if (SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx2 > 3)
2709 return false;
2710
2711 // It both ops are fixed one must be the tied source.
2712 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2713 SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx1 != 1 && SrcOpIdx2 != 1)
2714 return false;
2715
2716 // Look for two different register operands assumed to be commutable
2717 // regardless of the FMA opcode. The FMA opcode is adjusted later if
2718 // needed.
2719 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2720 SrcOpIdx2 == CommuteAnyOperandIndex) {
2721 // At least one of operands to be commuted is not specified and
2722 // this method is free to choose appropriate commutable operands.
2723 unsigned CommutableOpIdx1 = SrcOpIdx1;
2724 if (SrcOpIdx1 == SrcOpIdx2) {
2725 // Both of operands are not fixed. Set one of commutable
2726 // operands to the tied source.
2727 CommutableOpIdx1 = 1;
2728 } else if (SrcOpIdx1 == CommuteAnyOperandIndex) {
2729 // Only one of the operands is not fixed.
2730 CommutableOpIdx1 = SrcOpIdx2;
2731 }
2732
2733 // CommutableOpIdx1 is well defined now. Let's choose another commutable
2734 // operand and assign its index to CommutableOpIdx2.
2735 unsigned CommutableOpIdx2;
2736 if (CommutableOpIdx1 != 1) {
2737 // If we haven't already used the tied source, we must use it now.
2738 CommutableOpIdx2 = 1;
2739 } else {
2740 Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg();
2741
2742 // The commuted operands should have different registers.
2743 // Otherwise, the commute transformation does not change anything and
2744 // is useless. We use this as a hint to make our decision.
2745 if (Op1Reg != MI.getOperand(2).getReg())
2746 CommutableOpIdx2 = 2;
2747 else
2748 CommutableOpIdx2 = 3;
2749 }
2750
2751 // Assign the found pair of commutable indices to SrcOpIdx1 and
2752 // SrcOpIdx2 to return those values.
2753 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
2754 CommutableOpIdx2))
2755 return false;
2756 }
2757
2758 return true;
2759 }
2760 }
2761
2762 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2763}
2764
2765#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL) \
2766 case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \
2767 Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
2768 break;
2769
2770#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE) \
2771 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \
2772 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \
2773 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \
2774 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
2775
2776#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE) \
2777 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
2778 CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)
2779
2780#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE) \
2781 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
2782 CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)
2783
2784#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \
2785 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
2786 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
2787
2788#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \
2789 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16) \
2790 CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32) \
2791 CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64)
2792
2794 bool NewMI,
2795 unsigned OpIdx1,
2796 unsigned OpIdx2) const {
2797 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2798 if (NewMI)
2799 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2800 return MI;
2801 };
2802
2803 switch (MI.getOpcode()) {
2804 case RISCV::TH_MVEQZ:
2805 case RISCV::TH_MVNEZ: {
2806 auto &WorkingMI = cloneIfNew(MI);
2807 WorkingMI.setDesc(get(MI.getOpcode() == RISCV::TH_MVEQZ ? RISCV::TH_MVNEZ
2808 : RISCV::TH_MVEQZ));
2809 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
2810 OpIdx2);
2811 }
2812 case RISCV::PseudoCCMOVGPRNoX0:
2813 case RISCV::PseudoCCMOVGPR: {
2814 // CCMOV can be commuted by inverting the condition.
2815 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
2817 auto &WorkingMI = cloneIfNew(MI);
2818 WorkingMI.getOperand(3).setImm(CC);
2819 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI*/ false,
2820 OpIdx1, OpIdx2);
2821 }
2822 case CASE_VFMA_SPLATS(FMACC):
2823 case CASE_VFMA_SPLATS(FMADD):
2824 case CASE_VFMA_SPLATS(FMSAC):
2825 case CASE_VFMA_SPLATS(FMSUB):
2826 case CASE_VFMA_SPLATS(FNMACC):
2828 case CASE_VFMA_SPLATS(FNMSAC):
2830 case CASE_VFMA_OPCODE_LMULS_MF4(FMACC, VV):
2831 case CASE_VFMA_OPCODE_LMULS_MF4(FMSAC, VV):
2832 case CASE_VFMA_OPCODE_LMULS_MF4(FNMACC, VV):
2833 case CASE_VFMA_OPCODE_LMULS_MF4(FNMSAC, VV):
2834 case CASE_VFMA_OPCODE_LMULS(MADD, VX):
2835 case CASE_VFMA_OPCODE_LMULS(NMSUB, VX):
2836 case CASE_VFMA_OPCODE_LMULS(MACC, VX):
2837 case CASE_VFMA_OPCODE_LMULS(NMSAC, VX):
2838 case CASE_VFMA_OPCODE_LMULS(MACC, VV):
2839 case CASE_VFMA_OPCODE_LMULS(NMSAC, VV): {
2840 // It only make sense to toggle these between clobbering the
2841 // addend/subtrahend/minuend one of the multiplicands.
2842 assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
2843 assert((OpIdx1 == 3 || OpIdx2 == 3) && "Unexpected opcode index");
2844 unsigned Opc;
2845 switch (MI.getOpcode()) {
2846 default:
2847 llvm_unreachable("Unexpected opcode");
2848 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMACC, FMADD)
2849 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMADD, FMACC)
2856 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMACC, FMADD, VV)
2860 CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX)
2861 CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX)
2862 CASE_VFMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VX)
2863 CASE_VFMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VX)
2864 CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VV)
2865 CASE_VFMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VV)
2866 }
2867
2868 auto &WorkingMI = cloneIfNew(MI);
2869 WorkingMI.setDesc(get(Opc));
2870 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2871 OpIdx1, OpIdx2);
2872 }
2873 case CASE_VFMA_OPCODE_LMULS_MF4(FMADD, VV):
2877 case CASE_VFMA_OPCODE_LMULS(MADD, VV):
2878 case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): {
2879 assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
2880 // If one of the operands, is the addend we need to change opcode.
2881 // Otherwise we're just swapping 2 of the multiplicands.
2882 if (OpIdx1 == 3 || OpIdx2 == 3) {
2883 unsigned Opc;
2884 switch (MI.getOpcode()) {
2885 default:
2886 llvm_unreachable("Unexpected opcode");
2887 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FMADD, FMACC, VV)
2891 CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VV)
2892 CASE_VFMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VV)
2893 }
2894
2895 auto &WorkingMI = cloneIfNew(MI);
2896 WorkingMI.setDesc(get(Opc));
2897 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2898 OpIdx1, OpIdx2);
2899 }
2900 // Let the default code handle it.
2901 break;
2902 }
2903 }
2904
2905 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2906}
2907
2908#undef CASE_VFMA_CHANGE_OPCODE_SPLATS
2909#undef CASE_VFMA_CHANGE_OPCODE_LMULS
2910#undef CASE_VFMA_CHANGE_OPCODE_COMMON
2911#undef CASE_VFMA_SPLATS
2912#undef CASE_VFMA_OPCODE_LMULS
2913#undef CASE_VFMA_OPCODE_COMMON
2914
2915// clang-format off
2916#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL) \
2917 RISCV::PseudoV##OP##_##LMUL##_TIED
2918
2919#define CASE_WIDEOP_OPCODE_LMULS_MF4(OP) \
2920 CASE_WIDEOP_OPCODE_COMMON(OP, MF4): \
2921 case CASE_WIDEOP_OPCODE_COMMON(OP, MF2): \
2922 case CASE_WIDEOP_OPCODE_COMMON(OP, M1): \
2923 case CASE_WIDEOP_OPCODE_COMMON(OP, M2): \
2924 case CASE_WIDEOP_OPCODE_COMMON(OP, M4)
2925
2926#define CASE_WIDEOP_OPCODE_LMULS(OP) \
2927 CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \
2928 case CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
2929// clang-format on
2930
2931#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL) \
2932 case RISCV::PseudoV##OP##_##LMUL##_TIED: \
2933 NewOpc = RISCV::PseudoV##OP##_##LMUL; \
2934 break;
2935
2936#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) \
2937 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \
2938 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \
2939 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \
2940 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \
2941 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)
2942
2943#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP) \
2944 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \
2945 CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
2946
2948 LiveVariables *LV,
2949 LiveIntervals *LIS) const {
2951 switch (MI.getOpcode()) {
2952 default:
2953 return nullptr;
2954 case CASE_WIDEOP_OPCODE_LMULS_MF4(FWADD_WV):
2955 case CASE_WIDEOP_OPCODE_LMULS_MF4(FWSUB_WV): {
2956 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
2957 MI.getNumExplicitOperands() == 7 &&
2958 "Expect 7 explicit operands rd, rs2, rs1, rm, vl, sew, policy");
2959 // If the tail policy is undisturbed we can't convert.
2960 if ((MI.getOperand(RISCVII::getVecPolicyOpNum(MI.getDesc())).getImm() &
2961 1) == 0)
2962 return nullptr;
2963 // clang-format off
2964 unsigned NewOpc;
2965 switch (MI.getOpcode()) {
2966 default:
2967 llvm_unreachable("Unexpected opcode");
2970 }
2971 // clang-format on
2972
2973 MachineBasicBlock &MBB = *MI.getParent();
2974 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
2975 .add(MI.getOperand(0))
2976 .addReg(MI.getOperand(0).getReg(), RegState::Undef)
2977 .add(MI.getOperand(1))
2978 .add(MI.getOperand(2))
2979 .add(MI.getOperand(3))
2980 .add(MI.getOperand(4))
2981 .add(MI.getOperand(5))
2982 .add(MI.getOperand(6));
2983 break;
2984 }
2985 case CASE_WIDEOP_OPCODE_LMULS(WADD_WV):
2986 case CASE_WIDEOP_OPCODE_LMULS(WADDU_WV):
2987 case CASE_WIDEOP_OPCODE_LMULS(WSUB_WV):
2988 case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV): {
2989 // If the tail policy is undisturbed we can't convert.
2990 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
2991 MI.getNumExplicitOperands() == 6);
2992 if ((MI.getOperand(5).getImm() & 1) == 0)
2993 return nullptr;
2994
2995 // clang-format off
2996 unsigned NewOpc;
2997 switch (MI.getOpcode()) {
2998 default:
2999 llvm_unreachable("Unexpected opcode");
3004 }
3005 // clang-format on
3006
3007 MachineBasicBlock &MBB = *MI.getParent();
3008 MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
3009 .add(MI.getOperand(0))
3010 .addReg(MI.getOperand(0).getReg(), RegState::Undef)
3011 .add(MI.getOperand(1))
3012 .add(MI.getOperand(2))
3013 .add(MI.getOperand(3))
3014 .add(MI.getOperand(4))
3015 .add(MI.getOperand(5));
3016 break;
3017 }
3018 }
3019 MIB.copyImplicitOps(MI);
3020
3021 if (LV) {
3022 unsigned NumOps = MI.getNumOperands();
3023 for (unsigned I = 1; I < NumOps; ++I) {
3024 MachineOperand &Op = MI.getOperand(I);
3025 if (Op.isReg() && Op.isKill())
3026 LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
3027 }
3028 }
3029
3030 if (LIS) {
3032
3033 if (MI.getOperand(0).isEarlyClobber()) {
3034 // Use operand 1 was tied to early-clobber def operand 0, so its live
3035 // interval could have ended at an early-clobber slot. Now they are not
3036 // tied we need to update it to the normal register slot.
3037 LiveInterval &LI = LIS->getInterval(MI.getOperand(1).getReg());
3039 if (S->end == Idx.getRegSlot(true))
3040 S->end = Idx.getRegSlot();
3041 }
3042 }
3043
3044 return MIB;
3045}
3046
3047#undef CASE_WIDEOP_CHANGE_OPCODE_LMULS
3048#undef CASE_WIDEOP_CHANGE_OPCODE_COMMON
3049#undef CASE_WIDEOP_OPCODE_LMULS
3050#undef CASE_WIDEOP_OPCODE_COMMON
3051
3055 const DebugLoc &DL, Register DestReg,
3056 int64_t Amount,
3057 MachineInstr::MIFlag Flag) const {
3058 assert(Amount > 0 && "There is no need to get VLEN scaled value.");
3059 assert(Amount % 8 == 0 &&
3060 "Reserve the stack by the multiple of one vector size.");
3061
3063 assert(isInt<32>(Amount / 8) &&
3064 "Expect the number of vector registers within 32-bits.");
3065 uint32_t NumOfVReg = Amount / 8;
3066
3067 BuildMI(MBB, II, DL, get(RISCV::PseudoReadVLENB), DestReg).setMIFlag(Flag);
3068 if (llvm::has_single_bit<uint32_t>(NumOfVReg)) {
3069 uint32_t ShiftAmount = Log2_32(NumOfVReg);
3070 if (ShiftAmount == 0)
3071 return;
3072 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg)
3073 .addReg(DestReg, RegState::Kill)
3074 .addImm(ShiftAmount)
3075 .setMIFlag(Flag);
3076 } else if (STI.hasStdExtZba() &&
3077 ((NumOfVReg % 3 == 0 && isPowerOf2_64(NumOfVReg / 3)) ||
3078 (NumOfVReg % 5 == 0 && isPowerOf2_64(NumOfVReg / 5)) ||
3079 (NumOfVReg % 9 == 0 && isPowerOf2_64(NumOfVReg / 9)))) {
3080 // We can use Zba SHXADD+SLLI instructions for multiply in some cases.
3081 unsigned Opc;
3082 uint32_t ShiftAmount;
3083 if (NumOfVReg % 9 == 0) {
3084 Opc = RISCV::SH3ADD;
3085 ShiftAmount = Log2_64(NumOfVReg / 9);
3086 } else if (NumOfVReg % 5 == 0) {
3087 Opc = RISCV::SH2ADD;
3088 ShiftAmount = Log2_64(NumOfVReg / 5);
3089 } else if (NumOfVReg % 3 == 0) {
3090 Opc = RISCV::SH1ADD;
3091 ShiftAmount = Log2_64(NumOfVReg / 3);
3092 } else {
3093 llvm_unreachable("Unexpected number of vregs");
3094 }
3095 if (ShiftAmount)
3096 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg)
3097 .addReg(DestReg, RegState::Kill)
3098 .addImm(ShiftAmount)
3099 .setMIFlag(Flag);
3100 BuildMI(MBB, II, DL, get(Opc), DestReg)
3101 .addReg(DestReg, RegState::Kill)
3102 .addReg(DestReg)
3103 .setMIFlag(Flag);
3104 } else if (llvm::has_single_bit<uint32_t>(NumOfVReg - 1)) {
3105 Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
3106 uint32_t ShiftAmount = Log2_32(NumOfVReg - 1);
3107 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister)
3108 .addReg(DestReg)
3109 .addImm(ShiftAmount)
3110 .setMIFlag(Flag);
3111 BuildMI(MBB, II, DL, get(RISCV::ADD), DestReg)
3112 .addReg(ScaledRegister, RegState::Kill)
3113 .addReg(DestReg, RegState::Kill)
3114 .setMIFlag(Flag);
3115 } else if (llvm::has_single_bit<uint32_t>(NumOfVReg + 1)) {
3116 Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
3117 uint32_t ShiftAmount = Log2_32(NumOfVReg + 1);
3118 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister)
3119 .addReg(DestReg)
3120 .addImm(ShiftAmount)
3121 .setMIFlag(Flag);
3122 BuildMI(MBB, II, DL, get(RISCV::SUB), DestReg)
3123 .addReg(ScaledRegister, RegState::Kill)
3124 .addReg(DestReg, RegState::Kill)
3125 .setMIFlag(Flag);
3126 } else if (STI.hasStdExtM() || STI.hasStdExtZmmul()) {
3127 Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
3128 movImm(MBB, II, DL, N, NumOfVReg, Flag);
3129 BuildMI(MBB, II, DL, get(RISCV::MUL), DestReg)
3130 .addReg(DestReg, RegState::Kill)
3132 .setMIFlag(Flag);
3133 } else {
3134 Register Acc;
3135 uint32_t PrevShiftAmount = 0;
3136 for (uint32_t ShiftAmount = 0; NumOfVReg >> ShiftAmount; ShiftAmount++) {
3137 if (NumOfVReg & (1U << ShiftAmount)) {
3138 if (ShiftAmount)
3139 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg)
3140 .addReg(DestReg, RegState::Kill)
3141 .addImm(ShiftAmount - PrevShiftAmount)
3142 .setMIFlag(Flag);
3143 if (NumOfVReg >> (ShiftAmount + 1)) {
3144 // If we don't have an accmulator yet, create it and copy DestReg.
3145 if (!Acc) {
3146 Acc = MRI.createVirtualRegister(&RISCV::GPRRegClass);
3147 BuildMI(MBB, II, DL, get(TargetOpcode::COPY), Acc)
3148 .addReg(DestReg)
3149 .setMIFlag(Flag);
3150 } else {
3151 BuildMI(MBB, II, DL, get(RISCV::ADD), Acc)
3152 .addReg(Acc, RegState::Kill)
3153 .addReg(DestReg)
3154 .setMIFlag(Flag);
3155 }
3156 }
3157 PrevShiftAmount = ShiftAmount;
3158 }
3159 }
3160 assert(Acc && "Expected valid accumulator");
3161 BuildMI(MBB, II, DL, get(RISCV::ADD), DestReg)
3162 .addReg(DestReg, RegState::Kill)
3163 .addReg(Acc, RegState::Kill)
3164 .setMIFlag(Flag);
3165 }
3166}
3167
3170 static const std::pair<MachineMemOperand::Flags, const char *> TargetFlags[] =
3171 {{MONontemporalBit0, "riscv-nontemporal-domain-bit-0"},
3172 {MONontemporalBit1, "riscv-nontemporal-domain-bit-1"}};
3173 return ArrayRef(TargetFlags);
3174}
3175
3176// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
3178 return MI.getOpcode() == RISCV::ADDIW && MI.getOperand(1).isReg() &&
3179 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0;
3180}
3181
3182// Returns true if this is the zext.w pattern, adduw rd, rs1, x0.
3184 return MI.getOpcode() == RISCV::ADD_UW && MI.getOperand(1).isReg() &&
3185 MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0;
3186}
3187
3188// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
3190 return MI.getOpcode() == RISCV::ANDI && MI.getOperand(1).isReg() &&
3191 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 255;
3192}
3193
3194static bool isRVVWholeLoadStore(unsigned Opcode) {
3195 switch (Opcode) {
3196 default:
3197 return false;
3198 case RISCV::VS1R_V:
3199 case RISCV::VS2R_V:
3200 case RISCV::VS4R_V:
3201 case RISCV::VS8R_V:
3202 case RISCV::VL1RE8_V:
3203 case RISCV::VL2RE8_V:
3204 case RISCV::VL4RE8_V:
3205 case RISCV::VL8RE8_V:
3206 case RISCV::VL1RE16_V:
3207 case RISCV::VL2RE16_V:
3208 case RISCV::VL4RE16_V:
3209 case RISCV::VL8RE16_V:
3210 case RISCV::VL1RE32_V:
3211 case RISCV::VL2RE32_V:
3212 case RISCV::VL4RE32_V:
3213 case RISCV::VL8RE32_V:
3214 case RISCV::VL1RE64_V:
3215 case RISCV::VL2RE64_V:
3216 case RISCV::VL4RE64_V:
3217 case RISCV::VL8RE64_V:
3218 return true;
3219 }
3220}
3221
3223 // RVV lacks any support for immediate addressing for stack addresses, so be
3224 // conservative.
3225 unsigned Opcode = MI.getOpcode();
3226 if (!RISCVVPseudosTable::getPseudoInfo(Opcode) &&
3227 !isRVVWholeLoadStore(Opcode) && !isRVVSpillForZvlsseg(Opcode))
3228 return false;
3229 return true;
3230}
3231
3232std::optional<std::pair<unsigned, unsigned>>
3234 switch (Opcode) {
3235 default:
3236 return std::nullopt;
3237 case RISCV::PseudoVSPILL2_M1:
3238 case RISCV::PseudoVRELOAD2_M1:
3239 return std::make_pair(2u, 1u);
3240 case RISCV::PseudoVSPILL2_M2:
3241 case RISCV::PseudoVRELOAD2_M2:
3242 return std::make_pair(2u, 2u);
3243 case RISCV::PseudoVSPILL2_M4:
3244 case RISCV::PseudoVRELOAD2_M4:
3245 return std::make_pair(2u, 4u);
3246 case RISCV::PseudoVSPILL3_M1:
3247 case RISCV::PseudoVRELOAD3_M1:
3248 return std::make_pair(3u, 1u);
3249 case RISCV::PseudoVSPILL3_M2:
3250 case RISCV::PseudoVRELOAD3_M2:
3251 return std::make_pair(3u, 2u);
3252 case RISCV::PseudoVSPILL4_M1:
3253 case RISCV::PseudoVRELOAD4_M1:
3254 return std::make_pair(4u, 1u);
3255 case RISCV::PseudoVSPILL4_M2:
3256 case RISCV::PseudoVRELOAD4_M2:
3257 return std::make_pair(4u, 2u);
3258 case RISCV::PseudoVSPILL5_M1:
3259 case RISCV::PseudoVRELOAD5_M1:
3260 return std::make_pair(5u, 1u);
3261 case RISCV::PseudoVSPILL6_M1:
3262 case RISCV::PseudoVRELOAD6_M1:
3263 return std::make_pair(6u, 1u);
3264 case RISCV::PseudoVSPILL7_M1:
3265 case RISCV::PseudoVRELOAD7_M1:
3266 return std::make_pair(7u, 1u);
3267 case RISCV::PseudoVSPILL8_M1:
3268 case RISCV::PseudoVRELOAD8_M1:
3269 return std::make_pair(8u, 1u);
3270 }
3271}
3272
3274 return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
3275 !MI.isInlineAsm();
3276}
3277
3278bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) {
3279 int16_t MI1FrmOpIdx =
3280 RISCV::getNamedOperandIdx(MI1.getOpcode(), RISCV::OpName::frm);
3281 int16_t MI2FrmOpIdx =
3282 RISCV::getNamedOperandIdx(MI2.getOpcode(), RISCV::OpName::frm);
3283 if (MI1FrmOpIdx < 0 || MI2FrmOpIdx < 0)
3284 return false;
3285 MachineOperand FrmOp1 = MI1.getOperand(MI1FrmOpIdx);
3286 MachineOperand FrmOp2 = MI2.getOperand(MI2FrmOpIdx);
3287 return FrmOp1.getImm() == FrmOp2.getImm();
3288}
3289
3290std::optional<unsigned>
3292 // TODO: Handle Zvbb instructions
3293 switch (Opcode) {
3294 default:
3295 return std::nullopt;
3296
3297 // 11.6. Vector Single-Width Shift Instructions
3298 case RISCV::VSLL_VX:
3299 case RISCV::VSRL_VX:
3300 case RISCV::VSRA_VX:
3301 // 12.4. Vector Single-Width Scaling Shift Instructions
3302 case RISCV::VSSRL_VX:
3303 case RISCV::VSSRA_VX:
3304 // Only the low lg2(SEW) bits of the shift-amount value are used.
3305 return Log2SEW;
3306
3307 // 11.7 Vector Narrowing Integer Right Shift Instructions
3308 case RISCV::VNSRL_WX:
3309 case RISCV::VNSRA_WX:
3310 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
3311 case RISCV::VNCLIPU_WX:
3312 case RISCV::VNCLIP_WX:
3313 // Only the low lg2(2*SEW) bits of the shift-amount value are used.
3314 return Log2SEW + 1;
3315
3316 // 11.1. Vector Single-Width Integer Add and Subtract
3317 case RISCV::VADD_VX:
3318 case RISCV::VSUB_VX:
3319 case RISCV::VRSUB_VX:
3320 // 11.2. Vector Widening Integer Add/Subtract
3321 case RISCV::VWADDU_VX:
3322 case RISCV::VWSUBU_VX:
3323 case RISCV::VWADD_VX:
3324 case RISCV::VWSUB_VX:
3325 case RISCV::VWADDU_WX:
3326 case RISCV::VWSUBU_WX:
3327 case RISCV::VWADD_WX:
3328 case RISCV::VWSUB_WX:
3329 // 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
3330 case RISCV::VADC_VXM:
3331 case RISCV::VADC_VIM:
3332 case RISCV::VMADC_VXM:
3333 case RISCV::VMADC_VIM:
3334 case RISCV::VMADC_VX:
3335 case RISCV::VSBC_VXM:
3336 case RISCV::VMSBC_VXM:
3337 case RISCV::VMSBC_VX:
3338 // 11.5 Vector Bitwise Logical Instructions
3339 case RISCV::VAND_VX:
3340 case RISCV::VOR_VX:
3341 case RISCV::VXOR_VX:
3342 // 11.8. Vector Integer Compare Instructions
3343 case RISCV::VMSEQ_VX:
3344 case RISCV::VMSNE_VX:
3345 case RISCV::VMSLTU_VX:
3346 case RISCV::VMSLT_VX:
3347 case RISCV::VMSLEU_VX:
3348 case RISCV::VMSLE_VX:
3349 case RISCV::VMSGTU_VX:
3350 case RISCV::VMSGT_VX:
3351 // 11.9. Vector Integer Min/Max Instructions
3352 case RISCV::VMINU_VX:
3353 case RISCV::VMIN_VX:
3354 case RISCV::VMAXU_VX:
3355 case RISCV::VMAX_VX:
3356 // 11.10. Vector Single-Width Integer Multiply Instructions
3357 case RISCV::VMUL_VX:
3358 case RISCV::VMULH_VX:
3359 case RISCV::VMULHU_VX:
3360 case RISCV::VMULHSU_VX:
3361 // 11.11. Vector Integer Divide Instructions
3362 case RISCV::VDIVU_VX:
3363 case RISCV::VDIV_VX:
3364 case RISCV::VREMU_VX:
3365 case RISCV::VREM_VX:
3366 // 11.12. Vector Widening Integer Multiply Instructions
3367 case RISCV::VWMUL_VX:
3368 case RISCV::VWMULU_VX:
3369 case RISCV::VWMULSU_VX:
3370 // 11.13. Vector Single-Width Integer Multiply-Add Instructions
3371 case RISCV::VMACC_VX:
3372 case RISCV::VNMSAC_VX:
3373 case RISCV::VMADD_VX:
3374 case RISCV::VNMSUB_VX:
3375 // 11.14. Vector Widening Integer Multiply-Add Instructions
3376 case RISCV::VWMACCU_VX:
3377 case RISCV::VWMACC_VX:
3378 case RISCV::VWMACCSU_VX:
3379 case RISCV::VWMACCUS_VX:
3380 // 11.15. Vector Integer Merge Instructions
3381 case RISCV::VMERGE_VXM:
3382 // 11.16. Vector Integer Move Instructions
3383 case RISCV::VMV_V_X:
3384 // 12.1. Vector Single-Width Saturating Add and Subtract
3385 case RISCV::VSADDU_VX:
3386 case RISCV::VSADD_VX:
3387 case RISCV::VSSUBU_VX:
3388 case RISCV::VSSUB_VX:
3389 // 12.2. Vector Single-Width Averaging Add and Subtract
3390 case RISCV::VAADDU_VX:
3391 case RISCV::VAADD_VX:
3392 case RISCV::VASUBU_VX:
3393 case RISCV::VASUB_VX:
3394 // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
3395 case RISCV::VSMUL_VX:
3396 // 16.1. Integer Scalar Move Instructions
3397 case RISCV::VMV_S_X:
3398 return 1U << Log2SEW;
3399 }
3400}
3401
3402unsigned RISCV::getRVVMCOpcode(unsigned RVVPseudoOpcode) {
3404 RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
3405 if (!RVV)
3406 return 0;
3407 return RVV->BaseInstr;
3408}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
@ MachineOutlinerDefault
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static ARCCC::CondCode getOppositeBranchCondition(ARCCC::CondCode CC)
Return the inverse of passed condition, i.e. turning COND_E to COND_NE.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:693
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
bool End
Definition: ELF_riscv.cpp:480
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static M68k::CondCode getCondFromBranchOpc(unsigned BrOpc)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
#define P(N)
const char LLVMTargetMachineRef TM
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)
static bool isRVVWholeLoadStore(unsigned Opcode)
static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs)
static bool getFPFusedMultiplyPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce)
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)
static cl::opt< bool > PreferWholeRegisterMove("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))
#define CASE_VFMA_SPLATS(OP)
unsigned getPredicatedOpcode(unsigned Opcode)
static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, MachineCombinerPattern Pattern)
#define CASE_WIDEOP_OPCODE_LMULS(OP)
static bool isFSUB(unsigned Opc)
MachineOutlinerConstructionID
static bool isFMUL(unsigned Opc)
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
#define CASE_OPERAND_UIMM(NUM)
#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)
static bool isFADD(unsigned Opc)
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
#define CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
static unsigned getAddendOperandIdx(MachineCombinerPattern Pattern)
static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVII::VLMUL LMul)
#define CASE_VFMA_OPCODE_LMULS(OP, TYPE)
static MachineInstr * canFoldAsPredicatedOp(Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
Identify instructions that can be folded into a CCMOV instruction, and return the defining instructio...
static bool getFPPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce)
static bool canCombineFPFusedMultiply(const MachineInstr &Root, const MachineOperand &MO, bool DoRegPressureReduce)
static cl::opt< MachineTraceStrategy > ForceMachineCombinerStrategy("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy.")))
#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
This file declares the machine register scavenger class.
static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
This file defines the SmallVector class.
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
Value * RHS
Value * LHS
static unsigned getSize(unsigned Kind)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
const T & front() const
front - Get the first element.
Definition: ArrayRef.h:168
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
static DILocation * getMergedLocation(DILocation *LocA, DILocation *LocB)
When two instructions are combined into a single instruction we also need to combine the original loc...
This class represents an Operation in the Expression.
bool isBigEndian() const
Definition: DataLayout.h:239
A debug info location.
Definition: DebugLoc.h:33
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:677
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
LiveInterval & getInterval(Register Reg)
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
Definition: LiveInterval.h:408
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
bool hasValue() const
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
TypeSize getValue() const
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:37
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:43
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:317
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
unsigned pred_size() const
reverse_iterator rend()
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Instructions::const_iterator const_instr_iterator
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void setStackID(int ObjectIdx, uint8_t ID)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:544
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:327
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:377
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:541
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:790
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:775
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:757
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:473
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:554
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:372
void clearKillInfo()
Clears kill flags on all operands.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static MachineOperand CreateImm(int64_t Val)
Register getReg() const
getReg - Returns the register number.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
MI-level patchpoint operands.
Definition: StackMaps.h:76
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const
MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override
const MCInstrDesc & getBrCond(RISCVCC::CondCode CC) const
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const override
RISCVInstrInfo(RISCVSubtarget &STI)
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
const RISCVSubtarget & STI
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
MachineTraceStrategy getMachineCombinerTraceStrategy() const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
virtual outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
MCInst getNop() const override
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
void getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
void copyPhysRegVector(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, unsigned Opc, unsigned NF=1) const
bool optimizeCondBranch(MachineInstr &MI) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool hasStdExtCOrZca() const
unsigned getXLen() const
const RISCVRegisterInfo * getRegisterInfo() const override
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:68
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:321
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:356
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:342
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
MI-level stackmap operands.
Definition: StackMaps.h:35
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:50
MI-level Statepoint operands.
Definition: StackMaps.h:158
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given statepoint should emit.
Definition: StackMaps.h:207
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
virtual bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Target - Wrapper for Target specific information.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:660
#define INT64_MAX
Definition: DataTypes.h:71
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CondCode getOppositeBranchCondition(CondCode)
unsigned getBrCond(CondCode CC)
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool isRVVWideningReduction(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI)
@ OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_UIMM10_LSB00_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
static bool isValidSEW(unsigned SEW)
void printVType(unsigned VType, raw_ostream &OS)
static unsigned getSEW(unsigned VType)
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2)
std::optional< unsigned > getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW)
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex)
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)
bool isSEXT_W(const MachineInstr &MI)
bool isFaultFirstLoad(const MachineInstr &MI)
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
bool isZEXT_B(const MachineInstr &MI)
bool isRVVSpill(const MachineInstr &MI)
bool isZEXT_W(const MachineInstr &MI)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Dead
Unused definition.
@ Define
Register definition.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:718
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:329
@ Offset
Definition: DWP.cpp:456
MachineTraceStrategy
Strategies for selecting traces.
@ TS_MinInstrCount
Select the trace through a block that has the fewest instructions.
@ TS_Local
Select the trace that contains only the current basic block.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1731
static const MachineMemOperand::Flags MONontemporalBit1
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
Definition: STLExtras.h:2415
static const MachineMemOperand::Flags MONontemporalBit0
const Value * getUnderlyingObject(const Value *V, unsigned MaxLookup=6)
This method strips off any GEP address adjustments and pointer casts from the specified value,...
unsigned getDeadRegState(bool B)
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:269
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:319
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:313
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
unsigned getKillRegState(bool B)
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:233
unsigned getRenamableRegState(bool B)
DWARFExpression::Operation Op
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
Definition: STLExtras.h:2060
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:452
#define N
Description of the encoding of one expression Op.
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Used to describe a register and immediate addition.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.